DISPLAY FIELD, DISPLAY DEVICE AND CONTROL METHOD

Abstract

A display field, a display device, and a control method according to the embodiments of the present disclosure comprise: a shift register unit and a plurality of output control signal lines coupled to the shift register unit, wherein the plurality of output control signal lines are arranged between the shift register unit and a display area of ​​the display field; wherein the shift register unit comprises: a shift register configured to output a cascade signal via a cascade output terminal; an output circuit coupled to the shift register configured to control a control output terminal based on a signal at an output control signal terminal and a signal at a first reference signal terminal to output a gate sampling signal, wherein the output control signal terminal is coupled to one of the plurality of output control signal lines.

Description

Reference to related applications

[0001] This application claims priority over Chinese patent application No. 202310462243.6, filed with the State Intellectual Property Office of the People's Republic of China on April 26, 2023, entitled "Display field, display device and control method", the full contents of which are hereby incorporated by reference. Technical field

[0002] The present disclosure relates to the field of display technology and in particular to a display field, a display device and a control method. State of the art

[0003] With the rapid development of display technology, display arrays are showing a trend towards high integration and low cost. Gate-Driver-on-Array (GOA) technology integrates a driver circuit onto an array substrate of a display array to enable scan-based control of the display array. Currently, the driver circuit typically consists of several cascaded shift register units. Disclosure of the invention

[0004] Some embodiments of the present disclosure provide a display field with: a shift register unit and a plurality of output control signal lines connected to the shift register unit, wherein the plurality of output control signal lines are arranged between the shift register unit coupled thereto and a display area of ​​the display field; the shift register unit comprises: a shift register configured to output a cascade signal via a cascade output terminal; an output circuit coupled to the shift register, configured to control a drive output terminal based on a signal at an output control signal terminal and a signal at a first reference signal terminal, in order to output a gate sampling signal, wherein the output control signal terminal is coupled to one of the plurality of output control signal lines.

[0005] In some possible embodiments of the present disclosure, the output circuit comprises a first and a second output circuit; wherein the first output circuit is coupled to a cascade output terminal or a first node in the shift register and is configured to transmit a signal from the output control signal terminal to the drive output terminal in response to a signal at the cascade output terminal or at the first node; wherein the second output circuit is coupled to a second node in the shift register and is configured to transmit a signal from the first reference signal terminal to the drive output terminal in response to a signal at the second node.

[0006] In some possible embodiments of the present disclosure, the first output circuit comprises a first output transistor; wherein a gate of the first output transistor is coupled to the cascade output terminal or the first node, a first electrode of the first output transistor is coupled to the output control signal terminal and a second electrode of the first output transistor is coupled to the drive output terminal.

[0007] In some possible embodiments of the present disclosure, the second output circuit comprises a second output transistor; wherein a gate of the second output transistor is coupled to the second node, a first electrode of the second output transistor is coupled to the first reference signal terminal and a second electrode of the second output transistor is coupled to the drive output terminal.

[0008] In some possible embodiments of the present disclosure, the shift register comprises: an input sub-circuit configured to deliver a signal to the third node at an input signal terminal in response to a signal at a first clock signal terminal; a control circuit configured to control the signals at the first and second nodes and to supply the signal at the third node to the first or second node; a cascade sub-circuit configured to cause the cascade output terminal to output the cascade signal in response to the signals at the first and second nodes.

[0009] In some possible embodiments of the present disclosure, the input circuit comprises a first transistor; wherein a gate of the first transistor is coupled to the first clock signal terminal, a first electrode of the first transistor is coupled to the input signal terminal and a second electrode of the first transistor is coupled to the third node.

[0010] In some possible implementations of the present disclosure, the control circuit comprises a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. wherein a gate of the second transistor is coupled to the third node, a first electrode of the second transistor is coupled to the first clock signal terminal and a second electrode of the second transistor is coupled to the fourth node, wherein a gate of the third transistor is coupled to a second reference signal terminal, a first electrode of the third transistor to the fourth node and a second electrode of the third transistor to a gate of the fourth transistor, a first electrode of the fourth transistor is coupled to a second clock signal terminal and a second electrode of the fourth transistor is coupled to a first electrode of the fifth transistor, a gate of the fifth transistor is coupled to the second clock signal terminal and a second electrode of the fifth transistor is coupled to the first node, a gate of the sixth transistor is coupled to the first clock signal terminal, a first electrode of the sixth transistor is coupled to the input signal terminal, and a second electrode of the sixth transistor is coupled to a first electrode of the seventh transistor. a gate of the seventh transistor is coupled to the second reference signal terminal and a second electrode of the seventh transistor is coupled to the fifth node, a gate of the eighth transistor is coupled to the fifth node, a first electrode of the eighth transistor is coupled to the fifth node and a second electrode of the eighth transistor is coupled to the second node, a gate of the ninth transistor is coupled to the first clock signal terminal, a first electrode of the ninth transistor is coupled to the second reference signal terminal, and a second electrode of the ninth transistor is coupled to a gate of the tenth transistor. a first electrode of the tenth transistor is coupled to a third reference signal terminal and a second electrode of the tenth transistor is coupled to a sixth node, a gate of the eleventh transistor is coupled to the fifth node, a first electrode of the eleventh transistor is coupled to the sixth node, and a second electrode of the eleventh transistor is coupled to the second clock signal terminal. a gate of the twelfth transistor is coupled to a first electrode of the fifteenth transistor, a first electrode of the twelfth transistor is coupled to the first node and a second electrode of the twelfth transistor is coupled to a fourth reference signal terminal, a gate of the thirteenth transistor with a fifth reference signal terminal, a first electrode of the thirteenth transistor coupled to the fourth reference signal terminal, and a second electrode of the thirteenth transistor coupled to a first electrode of the fourteenth transistor. a gate of the fourteenth transistor is coupled to the first reference signal terminal, and a second electrode of the fourteenth transistor is coupled to the first electrode of the fifteenth transistor, a gate of the fifteenth transistor is coupled to the first reference signal terminal, the first electrode of the fifteenth transistor is coupled to the third node, and a second electrode of the fifteenth transistor is coupled to the second node, a first electrode of the first capacitor is coupled to the gate of the fourth transistor, and a second electrode of the first capacitor is coupled to the second electrode of the fourth transistor, a first electrode of the second capacitor is coupled to the sixth node, and a second electrode of the second capacitor is coupled to the second electrode of the seventh transistor, a first electrode of the third capacitor is coupled to the fourth reference signal terminal, and a second electrode of the third capacitor is coupled to the first node, a first electrode of the fourth capacitor is coupled to the cascade output terminal, and a second electrode of the fourth capacitor is coupled to the first reference signal terminal.

[0011] In some possible embodiments of the present disclosure, the cascade sub-circuit comprises a first cascade transistor and a second cascade transistor; where a gate of the first cascade transistor is connected to the first node, a first electrode of the The first cascade transistor is coupled to the fourth reference signal terminal, and a second electrode of the first cascade transistor is coupled to the cascade output terminal; a gate of the second cascade transistor is coupled to the second node, a first electrode of the second cascade transistor is coupled to the cascade output terminal, and a second electrode of the second cascade transistor is coupled to the first reference signal terminal.

[0012] In some possible embodiments of the present disclosure, the input circuit comprises a sixteenth and a seventeenth transistor; wherein a gate of the sixteenth transistor is coupled to the first clock signal terminal, a first electrode of the sixteenth transistor is coupled to the input signal terminal and a second electrode of the sixteenth transistor is coupled to the seventh node; a gate of the seventeenth transistor is coupled to the first clock signal terminal, a first electrode of the seventeenth transistor is coupled to the seventh node, and a second electrode of the seventeenth transistor is coupled to the third node.

[0013] In some possible implementations of the present disclosure, the control circuit comprises an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a fifth capacitor, and a sixth capacitor; wherein a gate of the eighteenth transistor is coupled to the cascade output terminal, a first electrode of the eighteenth transistor is coupled to a third clock signal terminal and a second electrode of the eighteenth transistor is coupled to a seventh node; a gate of the nineteenth transistor is coupled to the input signal terminal, a first electrode of the nineteenth transistor is coupled to the first reference signal terminal, and a second electrode of the nineteenth transistor is coupled to the second node; a gate of the twentieth transistor is coupled to the second node, a first electrode of the twentieth transistor is coupled to the first reference signal terminal, and a second electrode of the twentieth transistor is coupled to an eighth node; a gate of the twenty-first transistor is coupled to the second node, a first electrode of the twenty-first transistor is coupled to the eighth node, and a second electrode of the twenty-first transistor is coupled to the third node; a gate of the twenty-second transistor is coupled to the third node, a first electrode of the twenty-second transistor is coupled to the eighth node, and a second electrode of the twenty-second transistor is coupled to a sixth reference signal terminal; a gate of the twenty-third transistor is coupled to a fourth clock signal terminal, a first electrode of the twenty-third transistor is coupled to the second node, and a second electrode of the twenty-third transistor is coupled to the sixth reference signal terminal; a first electrode of the fifth capacitor is coupled to the first reference signal terminal and a second electrode of the fifth capacitor is coupled to the first electrode of the twenty-third transistor; a first electrode of the sixth capacitor is coupled to the cascade output terminal and a second electrode of the sixth capacitor is coupled to the first node.

[0014] In some possible embodiments of the present disclosure, the cascade sub-circuit comprises a first cascade transistor and a second cascade transistor; wherein a gate of the first cascade transistor is coupled to the first node, a first electrode of the first cascade transistor is coupled to the cascade output terminal and a second electrode of the first cascade transistor is coupled to the third clock signal terminal; a gate of the second cascade transistor is coupled to the second node, a first electrode of the second cascade transistor is coupled to the first reference signal terminal, and a second electrode of the second cascade transistor is coupled to the cascade output terminal.

[0015] In some possible embodiments of the present disclosure, the control circuit comprises a twenty-fourth transistor, a twenty-fifth transistor, a twenty-sixth transistor, a twenty-seventh transistor, a twenty-eighth transistor, a seventh capacitor and an eighth capacitor; wherein a gate of the twenty-fourth transistor is coupled to the first clock signal terminal, a first electrode of the twenty-fourth transistor is coupled to a seventh reference signal terminal, and a second electrode of the twenty-fourth transistor is coupled to the second node; a gate of the twenty-fifth transistor is coupled to the third node, a first electrode of the twenty-fifth transistor is coupled to the second node, and a second electrode of the twenty-fifth transistor is coupled to the first clock signal terminal; a gate of the twenty-sixth transistor is coupled to the second node, a first electrode of the twenty-sixth transistor is coupled to the first reference signal terminal, and a second electrode of the twenty-sixth transistor is coupled to a first electrode of the twenty-seventh transistor; a gate of the twenty-seventh transistor is coupled to the third clock signal terminal, and a second electrode of the twenty-seventh transistor is coupled to a first electrode of the twenty-eighth transistor; a gate of the twenty-eighth transistor is coupled to the seventh reference signal terminal, the first electrode of the twenty-eighth transistor is coupled to the third node, and a second electrode of the twenty-eighth transistor is coupled to the first node; a first electrode of the seventh capacitor is coupled to the first reference signal terminal, and a second electrode of the seventh capacitor is coupled to the first node; a first electrode of the eighth capacitor is coupled to the cascade output terminal, and a second electrode of the eighth capacitor is coupled to the first node.

[0016] Some embodiments of the present disclosure provide a display field that includes: a substrate with a display area and a non-display area; the display area includes: a plurality of subpixels; a plurality of scanning lines, wherein a row of the subpixels of the plurality of subpixels is coupled to at least one of the plurality of scanning lines; including the non-display area: a gate control circuit with a plurality of shift register units, wherein a control output connection of each shift register unit of the plurality of shift register units is coupled to at least one of the plurality of sampling lines.

[0017] In some possible implementations of the present disclosure, the display field also includes a plurality of output control signal lines coupled to the gate drive circuit, the output control signal lines running in the same direction as the arrangement of the shift register units.

[0018] In some possible implementations of the present disclosure, the majority of output control signal lines are arranged between the gate drive circuit to which they are coupled and the display area.

[0019] In some possible embodiments of the present disclosure, in two adjacent shift register units of the plurality of shift register units, the input signal connection of the next shift register unit is coupled to the cascade output connection of the previous shift register unit; wherein the majority of output control signal lines comprise a first and a second output control signal line, wherein the first output control signal line is coupled to the output control signal terminals of odd-numbered shift register units and the second output control signal line is coupled to the output control signal terminals of even-numbered shift register units.

[0020] In some possible embodiments of the present disclosure, the display field also includes a plurality of output control auxiliary signal lines, wherein a first insulating layer is provided between the majority of output control auxiliary signal lines and the majority of output control signal lines; the majority of output control auxiliary signal lines correspond one-to-one to the majority of output control signal lines, and each of the output control auxiliary signal lines is coupled to a corresponding output control signal line via a first through-hole penetrating the first insulating layer.

[0021] In some possible embodiments of the present disclosure, the display field also includes a plurality of clock signal lines coupled to the gate drive circuit, wherein the plurality of clock signal lines run in the same direction as the arrangement of the plurality of shift register units.

[0022] In some possible embodiments of the present disclosure, the majority of clock signal lines are arranged on a side of the gate drive circuit coupled thereto that faces away from the display area.

[0023] In some possible embodiments of the present disclosure, the orthographic projections of the plurality of output control signal lines on the substrate are located between the orthographic projections of the plurality of clock signal lines on the substrate and the display area.

[0024] In some possible embodiments of the present disclosure, the orthographic projection of the gate drive circuit on the substrate is located between the orthographic projections of the plurality of clock signal lines on the substrate and the orthographic projections of the plurality of output control signal lines on the substrate, and the orthographic projections of the plurality of output control signal lines on the substrate are located between the orthographic projection of the gate drive circuit on the substrate and the display area.

[0025] In some possible embodiments of the present disclosure, the orthographic projection of the first output transistor on the substrate is located between the orthographic projection of the first cascade transistor on the substrate and the display area.

[0026] In some possible embodiments of the present disclosure, the channel width of the first output transistor is larger than the channel width of the first cascade transistor.

[0027] In some possible embodiments of the present disclosure, the channel width of the first output transistor is at least 100 µm.

[0028] In some possible embodiments of the present disclosure, the channel width of the first cascade transistor is at most 60 µm.

[0029] In some possible embodiments of the present disclosure, the orthographic projection of the second output transistor on the substrate is located between the orthographic projection of the second cascade transistor on the substrate and the display area.

[0030] In some possible embodiments of the present disclosure, the channel width of the second output transistor is larger than the channel width of the second cascade transistor.

[0031] In some possible embodiments of the present disclosure, the channel width of the second output transistor is at least 100 µm.

[0032] In some possible embodiments of the present disclosure, the channel width of the second cascade transistor is at most 60 µm.

[0033] Some embodiments of the present disclosure provide a display device comprising: the display field described above; a control circuit coupled to the display field, configured to input a first output control signal to the output control signal terminals of the majority of shift register units in a full-screen control mode, causing the shift register units to sequentially output gate sampling signals to drive the sampling lines line by line; and in a partial-screen control mode, it inputs a second output control signal to the output control signal terminals of the majority of shift register units, causing some of the majority of shift register units to sequentially output gate sampling signals and the remaining shift register units to output inactive sampling signals.

[0034] Some embodiments of the present disclosure provide a control method comprising the following: If it is determined that a full-screen drive mode should be used, an initial output control signal is input to the output control signal terminals of a plurality of shift register units, causing the plurality of shift register units to sequentially output gate sampling signals to drive sampling units line by line; If it is determined that a partial drive mode is to be used, a second output control signal is input to the output control signal terminals of the majority of shift register units, causing a portion of the majority of shift register units to sequentially output gate sampling signals and the remaining shift register units to output inactive sampling signals in order to drive a portion of the sampling power.

[0035] In some possible embodiments of the present disclosure, the first output control signal is a fixed voltage signal with a first level.

[0036] In some possible embodiments of the present disclosure, the second output control signal comprises a fixed voltage signal component with a first level and a fixed voltage signal component with a second level, wherein the fixed voltage signal component with the first level is fed into the part of the shift register units and the fixed voltage signal component with the second level is fed into the remaining shift register units.

[0037] In some possible embodiments of the present disclosure, the first output control signal is a clock signal.

[0038] In some possible embodiments of the present disclosure, the second output control signal comprises a clock signal component and a fixed voltage signal component with a first level, wherein the clock signal component of the second output control signal is fed into the part of the shift register units and the fixed voltage signal component with the first level is fed into the remaining shift register units. Brief description of the drawings Fig. Figure 1 shows a schematic representation of some structures of a shift register unit provided in an embodiment of the present disclosure. Fig. Figure 2 shows a schematic representation of further structures of a shift register unit provided in an embodiment of the present disclosure. Fig. Figure 3 shows a schematic representation of some structures of a display field provided in an embodiment of the present disclosure. Fig. Figure 4 shows a schematic representation of some structures of a display device provided in an embodiment of the present disclosure. Fig. Figure 5 shows a flowchart of a control method provided in an embodiment of the present disclosure. Fig. Figure 6 shows some diagrams of signal timings provided in one embodiment of the present disclosure. Fig. Figure 7 shows further diagrams of signal times provided in one embodiment of the present disclosure. Fig. Figure 8 shows a schematic representation of further structures of a shift register unit provided in an embodiment of the present disclosure. Fig. Figure 9 shows further diagrams of signal times provided in one embodiment of the present disclosure. Fig. Figure 10 shows further diagrams of signal times provided in one embodiment of the present disclosure. Fig. Figure 11 shows a schematic representation of further structures of a shift register unit provided in an embodiment of the present disclosure. Fig. Figure 12 shows further diagrams of signal clocks provided in embodiments of the present disclosure; Fig. 13 shows further diagrams of signal clocks provided in embodiments of the present disclosure; Fig. Figure 14 shows a schematic layout diagram of a shift register unit provided in embodiments of the present disclosure; Fig. Figure 15 shows a schematic layout diagram of a semiconductor layer provided in embodiments of the present disclosure; Fig. Figure 16 shows a schematic layout diagram of a conductive gate layer provided in embodiments of the present disclosure; Fig. Figure 17 shows a schematic layout diagram of a capacitor electrode layer provided in embodiments of the present disclosure; Fig. Figure 18 shows a schematic layout diagram of a cascade wiring layer provided in embodiments of the present disclosure; Fig. Figure 19 shows a schematic layout diagram of a transmission wiring layer provided in embodiments of the present disclosure; Fig. Figure 20 shows a schematic layout diagram of an auxiliary wiring layer provided in embodiments of the present disclosure. Embodiments of the invention

[0039] To further clarify the objectives, technical solutions, and advantages of the embodiments of this disclosure, the technical solutions of the embodiments of this disclosure are described clearly and completely below in conjunction with the accompanying drawings. It is understood that the described embodiments represent only a subset of the embodiments of this disclosure, not all of them. Furthermore, the embodiments and features within the embodiments of this disclosure may be combined, provided there is no conflict. Based on the described embodiments of this disclosure, all other embodiments developed by persons skilled in the art without inventive step fall within the scope of protection of this disclosure.

[0040] Unless otherwise defined, the technical or scientific terms used in this disclosure have the same general meaning as they would be understood by those skilled in the art in the field to which this disclosure relates. The terms “a first”, “a second”, and similar terms in this disclosure do not denote any order, quantity, or importance. They serve only to distinguish between different components. Terms such as “comprise” or “include” mean that the element or object preceding the term includes the elements or objects listed after the term and their equivalents, without excluding any other elements or objects. Terms such as “coupled” or “connected” are not limited to physical or mechanical coupling and may also include electrical coupling, whether direct or indirect.

[0041] It should be noted that the sizes and shapes of the graphics in the drawings are not to scale and serve only to illustrate the present disclosure. Identical or similar reference numerals consistently denote identical or similar elements or elements with identical or similar functions.

[0042] One embodiment of the present disclosure provides a shift register unit as described in Fig. 1 shown, which includes the following: a shift register 100 configured to output a cascade signal via a cascade output terminal OT; an output circuit 200 coupled to the shift register 100 and configured to control a drive output terminal OUT based on a signal at an output control signal terminal CS and a signal at a first reference signal terminal VREF1 to output a gate sampling signal.

[0043] The embodiment of the present disclosure provides a shift register unit that controls the gate sampling signal at the drive output terminal in the output circuit by causing the shift register to output the cascade signal and controlling the signal at the output control signal terminal. When the shift register unit is used on a display panel, the signal at the output control signal terminal can be controlled to sample any desired area of ​​the display panel. This allows the refresh rate of different areas to be flexibly adjusted, saving power and reducing losses.

[0044] In some embodiments of the present disclosure, as in Fig. As shown in Figure 2, the output circuit 200 comprises a first output circuit 210 and a second output circuit 220. The first output circuit 210 is coupled to a first node N1 in the shift register 100 and configured to transmit a signal from the output control signal terminal CS to the control output terminal OUT in response to a signal at the first node N1. The second output circuit 220 is coupled to a second node N2 in the shift register 100 and configured to transmit a signal from the first reference signal terminal VREF1 to the control output terminal OUT in response to a signal at the second node N2.

[0045] In some embodiments of the present disclosure, as in Fig. As shown in Figure 2, the first output circuit 210 comprises a first output transistor T1. A gate of the first output transistor T1 is coupled to the first node N1, a first electrode of the first output transistor T1 is coupled to the output control signal terminal CS, and a second electrode of the first output transistor T1 is coupled to the control output terminal OUT.

[0046] In some embodiments of the present disclosure, as in Fig. As shown in Figure 2, the second output circuit 220 comprises a second output transistor T2. A gate of the second output transistor T2 is coupled to the second node N2, a first electrode of the second output transistor T2 to the first reference signal terminal VREF1, and a second electrode of the second output transistor T2 to the control output terminal OUT.

[0047] Alternatively, the first output circuit can be coupled to a cascade output terminal in the shift register. The first output circuit is configured to transmit a signal from the output control signal terminal to the drive output terminal in response to a signal at the cascade output terminal. Based on this, the gate of the first output transistor is coupled to the cascade output terminal in the shift register.

[0048] In the embodiments of the present disclosure, coupling the gate of the first output transistor to the first node offers a better technical effect than coupling the gate of the first output transistor to the cascade output terminal in the shift register. Fig. For example, in step 2, the gate of the first output transistor T1 is coupled to the first node N1, and the drive output terminal OUT can output a low-level signal with a voltage of VGL. If the gate of the first output transistor is coupled to the cascade output terminal in the shift register, the voltage of the low-level signal that the cascade output terminal can output can only be VGL, which means that the voltage of the low-level signal that the drive output terminal OUT can output can only be VGL-Vth.

[0049] In some embodiments of the present disclosure, as in Fig. As shown in Figure 2, the shift register 100 comprises: an input sub-circuit 110 configured to supply a signal from an input signal terminal IN to a third node N3 in response to a signal at a first clock signal terminal CK1; a control sub-circuit 120 configured to control signals at the first node N1 and the second node N2 and to supply a signal from the third node N3 to the first node N1 or the second node N2; a cascade sub-circuit 130 configured to cause a cascade output terminal OT to output a cascade signal in response to signals at the first node N1 and the second node N2.

[0050] In some embodiments of the present disclosure, as in Fig. As shown in Figure 2, the input sub-circuit 110 comprises a first transistor M1. A gate of the first transistor M1 is coupled to the first clock signal terminal CK1, a first electrode of the first transistor M1 to the input signal terminal IN, and a second electrode of the first transistor M1 to the third node N3.

[0051] In some embodiments of the present disclosure, as in Fig. As shown in Figure 2, the control circuit 120 comprises a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4.

[0052] A gate of the second transistor M2 is coupled to a third node N3, a first electrode of the second transistor M2 is coupled to the first clock signal terminal CK1, and a second electrode of the second transistor M2 is coupled to a fourth node N4. A gate of the third transistor M3 is coupled to a second reference signal terminal VREF2, a first electrode of the third transistor M3 to the fourth node N4, and a second electrode of the third transistor M3 to a gate of the fourth transistor M4. A first electrode of the fourth transistor M4 is coupled to a second clock signal terminal CK2, and a second electrode of the fourth transistor M4 is coupled to a first electrode of the fifth transistor M5. A gate of the fifth transistor M5 is coupled to the second clock signal terminal CK2, and a second electrode of the fifth transistor M5 is coupled to the first node N1.A gate of the sixth transistor M6 is coupled to the first clock signal terminal CK1, a first electrode of the sixth transistor M6 to the input signal terminal IN, and a second electrode of the sixth transistor M6 to a first electrode of the seventh transistor M7. A gate of the seventh transistor M7 is coupled to the second reference signal terminal VREF2, and a second electrode of the seventh transistor M7 to a fifth node N5. A gate of the eighth transistor M8 is coupled to the fifth node N5, a first electrode of the eighth transistor M8 is coupled to the fifth node N5, and a second electrode of the eighth transistor M8 is coupled to the second node N2.A gate of the ninth transistor M9 is coupled to the first clock signal terminal CK1, a first electrode of the ninth transistor M9 is coupled to the second reference signal terminal VREF2, and a second electrode of the ninth transistor M9 is coupled to a gate of the tenth transistor M10. A first electrode of the tenth transistor M10 is coupled to a third reference signal terminal VREF3, and a second electrode of the tenth transistor M10 is coupled to a sixth node N6. A gate of the eleventh transistor M11 is coupled to the fifth node N5, a first electrode of the eleventh transistor M11 is coupled to the sixth node N6, and a second electrode of the eleventh transistor M11 is coupled to the second clock signal terminal CK2.A gate of the twelfth transistor M12 is coupled to a first electrode of the fifteenth transistor M15, a first electrode of the twelfth transistor M12 is coupled to the first node N1, and a second electrode of the twelfth transistor M12 is coupled to a fourth reference signal terminal VREF4. A gate of the thirteenth transistor M13 is coupled to a fifth reference signal terminal VREF5, a first electrode of the thirteenth transistor M13 to the fourth reference signal terminal VREF4, and a second electrode of the thirteenth transistor M13 to a first electrode of the fourteenth transistor M14. A gate of transistor M14 is coupled to the first reference signal terminal VREF1, and a second electrode of the fourteenth transistor M14 is coupled to the first electrode of the fifteenth transistor M15.A gate of the fifteenth transistor M15 is coupled to the first reference signal terminal VREF1, the first electrode of the fifteenth transistor M15 to the third node N3, and a second electrode of the fifteenth transistor M15 to the second node N2. A first electrode of the first capacitor C1 is coupled to the gate of the fourth transistor M4, and a second electrode of the first capacitor C1 to the second electrode of the fourth transistor M4. A first electrode of the second capacitor C2 is coupled to the sixth node N6, and a second electrode of the second capacitor C2 to the second electrode of the seventh transistor M7. A first electrode of the third capacitor C3 is coupled to the fourth reference signal terminal VREF4, and a second electrode of the third capacitor C3 to the first node N1.A first electrode of the fourth capacitor C4 is coupled to the cascade output terminal OT and a second electrode of the fourth capacitor C4 is coupled to the first reference signal terminal VREF1.

[0053] In some embodiments of the present disclosure, as in Fig. As shown in Figure 2, the cascade sub-circuit 130 comprises a first cascade transistor T3 and a second cascade transistor T4. A gate of the first cascade transistor T3 is coupled to the first node N1, a first electrode of the first cascade transistor T3 to the fourth reference signal terminal VREF4, and a second electrode of the first cascade transistor T3 to the cascade output terminal OT. A gate of the second cascade transistor T4 is coupled to the second node N2, a first electrode of the second cascade transistor T4 is coupled to the cascade output terminal OT, and a second electrode of the second cascade transistor T4 is coupled to the first reference signal terminal VREF1.

[0054] For example, the effective pulse signal of the cascade signal output from the cascade output terminal can be a high-level signal, the effective pulse signal of the gate sampling signal output from the drive output terminal can be a high-level signal, the effective pulse signal of the first reference signal output from the first reference signal terminal can be a low-level signal, the effective pulse signal of the second reference signal output from the second reference signal terminal can be a low-level signal, the effective pulse signal of the third reference signal output from the third reference signal terminal can be a high-level signal, and the effective pulse signal of the fourth reference signal output from the fourth reference signal terminal can be a high-level signal.Alternatively, the effective pulse signal of the cascade signal output from the cascade output terminal can be a low-level signal, the effective pulse signal of the gate sampling signal output from the drive output terminal can be a low-level signal, the effective pulse signal of the first reference signal output from the first reference signal terminal can be a high-level signal, the effective pulse signal of the second reference signal output from the second reference signal terminal can be a high-level signal, the effective pulse signal of the third reference signal output from the third reference signal terminal can be a low-level signal, and the effective pulse signal of the fourth reference signal output from the fourth reference signal terminal can be a low-level signal.

[0055] To simplify the manufacturing process, all transistors can be P-type transistors, for example. Alternatively, all transistors can be N-type transistors, without being restricted in this respect. Furthermore, an N-type transistor is turned on by a high-level signal and turned off by a low-level signal, while a P-type transistor is turned off by a high-level signal and turned on by a low-level signal.

[0056] It should be noted that the transistors mentioned in the above embodiments of the present disclosure can be, without limitation, thin-film transistors (TFTs) or metal-oxide-semiconductor field-effect transistors (MOSs). In specific implementations, depending on the transistor type and input signal, the first electrode of the transistor can serve as the source and the second electrode as the drain. Alternatively, the first electrode can serve as the drain and the second electrode as the source, without any specific distinction being made here.

[0057] Embodied embodiments of the present disclosure provide a display field as shown in Fig. 3 shown, which includes: a substrate 1000 with a display area AA and a non-display area BB; where the display area AA includes: a plurality of subpixels SPX; a plurality of sampling lines GA, wherein a row of subpixels SPX of the plurality of subpixels SPX is coupled to at least one sampling line GA of the plurality of sampling lines GA; where the non-display area includes BB: a gate control circuit 10 with the above-mentioned shift register units (e.g. SR1, SR2, SR3, SR4, SR5, SR6, SR7 and SR8 in Fig. 3), wherein a control output connection OUT of each of the plurality of shift register units (e.g. SR1, SR2, SR3, SR4, SR5, SR6, SR7 and SR8 in Fig. 3) is coupled to at least one of the majority of sampling lines GA.

[0058] In some embodiments of the present disclosure, as in Fig. As shown in Figure 3, the display field also includes a plurality of output control signal lines (e.g., CS-1 and CS-2 in Figure 3). Fig. 3), which are coupled to the shift register units in the gate drive circuit 10. The output control signal connection of a shift register unit is coupled to one of the majority of output control signal lines. In addition, the majority of output control signal lines (e.g., CS-1 and CS-2 in Fig. 3) in the same direction as the arrangement of the majority of shift register units (e.g. SR1, SR2, SR3, SR4, SR5, SR6, SR7 and SR8 in Fig. 3) For example, the majority of output control signal lines (e.g., CS-1 and CS-2 in Fig. 3) in a second direction F2, and the majority of shift register units (e.g. SR1, SR2, SR3, SR4, SR5, SR6, SR7 and SR8 in Fig. 3) are also arranged in the second direction F2. F1 in Fig. 3 represents the first direction.

[0059] In some embodiments of the present disclosure, as in Fig. As shown in Figure 3, the majority of output control signal lines (e.g., CS-1 and CS-2 in) are Fig. 3) arranged between the gate drive circuit 10 with which they are coupled and the display area AA.

[0060] In some embodiments of the present disclosure, as in Fig. Figure 3 shows that the majority of shift register units (e.g., SR1, SR2, SR3, SR4, SR5, SR6, SR7 and SR8) are located in two adjacent shift register units. Fig. 3) The input signal terminal IN of the next shift register unit is coupled to the cascade output terminal OT of the previous shift register unit. It should be noted that the input signal terminal IN of the first shift register unit SR1 is the input signal terminal of the majority of shift register units (e.g., SR1, SR2, SR3, SR4, SR5, SR6, SR7, and SR8 in the Fig. 3) is coupled with a frame start signal line stv.

[0061] In some embodiments of the present disclosure, as in Fig. Figure 3 shows the majority of output control signal lines (e.g., CS-1 and CS-2 in Fig. 3) A first output control signal line CS-1 and a second output control signal line CS-2. The first output control signal line CS-1 is coupled to the output control signal terminals CS of odd-numbered shift register units, and the second output control signal line CS-2 is coupled to the output control signal terminals CS of even-numbered shift register units. For example, the first output control signal line CS-1 is coupled to the output control signal terminals CS of shift register units SR1, SR3, SR5, and SR7, and the second output control signal line CS-2 is coupled to the output control signal terminals CS of shift register units SR2, SR4, SR6, and SR8.

[0062] In some embodiments of the present disclosure, as in Fig. As shown in Figure 3, the display field also includes a plurality of clock signal lines (e.g., clk1 and clk2 in Figure 3). Fig. 3), which are coupled to the gate drive circuit. The clock signal lines (e.g., clk1 and clk2 in Fig. 3) run in the same direction as the arrangement of the shift register units.

[0063] In some embodiments of the present disclosure, as in Fig. Figure 3 shows a plurality of output control auxiliary signal lines. A first insulating layer is located between the output control auxiliary signal lines and the output control signal lines. The output control auxiliary signal lines correspond one-to-one to the output control signal lines, and each of the output control auxiliary signal lines is coupled to the corresponding output control signal line via a first through-hole that penetrates the first insulating layer.

[0064] In some embodiments of the present disclosure, as in the Fig. As shown in Figures 14 to 20, the substrate is successively provided with a semiconductor layer 010, a conductive gate layer 020, a capacitor electrode layer 030, a cascade wiring layer 040, a signal transmission wiring layer 050, and an auxiliary wiring layer 060. An insulating layer is located between each pair of adjacent layers of the semiconductor layer 010, the conductive gate layer 020, the capacitor electrode layer 030, the cascade wiring layer 040, the signal transmission wiring layer 050, and the auxiliary wiring layer 060. The two layers to be coupled are connected via a through-hole penetrating the insulating layer.

[0065] For example, semiconductor layer 010 comprises an active layer of each of the transistors mentioned above. The semiconductor layer can be formed by structuring a semiconductor material. The semiconductor layer can be used to form the active layers of the aforementioned transistors. The semiconductor layer can consist of, for example, amorphous silicon, polycrystalline silicon, oxide semiconductor materials, and the like. It should be noted that the source and drain regions mentioned above can be conductive regions doped with n-type or p-type impurities.

[0066] For example, the conductive gate layer 020 encompasses the gate and sampling output of each of the transistors mentioned above. The gates of some transistors can serve as a plate of the capacitor mentioned above.

[0067] For example, the capacitor electrode layer 030 comprises the other plate of each of the capacitors mentioned above. Two plates with opposing faces form one of the capacitors mentioned above.

[0068] For example, the cascade wiring layer 040 includes cascade wiring lines for coupling the input signal terminal IN of the next shift register unit with the cascade output terminal OT of the previous shift register unit.

[0069] For example, the signal transmission wiring layer 050 includes clock signal lines, output control signal lines, and the source and drain electrode of each of the transistors mentioned above.

[0070] For example, the auxiliary wiring layer 060 includes the output control auxiliary signal lines SC-1 and SC-2, as well as other reference signal lines.

[0071] In some embodiments of the present disclosure, as in Fig. As shown in Figure 14, the majority of clock signal lines clk1 and clk2 are arranged on a side of the gate drive circuit, with which they are coupled, facing away from the display area.

[0072] In some embodiments of the present disclosure, as in Fig. As shown in Figure 14, the orthographic projections of the majority of output control signal lines (such as CS-1 and CS-2) on the substrate are located between the orthographic projections of the majority of clock signal lines (such as clk1 and clk2) on the substrate and the display area.

[0073] In some embodiments of the present disclosure, as in Fig. As shown in Figure 14, the orthographic projection of the gate drive circuit 10 on the substrate is located between the orthographic projections of the majority of clock signal lines (e.g., clk1 and clk2) and the orthographic projections of the majority of output control signal lines (e.g., CS-1 and CS-2). The orthographic projections of the majority of output control signal lines (e.g., CS-1 and CS-2) on the substrate are located between the orthographic projection of the gate drive circuit 10 on the substrate and the display area.

[0074] In some embodiments of the present disclosure, as in Fig. As shown in Figure 14, the orthographic projection of the first output transistor on the substrate is located between the orthographic projection of the first cascade transistor on the substrate and the display area.

[0075] In some embodiments of the present disclosure, as in Fig. As shown in Figure 14, the channel width of the first output transistor is larger than the channel width of the first cascade transistor.

[0076] In some embodiments of the present disclosure, the channel width of the first output transistor is at least 100 µm.

[0077] In some embodiments of the present disclosure, the channel width of the first cascade transistor is at most 60 µm.

[0078] In some embodiments of the present disclosure, as in Fig. As shown in Figure 14, the orthographic projection of the second output transistor on the substrate is located between the orthographic projection of the second cascade transistor on the substrate and the display area.

[0079] In some embodiments of the present disclosure, as in Fig. As shown in Figure 14, the channel width of the second output transistor is larger than the channel width of the second cascade transistor.

[0080] In some embodiments of the present disclosure, the channel width of the second output transistor is at least 100 µm.

[0081] In some embodiments of the present disclosure, the channel width of the second cascade transistor is at most 60 µm.

[0082] One embodiment of the present disclosure provides a display device as described in Fig. Figure 4 shows that this includes: the display field described above; a control circuit 11 which is coupled to the display field and is configured to send a first output control signal to the output control signal terminals CS of the majority of shift register units (e.g., SR1, SR2, SR3, SR4, SR5, SR6, SR7 and SR8) in a full-screen control mode. Fig. 4) to enter, thereby assigning the majority of shift register units (e.g., SR1, SR2, SR3, SR4, SR5, SR6, SR7 and SR8) to the Fig. 4) is caused to sequentially output gate sampling signals and thereby control the sampling power line by line; and in a partial drive mode, a second output control signal is sent to the output control signal terminals CS of the majority of shift register units (e.g., SR1, SR2, SR3, SR4, SR5, SR6, SR7 and SR8 in Fig. 4) input a signal such that a portion of the plurality of shift register units sequentially outputs gate sampling signals, while the remaining shift register units of the plurality of shift register units output inactive sampling signals. For example, a second output control signal is input to the output control signal terminals CS of the plurality of shift register units SR1, SR2, SR3, SR4, SR5, SR6, SR7, and SR8, causing shift register units SR1, SR2, SR6, SR7, and SR8 to sequentially output gate sampling signals, while the remaining shift register units SR3, SR4, and SR5 output inactive sampling signals.

[0083] For example, the gate sampling signal is a high-level signal and the inactive sampling signal is a low-level signal. Alternatively, the gate sampling signal is a low-level signal and the inactive sampling signal is a high-level signal, without being limited to these.

[0084] One embodiment of the present disclosure provides a control method as described in Fig. 5 shown, which includes the following: S100: When a full-screen drive mode is used, an initial output control signal is input to the output control signal terminals of a plurality of shift register units, causing these plurality of shift register units to sequentially output gate sampling signals to drive the sampling units line by line; S200: When a partial drive mode is used, a second output control signal is applied to the output control signal terminals of the majority of shift register units, causing some of the shift register units to sequentially output gate sampling signals, while the remaining shift register units output inactive sampling signals to drive some of the sampling power.

[0085] In some embodiments of the present disclosure, as in Fig. As shown in Figure 6, the first output control signal cs1 is a fixed voltage signal with a first level V1. For example, the fixed voltage signal with the first level V1 has a high level or the fixed voltage signal with the first level V1 has a low level, without being limited to this.

[0086] For example, in full-screen control mode, the first output control signal cs1 is fed into the output control signal connections of the majority of shift register units via the first output control signal line CS-1 and the second output control signal line CS-2. Fig. Figure 6 shows a signal timing diagram of the gate sampling signals out1 to out8, which are connected to the sampling powers (e.g., GA1, GA2, GA3, GA4, GA5, GA6, GA7 and GA8) in Fig. 4) be created.

[0087] As in Fig. Figure 6 shows the input signal at input signal terminal IN, ck1 represents the first clock signal at the first clock signal terminal CK1, ck2 represents the second clock signal at the second clock signal terminal CK2, cs1 represents the first output control signal at output control signal terminal CS, ot1 represents the cascade signal at cascade signal terminal OT in the first shift register unit SR1, ot2 represents the cascade signal at cascade signal terminal OT in the second shift register unit SR2, ot3 represents the cascade signal at cascade signal terminal OT in the third shift register unit SR3, ot4 represents the cascade signal at cascade signal terminal OT in the fourth shift register unit SR4, ot5 represents the cascade signal at cascade signal terminal OT in the fifth shift register unit SR5, and ot6 represents the cascade signal at cascade signal terminal OT in the sixth shift register unit SR6.ot7 represents the cascade signal at the cascade signal terminal OT in the seventh shift register unit SR7, ot8 represents the cascade signal at the cascade signal terminal OT in the eighth shift register unit SR8, out1 represents the gate sampling signal at the control output terminal OUT in the first shift register unit SR1, out2 represents the gate sampling signal at the control output terminal OUT in the second shift register unit SR2, out3 represents the gate sampling signal at the control output terminal OUT in the third shift register unit SR3, out4 represents the gate sampling signal at the control output terminal OUT in the fourth shift register unit SR4, out5 represents the gate sampling signal at the control output terminal OUT in the fifth shift register unit SR5, out6 represents the gate sampling signal at the control output terminal OUT in the sixth shift register unit SR6,out7 represents the gate sampling signal at the control output terminal OUT in the seventh shift register unit SR7, and out8 represents the gate sampling signal at the control output terminal OUT in the eighth shift register unit SR8.

[0088] The following describes the operation of the shift register unit in one embodiment of the present disclosure. The structure of the shift register unit is described in Fig. 2 as an example and in combination with the one in Fig. The signal timing diagram shown in section 6 is used.

[0089] As in Fig. Figure 2 illustrates an example where all transistors are P-type transistors, the effective pulse signal of the first reference signal, output from the first reference signal terminal VREF1, is a low-level signal, the effective pulse signal of the second reference signal, output from the second reference signal terminal VREF2, is a low-level signal, the effective pulse signal of the third reference signal, output from the third reference signal terminal VREF3, is a high-level signal, the effective pulse signal of the fourth reference signal, output from the fourth reference signal terminal VREF4, is a high-level signal, the effective pulse signal of the fifth reference signal, output from the fifth reference signal terminal VREF5, is a high-level signal, and the fixed voltage signal with the first level V1 of the first output control signal cs1 is a high-level signal.

[0090] Since the gates of the third transistor M3 and the seventh transistor M7 are both coupled to the second reference voltage terminal VREF2, from which a low-level signal is input, and the gates of the fourteenth transistor M14 and the fifteenth transistor M15 are both coupled to the first reference voltage terminal VREF1, from which a low-level signal is input, the third transistor M3, the seventh transistor M7, the fourteenth transistor M14, and the fifteenth transistor M15 are normally switched on. Since the gate of the thirteenth transistor M13 is coupled to the fifth reference voltage terminal VREF5, from which a high-level signal is input, the thirteenth transistor M13 is normally switched off.For the sake of simplicity, the states of the third transistor M3, the seventh transistor M7, the thirteenth transistor M13, the fourteenth transistor M14 and the fifteenth transistor M15 at any given time will not be analyzed in detail below.

[0091] In the first phase H1, the input signal is high, the first clock signal ck1 is low, and the second clock signal ck2 is high. Then, the first transistor M1 is turned on by the low level of the first clock signal ck1 and outputs the high level of the input signal to the third node N3. The second transistor M2 is turned off by the high level of the third node N3. The twelfth transistor M12 is turned off by the high level of the third node N3. The fifteenth transistor M15 outputs the high level of the third node N3 to the second node N2, and then the second cascade transistor T4 and the second output transistor T2 are turned off. The ninth transistor M9 is turned on by the low level of the first clock signal ck1 and outputs the low level of the second reference signal terminal VREF2 to the fourth node N4.The tenth transistor, M10, is switched on by the low level of the fourth node, N4, and supplies the high level of the third reference signal terminal, VREF3, to the sixth node, N6. The third transistor, M3, supplies the low level of the fourth node, N4, to the gate of the fourth transistor, M4, which then switches on. The fourth transistor, M4, supplies the high level of the second clock signal, ck2, to the first electrode of the fifth transistor, M5. The fifth transistor, M5, is switched off by the high level of the second clock signal, ck2. Then, the first cascade transistor, T3, and the first output transistor, T1, are switched off. The sixth transistor, M6, is switched on by the low level of the first clock signal, ck1. The sixth transistor, M6, and the seventh transistor, M7, supply the high level of the input signal, in, to the fifth node, N5, which in turn switches off the eighth transistor, M8, and the eleventh transistor, M11, by the high level of the fifth node, N5.The cascade signal output from the cascade signal terminal OT remains at a low level, and the gate sampling signal output from the control output terminal OUT remains at a low level.

[0092] In a second phase, H2, the input signal is set to a low level, the first clock signal, ck1, is set to a high level, and the second clock signal, ck2, is set to a low level. Then, the first transistor, M1, is switched off by the high level of the first clock signal, ck1. The third node, N3, remains at a high level, and the second transistor, M2, is switched off by the high level of the third node, N3. The twelfth transistor, M12, is switched off by the high level of the third node, N3. The fifteenth transistor, M15, supplies the high level of the third node, N3, to the second node, N2, thereby switching off the second cascade transistor, T4, and the second output transistor, T2. The ninth transistor, M9, is switched off by the high level of the first clock signal, ck1, thus keeping the fourth node, N4, at a low level.The tenth transistor, M10, is switched on by the low level of the fourth node, N4, and supplies the high level of the third reference signal terminal, VREF3, to the sixth node, N6. The third transistor, M3, supplies the low level of the fourth node, N4, to the gate of the fourth transistor, M4, which then switches on. The fourth transistor, M4, supplies the low level of the second clock signal, ck2, to the first electrode of the fifth transistor, M5. This transistor is switched on by the low level of the second clock signal, ck2, and supplies the low level of its first electrode to the first node, N1. This, in turn, switches on the first cascade transistor, T3, and the first output transistor, T1, via the low level of the first node, N1. The first cascade transistor, T3, supplies the high level of the fourth reference signal terminal, VREF4, to the cascade signal terminal, OT.The first output transistor T1 supplies the high level of the first output control signal cs1 from output control signal terminal CS to the drive output terminal OUT. The sixth transistor M6 is switched off by the high level of the first clock signal ck1, and the fifth node N5 remains high. This causes the eighth transistor M8 and the eleventh transistor M11 to be switched off by the high level of the fifth node N5. The cascade signal output from cascade signal terminal OT remains low, and the gate sample signal output from drive output terminal OUT remains low. The cascade signal output from cascade signal terminal OT is high, and the gate sample signal output from drive output terminal OUT is high.

[0093] In a third phase, H3, the input signal is low, the first clock signal ck1 is low, and the second clock signal ck2 is high. This turns on the first transistor M1 via the low level of the first clock signal ck1, which then outputs the low level of the input signal to the third node N3. The second transistor M2 is turned on via the low level of the third node N3 and outputs the low level of the first clock signal ck1 to the fourth node N4. The twelfth transistor, M12, is turned on via the low level of the third node N3 and outputs the high level of the fourth reference signal terminal VREF4 to the first node N1. The first cascade transistor T3 and the first output transistor T1 are then turned off.The fifteenth transistor, M15, passes the low level of the third node, N3, to the second node, N2, which in turn turns on the second cascade transistor, T4, and the second output transistor, T2. The second cascade transistor, T4, passes the low level of the first reference signal terminal, VREF1, to the cascade signal terminal, OT, and the second output transistor, T2, passes the low level of the first reference signal terminal, VREF1, to the drive output terminal, OUT. The ninth transistor, M9, is turned on by the low level of the first clock signal, ck1, and passes the low level of the second reference signal terminal, VREF2, to the fourth node, N4. The tenth transistor, M10, is turned on by the low level of the fourth node, N4, and passes the high level of the third reference signal terminal, VREF3, to the sixth node, N6.The third transistor, M3, passes the low level from the fourth node, N4, to the gate of the fourth transistor, M4, which is then switched on. The fourth transistor, M4, supplies the high level of the second clock signal, ck2, to the first electrode of the fifth transistor, M5. The fifth transistor, M5, is switched off by the high level of the second clock signal, ck2. This causes the first cascade transistor, T3, and the first output transistor, T1, to switch off by the high level from the first node, N1. The sixth transistor, M6, is switched on by the low level of the first clock signal, ck1. The sixth transistor, M6, and the seventh transistor, M7, supply the low level of the input signal, in, to the fifth node, N5. This causes the eighth transistor, M8, and the eleventh transistor, M11, to switch on by the low level from the fifth node, N5.The eighth transistor, M8, supplies the low level of the fifth node, N5, to the second node, N2, and the eleventh transistor, M11, supplies the high level of the second clock signal, ck2, to the sixth node, N6. The cascade signal output from the cascade signal terminal OT remains at a low level, and the gate sample signal output from the drive output terminal OUT remains at a low level. The cascade signal output from the cascade signal terminal OT is at a low level, and the gate sample signal output from the drive output terminal OUT is at a low level.

[0094] In the following periods, the shift register units repeat the above-mentioned operating process from phases H1 to H3.

[0095] In some embodiments of the present disclosure, as in Fig. As shown in Figure 7, the second output control signal cs2 comprises a fixed voltage signal component with a first level V1 and a fixed voltage signal component with a second level V2. The fixed voltage signal component with the first level V1 is supplied to some of the shift register units, while the fixed voltage signal component with the second level V2 is supplied to the remaining shift register units.

[0096] For example, the fixed voltage signal component with the first level V1 of the second output control signal cs2 is input into the shift register units SR1, SR2, SR6, SR7 and SR8, while the fixed voltage signal component with the second level V2 of the second output control signal cs2 is input into the shift register units SR3, SR4 and SR5.

[0097] For example, in partial control mode, the second output control signal cs2 is fed into the output control signal terminals of the majority of shift register units via the first output control signal line CS-1 and the second output control signal line CS-2. Fig. Figure 7 shows a signal timing diagram of the gate sampling signals out1 to out8, which are connected to the sampling powers (e.g., GA1, GA2, GA3, GA4, GA5, GA6, GA7 and GA8) in Fig. 4) be created.

[0098] As in Fig. Figure 7 represents the input signal at input signal terminal IN, ck1 represents the first clock signal at the first clock signal terminal CK1, ck2 represents the second clock signal at the second clock signal terminal CK2, cs2 represents the second output control signal at output control signal terminal CS, ot1 represents the cascade signal at cascade signal terminal OT in the first shift register unit SR1, ot2 represents the cascade signal at cascade signal terminal OT in the second shift register unit SR2, ot3 represents the cascade signal at cascade signal terminal OT in the third shift register unit SR3, ot4 represents the cascade signal at cascade signal terminal OT in the fourth shift register unit SR4, ot5 represents the cascade signal at cascade signal terminal OT in the fifth shift register unit SR5, and ot6 represents the cascade signal at cascade signal terminal OT in the sixth shift register unit SR6.ot7 represents the cascade signal at the cascade signal connection OT in the seventh shift register unit SR7, ot8 represents the cascade signal at the cascade signal connection OT in the eighth shift register unit SR8, out1 represents the gate sampling signal at the control output connection OUT in the first shift register unit SR1, out2 represents the gate sampling signal at the control output connection OUT in the second shift register unit SR2, out3 represents the gate sampling signal at the control output connection OUT in the third shift register unit SR3, out4 represents the gate sampling signal at the control output connection OUT in the fourth shift register unit SR4, out5 represents the gate sampling signal at the control output connection OUT in the fifth shift register unit SR5, out6 represents the gate sampling signal at the control output connection OUT in the sixth shift register unit SR6,out7 represents the gate sampling signal at the control output terminal OUT in the seventh shift register unit SR7, and out8 represents the gate sampling signal at the control output terminal OUT in the eighth shift register unit SR8.

[0099] The following describes the operation of the shift register unit in the embodiment of the present disclosure. The structure of the shift register unit is described in... Fig. 2 as an example and in combination with the one in Fig. The signal timing diagram shown in section 7 is used.

[0100] As in Fig. Figure 2 illustrates an example where all transistors are P-type transistors, the effective pulse signal of the first reference signal, output from the first reference signal terminal VREF1, is a low-level signal, the effective pulse signal of the second reference signal, output from the second reference signal terminal VREF2, is a low-level signal, the effective pulse signal of the third reference signal, output from the third reference signal terminal VREF3, is a high-level signal, the effective pulse signal of the fourth reference signal, output from the fourth reference signal terminal VREF4, is a high-level signal, the effective pulse signal of the fifth reference signal, output from the fifth reference signal terminal VREF5, is a high-level signal, and the fixed voltage signal component with the first level V1, which the second output control signal cs2 has, is a high-level signal.while the fixed voltage signal component with the second level V2 is a low-level signal.

[0101] Since the gates of the third transistor M3 and the seventh transistor M7 are both coupled to the second reference voltage terminal VREF2, from which a low-level signal is input, and the gates of the fourteenth transistor M14 and the fifteenth transistor M15 are both coupled to the first reference voltage terminal VREF1, from which a low-level signal is input, the third transistor M3, the seventh transistor M7, the fourteenth transistor M14, and the fifteenth transistor M15 are normally switched on. Since the gate of the thirteenth transistor M13 is coupled to the fifth reference voltage terminal VREF5, from which a high-level signal is input, the thirteenth transistor M13 is normally switched off.For the sake of simplicity, the states of the third transistor M3, the seventh transistor M7, the thirteenth transistor M13, the fourteenth transistor M14 and the fifteenth transistor M15 at any given time will not be analyzed in detail below.

[0102] In the first phase H1, the input signal is high, the first clock signal ck1 is low, and the second clock signal ck2 is high. Then, the first transistor M1 is turned on by the low level of the first clock signal ck1 and outputs the high level of the input signal to the third node N3. The second transistor M2 is turned off by the high level of the third node N3. The twelfth transistor M12 is turned off by the high level of the third node N3. The fifteenth transistor M15 outputs the high level of the third node N3 to the second node N2, and then the second cascade transistor T4 and the second output transistor T2 are turned off. The ninth transistor M9 is turned on by the low level of the first clock signal ck1 and outputs the low level of the second reference signal terminal VREF2 to the fourth node N4.The tenth transistor, M10, is switched on by the low level of the fourth node, N4, and supplies the high level of the third reference signal terminal, VREF3, to the sixth node, N6. The third transistor, M3, supplies the low level of the fourth node, N4, to the gate of the fourth transistor, M4, which then switches on. The fourth transistor, M4, supplies the high level of the second clock signal, ck2, to the first electrode of the fifth transistor, M5. The fifth transistor, M5, is switched off by the high level of the second clock signal, ck2. Then, the first cascade transistor, T3, and the first output transistor, T1, are switched off. The sixth transistor, M6, is switched on by the low level of the first clock signal, ck1. The sixth transistor, M6, and the seventh transistor, M7, supply the high level of the input signal, in, to the fifth node, N5, which in turn switches off the eighth transistor, M8, and the eleventh transistor, M11, by the high level of the fifth node, N5.The cascade signal output from the cascade signal terminal OT remains at a low level, and the gate sampling signal output from the control output terminal OUT remains at a low level.

[0103] In a second phase, H2, the input signal is set to a low level, the first clock signal, ck1, is set to a high level, and the second clock signal, ck2, is set to a low level. Then, the first transistor, M1, is switched off by the high level of the first clock signal, ck1. The third node, N3, remains at a high level, and the second transistor, M2, is switched off by the high level of the third node, N3. The twelfth transistor, M12, is switched off by the high level of the third node, N3. The fifteenth transistor, M15, supplies the high level of the third node, N3, to the second node, N2, thereby switching off the second cascade transistor, T4, and the second output transistor, T2. The ninth transistor, M9, is switched off by the high level of the first clock signal, ck1, thus keeping the fourth node, N4, at a low level.The tenth transistor, M10, is switched on by the low level of the fourth node, N4, and supplies the high level of the third reference signal terminal, VREF3, to the sixth node, N6. The third transistor, M3, supplies the low level of the fourth node, N4, to the gate of the fourth transistor, M4, which then switches on. The fourth transistor, M4, supplies the low level of the second clock signal, ck2, to the first electrode of the fifth transistor, M5. This transistor is switched on by the low level of the second clock signal, ck2, and supplies the low level of its first electrode to the first node, N1. This, in turn, switches on the first cascade transistor, T3, and the first output transistor, T1, via the low level of the first node, N1. The first cascade transistor, T3, supplies the high level of the fourth reference signal terminal, VREF4, to the cascade signal terminal, OT.The first output transistor T1 supplies the high level of the first output control signal cs1 from output control signal terminal CS to the drive output terminal OUT. The sixth transistor M6 is switched off by the high level of the first clock signal ck1, and the fifth node N5 remains high. This causes the eighth transistor M8 and the eleventh transistor M11 to be switched off by the high level of the fifth node N5. The cascade signal output from cascade signal terminal OT remains low, and the gate sample signal output from drive output terminal OUT remains low. The cascade signal output from cascade signal terminal OT is high, and the gate sample signal output from drive output terminal OUT is high.

[0104] In a third phase, H3, the input signal is low, the first clock signal ck1 is low, and the second clock signal ck2 is high. This turns on the first transistor M1 via the low level of the first clock signal ck1, which then outputs the low level of the input signal to the third node N3. The second transistor M2 is turned on via the low level of the third node N3 and outputs the low level of the first clock signal ck1 to the fourth node N4. The twelfth transistor, M12, is turned on via the low level of the third node N3 and outputs the high level of the fourth reference signal terminal VREF4 to the first node N1. The first cascade transistor T3 and the first output transistor T1 are then turned off.The fifteenth transistor, M15, passes the low level of the third node, N3, to the second node, N2, which in turn turns on the second cascade transistor, T4, and the second output transistor, T2. The second cascade transistor, T4, passes the low level of the first reference signal terminal, VREF1, to the cascade signal terminal, OT, and the second output transistor, T2, passes the low level of the first reference signal terminal, VREF1, to the drive output terminal, OUT. The ninth transistor, M9, is turned on by the low level of the first clock signal, ck1, and passes the low level of the second reference signal terminal, VREF2, to the fourth node, N4. The tenth transistor, M10, is turned on by the low level of the fourth node, N4, and passes the high level of the third reference signal terminal, VREF3, to the sixth node, N6.The third transistor, M3, passes the low level from the fourth node, N4, to the gate of the fourth transistor, M4, which is then switched on. The fourth transistor, M4, supplies the high level of the second clock signal, ck2, to the first electrode of the fifth transistor, M5. The fifth transistor, M5, is switched off by the high level of the second clock signal, ck2. This causes the first cascade transistor, T3, and the first output transistor, T1, to switch off by the high level from the first node, N1. The sixth transistor, M6, is switched on by the low level of the first clock signal, ck1. The sixth transistor, M6, and the seventh transistor, M7, supply the low level of the input signal, in, to the fifth node, N5. This causes the eighth transistor, M8, and the eleventh transistor, M11, to switch on by the low level from the fifth node, N5.The eighth transistor, M8, supplies the low level of the fifth node, N5, to the second node, N2, and the eleventh transistor, M11, supplies the high level of the second clock signal, ck2, to the sixth node, N6. The cascade signal output from the cascade signal terminal OT remains at a low level, and the gate sample signal output from the drive output terminal OUT remains at a low level. The cascade signal output from the cascade signal terminal OT is at a low level, and the gate sample signal output from the drive output terminal OUT is at a low level.

[0105] In the following periods, the shift register unit repeats the operating process described above from phases H1 to H3.

[0106] In the disclosed embodiment, controlling the signal at the output control signal terminal controls the gate sampling signal at the drive output terminal in the output circuit. This enables and prevents the scanning of any area of ​​the display field. This saves power and reduces losses.

[0107] The disclosed embodiment also provides a schematic representation of a further structure of the shift register unit, as shown in Fig. Figure 8 shows a modification of the implementation of the embodiment described above. Only the differences between this embodiment and the embodiment described above are described below; the essential similarities are not discussed in detail here.

[0108] In further embodiments of the present disclosure, as in Fig. As shown in Figure 8, the input circuit 110 comprises a sixteenth transistor M16 and a seventeenth transistor M17. A gate of the sixteenth transistor M16 is coupled to the first clock signal terminal CK1, a first electrode of the sixteenth transistor M16 is coupled to the input signal terminal IN, and a second electrode of the sixteenth transistor M16 is coupled to a seventh node N7. A gate of the seventeenth transistor M17 is coupled to the first clock signal terminal CK1, a first electrode of the seventeenth transistor M17 is coupled to the seventh node N7, and a second electrode of the seventeenth transistor M17 is coupled to the third node N3.

[0109] In further embodiments of the present disclosure, as in Fig. As shown in Figure 8, the control circuit 120 comprises an eighteenth transistor M18, a nineteenth transistor M19, a twentieth transistor M20, a twenty-first transistor M21, a twenty-second transistor M22, a twenty-third transistor M23, a fifth capacitor C5, and a sixth capacitor C6. One gate of the eighteenth transistor M18 is coupled to the cascade output terminal OT, one electrode of the eighteenth transistor M18 is coupled to the third clock signal terminal CK3, and one electrode of the eighteenth transistor M18 is coupled to the seventh node N7. One gate of the nineteenth transistor M19 is coupled to the input signal terminal IN, one electrode of the nineteenth transistor M19 is coupled to the first reference signal terminal VREF 1, and one electrode of the nineteenth transistor M19 is coupled to the second node N2.A gate of the twentieth transistor M20 is coupled to the second node N2, a first electrode of the twentieth transistor M20 is coupled to the first reference signal terminal VREF1, and a second electrode of the twentieth transistor M20 is coupled to the eighth node N8. A gate of the twenty-first transistor M21 is coupled to the second node N2, a first electrode of the twenty-first transistor M21 is coupled to the eighth node N8, and a second electrode of the twenty-first transistor M21 is coupled to the third node N3. A gate of the twenty-second transistor M22 is coupled to the third node N3, a first electrode of the twenty-second transistor M22 is coupled to the eighth node N8, and a second electrode of the twenty-second transistor M22 is coupled to the sixth reference signal terminal VREF6.A gate of the twenty-third transistor M23 is connected to the fourth clock signal terminal CK4, a first electrode of the twenty-third transistor M23 to the second node N2, and a second electrode of the twenty-third transistor M23 to the sixth reference signal terminal VREF6. A first electrode of the fifth capacitor C5 is connected to the first reference signal terminal VREF1, and a second electrode of the fifth capacitor C5 is connected to the first electrode of the twenty-third transistor M23. A first electrode of the sixth capacitor C6 is connected to the cascade output terminal OT, and a second electrode of the sixth capacitor C6 is connected to the first node N1.

[0110] In further embodiments of the present disclosure, as in Fig. As shown in Figure 8, the cascade sub-circuit 130 comprises a first cascade transistor T3 and a second cascade transistor T4. A gate of the first cascade transistor T3 is connected to the first node N1, a first electrode of the first cascade transistor T3 to the cascade output terminal OT, and a second electrode of the first cascade transistor T3 to the third clock signal terminal CK3. A gate of the second cascade transistor T4 is connected to the second node N2, a first electrode of the second cascade transistor T4 to the first reference signal terminal VREF1, and a second electrode of the second cascade transistor T4 to the cascade output terminal OT.

[0111] In further embodiments of the present disclosure, as in Fig. Figure 9 shows the first output control signals CS-1 and CS-2 as clock signals.

[0112] For example, in full-screen control mode, the first output control signals CS-1 and CS-2 are fed into the output control signal connections of the majority of shift register units via the first output control signal line CS-1 and the second output control signal line CS-2, respectively. Fig. Figure 9 shows a signal timing diagram of the gate sampling signals out1 to out8, which correspond to sampling powers (e.g., GA1, GA2, GA3, GA4, GA5, GA6, GA7 and GA8) in Fig. 4) be applied.

[0113] As in Fig. Figure 9 represents the input signal at input signal terminal IN, ck1 represents the first clock signal at the first clock signal terminal CK1, ck3 represents the third clock signal at the third clock signal terminal CK3, ck4 represents the fourth clock signal at the fourth clock signal terminal CK4, cs-1 represents the first output control signal on the first output control signal line CS-1, cs-2 represents the first output control signal on the second output control signal line CS-2, out1 represents the gate sampling signal at the control output terminal OUT in the first shift register unit SR1, out2 represents the gate sampling signal at the control output terminal OUT in the second shift register unit SR2, out3 represents the gate sampling signal at the control output terminal OUT in the third shift register unit SR3, out4 represents the gate sampling signal at the control output terminal OUT in the fourth shift register unit SR4,out5 represents the gate sampling signal at the control output OUT in the fifth shift register unit SR5, out6 represents the gate sampling signal at the driver output OUT in the sixth shift register unit SR6, out7 represents the gate sampling signal at the control output OUT in the seventh shift register unit SR7, and out8 represents the gate sampling signal at the control output OUT in the eighth shift register unit SR8.

[0114] The following describes the functioning of the shift register unit in the embodiment of the present disclosure using the example of the one in Fig. 8 structure of the shift register unit shown and in combination with the in Fig. The signal timing diagram shown in section 9 is described.

[0115] As in Fig. Figure 8 illustrates an example in which all transistors are P-type transistors, the effective pulse signal of the first reference signal output from the first reference signal terminal VREF1 is a high-level signal, and the effective pulse signal of the sixth reference signal output from the sixth reference signal terminal VREF6 is a low-level signal.

[0116] In the first phase H1, the input signal is low, the first clock signal ck1 is low, the third clock signal ck3 is high, the fourth clock signal ck4 is high, the first output control signal cs-1 on the first output control signal line CS-1 is low, and the first output control signal cs-2 on the second output control signal line CS-2 is high. The sixteenth transistor M16 is switched on by the low level of the first clock signal ck1 and supplies the low level of the input signal to the seventh node N7. The seventeenth transistor M17 is switched on by the low level of the first clock signal ck1 and supplies the low level of the seventh node N7 to the third node N3 and the first node N1.The twenty-second transistor, M22, is switched on by the low level of the third node, N3, and supplies the low level of the sixth reference signal terminal, VREF6, to the eighth node, N8. The nineteenth transistor, M19, is switched on by the low level of the input signal and supplies the high level of the first reference signal terminal, VREF1, to the second node, N2. The twentieth transistor, M20, is switched off by the high level of the second node, N2. The twenty-first transistor, M21, is switched off by the high level of the second node, N2. The twenty-third transistor, M23, is switched off by the high level of the fourth clock signal, ck4. The second cascade transistor, T4, and the second output transistor, T2, are switched off by the high level of the second node, N2. The first cascade transistor, T3, and the first output transistor, T1, are switched on by the low level of the first node, N1.The first cascade transistor T3 supplies the high level of the third clock signal ck3 to the cascade signal terminal OT, and the first output transistor T1 supplies the high-level signal from the output control signal terminal CS to the drive output terminal OUT. The eighteenth transistor M18 is switched off by the high level of the cascade signal. The cascade signal output at the cascade signal terminal OT is then high, and the gate sampling signal output at the drive output terminal OUT is high.

[0117] In a second phase H2, the input signal is high, the first clock signal ck1 is high, the third clock signal ck3 is low, the fourth clock signal ck4 is high, the first output control signal cs-1 on the first output control signal line CS-1 is high, and the first output control signal cs-2 on the second output control signal line CS-2 is low. The sixteenth transistor M16 is switched off by the high level of the first clock signal ck1, and the seventh node N7 remains low. The seventeenth transistor M17 is switched off by the high level of the first clock signal ck1, and the third node N3 and the first node N1 remain low. The twenty-second transistor M22 is switched on by the low level of the third node N3 and supplies the low level of the sixth reference signal terminal VREF6 to the eighth node N8.The nineteenth transistor, M19, is switched off by the high level of the input signal, and the second node, N2, remains high. The twentieth transistor, M20, is switched off by the high level of the second node, N2. The twenty-first transistor, M21, is switched off by the high level of the second node, N2. The twenty-third transistor, M23, is switched off by the high level of the fourth clock signal, ck4. The second cascade transistor, T4, and the second output transistor, T2, are switched off by the high level of the second node, N2. The first cascade transistor, T3, and the first output transistor, T1, are switched on by the low level of the first node, N1. The first cascade transistor, T3, outputs the low level of the third clock signal, ck3, to the cascade signal terminal, OT, and the first output transistor, T1, outputs the low-level signal at the output control signal terminal, CS, to the drive output terminal, OUT.The eighteenth transistor M18 is switched on by the low level of the cascade signal and supplies the low level of the third clock signal ck3 to the seventh node N7. Then the cascade signal at the cascade signal terminal OT is low, and the gate sampling signal at the drive output terminal OUT is low.

[0118] In a third phase, H3, the input signal is high, the first clock signal ck1 is high, the third clock signal ck3 is high, the fourth clock signal ck4 is low, the first output control signal cs-1 on the first output control signal line CS-1 is low, and the first output control signal cs-2 on the second output control signal line CS-2 is high. The sixteenth transistor M16 is switched off by the high level of the first clock signal ck1, and the seventh node N7 remains low. The seventeenth transistor M17 is switched off by the high level of the first clock signal ck1, and the third node N3 and the first node N1 remain low. The twenty-second transistor M22 is switched on by the low level of the third node N3 and supplies the low level of the sixth reference signal terminal VREF6 to the eighth node N8.The nineteenth transistor M19 is switched off by the high level of the input signal, and the second node N2 remains at a high level. The twentieth transistor M20 is switched off by the high level of the second node N2. The twenty-first transistor M21 is switched off by the high level of the second node N2. The twenty-third transistor M23 is switched on by the low level of the fourth clock signal ck4. The second cascade transistor T4 and the second output transistor T2 are switched on by the low level of the second node N2. The second cascade transistor T4 supplies the high level of the first reference signal terminal VREF1 to the cascade signal terminal OT, and the second output transistor T2 supplies the high level of the first reference signal terminal VREF1 to the drive output terminal OUT. The first cascade transistor T3 and the first output transistor T1 are switched on by the low level of the first node N1.The first cascade transistor T3 supplies the high level of the third clock signal ck3 to the cascade signal terminal OT, and the first output transistor T1 supplies the high-level signal from the output control signal terminal CS to the drive output terminal OUT. The eighteenth transistor M18 is switched off by the high level of the cascade signal. The cascade signal output at the cascade signal terminal OT is high, and the gate sampling signal output at the drive output terminal OUT is high.

[0119] In the following periods, the shift register unit repeats the operating process of the phases H1 to H3 described above.

[0120] In further embodiments of the present disclosure, as in Fig. As shown in Figure 10, the second output control signals cs-1' and cs-2' comprise a clock signal component and a fixed voltage signal component with a first level V1. The clock signal component of the second output control signals cs-1' and cs-2' is fed into some of the shift register units, while the fixed voltage signal component with the first level V1 is fed into the remaining shift register units. For example, the clock signal component of the second output control signals cs-1' and cs-2' is fed into shift register units SR1, SR2, SR6, SR7, and SR8, while the fixed voltage signal component with the first level V1 is fed into shift register units SR3, SR4, and SR5.

[0121] For example, in partial control mode, the second output control signals cs-1' and cs-2' are fed into the output control signal connections of the majority of shift register units via the first output control signal line CS-1 and the second output control signal line CS-2, respectively. Fig. Figure 10 shows a signal timing diagram of the gate sampling signals out1 to out8, which correspond to the sampling powers (e.g., GA1, GA2, GA3, GA4, GA5, GA6, GA7 and GA8) in Fig. 4) be applied.

[0122] As in Fig. Figure 10 represents the input signal at input signal terminal IN, ck1 represents the first clock signal at the first clock signal terminal CK1, ck3 represents the third clock signal at the third clock signal terminal CK3, ck4 represents the fourth clock signal at the fourth clock signal terminal CK4, cs-1' represents the second output control signal on the first output control signal line CS-1, cs-2' represents the second output control signal on the second output control signal line CS-2, out1 represents the gate sampling signal at the control output terminal OUT in the first shift register unit SR1, and out2 represents the gate sampling signal at the control output terminal OUT in the second shift register unit SR2, out3 represents the gate sampling signal at the control output terminal OUT in the third shift register unit SR3, and out4 represents the gate sampling signal at the control output terminal OUT in the fourth shift register unit SR4.out5 represents the gate sampling signal at the control output OUT of the fifth shift register unit SR5, out6 represents the gate sampling signal at the control output OUT of the sixth shift register unit SR6, out7 represents the gate sampling signal at the control output OUT of the seventh shift register unit SR7, and out8 represents the gate sampling signal at the control output OUT of the eighth shift register unit SR8.

[0123] The following describes the functioning of the shift register unit in the embodiment of the present disclosure using the example of the one in Fig. 8 structure of the shift register unit shown and in combination with the in Fig. The signal timing diagram shown in 10 is described.

[0124] As in Fig. Figure 8 illustrates an example where all transistors are P-type transistors, the effective pulse signal of the first reference signal output from the first reference signal terminal VREF1 is a high-level signal, and the effective pulse signal of the sixth reference signal output from the sixth reference signal terminal VREF6 is a low-level signal.

[0125] In the first phase H1, the input signal is low, the first clock signal ck1 is low, the third clock signal ck3 is high, the fourth clock signal ck4 is high, the second output control signal cs-1' on the first output control signal line CS-1 is low, and the second output control signal cs-2' on the second output control signal line CS-2 is high. The sixteenth transistor M16 is switched on by the low level of the first clock signal ck1 and supplies the low level of the input signal to the seventh node N7. The seventeenth transistor M17 is switched on by the low level of the first clock signal ck1 and supplies the low level of the seventh node N7 to the third node N3 and the first node N1.The twenty-second transistor, M22, is switched on by the low level of the third node, N3, and supplies the low level of the sixth reference signal terminal, VREF6, to the eighth node, N8. The nineteenth transistor, M19, is switched on by the low level of the input signal and supplies the high level of the first reference signal terminal, VREF1, to the second node, N2. The twentieth transistor, M20, is switched off by the high level of the second node, N2. The twenty-first transistor, M21, is switched off by the high level of the second node, N2. The twenty-third transistor, M23, is switched off by the high level of the fourth clock signal, ck4. The second cascade transistor, T4, and the second output transistor, T2, are switched off by the high level of the second node, N2. The first cascade transistor, T3, and the first output transistor, T1, are switched on by the low level of the first node, N1.The first cascade transistor T3 supplies the high level of the third clock signal ck3 to the cascade signal terminal OT, and the first output transistor T1 supplies the high signal at the output control signal terminal CS to the drive output terminal OUT. The eighteenth transistor M18 is switched off by the high level of the cascade signal. Then the cascade signal at the cascade signal terminal OT is high, and the gate sampling signal at the drive output terminal OUT is also high.

[0126] In a second phase H2, the input signal is set to a high level, the first clock signal ck1 is set to a high level, the third clock signal ck3 is set to a low level, the fourth clock signal ck4 is set to a high level, the second output control signal cs-1' is set to a high level on the first output control signal line CS-1, and the second output control signal cs-2' is set to a low level on the second output control signal line CS-2. The sixteenth transistor M16 is switched off by the high level of the first clock signal ck1, and the seventh node N7 remains at a low level. The seventeenth transistor M17 is switched off by the high level of the first clock signal ck1, and the third node N3 and the first node N1 remain at a low level. The twenty-second transistor M22 is switched on by the low level of the third node N3 and supplies the low level of the sixth reference signal terminal VREF6 to the eighth node N8.The nineteenth transistor, M19, is switched off by the high level of the input signal, and the second node, N2, remains high. The twentieth transistor, M20, is switched off by the high level of the second node, N2. The twenty-first transistor, M21, is switched off by the high level of the second node, N2. The twenty-third transistor, M23, is switched off by the high level of the fourth clock signal, ck4. The second cascade transistor, T4, and the second output transistor, T2, are switched off by the high level of the second node, N2. The first cascade transistor, T3, and the first output transistor, T1, are switched on by the low level of the first node, N1. The first cascade transistor, T3, outputs the low level of the third clock signal, ck3, to the cascade signal terminal, OT, and the first output transistor, T1, outputs the low-level signal at the output control signal terminal, CS, to the drive output terminal, OUT.The eighteenth transistor M18 is switched on by the low level of the cascade signal and outputs the low level of the third clock signal ck3 to the seventh node N7. The cascade signal output from the cascade signal terminal OT is then low, and the gate sampling signal output from the drive output terminal OUT is low.

[0127] In a third phase H3, the input signal is set to a high level, the first clock signal ck1 is set to a high level, the third clock signal ck3 is set to a high level, the fourth clock signal ck4 is set to a low level, the second output control signal cs-1' is set to a low level on the first output control signal line CS-1, and the second output control signal cs-2' is set to a high level on the second output control signal line CS-2. The sixteenth transistor M16 is switched off by the high level of the first clock signal ck1, and the seventh node N7 remains at a low level. The seventeenth transistor M17 is switched off by the high level of the first clock signal ck1, and the third node N3 and the first node N1 remain at low levels. The twenty-second transistor M22 is switched on by the low level of the third node N3 and supplies the low level of the sixth reference signal terminal VREF6 to the eighth node N8.The nineteenth transistor M19 is switched off by the high level of the input signal, and the second node N2 remains at a high level. The twentieth transistor M20 is switched off by the high level of the second node N2. The twenty-first transistor M21 is switched off by the high level of the second node N2. The twenty-third transistor M23 is switched on by the low level of the fourth clock signal ck4. The second cascade transistor T4 and the second output transistor T2 are switched on by the low level of the second node N2. The second cascade transistor T4 supplies the high level of the first reference signal terminal VREF1 to the cascade signal terminal OT, and the second output transistor T2 supplies the high level of the first reference signal terminal VREF1 to the drive output terminal OUT. The first cascade transistor T3 and the first output transistor T1 are switched on by the low level of the first node N1.The first cascade transistor T3 supplies the high level of the third clock signal ck3 to the cascade signal terminal OT, and the first output transistor T1 supplies the high-level signal at the output control signal terminal CS to the drive output terminal OUT. The eighteenth transistor M18 is switched off by the high level of the cascade signal. Then the cascade signal at the cascade signal terminal OT is high, and the gate sampling signal at the drive output terminal OUT is high.

[0128] In the following periods, the shift register unit repeats the operating process of the phases H1 to H3 described above.

[0129] In embodiments of the present disclosure, the gate sampling signal at the drive output terminal is controlled in the output circuit by controlling the signal at the output control signal terminal. This controls or prevents the sampling of arbitrary areas of the display field, thereby saving power and reducing losses.

[0130] In embodiments of the present disclosure, a schematic representation of a further structure of a shift register unit is shown, as depicted in FIG., which represents a modification of the implementation of the embodiment mentioned above. Only the differences between this and the embodiment mentioned above are described below; the similarities are not discussed in detail.

[0131] In further embodiments of the present disclosure, as in Fig. As shown in Figure 11, the first output circuit 210 is coupled to the cascade output terminal OT of the shift register 100 and is configured to transmit a signal from the output control signal terminal CS to the control output terminal OUT in response to a signal at the cascade output terminal OT.

[0132] In further embodiments of the present disclosure, as in Fig. As shown in Figure 11, the gate of the first output transistor T1 is coupled to the cascade output terminal OT, the first electrode of the first output transistor T1 is coupled to the output control signal terminal CS, and the second electrode of the first output transistor T1 is coupled to the control output terminal OUT.

[0133] In further embodiments of the present disclosure, as in Fig. As shown in Figure 11, the control circuit comprises a twenty-fourth transistor M24, a twenty-fifth transistor M25, a twenty-sixth transistor M26, a twenty-seventh transistor M27, a twenty-eighth transistor M28, a seventh capacitor C7, and an eighth capacitor C8. One gate of the twenty-fourth transistor M24 is coupled to the first clock signal terminal CK1, one electrode of the twenty-fourth transistor M24 is coupled to the seventh reference signal terminal VREF7, and one electrode of the twenty-fourth transistor M24 is coupled to the second node N2. One gate of the twenty-fifth transistor M25 is coupled to the third node N3, one electrode of the twenty-fifth transistor M25 is coupled to the second node N2, and one electrode of the twenty-fifth transistor M25 is coupled to the first clock signal terminal CK1.A gate of the twenty-sixth transistor M26 is coupled to the second node N2, a first electrode of transistor M26 is coupled to the first reference signal terminal VREF1, a second electrode of the twenty-sixth transistor M26 is coupled to a first electrode of the twenty-seventh transistor M27. A gate of the twenty-seventh transistor M27 is coupled to the third clock signal terminal CK3, and a second electrode of the twenty-seventh transistor M27 is coupled to a first electrode of the twenty-eighth transistor M28. A gate of the twenty-eighth transistor M28 is coupled to the seventh reference signal terminal VREF7, the first electrode of the twenty-eighth transistor M28 is coupled to the third node N3, and a second electrode of the twenty-eighth transistor M28 is coupled to the first node N1.A first electrode of the seventh capacitor C7 is coupled to the first reference signal terminal VREF1, and a second electrode of the seventh capacitor C7 is coupled to the first node N1. A first electrode of the eighth capacitor C8 is coupled to the cascade output terminal OT, and a second electrode of the eighth capacitor C8 is coupled to the first node N1.

[0134] In further embodiments of the present disclosure, as in Fig. As shown in Figure 12, the first output control signals cs-1 and cs-2 are clock signals.

[0135] For example, in full-screen control mode, the first output control signals CS-1 and CS-2 are fed into the output control signal connections of the majority of shift register units via the first and second output control signal lines CS-1 and CS-2, respectively. A timing diagram of the gate sampling signals out1 to out8, which are connected to the sampling powers (e.g., GA1, GA2, GA3, GA4, GA5, GA6, GA7, and GA8) in Fig. 4) are created, is in Fig. 12 shown.

[0136] As shown in FIG., in represents the input signal at the input signal terminal IN, ck1 represents the first clock signal at the first clock signal terminal CK1, ck3 represents the third clock signal at the third clock signal terminal CK3, cs-1 represents the first output control signal on the first output control signal line CS-1, cs-2 represents the first output control signal on the second output control signal line CS-2, out1 represents the gate sample signal at the control output terminal OUT in the first shift register unit SR1, out2 represents the gate sample signal at the control output terminal OUT in the second shift register unit SR2, out3 represents the gate sample signal at the control output terminal OUT in the third shift register unit SR3, out4 represents the gate sample signal at the control output terminal OUT in the fourth shift register unit SR4, and out5 represents the gate sample signal at the control output terminal OUT in the fifth shift register unit SR5.out6 represents the gate sampling signal at the control output terminal OUT in the sixth shift register unit SR6, out7 represents the gate sampling signal at the control output terminal OUT of the seventh shift register unit SR7, and out8 represents the gate sampling signal at the control output terminal OUT of the eighth shift register unit SR8.

[0137] The following describes the functioning of the shift register unit in the embodiment of the present disclosure using the example of the one in Fig. 11 structure shown in connection with the one in Fig. The signal timing diagram shown in section 12 is described.

[0138] As in Fig. Figure 11 illustrates an example where all transistors are P-type transistors, the effective pulse signal of the first reference signal output from the first reference signal terminal VREF1 is a high-level signal, and the effective pulse signal of the sixth reference signal output from the seventh reference signal terminal VREF7 is a low-level signal.

[0139] Since the twenty-eighth transistor M28 is coupled to the seventh reference signal terminal VREF7 and receives a low-level signal from it, the twenty-eighth transistor M28 is normally conducting. For the sake of simplicity, the state of the twenty-eighth transistor M28 at any given time will not be discussed further.

[0140] In the first phase H1, the input signal is low, the first clock signal ck1 is low, the third clock signal ck3 is high, the first output control signal cs-1 is low on the first output control signal line CS-1, and the first output control signal cs-2 is high on the second output control signal line CS-2. The first transistor M1 is switched on by the low level of the first clock signal ck1 and supplies the low level of the input signal to the third node N3. The twenty-eighth transistor M28 supplies the low level of the third node N3 to the first node N1. The first cascade transistor T3 and the first output transistor T1 are switched on by the low level of the first node N1.The first cascade transistor T3 supplies the high level of the third clock signal ck3 to the cascade signal terminal OT, and the first output transistor T1 supplies the high-level signal at the output control signal terminal CS to the drive output terminal OUT. The twenty-fifth transistor M25 is switched on by the low level of the third node N3 and supplies the low level of the first clock signal ck1 to the second node N2. The twenty-fourth transistor M24 is switched on by the low level of the first clock signal ck1 and supplies the low level of the seventh reference signal terminal VREF7 to the second node N2. The twenty-sixth transistor M26 is switched on by the low level of the second node N2 and supplies the high level of the first reference signal terminal VREF1 to the first electrode of the twenty-seventh transistor M27. The twenty-seventh transistor M27 is switched off by the high level of the third clock signal ck3.The second cascade transistor T4 and the second output transistor T2 are switched on by the low level of the second node N2. The second cascade transistor T4 supplies the high level of the first reference signal terminal VREF1 to the cascade signal terminal OT, and the second output transistor T2 supplies the high level of the first reference signal terminal VREF1 to the drive output terminal OUT. Then the cascade signal from the cascade signal terminal OT is high, and the gate sampling signal from the drive output terminal OUT is high.

[0141] In a second phase H1, the input signal is set to a high level, the first clock signal ck1 is set to a high level, the third clock signal ck3 is set to a low level, the first output control signal cs-1 is set to a high level on the first output control signal line CS-1, and the first output control signal cs-2 is set to a low level on the second output control signal line CS-2. The first transistor M1 is switched off by the high level of the first clock signal ck1, and the third node N3 remains at a low level. The twenty-eighth transistor M28 supplies the low level of the third node N3 to the first node N1. The first cascade transistor T3 and the first output transistor T1 are switched off by the high level of the first node N1.The first cascade transistor, T3, supplies the low level of the third clock signal, ck3, to the cascade signal terminal OT, and the first output transistor, T1, supplies the low-level signal at the output control signal terminal CS to the drive output terminal OUT. The twenty-fourth transistor, M24, is turned off by the high level of the first clock signal, ck1, and the second node, N2, remains low. The twenty-fifth transistor, M25, is turned on by the low level of the third node, N3, and supplies the high level of the first clock signal, ck1, to the second node, N2. The second node, N2, is high. The twenty-sixth transistor, M26, is turned off by the high level of the second node, N2, and the twenty-seventh transistor, M27, is turned on by the low level of the third clock signal, ck3. The second cascade transistor T4 and the second output transistor T2 are switched off by the high level of the second node N2.Then the cascade signal output from the cascade signal terminal OT is at a low level, and the gate sampling signal output from the control output terminal OUT is at a low level.

[0142] In a third phase H1, the input signal is high, the first clock signal ck1 is low, the third clock signal ck3 is high, the first output control signal cs-1 is low on the first output control signal line CS-1, and the first output control signal cs-2 is high on the second output control signal line CS-2. The first transistor M1 is switched on by the low level of the first clock signal ck1 and supplies the high level of the input signal to the third node N3. The twenty-eighth transistor M28 supplies the high level of the third node N3 to the first node N1. The first cascade transistor T3 and the first output transistor T1 are switched off by the high level of the first node N1. The twenty-fifth transistor M25 is switched off by the high level of the third node N3.The twenty-fourth transistor, M24, is switched on by the low level of the first clock signal, ck1, and supplies the low level of the seventh reference signal terminal, VREF7, to the second node, N2. The twenty-sixth transistor, M26, is switched on by the low level of the second node, N2. The twenty-sixth transistor, M26, supplies the high level of the first reference signal terminal, VREF1, to the first electrode of the twenty-seventh transistor, M27. The twenty-seventh transistor, M27, is switched off by the high level of the third clock signal, ck3. The second cascade transistor, T4, and the second output transistor, T2, are switched on by the low level of the second node, N2. The second cascade transistor, T4, supplies the high level of the first reference signal terminal, VREF1, to the cascade signal terminal, OT. The second output transistor, T2, supplies the high level of the first reference signal terminal, VREF1, to the drive output terminal, OUT.Then the cascade signal at the cascade signal terminal OT is at a high level, and the gate sampling signal at the control output terminal OUT is also at a high level.

[0143] In the following periods, the shift register unit repeats the operating process described above for phases H1 to H3.

[0144] In further embodiments of the present disclosure, as in Fig. As shown in Figure 13, the second output control signals cs-1' and cs-2' comprise a clock signal component and a fixed voltage signal component with a first level V1. The clock signal component of the second output control signals cs-1' and cs-2' is fed to some of the shift register units, while the fixed voltage signal component with the first level V1 is fed to the remaining shift register units. For example, the clock signal component of the second output control signals cs-1' and cs-2' is fed to shift register units SR1, SR2, SR6, SR7, and SR8, while the fixed voltage signal component with the first level V1 is fed to shift register units SR3, SR4, and SR5.

[0145] In the following periods, the shift register units repeat the above-mentioned operating process of periods H1 to H3.

[0146] For example, in partial drive mode, the second output control signals cs-1' and cs-2' are fed into the output control signal connections of the majority of shift register units via the first output control signal line CS-1 and the second output control signal line CS-2, respectively. A timing diagram of the gate sampling signals out1 to out8, which are fed to the sampling lines (e.g., GA1, GA2, GA3, GA4, GA5, GA6, GA7, and GA8) in Fig. 4) are applied, is in Fig. 13 shown.

[0147] As shown in FIG. As shown, represents the input signal at input signal terminal IN, ck1 represents the first clock signal at the first clock signal terminal CK1, ck3 represents the third clock signal at the third clock signal terminal CK3, cs-1' represents the second output control signal on the first output control signal line CS-1, cs-2' represents the second output control signal on the second output control signal line CS-2, out1 represents the gate sampling signal at the control output terminal OUT in the first shift register unit SR1, out2 represents the gate sampling signal at the control output terminal OUT in the second shift register unit SR2, out3 represents the gate sampling signal at the control output terminal OUT in the third shift register unit SR3, out4 represents the gate sampling signal at the control output terminal OUT in the fourth shift register unit SR4, out5 represents the gate sampling signal at the control output terminal OUT in the fifth shift register unit SR5,out6 represents the gate sampling signal at the control output terminal OUT in the sixth shift register unit SR6, out7 represents the gate sampling signal at the control output terminal OUT in the seventh shift register unit SR7, and out8 represents the gate sampling signal at the control output terminal OUT in the eighth shift register unit SR8.

[0148] The following describes the operation of the shift register unit in the embodiment of the present disclosure. The structure of the shift register unit is described in Fig. 11. For example, in conjunction with the signal timing diagram in Fig. 13 used.

[0149] As in Fig.Figure 11 illustrates an example where all transistors are P-type transistors, the effective pulse signal of the first reference signal output from the first reference signal terminal VREF1 is a high-level signal, and the effective pulse signal of the sixth reference signal output from the seventh reference signal terminal VREF7 is a low-level signal.

[0150] Since the twenty-eighth transistor M28 is coupled to the seventh reference signal terminal VREF7 and receives a low-level signal from it, the twenty-eighth transistor M28 is normally switched on. For the sake of simplicity, the state of the twenty-eighth transistor M28 at any given time will not be described in detail below.

[0151] In the first phase H1, the input signal is low, the first clock signal ck1 is low, the third clock signal ck3 is high, the first output control signal cs-1 is low on the first output control signal line CS-1, and the first output control signal cs-2 is high on the second output control signal line CS-2. The first transistor M1 is switched on by the low level of the first clock signal ck1 and supplies the low level of the input signal to the third node N3. The twenty-eighth transistor M28 supplies the low level of the third node N3 to the first node N1. The first cascade transistor T3 and the first output transistor T1 are switched on by the low level of the first node N1.The first cascade transistor T3 supplies the high level of the third clock signal ck3 to the cascade signal terminal OT, and the first output transistor T1 supplies the high-level signal at the output control signal terminal CS to the drive output terminal OUT. The twenty-fifth transistor M25 is switched on by the low level of the third node N3 and supplies the low level of the first clock signal ck1 to the second node N2. The twenty-fourth transistor M24 is switched on by the low level of the first clock signal ck1 and supplies the low level of the seventh reference signal terminal VREF7 to the second node N2. The twenty-sixth transistor M26 is switched on by the low level of the second node N2 and supplies the high level of the first reference signal terminal VREF1 to the first electrode of the twenty-seventh transistor M27. The twenty-seventh transistor M27 is switched off by the high level of the third clock signal ck3.The second cascade transistor T4 and the second output transistor T2 are switched on by the low level of the second node N2. The second cascade transistor T4 supplies the high level of the first reference signal terminal VREF1 to the cascade signal terminal OT, and the second output transistor T2 supplies the high level of the first reference signal terminal VREF1 to the drive output terminal OUT. Then the cascade signal from the cascade signal terminal OT is high, and the gate sampling signal from the drive output terminal OUT is high.

[0152] In a second phase H1, the input signal is set to a high level, the first clock signal ck1 is set to a high level, the third clock signal ck3 is set to a low level, the first output control signal cs-1 is set to a high level on the first output control signal line CS-1, and the first output control signal cs-2 is set to a low level on the second output control signal line CS-2. The first transistor M1 is switched off by the high level of the first clock signal ck1, and the third node N3 remains at a low level. The twenty-eighth transistor M28 supplies the low level of the third node N3 to the first node N1. The first cascade transistor T3 and the first output transistor T1 are switched off by the high level of the first node N1.The first cascade transistor, T3, supplies the low level of the third clock signal, ck3, to the cascade signal terminal OT, and the first output transistor, T1, supplies the low-level signal at the output control signal terminal CS to the drive output terminal OUT. The twenty-fourth transistor, M24, is turned off by the high level of the first clock signal, ck1, and the second node, N2, remains low. The twenty-fifth transistor, M25, is turned on by the low level of the third node, N3, and supplies the high level of the first clock signal, ck1, to the second node, N2. The second node, N2, is high. The twenty-sixth transistor, M26, is turned off by the high level of the second node, N2, and the twenty-seventh transistor, M27, is turned on by the low level of the third clock signal, ck3. The second cascade transistor T4 and the second output transistor T2 are switched off by the high level of the second node N2.Then the cascade signal output from the cascade signal terminal OT is at a low level, and the gate sampling signal output from the control output terminal OUT is at a low level.

[0153] In a third phase H1, the input signal is high, the first clock signal ck1 is low, the third clock signal ck3 is high, the first output control signal cs-1 is low on the first output control signal line CS-1, and the first output control signal cs-2 is high on the second output control signal line CS-2. The first transistor M1 is switched on by the low level of the first clock signal ck1 and supplies the high level of the input signal to the third node N3. The twenty-eighth transistor M28 supplies the high level of the third node N3 to the first node N1. The first cascade transistor T3 and the first output transistor T1 are switched off by the high level of the first node N1. The twenty-fifth transistor M25 is switched off by the high level of the third node N3.The twenty-fourth transistor, M24, is switched on by the low level of the first clock signal, ck1, and supplies the low level of the seventh reference signal terminal, VREF7, to the second node, N2. The twenty-sixth transistor, M26, is switched on by the low level of the second node, N2. The twenty-sixth transistor, M26, supplies the high level of the first reference signal terminal, VREF1, to the first electrode of the twenty-seventh transistor, M27. The twenty-seventh transistor, M27, is switched off by the high level of the third clock signal, ck3. The second cascade transistor, T4, and the second output transistor, T2, are switched on by the low level of the second node, N2. The second cascade transistor, T4, supplies the high level of the first reference signal terminal, VREF1, to the cascade signal terminal, OT. The second output transistor, T2, supplies the high level of the first reference signal terminal, VREF1, to the drive output terminal, OUT.Then the cascade signal at the cascade signal terminal OT is at a high level, and the gate sampling signal at the control output terminal OUT is at a high level.

[0154] In the following periods, the shift register unit repeats the operating process described above for phases H1 to H3.

[0155] In the described embodiment, controlling the signal at the output control signal terminal controls the gate sampling signal at the drive output terminal in the output circuit. This controls or prevents the sampling of any area of ​​the display field, thereby saving power and reducing losses.

[0156] Although preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they understand the underlying inventive concepts. Therefore, the appended claims are to be interpreted as covering the preferred embodiments as well as any changes and modifications that fall within the scope of the present disclosure.

[0157] It is clear that those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Insofar as such changes and modifications fall within the scope of the claims and their equivalents, the present disclosure shall encompass these changes and modifications. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] CH 202310462243.6

[0001]

Claims

[1] A display field comprising: a shift register unit and a plurality of output control signal lines coupled to the shift register unit, wherein the plurality of output control signal lines are arranged between the shift register unit and a display area of ​​the display field; the shift register unit comprises: a shift register configured to output a cascade signal via a cascade output terminal; an output circuit coupled to the shift register, configured to control a drive output terminal based on a signal at an output control signal terminal and a signal at a first reference signal terminal, in order to output a gate sampling signal, wherein the output control signal terminal is coupled to one of the plurality of output control signal lines. [2] Display field according to claim 1, wherein the output circuit comprises a first output circuit and a second output circuit; wherein the first output circuit is coupled to the cascade output terminal or a first node in the shift register and is configured to transfer the signal from the output control signal terminal to the drive output terminal in response to a signal at the cascade output terminal or at the first node; and The second output circuit is coupled to a second node in the shift register and is configured to transfer the signal from the first reference signal terminal to the control output terminal in response to a signal at the second node. [3] Display panel according to claim 2, wherein the first output circuit comprises a first output transistor; wherein a gate of the first output transistor is coupled to the cascade output terminal or the first node, a first electrode of the first output transistor is coupled to the output control signal terminal and a second electrode of the first output transistor is coupled to the drive output terminal. [4] Display field according to claim 2, wherein the second output circuit comprises a second output transistor; wherein a gate of the second output transistor is coupled to the second node, a first electrode of the second output transistor is coupled to the first reference signal terminal and a second electrode of the second output transistor is coupled to the drive output terminal. [5] Display field according to one of claims 1-4, wherein the shift register comprises: an input sub-circuit configured to deliver a signal at an input signal terminal to a third node in response to a signal at a first clock signal terminal; a control circuit configured to control the signals at the first and second nodes and to supply the signal at the third node to the first or second node; a cascade sub-circuit configured to cause the cascade output terminal to output the cascade signal in response to signals at the first and second nodes. [6] Display panel according to claim 5, wherein the input sub-circuit comprises a first transistor; wherein a gate of the first transistor is coupled to the first clock signal terminal, a first electrode of the first transistor is coupled to the input signal terminal and a second electrode of the first transistor is coupled to the third node. [7] Display panel according to claim 5, wherein the control circuit comprises a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a first capacitor, a second capacitor, a third capacitor and a fourth capacitor; wherein a gate of the second transistor is coupled to the third node, a first electrode of the second transistor is coupled to the first clock signal terminal and a second electrode of the second transistor is coupled to a fourth node; wherein a gate of the third transistor is coupled to a second reference signal terminal, a first electrode of the third transistor to the fourth node and a second electrode of the third transistor to a gate of the fourth transistor; a first electrode of the fourth transistor is coupled to a second clock signal terminal and a second electrode of the fourth transistor is coupled to a first electrode of the fifth transistor; a gate of the fifth transistor is coupled to the second clock signal terminal and a second electrode of the fifth transistor is coupled to the first node; a gate of the sixth transistor is coupled to the first clock signal terminal, a first electrode of the sixth transistor is coupled to the input signal terminal, and a second electrode of the sixth transistor is coupled to a first electrode of the seventh transistor; a gate of the seventh transistor is coupled to the second reference signal terminal and a second electrode of the seventh transistor is coupled to the fifth node; a gate of the eighth transistor is coupled to the fifth node, a first electrode of the eighth transistor is coupled to the fifth node and a second electrode of the eighth transistor is coupled to the second node; a gate of the ninth transistor is coupled to the first clock signal terminal, a first electrode of the ninth transistor is coupled to the second reference signal terminal, and a second electrode of the ninth transistor is coupled to the gate of the tenth transistor; a first electrode of the tenth transistor is coupled to a third reference signal connection and a second electrode of the tenth transistor is coupled to a sixth node; a gate of the eleventh transistor is coupled to the fifth node, a first electrode of the eleventh transistor to the sixth node, and a second electrode of the eleventh transistor to the second clock signal terminal; a gate of the twelfth transistor is coupled to a first electrode of the fifteenth transistor, a first electrode of the twelfth transistor to the first node, and a second electrode of the twelfth transistor is coupled to a fourth reference signal terminal; a gate of the thirteenth transistor is coupled to a fifth reference signal terminal, a first electrode of the thirteenth transistor is coupled to the fourth reference signal terminal, and a second electrode of the thirteenth transistor is coupled to a first electrode of the fourteenth transistor; a gate of the fourteenth transistor is coupled to the first reference signal terminal, and a second electrode of the fourteenth transistor is coupled to the first electrode of the fifteenth transistor; a gate of the fifteenth transistor is coupled to the first reference signal terminal, the first electrode of the fifteenth transistor is coupled to the third node, and a second electrode of the fifteenth transistor is coupled to the second node; a first electrode of the first capacitor is coupled to the gate of the fourth transistor, and a second electrode of the first capacitor is coupled to the second electrode of the fourth transistor; a first electrode of the second capacitor is coupled to the sixth node, and a second electrode of the second capacitor is coupled to the second electrode of the seventh transistor; a first electrode of the third capacitor is coupled to the fourth reference signal terminal, and a second electrode of the third capacitor is coupled to the first node; a first electrode of the fourth capacitor is coupled to the cascade output terminal, and a second electrode of the fourth capacitor is coupled to the first reference signal terminal. [8] Display panel according to claim 5, wherein the cascade sub-circuit comprises a first cascade transistor and a second cascade transistor; wherein a gate of the first cascade transistor is coupled to the first node, a first electrode of the first cascade transistor is coupled to the fourth reference signal terminal and a second electrode of the first cascade transistor is coupled to the cascade output terminal; wherein a gate of the second cascade transistor is coupled to the second node, a first electrode of the second cascade transistor is coupled to the cascade output terminal and a second electrode of the second cascade transistor is coupled to the first reference signal terminal. [9] Display panel according to claim 5, wherein the input sub-circuit comprises a sixteenth transistor and a seventeenth transistor; wherein a gate of the sixteenth transistor is coupled to the first clock signal terminal, a first electrode of the sixteenth transistor is coupled to the input signal terminal, and a second electrode of the sixteenth transistor is coupled to the seventh node; and a gate of the seventeenth transistor is coupled to the first clock signal terminal, a first electrode of the seventeenth transistor is coupled to the seventh node, and a second electrode of the seventeenth transistor is coupled to the third node. [10] Display panel according to claim 5, wherein the control circuit comprises an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a fifth capacitor and a sixth capacitor; wherein a gate of the eighteenth transistor is coupled to the cascade output terminal, a first electrode of the eighteenth transistor is coupled to a third clock signal terminal and a second electrode of the eighteenth transistor is coupled to a seventh node; a gate of the nineteenth transistor is coupled to the input signal terminal, a first electrode of the nineteenth transistor is coupled to the first reference signal terminal, and a second electrode of the nineteenth transistor is coupled to the second node; a gate of the twentieth transistor is coupled to the second node, a first electrode of the twentieth transistor is coupled to the first reference signal terminal, and a second electrode of the twentieth transistor is coupled to an eighth node; a gate of the twenty-first transistor is coupled to the second node, a first electrode of the twenty-first transistor is coupled to the eighth node, and a second electrode of the twenty-first transistor is coupled to the third node; a gate of the twenty-second transistor is coupled to the third node, a first electrode of the twenty-second transistor is coupled to the eighth node, and a second electrode of the twenty-second transistor is coupled to a sixth reference signal terminal; a gate of the twenty-third transistor is coupled to a fourth clock signal terminal, a first electrode of the twenty-third transistor is coupled to the second node, and a second electrode of the twenty-third transistor is coupled to the sixth reference signal terminal; a first electrode of the fifth capacitor is coupled to the first reference signal terminal and a second electrode of the fifth capacitor is coupled to the first electrode of the twenty-third transistor; a first electrode of the sixth capacitor is coupled to the cascade output terminal and a second electrode of the sixth capacitor is coupled to the first node. [11] Display field according to claim 5, wherein the cascade sub-circuit comprises a first cascade transistor and a second cascade transistor; wherein a gate of the first cascade transistor is coupled to the first node, a first electrode of the first cascade transistor is coupled to the cascade output terminal, and a second electrode of the first cascade transistor is coupled to a third clock signal terminal; a gate of the second cascade transistor is coupled to the second node, a first electrode of the second cascade transistor is coupled to the first reference signal terminal, and a second electrode of the second cascade transistor is coupled to the cascade output terminal. [12] Display panel according to claim 5, wherein the control circuit comprises a twenty-fourth transistor, a twenty-fifth transistor, a twenty-sixth transistor, a twenty-seventh transistor, a twenty-eighth transistor, a seventh capacitor and an eighth capacitor; wherein a gate of the twenty-fourth transistor is coupled to the first clock signal terminal, a first electrode of the twenty-fourth transistor is coupled to a seventh reference signal terminal, and a second electrode of the twenty-fourth transistor is coupled to the second node; a gate of the twenty-fifth transistor is coupled to the third node, a first electrode of the twenty-fifth transistor is coupled to the second node, and a second electrode of the twenty-fifth transistor is coupled to the first clock signal terminal; a gate of the twenty-sixth transistor is coupled to the second node, a first electrode of the twenty-sixth transistor is coupled to the first reference signal terminal, and a second electrode of the twenty-sixth transistor is coupled to a first electrode of the twenty-seventh transistor; a gate of the twenty-seventh transistor with a third clock signal connection, and a second electrode of the twenty-seventh transistor coupled to a first electrode of the twenty-eighth transistor; a gate of the twenty-eighth transistor is coupled to the seventh reference signal terminal, the first electrode of the twenty-eighth transistor is coupled to the third node, and a second electrode of the twenty-eighth transistor is coupled to the first node; a first electrode of the seventh capacitor is coupled to the first reference signal terminal, and a second electrode of the seventh capacitor is coupled to the first node; a first electrode of the eighth capacitor is coupled to the cascade output terminal, and a second electrode of the eighth capacitor is coupled to the first node. [13] A display field comprising: a substrate with a display area and a non-display area; the display area includes: a plurality of subpixels; a plurality of scanning lines, wherein a row of the subpixels of the plurality of subpixels is coupled to at least one of the plurality of scanning lines; including the non-display area: a gate control circuit with a plurality of shift register units in a display field according to one of claims 1-12, wherein a control output connection of each shift register unit of the plurality of shift register units is coupled to at least one of the plurality of sampling lines. [14] Display field according to claim 13, further comprising a plurality of output control signal lines coupled to the gate control circuit, wherein the plurality of output control signal lines run in the same direction as the arrangement of the plurality of shift register units. [15] Display field according to claim 14, wherein the majority of the output control signal lines are arranged between the gate control circuit to which they are coupled and the display area. [16] Display field according to claim 15, wherein in two adjacent shift register units of the plurality of shift register units the input signal connection of the next shift register unit is coupled to the cascade output connection of the previous shift register unit; wherein the plurality of output control signal lines comprise a first and a second output control signal line; wherein the first output control signal line is coupled to the output control signal connections of odd-numbered shift register units and the second output control signal line is coupled to the output control signal connections of even-numbered shift register units. [17] Display field according to claim 14, further comprising a plurality of output control auxiliary signal lines, wherein a first insulating layer is provided between the majority of output control auxiliary signal lines and the majority of output control signal lines; the majority of output control auxiliary signal lines correspond one-to-one to the majority of output control signal lines, and each of the output control auxiliary signal lines is coupled to a corresponding output control signal line via a first through-hole that penetrates the first insulating layer. [18] Display field according to one of claims 13 to 17, further comprising a plurality of clock signal lines coupled to the gate control circuit; wherein the plurality of clock signal lines run in the same direction as the plurality of shift register units. [19] Display field according to claim 18, wherein the majority of clock signal lines are arranged on a side of the gate control circuit facing away from the display area, with which they are coupled. [20] Display field according to claim 18, wherein the orthographic projections of the plurality of output control signal lines on the substrate are located between the orthographic projections of the plurality of clock signal lines on the substrate and the display area. [21] Display field according to claim 18, wherein the orthographic projections of the gate control circuit on the substrate are located between the orthographic projections of the plurality of clock signal lines on the substrate and the orthographic projections of the plurality of output control signal lines on the substrate, and wherein the orthographic projections of the plurality of output control signal lines on the substrate are located between the orthographic projection of the gate control circuit on the substrate and the display area. [22] Display field according to one of claims 13-21, wherein the orthographic projection of the first output transistor on the substrate is located between the orthographic projection of the first cascade transistor on the substrate and the display area. [23] Display field according to one of claims 13-21, wherein the channel width of the first output transistor is larger than the channel width of the first cascade transistor. [24] Display field according to claim 23, wherein the channel width of the first output transistor is at least 100 µm. [25] Display field according to claim 23, wherein the channel width of the first cascade transistor is at most 60 µm. [26] Display field according to one of claims 13-21, wherein the orthographic projection of the second output transistor on the substrate is located between the orthographic projection of the second cascade transistor on the substrate and the display area. [27] Display field according to one of claims 13-21, wherein the channel width of the second output transistor is larger than the channel width of the second cascade transistor. [28] Display field according to claim 27, wherein the channel width of the second output transistor is at least 100 µm. [29] Display field according to claim 27, wherein the channel width of the second cascade transistor is at most 60 µm. [30] Display device, comprising: a display field according to one of claims 13-29; a control circuit coupled to the display field, configured so that it, When a full-screen drive mode is used, an initial output control signal is input to the output control signal terminals of the majority of shift register units, causing the majority of shift register units to sequentially output gate sampling signals to drive the sampling units line by line, and When a partial drive mode is used, a second output control signal is input to the output control signal terminals of the majority of shift register units, causing some of the majority of shift register units to sequentially output gate sampling signals and the remaining shift register units to output inactive sampling signals. [31] A control procedure, comprising: If it is determined that a full-screen drive mode should be used, an initial output control signal is input to the output control signal terminals of a plurality of shift register units, causing the plurality of shift register units to sequentially output gate sampling signals to drive sampling units line by line; If it is determined that a partial drive mode is to be used, a second output control signal is input to the output control signal terminals of the majority of shift register units, causing a portion of the majority of shift register units to sequentially output gate sampling signals and the remaining shift register units to output inactive sampling signals in order to drive a portion of the sampling power. [32] Control method according to claim 31, wherein the first output control signal is a fixed voltage signal with a first level. [33] Control method according to claim 31 or 32, wherein the second output control signal comprises a fixed voltage signal component with a first level and a fixed voltage signal component with a second level, wherein the fixed voltage signal component with the first level is fed into the part of the shift register units and the fixed voltage signal component with the second level is fed into the remaining shift register units. [34] Control method according to claim 31, wherein the first output control signal is a clock signal. [35] Control method according to claim 31 or 34, wherein the second output control signal comprises a clock signal component and a fixed voltage signal component with a first level; and the clock signal component of the second output control signal is fed into the part of the shift register units and the fixed voltage signal component with the first level is fed into the remaining shift register units.

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