SEMICONDUCTOR DEVICE

Abstract

The intention is to suppress the occurrence of a breakdown near a wiring area that passes through the interior of an active region when an IGBT is switched off. A semiconductor device (1) comprises a wiring area (4) that passes through the interior of an active region (2) containing an IGBT.The wiring area (4) comprises a drift layer (11) of a first conductivity type; a collector layer (16) of a second conductivity type, which is located closer to a back side than the drift layer (11); a trough layer (17) of a second conductivity type, which is located closer to a front side than the drift layer (11); a gate runner (5), which is located closer to a front side than the trough layer (17) and supplies a gate potential to a gate electrode (21); an emitter electrode (22), which is located closer to the front side than the gate runner (5); and a contact area (third contact area (30)) that electrically connects the trough layer (17) and the emitter electrode (22). The gate runner (5) is designed as a single layer (first gate runner (5A)) and has an opening (5C) at a position corresponding to and larger than the contact area.

Description

Technical field

[0001] The present invention relates to a semiconductor device. State of the art

[0002] An insulated-gate bipolar transistor (IGBT) is a type of semiconductor device.

[0003] Fig. Figure 8 shows a top view of a conventional semiconductor device. Fig. Figure 9 shows an enlarged view of section D in Fig. 8. Fig. Figure 10 shows a section view along CC' in Fig. 9. Furthermore, the following are in the Fig. 8 and Fig. 9 Some components have been omitted to make the drawings easier to understand.

[0004] As in Fig. As shown in Figure 8, a conventional semiconductor device 1 comprises an active region 2 with an IGBT, an edge termination region 3 surrounding the perimeter of the active region 2, a wiring region 4 passing through the interior of the active region 2, a gate runner 5, and a gate pad 6. As further shown in the Fig. 9 and Fig. As shown in Figure 10, the conventional semiconductor device 1 has a drift layer 11, a body layer 12, an emitter layer 13, a contact layer 14, a buffer layer 15, a collector layer 16, a well layer 17, a gate electrode 21, an emitter electrode 22, a collector electrode 23, a gate insulating film (not shown), a trench (not shown), an intermediate insulating film 26, an insulating film 27, a first contact area 28 and a second contact area 29.

[0005] As in Fig. As shown in Figure 8, the gate runner 5, which supplies a gate potential to the gate electrode 21 of the IGBT, is located between the active area 2 and the edge termination area 3, as well as in the wiring area 4. The gate runner 5 is connected to the gate pad 6, which is connected to the outside.

[0006] As in the Fig. 9 and Fig. As shown in Figure 10, the gate runner 5 in the wiring area 4 consists of two layers: a first gate runner 5A, which is made of polysilicon, and a second gate runner 5B, which is made of metal. The first gate runner 5A and the second gate runner 5B are connected by a second contact area 29, which penetrates the interlayer insulating film 26. Since metal has a lower wiring resistance than polysilicon, the formation of the gate runner 5 from two layers reduces the wiring resistance of the gate runner 5.

[0007] Conventional techniques in which the gate runner 5 is formed from two layers in the wiring area 4 include, for example, Fig. 26 of the patent literature 1 and Fig. 20 of the patent literature 2. Citation list for patent literature Patent Literature 1: JP 2019-12840 A Patent Literature 2: JP 2018-200950 A Summary of the invention: Technical problem

[0008] However, in the conventional semiconductor device 1, as in Fig. As shown in Figure 10, when the IGBT is switched off, holes 31 are injected from the collector layer 16 at a position overlapping with the gate runner 5 in the wiring area 4, enter the basin layer 17, pass the first contact area 28 outside the wiring area 4, which connects the body layer 12 and the emitter electrode 22 via the contact layer 14, and are extracted along a path leading to the emitter electrode 22. This concentrates the holes 31 at the end of the first contact area 28, which can cause a breakdown at a location near the wiring area 4, as indicated by a breakdown point 32. Such a breakdown limits the breakdown tolerance of the IGBT's reverse safe operating area (RBSOA).

[0009] The problem to be solved by the present invention is to provide a semiconductor device that suppresses the occurrence of a breakdown near a wiring area passing through the interior of an active region when an IGBT is switched off. Solution to the problem

[0010] To solve the above problem, a semiconductor device according to the present invention comprises: an active region with an IGBT; an edge termination region surrounding the perimeter of the active region; and a wiring region extending through the interior of the active region, wherein the IGBT comprises a gate electrode, an emitter electrode provided on a front face, and a collector electrode provided on a rear face, wherein the wiring region comprises: a drift layer of a first conductivity type; a collector layer of a second conductivity type located closer to a rear face than the drift layer; a well layer of the second conductivity type located closer to a front face than the drift layer; and a gate runner located closer to a front face than the well layer, which supplies a gate potential to the gate electrode.an emitter electrode located closer to the front face than the gate runner; and a contact area electrically connecting the trough layer and the emitter electrode, wherein the gate runner is formed as a single layer and has an opening at a position corresponding to and larger than the contact area. Advantageous effects of the invention

[0011] According to the present invention, it is possible to suppress the occurrence of a breakdown near a wiring area that passes through the interior of an active area when an IGBT is switched off. Brief description of the drawings Fig. Figure 1 shows a top view of a semiconductor device according to embodiments. Fig. Figure 2 shows an enlarged view of section D in Fig. 1. Fig. Figure 3 shows a sectional view along AA' in Fig. 2. Fig. 4 shows a sectional view along BB' in Fig. 2. Fig. 5 shows a section view along CC' in Fig. 2. Fig. Figure 6 shows a top view of a semiconductor device according to a comparative example. Fig. Figure 7 shows an enlarged view of section D in Fig. 6. Fig. Figure 8 shows a top view of a conventional semiconductor device. Fig. Figure 9 shows an enlarged view of section D in Fig. 8. Fig. Figure 10 shows a section view along CC' in Fig. 9. Description of embodiments

[0012] In the following, embodiments of the present invention are described with reference to the drawings. In each drawing, identical or similar components are identified by the same reference numerals and symbols, and the repeating description is omitted.

[0013] Fig. Figure 1 shows a top view of a semiconductor device according to embodiments. Fig. Figure 2 shows an enlarged view of section D in Fig. 1. Fig. Figure 3 shows a sectional view along AA' in Fig. 2. Fig. 4 shows a sectional view along BB' in Fig. 2. Fig. 5 shows a section view along CC' in Fig. 2. Furthermore, in the Fig. 1 and Fig. 2 Some components have been omitted to make the drawings easier to understand.

[0014] As in Fig. As shown in Figure 1, the semiconductor device 1 of the embodiment has an active region 2 with an IGBT, an edge termination region 3 surrounding the perimeter of the active region 2, and a wiring region 4 extending through the interior of the active region 2. The semiconductor device 1 further has a gate runner 5 located between the active region 2 and the edge termination region 3, and within the wiring region 4. The gate runner 5 is a gate wiring element that supplies a gate potential to a gate electrode 21 of the IGBT (see Figure 1). Fig. 2 etc.), as well as a gate pad 6, which is externally connected and supplies a gate potential to the gate runner 5.

[0015] As with conventional gate runners, the gate runner 5 between the active region 2 and the edge termination region 3 is preferably formed from at least two layers. This reduces the wiring resistance of the gate runner 5. In the present embodiment, an example is described in which the gate runner 5 is formed from two layers: a first gate runner 5A, which is formed, for example, from polysilicon, and a second gate runner 5B, which is formed from a metal such as Al. The first gate runner 5A, which is located on the back side, and the second gate runner 5B, which is located on the front side, are connected by a contact area (not shown) that penetrates the interlayer insulating film 26 (see Fig. 3, Fig. 4, Fig. 5 to Fig. 6).

[0016] In contrast, in the present embodiment, the gate runner 5 in the wiring area 4 is formed as a single layer of the first gate runner 5A, which is formed, for example, from polysilicon. As in the Fig. 2 and Fig. As shown in Figure 5, the semiconductor device 1 of the present embodiment has a third contact area 30 in the wiring area 4, which electrically connects the trough layer 17 and the emitter electrode 22.

[0017] In the present embodiment, the well layer 17 and the emitter electrode 22 are electrically connected via the third contact area 30 in the wiring area 4. Therefore, when the IGBT is switched off, holes 31, injected by the collector layer 16 at a position overlapping with the gate runner 5, penetrate the well layer 17 in the wiring area 4 and can travel directly to the emitter electrode 22 via the third contact area 30. This prevents the holes 31 from concentrating at the end of the first contact area 28 outside the wiring area 4 and prevents breakdown from occurring near the wiring area 4. Consequently, the RBSOA breakdown strength of the IGBT is not limited by this breakdown, and the RBSOA breakdown strength can be improved.

[0018] In wiring region 4, the emitter electrode 22 is located closer to a front face than the first gate runner 5A. The intermediate insulating film 26 is provided between the emitter electrode 22 and the first gate runner 5A. The insulating film 27 is provided between the first gate runner 5A and the well layer 17. The first gate runner 5A has an opening 5C, which is larger than the third contact area 30, at a position corresponding to the third contact area 30. Therefore, the third contact area 30 has a structure that penetrates the intermediate insulating film 26, the first gate runner 5A, and the insulating film 27. The well layer 17 and the third contact area 30 are preferably connected via the contact layer 14, which has a higher impurity concentration than the well layer 17. The emitter electrode 22 is preferably provided in a position that covers the entire gate runner 5 in one lateral direction.

[0019] As in the Fig. 2 and Fig. As shown in Figure 3, the IGBT has in its active region 2 the gate electrode 21, the emitter electrode 22 provided on the front side, and the collector electrode 23 provided on a rear side. In the present embodiment, the IGBT has a groove 25, and the gate electrode 21 and a gate insulating film 24 are provided within the groove 25; however, the present invention is not limited thereto. The emitter electrode 22 and the collector electrode 23 are made of metal such as aluminum, and the gate electrode 21 is made, for example, of polysilicon.

[0020] The IGBT also includes the drift layer 11, which consists of a semiconductor of a first conductivity type (in the Fig. 3. In the example shown, the n-type body layer 12 is formed, which is located closer to a front face than the drift layer 11 and consists of a semiconductor of a second conductivity type (in the example shown). Fig. 3 example of the p-type) is formed, the emitter layer 13, which is provided closer to a front side than the body layer 12 and is formed from a semiconductor of the first conductivity type, the intermediate insulating film 26, which is provided between the emitter layer 13 and the gate electrode 21 and the emitter electrode 22, the buffer layer 15, which is provided closer to a back side than the drift layer 11 and is formed from a semiconductor of the first conductivity type, which has a higher impurity concentration than that of the drift layer 11, and the collector layer 16, which is provided between the buffer layer 15 and the collector electrode 23 and is formed from a semiconductor of the second conductivity type.The emitter electrode 22 is connected to the emitter layer 13 in the first contact area 28 and to the body layer 12 via the first contact area 28 and the contact layer 14, which is formed from a semiconductor of the second conductivity type. Although the buffer layer 15 is not essential, its inclusion is desirable.

[0021] The trench 25 has a depth that penetrates the body layer 12 and reaches the drift layer 11. The gate insulating film 24 is positioned within the trench 25 such that it surrounds the gate electrode 21.

[0022] As in the Fig. 2, Fig. 4 and Fig. As shown in Figure 5, the wiring area 4 comprises the drift layer 11, the collector layer 16, which is located closer to a rear side than the drift layer 11, the second conductivity-type basin layer 17, which is located closer to the front side than the drift layer 11, the gate runner 5 (first gate runner 5A), which is located closer to a front side than the basin layer 17 and supplies a gate potential to the gate electrode 21, the emitter electrode 22, which is located closer to the front side than the gate runner 5, and the contact area (third contact area 30), which electrically connects the basin layer 17 and the emitter electrode 22. The gate runner 5 is formed as a single layer (first gate runner 5A) and has the opening 5C, which is larger than the contact area (third contact area 30), at a position corresponding to the contact area (third contact area 30).The wiring area 4 further comprises the intermediate insulating film 26, the insulating film 27, the contact layer 14 and the buffer layer 15. Although the buffer layer 15 is not essential, it is desirable that it be provided.

[0023] As in Fig. As shown in Figure 4, the trough layer 17 exhibits a deeper fault diffusion depth than the trench 25. The trough layer 17 also extends to part of the outside of the wiring area 4, and as shown in Fig. As shown in Figure 5, the tub layer 17 becomes flatter halfway along and is connected to the body layer 12. As in Fig. As shown in Figure 4, the insulating film 27 is formed between the trough layer 17 and the first gate runner 5A, and the insulating film 27 is connected to the gate insulating film 24.

[0024] As in Fig. As shown in Figure 4, the gate electrode 21 is brought out of the trench 25 and connected to the first gate runner 5A.

[0025] Next, with reference to the comparative example in the Fig. 6 and Fig. 7 explains the effect of forming the gate runner 5 in the wiring area 4 as a single layer, i.e. the first gate runner 5A, and electrically connecting the trough layer 17 and the emitter electrode 22 via the third contact area 30 within the opening 5C of the first gate runner 5A, as in the present embodiment.

[0026] Fig. Figure 6 shows a top view of a semiconductor device according to a comparative example. Fig. Figure 7 shows an enlarged view of section D in Fig. 6.

[0027] In the comparative example, the gate runner 5 in wiring area 4 is formed from two layers, the first gate runner 5A and the second gate runner 5B, and the two are connected by the contact area (not shown), as in the conventional example in Fig. 10. Furthermore, the emitter electrode 22 and the second gate runner 5B are formed simultaneously using the same material as in the conventional structure in Fig. 10, and are therefore located in the same layer. To electrically connect the trough layer 17 and the emitter electrode 22 within the opening 5C of the first gate runner 5A via the third contact area 30, it is therefore necessary, as shown in Fig. As shown in Figure 7, it is necessary to make the width (dimension in the lateral direction) of the first gate runner 5A larger than the width of the second gate runner 5B and to provide the third contact area 30 in a position that avoids the second gate runner 5B. Consequently, the width of the wiring area 4 increases and the area of ​​the active area 2 decreases.

[0028] In contrast, according to the present embodiment, as described in Fig.As shown in Figure 2, the width of the wiring area 4 can be made smaller than in the comparison example, thus ensuring the area of ​​the active area 2. It is desirable that the opening 5C be located in a position that includes the center of the gate runner 5 in the width direction. Even more desirable is that the opening 5C be located in the center of the gate runner 5 in the width direction.

[0029] The present embodiment describes an example in which the first conductivity type is an n-type and the second conductivity type is a p-type; however, the conductivity types are not limited thereto, and the first conductivity type can be the p-type and the second conductivity type can be the n-type. In this case, the charge carriers injected by the collector layer 16 become electrons instead of holes.

[0030] As an example, the impurity concentrations are shown as follows: the drift layer 11 is low concentration n-, the emitter layer 13 is high concentration n+, the contact layer 14 is high concentration p+, the body layer 12, the collector layer 16 and the trough layer 17 are p, and the buffer layer 15 is n. Without being limited thereto, the impurity concentrations can be suitably varied as long as the intended operation of the present embodiment is possible.

[0031] While the embodiments of the present invention have been described above, the present invention is not limited to the configurations described in those embodiments, and various modifications can be made within the scope of the technical concepts of the present invention. In addition, some or all of the configurations described in each example can be used in combination. List of reference symbols 1 Semiconductor device 2 Active Area 3 Edge finishing area 4 Wiring area 5 Gate Runners 5A First Gate Runner (Polysilicon) 5B Second Gate Runner (Metal) 5C opening 6 Gate Pad 11 Drift layer 12 Body Layers 13 emitter layer 14 Contact layer 15 Buffer layer 16 Collector layer 17 tub layer 21 Gate electrode 22 Emitter electrode 23 Collector electrode 24 Gate insulating film 25 trenches 26 Interlayer insulating film 27 Insulating film 28 First contact area (in the IGBT) 29 Second contact area (between gate runners) 30 Third contact area (trough layer in the wiring area) 31 holes 32 Breakthrough Point QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2019-12840 A

[0007] JP 2018-200950 A

[0007]

Claims

[1] Semiconductor device comprising: an active area with an IGBT; a perimeter boundary area that surrounds the perimeter of the active area; and a wiring area that runs through the interior of the active area, wherein the IGBT comprises a gate electrode, an emitter electrode provided on a front side and a collector electrode provided on a rear side, wherein The wiring area includes: a drift layer of a first conductivity type; a collector layer of a second conductivity type, which is located closer to a back side than the drift layer; a trough layer of the second conductivity type, which is located closer to a front face than the drift layer; a gate runner that is positioned closer to a front face than the trough layer and supplies a gate potential to the gate electrode; an emitter electrode positioned closer to the front face than the gate runner; and a contact area that electrically connects the trough layer and the emitter electrode, and wherein The gate runner is designed as a single layer and has an opening at a position that corresponds to the contact area and is larger than the contact area. [2] Semiconductor device according to claim 1, wherein the opening is provided at a position that encloses the center of the gate runner in a width direction. [3] Semiconductor device according to claim 1, wherein the emitter electrode is provided in a position that covers the entire gate runner in the width direction. [4] Semiconductor device according to claim 1, wherein the gate runner is made of polysilicon. [5] Semiconductor device according to claim 1, wherein the IGBT has a trench and the gate electrode is provided inside the trench. [6] Semiconductor device according to claim 1, wherein the semiconductor device has a gate runner formed from at least two layers and configured to supply a gate potential to the gate electrode between the active region and the edge termination region. [7] Semiconductor device according to claim 6, wherein the gate runner provided in the wiring area is made of polysilicon, and the gate runner, which is formed of at least two layers and is provided between the active area and the edge termination area, has a back side made of polysilicon and a front side made of metal.

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