METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

Abstract

A semiconductor device manufacturing process is provided that makes it possible to reduce the width of a termination area and to relax an electric field in the termination area. A semiconductor device fabrication method comprising the semiconductor device, which includes a termination region in an environment of an active region, wherein the termination region is configured to form a plurality of second semiconductor regions acting as a RESURF region and having a second conductivity type, on a surface of a first semiconductor region having a first conductivity type, comprising: Use as a mask for forming the second semiconductor regions, a mask in which, if a distance from an outermost circumferential reference window is defined as x, the distance S(x) between an implant window at the position of distance x and the nearest implant window on one side of the active region is essentially equal to a value defined by S ( x ) = Smax − ( Smax − Smin ) ⋅ ( x / XN ) β 0.3 ≤ β ≤ 0.5 to implant impurities of the second conductivity type and thereby form the second semiconductor regions.

Description

Technical field

[0001] The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device. State of the art

[0002] In recent years, price competition in the field of power semiconductor devices has intensified, creating a need for cost reduction. To lower costs, it is necessary to increase wafer diameters, reduce process temperatures, and decrease chip sizes. This necessitates making termination transitions shallower, reducing termination widths, and mitigating electrical fields in termination areas.

[0003] The state of the art, which relates to a closing area structure, includes, for example, patent literature 1 and patent literature 2.

[0004] Patent literature 1 describes a termination structure (32) provided on an outer circumferential section of a semiconductor element, comprising: an N-type drift region (1) formed in a semiconductor substrate (30); and a P-type impurity region (2) formed on an upper surface section in the N-type drift region (1), wherein, when viewed macroscopically, a P-type impurity concentration in the P-type impurity region (2) decreases from an inner circumferential section to an outer circumferential section of the termination structure (32), and, when viewed microscopically, the P-type impurity region (2) is formed by a plurality of high-concentration P-type regions (2b) and low-concentration regions (2a) surrounding the high-concentration regions (2b), the low-concentration regions (2a) being separated from each other (Summary, Fig. 2).

[0005] Here, patent literature 1 describes that the impurity concentration in the low concentration areas (2a) is set to a value that satisfies a condition (RESURF condition) where the low concentration areas (2a) are completely depleted, and the impurity concentration in the high concentration areas (2b) is set to a value at a level where whether or not the high density areas (2b) are depleted depends on variations in wafer processing (paragraph 0020).

[0006] Furthermore, patent literature 1 discloses that an opening ratio of an implantation mask (20) used in ion implantation to form such a P-like impurity region (2) is reduced towards the outside of the termination structure (32) (paragraph 0042), and discloses that, while examples of a function for reducing the opening ratio include a linear function and the like, a function with a high reduction rate, such as an exponential function, is desirable, and that, for example, by using an exponential function that is downwardly convex or a function that decreases according to a polynomial when viewed macroscopically, the local concentration of the electric field can be reduced (paragraph 0043).

[0007] Patent literature 2 describes a configuration in which a P-RESURF layer (3) (field relaxation layer) with a lower concentration than a P-base layer (2) is formed to surround the P-base layer (2), and the P-RESURF layer (3) is configured by alternating arrangements of high-concentration P-RESURF layers (7a, 8a, 9a and 10a) and low-concentration P-RESURF layers (8b, 9b, 10b, 11b), wherein the widths of the high-concentration P-RESURF layers (7a, 8a, 9a and 10a) are gradually narrowed towards the outside and the widths of the low-concentration P-RESURF layers (8b, 9b, 10b and 11b) are gradually widened towards the outside, while the sum of the widths of the sets of high-concentration P-RESURF layers and the P-RESURF layers with low concentration are kept equal so that the widths w(7a) = w(8b) + w(8a) = w(9b) + w(9a) = w(10b) + w(10a) = w(11b) are satisfied (paragraphs 0027 to 0039, Fig. 3 and Fig. 4). List of citations from patent literature Patent literature 1: WO 2014 / 054319 Patent literature 2: WO 2013 / 136550 Summary of the invention; Technical task

[0008] Although the patent literature 1 describes a linear function and an exponential function (a x), which project downwards, and a function which decreases according to a polynomial as functions that decrease an opening ratio of the implantation mask (20), and patent literature 2 describes the configuration in which the widths of the high-concentration P-RESURF layers are gradually narrowed towards the outside and the widths of the low-concentration P-RESURF layers are gradually widened, while the sum of the widths of the sets of high-concentration P-RESURF layers and low-concentration P-RESURF layers is kept equal, that is, the concentration decreases linearly in a pseudo-way, the inventor of the present application discovered as a result of the simulation that it was desirable for the shape of the mask to be a different shape in order to reduce the width of the closure area and to relax the electric field in the closure area.

[0009] One object to be solved by the present invention is to provide a semiconductor device manufacturing method and a semiconductor device with which it is possible to reduce the width of a termination area and to relax an electric field in the termination area. Solution to the task

[0010] To solve the problem described above, a semiconductor device manufacturing method according to the present invention is, for example, a semiconductor device manufacturing method, wherein the semiconductor device comprises a termination region in the vicinity of an active region, wherein the termination region is configured such that a plurality of second semiconductor regions having a second conductivity type and configured such that a depletion layer propagating into a first semiconductor region having a first conductivity type becomes contiguous with the active region when a voltage is applied, are formed on a surface of the first semiconductor region, and at least one second semiconductor region comprising a second semiconductor region formed at a position furthest from the active region from the plurality of second semiconductor regions.is completely depleted and acts as a RESURF region, the method comprising: using a mask for forming the second semiconductor regions adapted such that, when in a thermal equilibrium state an implantation window corresponding to the second semiconductor region formed at the position furthest from the active region is defined as a reference window, a position of the reference window on the active region side is defined as XO, a distance between a position of the implantation window adjacent to the active region on the active region side and XO is defined as XN, and a distance between the reference window and the nearest implantation window on the active region side is defined as Smax.a distance between an end section of the active area and the implantation window adjacent to the active area is defined as Smin, a distance of XO is defined as x and an exponent is defined as β, a distance S(x) between the implantation window at the position of distance x and the next implantation window on the side of the active area is essentially equal to a value defined by, S(x)=Smax−(Smax−Smin)⋅(x / XN)β 0.3≤β≤0.5 to implant impurities of the second conductivity type and thereby form the second semiconductor regions.

[0011] Furthermore, a semiconductor device according to the present invention is, for example, a semiconductor device comprising: an active region; and a termination region formed around the active region, wherein the termination region comprises a first semiconductor region having a first conductivity type and a plurality of second semiconductor regions formed on a surface of the first semiconductor region, having a second conductivity type and configured such that a depletion layer propagating into the first semiconductor region becomes connected to the active region when a voltage is applied, and at least one second semiconductor region comprising a second semiconductor region formed at a position furthest from the active region from the plurality of second semiconductor regions, which is completely depleted and acts as a RESURF region when a voltage is applied.and the second semiconductor regions, which are formed using the semiconductor device manufacturing process described above, are contained in the termination region. Advantageous effects of the invention

[0012] According to the present invention, it is possible to realize a semiconductor device manufacturing method and a semiconductor device with which it is possible to reduce the width of a termination area and to relax an electric field in the termination area. Brief description of the drawings Fig. Figure 1 is a cross-sectional view of a semiconductor device in a first embodiment. Fig. Figure 2 is a top view to illustrate a shape of a mask in the first embodiment. Fig. Figure 3 is a diagram to illustrate a distance between an implantation window and the next implantation window on one side of an active area in the mask and a width of the implantation window in the first embodiment. Fig. Figure 4 is a diagram illustrating a dose profile in the first embodiment. Fig. Figure 5 is a diagram to illustrate the effect of reducing the width of a closure area when β is changed. Fig. Figure 6 is a diagram to illustrate a change in the stress when β is changed. Fig. Figure 7 is a diagram to illustrate a change in the decrease in the stress when β is changed. Fig. Figure 8 is a cross-sectional view of a semiconductor device with a non-RESURF structure as a comparison example. Fig. Figure 9 is a diagram to illustrate a difference between the electric field strength properties of the RESURF structure and the non-RESURF structure. Fig. Figure 10 is a diagram illustrating a dose profile in a second embodiment. Fig. Figure 11 is a diagram to illustrate a distance between an implantation window and the next implantation window on one side of an active area in a mask and a width of the implantation window in a third embodiment. Fig. Figure 12 is a diagram to illustrate a distance between an implantation window and the next implantation window on one side of an active area in a mask and a width of the implantation window in a fourth embodiment. Fig. Figure 13 is a cross-sectional view of a semiconductor device in a fifth embodiment. Fig. Figure 14 is a cross-sectional view of a semiconductor device in a sixth embodiment. Description of the embodiments

[0013] Examples of the present invention are described below with reference to the drawings. In each drawing and in each example, identical reference numerals have been assigned to identical or similar constituent components, and any duplicate description thereof has been omitted. First embodiment

[0014] Fig. Figure 1 is a cross-sectional view of a semiconductor device of a first embodiment.

[0015] A semiconductor device 10 in the first embodiment comprises, in the vicinity of an active region 11, a termination region 12 in which a plurality of second semiconductor regions 2 with a second conductivity type (for example, p-type) are formed on the surface of a first semiconductor region 1 with a first conductivity type (for example, n-type). Here, it is described that the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type can be p-type and the second conductivity type can be n-type.

[0016] In the active region 11, a semiconductor element such as an insulated-gate bipolar transistor (IGBT), a metal-oxide-semiconductor field-effect transistor (MOSFET), a diode, or the like is formed, but not shown in the drawing. A semiconductor substrate on which the semiconductor device 10 is formed can be made of Si, SiC, or the like, but the present invention is not limited thereto.

[0017] The first semiconductor area 1 and the second semiconductor areas 2 are also formed in the active area 11, and the second semiconductor areas 2 in the active area 11 are referred to herein as second semiconductor areas 2a.

[0018] Furthermore, the semiconductor device 10 comprises a channel stopper 6 formed in the termination region 12 and exhibiting the first conductivity type at a higher concentration than the first semiconductor region 1, an oxide layer 4 formed to cover the first semiconductor region 1, the second semiconductor region 2, and the channel stopper 6, and an electrode 5 formed in the active region 11. The electrode 5 is, for example, a gate electrode or an emitter electrode in the case of an IGBT, a gate electrode or a source electrode in the case of a MOSFET, or an anode electrode in the case of a diode. Fig. Figure 1 shows only a front side of the semiconductor device 10, and a back side is not shown. An electrode (not shown), for example a collector electrode in the case of the IGBT, a drain electrode in the case of the MOSFET, or a cathode electrode in the case of the diode, is provided on the back side of the semiconductor device 10.

[0019] In the semiconductor device 10 of the first embodiment, a depletion layer 3, which propagates into the first semiconductor region 1, is continuous from the active region 11 to each of the second semiconductor regions 2, and each of the second semiconductor regions 2 is a substantially intrinsic region 7 in a state of thermal equilibrium. One of the features is that the depletion (shrinkage of the intrinsic region 7) of each of the second semiconductor regions 2 begins due to the application of a voltage from the second semiconductor region 2 to an outer circumferential side (a side that is away from the active region 11) of the termination region 12.

[0020] Furthermore, in the semiconductor device 10 in the first embodiment, the depletion layer 3, which extends from the first semiconductor region 1 to the plurality of second semiconductor regions 2 in the termination region 12, is connected to the active region 11, even when a voltage is applied. One of the features of the semiconductor device 10 in the first embodiment is that at least one second semiconductor region 2, comprising the second semiconductor region 2 (2b, which will be described later), which is formed at a position furthest from the active region 11 among the plurality of second semiconductor regions 2, is completely depleted and functions as the RESURF region 8 when a voltage is applied.

[0021] The RESURF region 8 has a function capable of relaxing an electric field and increasing a withstanding voltage through a reduced surface field (RESURF). In the RESURF region 8, the second semiconductor region 2 is completely depleted and is in a state where it lacks the intrinsic region 7. Since the second semiconductor region 2 is not completely depleted when the impurity concentration is high and the intrinsic region 7 remains, the impurity concentration of the second semiconductor region 2 is reduced to such a low level that, when a voltage is applied, the second semiconductor region 2 is completely depleted.

[0022] As in Fig. As illustrated in Figure 1, it is desirable that, with respect to the second semiconductor regions 2 in the termination region 12, a plurality of second semiconductor regions 2 overlap from the side near the active region 11 to the side farther from the active region 11. The width of the termination region 12 can thus be reduced. It should be noted that the present invention is not limited to this and that a plurality of second semiconductor regions 2 can overlap each other on one side closer to the active region 11, and the second semiconductor regions 2 on the side farther from the active region 11 can be separated from each other in the termination region 12. In both cases, the second semiconductor regions 2 in the termination region 12 are connected to the second semiconductor regions 2a in the active region 11 and on the side closer to the active region 11.

[0023] Here, from the second semiconductor regions 2, where the depletion layer 3, which spreads into the first semiconductor region 1, is connected with the active region 11 in a thermal equilibrium state, the second semiconductor region 2, which is formed at the position furthest from the active region 11, is designated as the outermost circumferential second semiconductor region 2b, where the depletion layer 3 is continuous.

[0024] Fig. Figure 2 is a top view to illustrate the shape of the mask in the first embodiment. Fig. Figure 3 is a diagram illustrating the distance between an implantation window of the mask and the next implantation window on the side of the active area, and the width of the implantation window in the first embodiment. It should be noted that, for ease of viewing the drawings, the number of implantation windows is 22. Fig. 2 for simplified illustration smaller than the second semiconductor areas 2 in Fig. 1 is. In Fig. 3 the horizontal axis indicates a position POS, the left vertical axis indicates a distance S (corresponding to the width of a blocking section 21) between the implantation window 22 of the mask 20 and the next implantation window 22 on the side of the active area 11, and the right vertical axis indicates a width W of the implantation window 22.

[0025] Impurities of a second conductivity type are detected using the method described in Fig. The mask 20 shown in Figure 2 is implanted to form the second semiconductor regions 2. The mask 20 has the blocking section 21 for blocking the impurities and the implantation window 22, which is an opening for allowing the impurities to pass through. Due to the diffusion of the implanted impurities, the size of the second semiconductor region 2 becomes larger than the size of the implantation window 22.

[0026] Here, from the implantation windows 22, the implantation window 22 corresponding to the second semiconductor region 2a of the active region 11 is referred to as an implantation window 22a of the active region, and the implantation window 22 corresponding to the outermost perimeter second semiconductor region 2b where the depletion layer 3 is contiguous is referred to as a reference window 22b.

[0027] The shape of the mask 20 in the first embodiment is such that a distance S(x) between the implantation window 22 at a position of distance x and the next implantation window 22 on one side of the active area 11 is essentially equal to a value specified by the following equation (1), where a position of the reference window 22b on one side of the active area 11 is defined as XO, a distance between a position of the implantation window 22 adjacent to the active area 11 on one side of the active area 11 and XO is defined as XN, a distance between the reference window 22b and the next implantation window 22 on one side of the active area 11 is defined as Smax, a distance between an end section of the active area 11 and the implantation window 22 adjacent to the active area 11 is defined as Smin, a distance from XO is defined as x, and an exponent is defined as β. is.As will be described later, 0.3 ≤ β ≤ 0.5 is a desirable range for β. S(x)=Smax−(Smax−Smin)⋅(x / XN)β. Consequently, it is possible to reduce the width of the termination region 12 and to relax the electric field in the termination region 12. Details of the effects are described below.

[0028] Furthermore, the shape of the mask 20 in the first embodiment is such that a width W(x) of the implantation window 22 at a position of distance x decreases with increasing distance from the active area 11.

[0029] In this case, the width of the second semiconductor region 2 can be made smaller than in a case where the width W(x) of the implantation window 22 is constant regardless of the position of the distance x and therefore the width of the termination region 12 can be reduced.

[0030] In the first embodiment, as in Fig. Figure 3 illustrates that the width W(x) of the implantation window at the position of distance x is made such that it decreases linearly with increasing distance from the active area 11.

[0031] Fig. Figure 4 is a diagram illustrating a dose profile in the first embodiment. Fig. 4. A horizontal axis indicates a position POS and a vertical axis indicates a dose DO.

[0032] To form the RESURF region 8, it is necessary that the concentration of impurities in the second semiconductor regions 2 be set to a low value to such an extent that the second semiconductor regions 2 are completely depleted, at least on the side furthest from the active region 11, when a voltage is applied. For this purpose, it is desirable that the dose in the second semiconductor regions 2 in the termination region 12 at the time of implantation of the second conductivity-type impurities using the mask 20 be equal to or greater than 4 × 10 12 cm -2 and equal to or smaller than 3 × 10 13 cm -2 is.

[0033] To ensure the effect of the RESURF region 8, which relaxes the electric field, is sufficient, it is also desirable that the second semiconductor regions 2, corresponding to at least one region of 0 ≤ x ≤ XN / 2, are completely depleted and function as the RESURF region 8 when a voltage up to a withstanding voltage is applied. Furthermore, it is more desirable that the second semiconductor regions 2, corresponding to at least one region of 0 ≤ x ≤ XN × 2 / 3, are completely depleted. It should be noted that it is not necessary for the second semiconductor region 2 corresponding to x = XN to also be completely depleted.

[0034] In the first embodiment, when the impurities of the second conductivity type are implanted using the mask 20, the dose profile is such that a dose in the second semiconductor region 2a of the active region 11 is essentially equal to a dose in the second semiconductor region 2 of the termination region 12.

[0035] As a result, it is possible to form the second semiconductor region 2 by implanting the impurities of the second conductivity type using a single mask 20.

[0036] It should be noted that, although the dose may be smaller than the range described above, the dose required for the second semiconductor regions 2a in the active region 11 may be insufficient, since the second semiconductor regions 2a in the active region 11 are used for a body region of the semiconductor element formed in the active region 11. Two masks 20 are therefore required, and a configuration in which the dose in the second semiconductor regions 2 in the termination region 12 is smaller than the dose in the second semiconductor regions 2a in the active region 11 when the second conductivity-type impurities are implanted using the masks 20 can be assumed as needed.

[0037] Next, the effect that it is possible to reduce the width of the termination regions 12 and to relax the electric field in the termination region 12 depending on the shape of each mask 20 in the first embodiment will be described in detail.

[0038] Fig. Figure 5 is a diagram illustrating the effect of reducing the width of the closure area when β is changed. Fig. 5 specifies the horizontal axis as a position POS and a vertical axis as a distance S (corresponding to the width of the blocking section 21) between the implantation window 22 of the mask 20 and the next implantation window 22 on the side of the active area 11.

[0039] It is assumed that the distance S(x) between the implantation window 22 at the position of distance x from XO and the nearest implantation window 22 on one side of the active area 11 can be expressed by the following equation (2). S(x)=Smax−(Smax−Smin)⋅(x / Lx(β))β In the case where Lx(β) = XN, this equation becomes equation (1). Here, assuming that the number of implantation windows is 22 19 and the distance between the position of implantation window 22 adjacent to the active area 11 on the side of the active area 11, and XO Lx(β), the distance S(x) and Lx(0.3), Lx(0.4), Lx(0.5), Lx(1.0) and Lx(2.0) are calculated and in Fig. 5 for β = 0.3, 0.4, 0.5, 1.0 and 2.0 illustrated.

[0040] As a result, it can be stated that the smaller β is, the smaller Lx(β) is, meaning that the width of the termination area 12 can be made smaller.

[0041] Here, β = 1.0 corresponds to the distance S(x), which increases linearly towards the outer environment of the closure area 12 (as x approaches O). This is not strictly the same as, but approximately corresponds to, a case like that in patent literature 1, where the opening ratio of the implantation mask (20) decreases towards the outside of the closure structure (32) according to a linear function, and to a case like that in patent literature 2, where the concentration decreases linearly in a pseudo-way towards the outside. Furthermore, β = 2.0 corresponds to a case in patent literature 1, where the opening ratio of the implantation mask (20) decreases towards the outside of the closure structure (32) according to a polynomial. However, in the cases where β = 1.0 and β = 2.0, Lx(1.0) and Lx(2.0) become large compared to Lx(0.3) to Lx(0.5), which was found to be unsuitable for reducing the width of the termination area 12.

[0042] Furthermore, although in Fig. 5 not illustrated, calculations also performed for a case in which the distance S(x) depends on e x as an example of an exponential function (approximately corresponding to the case in which the opening ratio of the implantation mask (20) decreases towards the outside of the closure structure (32) according to an exponential function in patent literature 1), and the results are approximately close to the case of β = 2.0. Therefore, it is found that this case is also not suitable for reducing the width of the closure area 12.

[0043] Fig. Figure 6 is a diagram illustrating a change in the stress when β is changed. Fig. Figure 6 indicates the horizontal axis β and the vertical axis indicates a standing stress V.

[0044] Fig. Figure 6 illustrates the results of calculating the withstand voltage V under the assumption of a diode with a nominal withstand voltage of 750 V, assuming an interface charge density Qss 0 cm⁻¹. -2 The gradient of the decrease in the withstanding voltage V increases when β is less than 0.3. For β ≤ 0.3, the withstanding voltage V is equal to or greater than 850 V, and a withstanding voltage is obtained that is sufficiently higher than the nominal withstanding voltage of 750 V.

[0045] Fig. Figure 7 is a diagram illustrating the change in the decrease in the withstand stress when β is changed. Fig. Figure 7 indicates the horizontal axis β and the vertical axis indicates the amount ΔV of the decrease in the standing stress.

[0046] The in Fig. The illustrated withstand voltage V corresponds to an initial withstand voltage, since it is assumed that the interfacial charge density Qss 0 cm -2The interfacial charge density Qss can, however, change during load tests or actual use, and consequently the withstanding stress V also changes. The magnitude of the change in withstanding stress V is the magnitude ΔV of the decrease in withstanding stress, which is in Fig. Figure 7 illustrates this, and the top of the vertical axis corresponds to 0 V, while the bottom of the vertical axis corresponds to a negative value. Since an absolute value of the magnitude ΔV of the decrease in the withstanding voltage (negative value) is the smallest (corresponding to the peak in the graph of Fig. 7) When β = 0.4, it can be observed that the highest power output is achieved. Furthermore, it can be observed that the gradient of the magnitude ΔV of the decrease in the withstanding voltage is large, and the power output is likely to degrade in the range where β is less than 0.3 and in the range where β is greater than 0.5. Therefore, it is desirable to satisfy 0.3 ≤ β ≤ 0.5.

[0047] Fig. Figure 8 is a cross-sectional view of a semiconductor device with a non-RESURF structure as a comparison example.

[0048] In the case of the non-RESURF structure, as a comparative example, the concentration of impurities in the second semiconductor regions 2 in the termination region 12 is set high, such that the second semiconductor regions 2 in the termination region 12 are not completely depleted, even when a voltage up to the withstand voltage is applied, and the intrinsic region 7 remains. Therefore, the intrinsic region 7 that remains without being depleted becomes a dead space, and there is a region that is unusable for reducing the width of the termination region 12.

[0049] Fig. Figure 9 is a diagram illustrating a difference between the electric field strength properties of the RESURF structure and the non-RESURF structure. Fig. In figure 9, the horizontal axis indicates a position POS and the vertical axis indicates an electric field strength E.

[0050] In Fig. Figure 9 shows the dashed line diagram, referred to as “non-RESURF”, representing the property of the electric field strength E of the non-RESURF structure as a comparative example, and it can be seen that the electric field strength E changes extensively between the valley section corresponding to the blocking section 21 and the peak section corresponding to the implantation window 22.

[0051] On the other hand, the solid line diagram shown in Fig. 9, referred to as “RESURF”, describes the property of the electric field strength E of the RESURF structure of the present embodiment, and it can be stated that the electric field concentration is suppressed and the electric field is relaxed, since the change in the electric field strength E is small. Thus, it is possible to secure the withstanding voltage.

[0052] As described above, according to the first embodiment it is possible to reduce the width of the termination area 12 and to relax the electric field in the termination area 12 by adopting the RESURF structure in the termination area 12 and using the mask 20 with the shape in which the distance S(x) between the implantation window 22 at the position of distance x and the next implantation window 22 on the side of the active area 11 is essentially equal to the value defined by equation (1) and 0.3 ≤ β ≤ 0.5. Second embodiment

[0053] Fig. Figure 10 is a diagram illustrating a dose profile in the second embodiment. Fig. 10 is a diagram that Fig. 4 corresponds to the first embodiment.

[0054] The second embodiment differs from the first embodiment in its dose profile. The dose profile in the second embodiment is, as in Fig. Figure 10 shows a dose profile in which the dose of the second semiconductor region 2 in termination region 12a is greater on one side closer to the active region 11 in termination region 12 than the dose of the second semiconductor region 2 in termination region 12b is greater on one side further away from the active region 11 in termination region 12. As a result, the effect of suppressing a decrease in the standoff voltage due to positive interfacial charges is achieved. However, in the second embodiment, in order to change the dose depending on the region, it is necessary to implant impurities of a second conductivity type using two masks 20, and thus the second embodiment also differs from the first embodiment in this respect.

[0055] Apart from the above, this embodiment is the same as the first embodiment, and therefore the overlapping description is omitted. Third embodiment

[0056] Fig. Figure 11 is a diagram illustrating a distance between an implantation window and the next implantation window on the side of the active area in a mask and a width of the implantation window in a third embodiment. Fig. Figure 11 is a diagram that Fig. 3 corresponds to the first embodiment.

[0057] The third embodiment differs from the first embodiment in the width W(x) of an implantation window 22 at a position of a distance x. The shape of the mask 20 in the third embodiment is such that the width W(x) of the implantation window 22 at the position of distance x decreases linearly with increasing distance from an active area 11, and the gradient of a decrease on a side closer to the active area 11 (x > XN') is greater than the gradient of a decrease on a side further away from the active area 11 (x ≤ XN'). It should be noted that in Fig. 11 Wmax' is a value of the width W(x) of the implantation window 22 at a position where the distance x is XN'.

[0058] Next, the reason for the change in the gradient of the decrease in the width W(x) of the implantation window 22 is explained. Due to heat treatment after the implantation of the second conductivity-type impurities, the width of the second semiconductor regions 2 increases, and the peak concentration also decreases. The amount of decrease in the peak concentration is greater when the width W(x) of the implantation window 22 is smaller, and smaller when the width W(x) is larger. In contrast, the width of the implantation window 22 in the second semiconductor regions 2a in the active region 11 is significantly larger than the width W(x) of the implantation window in the termination region 12, and thus the decrease in the peak concentration in the second semiconductor regions 2a in the active region 11 is less than in the case of the second semiconductor regions 2 in the termination region 12.Therefore, a difference in peak concentrations occurs between the active region 11 and the adjacent second semiconductor region 2. In cases where there is a large difference in concentrations, there is a concern that an electric field concentration may occur at the end of the active region 11, leading to a decrease in the withstanding voltage. For this reason, it is preferred that the width W(x) of the implantation window 22 be larger in the vicinity of the active region 11. Conversely, if the width W(x) of the implantation window 22 is large, the overall width of the termination region 12 becomes large, and thus it is preferred that the width W(x) be as small as possible. Since the countermeasure against the electric field concentration at the end of the active region 11 is only sufficient in the vicinity of the active region 11, as shown in [reference missing], Fig. As shown in Figure 11, by making the shape of the mask such that the gradient of the decrease on a side closer to the active region 11 (x > XN') is greater than the gradient of the decrease on a side further away from the active region 11 (x ≤ XN'), it is possible to reduce the total width of the closure region 12 compared to the case of Fig. 3 to reduce, while the countermeasure against the electric field concentration at the end of the active area 11 is taken. This is the reason why the gradient of the decrease in the width W(x) of the implantation window 22 is changed.

[0059] Furthermore, as a consequence, even in a case where the impurities of the second conductivity type are removed using the single mask 20 with the same dose profile as the one in Fig. 4 shown in the first embodiment are implanted to form the second semiconductor region 2, also the effect of suppressing a decrease in the stand voltage due to positive interfacial charges, as in the case of the second embodiment.

[0060] Apart from the above, this embodiment is the same as the first embodiment, and therefore the overlapping description is omitted. Fourth embodiment

[0061] Fig. Figure 12 is a diagram illustrating a distance between an implantation window and the next implantation window on one side of an active area of ​​a mask and a width of the implantation window in a fourth embodiment. Fig. 12 is a diagram that Fig. 3 corresponds to the first embodiment.

[0062] The fourth embodiment differs from the first and third embodiments in the width W(x) of an implantation window 22 at a position of a distance x. The shape of a mask 20 in the fourth embodiment is such that, if a width of the implantation window 22 at a position of a distance XN is defined as Wmax and a width of the implantation window 22 as a reference window 22b is Wmin, a width W(x) of the implantation window 22 at the position of distance x is essentially equal to a value defined by the following equation (3). W(x)=Wmax−(Wmax−Wmin)⋅(1−x / XN)β In the fourth embodiment, the width W(x) of the implantation window 22 can be changed smoothly instead of linearly, and a decrease in the standing stress due to positive interface charges can be suppressed.

[0063] Apart from the above, this embodiment is the same as the first embodiment and the third embodiment, and therefore the overlapping description is omitted. Fifth embodiment

[0064] Fig. Figure 13 is a cross-sectional view of a semiconductor device in a fifth embodiment.

[0065] The fifth embodiment is an embodiment in which a semiconductor device 10 has second semiconductor regions 2c with high concentrations, which have higher concentrations of impurities of a second conductivity type than the surroundings thereof, than some of the second semiconductor regions 2a in an active region 11.

[0066] The second semiconductor regions 2c with high concentration are, for example, provided on portions of the surfaces of the second semiconductor regions 2a in the active region 11. This further suppresses the expansion of a depletion layer 3 towards the surface in the active region 11. The second semiconductor regions 2c with high concentration are, for example, provided at positions in contact with an electrode 5. Therefore, the contact resistance between the electrode 5 and the second semiconductor regions 2a in the active region 11, which functions, for example, as a body region, can be further reduced.

[0067] It is desirable that the concentrations of impurities of the second conductivity type in the second semiconductor regions 2c with high concentration are approximately 1 × 10 14 cm -3or higher. In other words, it is desirable that the concentrations of second-type conductivity impurities in the high-concentration second semiconductor regions 2c be an order of magnitude or more higher than the concentrations of second-type conductivity impurities in the second semiconductor regions 2a in the active region 11 surrounding the high-concentration second semiconductor regions 2c and the concentrations of second-type conductivity impurities in the second semiconductor regions 2 in the termination region 12. In this embodiment, the concentrations of second-type conductivity impurities in the high-concentration second semiconductor regions 2c are 2 × 10 14 cm 3 .

[0068] Apart from the above, this embodiment is the same as the first embodiment up to the fourth embodiment, and therefore the overlapping description is omitted. Sixth embodiment

[0069] Fig. Figure 14 is a cross-sectional view of a semiconductor device in a sixth embodiment.

[0070] The sixth embodiment is an embodiment in which a channel stopper electrode 9 is provided.

[0071] In this embodiment, a semiconductor device 10 comprises a channel-stopper electrode 9 formed on an oxide layer 4 and connected to a channel stopper 6 via an opening located in the oxide layer 4. The channel-stopper electrode 9 is positioned such that one end of it is closer to the active region 11 on the side closer to the active region 11 than the other end of the channel stopper 6 on the same side. In other words, the channel-stopper electrode 9 has a shape that protrudes towards the side of the active region 11 compared to the channel stopper 6.

[0072] To reduce the width of a termination region 12, it is necessary not only to reduce the overall dimension of the second semiconductor regions 2 in the termination region 12, but also to reduce the DCSP distance between the outermost perimeter of the second semiconductor region 2b, with which the depletion layer 3 is continuous, and the channel stopper 6. Equipotential lines are distributed in the region between the outermost perimeter of the second semiconductor region 2b, with which the depletion layer 3 is contiguous, and the channel stopper 6. The equipotential lines do not propagate to the channel stopper 6 if the DCSP distance is large; a multitude of equipotential lines reach the channel stopper 6 if the DCSP distance is narrowed. Since the channel stopper 6 has a high concentration, the equipotential lines do not propagate within the channel stopper 6.As a result, a large number of equipotential lines concentrate at the end of the channel stopper 6 on the side near the active region 11, and the electric field strength is locally extremely increased. Therefore, the lower limit for the distance DCSP is reached.

[0073] Therefore, the channel stopper electrode 9 is provided, and the configuration in which the end of the channel stopper electrode 9 is positioned closer to the active region 11 than the end of the channel stopper 6 on the side closer to the active region 11 is adopted in this embodiment. This results in a field plate effect of the channel stopper electrode 9. Since the equipotential lines, which are densely packed at the end of the channel stopper 6 on the side closer to the active region 11, shift by a certain percentage towards the end of the channel stopper electrode 9 on the side closer to the active region 11, the local increase in electric field strength generated at the end of the channel stopper 6 on the side closer to the active region 11 is reduced.This reduction effect is determined by a distance LFP between the end of the channel stopper electrode 9 on the side closer to the active region 11 and the end of the channel stopper 6 on the side closer to the active region 11. Although a large reduction effect can be achieved by increasing the distance LFP, the electric field strength within the oxide layer 4 under the end of the channel stopper electrode 9 on the side closer to the active region 11 also increases. The correct value of the distance LFP depends on the withstand voltage and the concentration of the first low-concentration semiconductor region 1 and can be set from several to several tens of µm. In this embodiment, the distance LFP is set to 20 µm. It is thus possible to shorten the distance DCSP by 10% or more compared to the case in which the field plate effect of the channel stopper electrode 9 is not used.

[0074] Apart from the above, this embodiment is the same as the first embodiment up to the fourth embodiment, and therefore the overlapping description is omitted.

[0075] While the examples of the present invention have been described above, the present invention is not limited to the configurations described in the examples, and various modifications can be made within the scope of the technical concepts of the present invention. Furthermore, some or all of the configurations described in the examples can be used in combination. Reference symbol list 1 first semiconductor area 2 second semiconductor area 2a second semiconductor area in the active area 2b outermost extensive second semiconductor region where the depletion layer is continuous 2c second semiconductor region with high concentration 3. Depletion layer 4 Oxide layer 5 electrode 6 channel stoppers 7 intrinsic area 8 RESURF area 9 Channel stopper electrode 10 Semiconductor device 11 active area 12, 12a, 12b Final section 20 masks 21 Blocking section 22 implantation windows 22a Implant window in the active area 22b Reference window S Distance between the implantation window and the next implantation window on the side of the active area W Width of the implantation window x distance β Exponent DO dose POS Position V Standing voltage ΔV reduction amount of the withstanding voltage Qss interface charge density E field strength QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] WO 2014 / 054319

[0007] WO 2013 / 136550

[0007]

Claims

[1] A semiconductor device manufacturing process, wherein the semiconductor device comprises a termination region in the vicinity of an active region, wherein the termination region is configured such that a plurality of second semiconductor regions, having a second conductivity type and configured such that a depletion layer propagating into a first semiconductor region having a first conductivity type becomes contiguous with the active region when a voltage is applied, are formed on a surface of the first semiconductor region, and at least one second semiconductor region, comprising a second semiconductor region formed at a position furthest from the active region from the plurality of second semiconductor regions, is fully depleted and acts as a RESURF region, the procedure includes: Using a mask to form the second semiconductor regions, adapted such that, from the second semiconductor regions where the depletion layer propagating into the first semiconductor region is connected to the active region in a state of thermal equilibrium, an implantation window corresponding to the second semiconductor region formed at the position furthest from the active region is defined as a reference window, a position of the reference window on the side of the active region is defined as XO, a distance between a position of the implantation window adjacent to the active region on the side of the active region and XO is defined as XN, a distance between the reference window and the nearest implantation window on the side of the active region is defined as Smax, and a distance between an end section of the active region and the implantation window is defined as Smax.that borders the active area, is defined as Smin, a distance from XO is defined as x and an exponent is defined as β, a distance S(x) between the implantation window at the position of distance x and the next implantation window on the side of the active area is essentially equal to a value defined by, S(x)=Smax−(Smax−Smin)⋅(x / XN)β 0.3≤β≤0.5 to implant impurities of the second conductivity type and thereby form the second semiconductor regions. [2] Manufacturing method for a semiconductor device according to claim 1, wherein in the mask a width W(x) of the implantation window at the position of distance x decreases with increasing distance from the active area. [3] Manufacturing method for a semiconductor device according to claim 2, wherein in the mask the width W(x) of the implantation window at the position of distance x decreases linearly with increasing distance from the active area. [4] Manufacturing method for a semiconductor device according to claim 2, wherein in the mask the width W(x) of the implantation window at the position of distance x decreases linearly with increasing distance from the active area and a gradient of decrease on a side closer to the active area is greater than a gradient of decrease on a side further away from the active area. [5] Manufacturing method for a semiconductor device according to claim 2, wherein if a width of an implantation window at a position of distance XN is defined as Wmax and a width of the implantation window as the reference window is defined as Wmin, the mask is a mask in which the width W(x) of the implantation window at the position of distance x is substantially equal to a value defined by W(x)=Wmax−(Wmax−Wmin)⋅(1−x / XN)β. [6] Manufacturing method for a semiconductor device according to claim 1, wherein when the impurities of the second conductivity type are implanted using the mask, a dose in the second semiconductor regions in the active region is substantially equal to a dose in the second semiconductor regions in the termination region. [7] Manufacturing method for a semiconductor device according to claim 1, wherein when the impurities of the second conductivity type are implanted using the mask, a dose in the second semiconductor regions in the termination region is smaller than a dose in the second semiconductor regions in the active region. [8] Manufacturing method for a semiconductor device according to claim 1, wherein when the impurities of the second conductivity type are implanted using the mask, a dose in the second semiconductor regions on one side closer to the active region is greater than a dose in the second semiconductor regions on one side further away from the active region in the termination region. [9] Manufacturing method for a semiconductor device according to claim 1, wherein a dose in the second semiconductor regions in the termination region, when the impurities of the second conductivity type are implanted using the mask, is equal to or greater than 4 × 10 12 cm -2 and equal to or smaller than 3 × 10 13 cm -2 is. [10] Manufacturing method for a semiconductor device according to claim 1, wherein the second semiconductor regions corresponding to a region of at least 0 ≤ x ≤ XN / 2 are completely depleted and function as the RESURF region when a voltage up to a withstand voltage is applied. [11] Semiconductor device comprising: an active region; and a termination region formed around the active region, wherein the termination region comprises a first semiconductor region having a first conductivity type and a plurality of second semiconductor regions formed on a surface of the first semiconductor region, having a second conductivity type and configured such that a depletion layer propagating into the first semiconductor region becomes contiguous with the active region when a voltage is applied, at least one second semiconductor region comprising a second semiconductor region formed at a position furthest from the active region among the plurality of second semiconductor regions, is completely depleted and functions as a RESURF region when a voltage is applied, and the second semiconductor regions, which are formed using the manufacturing process for a semiconductor device according to one of claims 1 to 10, are contained in the termination region. [12] Semiconductor device according to claim 11, wherein, in a thermal equilibrium state, the depletion layer propagating into the first semiconductor region is continuous from the active region to the second semiconductor region formed by the reference window, in a region from the second semiconductor region formed by an implantation window adjacent to the active region to the second semiconductor region formed by the reference window, each second semiconductor region is a substantially intrinsic region, and the depletion of each of the second semiconductor regions, which occurs as a result of the application of a voltage, starts from the second semiconductor region formed by the reference window. [13] Semiconductor device according to claim 11, wherein the second semiconductor area formed by an implantation window adjacent to the active area and the semiconductor area formed by the reference window overlap each other. [14] Semiconductor device according to claim 11, wherein from the second semiconductor regions in a region from the second semiconductor region formed by the implantation window adjacent to the active region to the second semiconductor region formed by the reference window, a plurality of the second semiconductor regions overlap each other on one side closer to the active region and the second semiconductor regions are separated from each other on one side further away from the active region. [15] Semiconductor device according to claim 11, wherein some of the second semiconductor regions in the active region are high concentration second semiconductor regions that have higher concentrations of second conductivity type impurities than an environment thereof. [16] Semiconductor device according to claim 11, further comprising: a channel stopper formed in the termination region and exhibiting a first conductivity type in a higher concentration than the first semiconductor region; an oxide layer formed in such a way as to cover the first semiconductor region, the second semiconductor regions, and the channel stopper; and a channel stopper electrode formed on the oxide layer and connected to the channel stopper via an opening located in the oxide layer, wherein one end of the channel stopper electrode on a side closer to the active area is positioned closer to the active area than an end section of the channel stopper on the side closer to the active area.

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