RADIO RECEIVER

Description

[0001] The present invention relates to a radio receiver according to the preamble of claim 1, a radio receiver according to claim 2 and a communication system according to claim 18 for transmitting data. Technological background

[0002] The Software Defined Radio (SDR) type radio receivers of interest here typically contain a receiving device, such as a radio chip, and are primarily used in battery-operated stationary sensor arrays with unidirectional or bidirectional data transmission. The data to be received includes, for example, data for operating the sensor array, such as update data, program data, control data, or the like, which are sent from a concentrator to the radio receiver. Among other reasons, to minimize energy consumption at the radio front end, the data or data telegrams are not sent in one go by the concentrator, but rather in fragmented form in the form of individual data packets or parts thereof (e.g., partial data packets), and are received by the radio receiver in this way.

[0003] Conventional radio chips are generally low-cost components with functions already integrated into the radio chip that can only be modified to a very limited extent. Especially in narrowband radio transmissions, for example, the sampling rate must be precisely matched, which cannot be adjusted so precisely on the radio chips. If the sampling rate cannot be precisely matched, complex computing power is required for resampling, which consumes a correspondingly large amount of electrical energy and is undesirable or even impossible due to the energy-autonomous environment. In addition, the A / D converter (analog / digital converter) contained in the radio chip is usually clocked by a clock generator, so the sampling rate of the radio chip can only be adjusted very imprecisely. On the other hand, efforts are being made to provide radio receivers with the greatest possible range, especially for the aforementioned applications. Closest state of the art

[0004] US 2008 / 232511 A1 discloses an apparatus and method for processing signals, comprising receiving an input signal and forming a stream of digital samples of the input signal by sampling at a sampling frequency, and mixing the stream of digital samples using a mixing sequence comprising a sine sequence and a cosine sequence based on the sampling frequency to generate an input sequence, each of the sine sequence and the cosine sequence containing a plurality of components in an arrangement such that at least one of the components has a zero value and the remaining components have a non-zero value, and filtering the input sequence using a plurality of polyphase filter parts, each corresponding to the non-zero components of the sine sequence and the cosine sequence, and selectively combining the outputs of the polyphase filter parts,to generate an in-phase sequence and a quadrature sequence.

[0005] DE 10 2004 052897 A1 describes a radio receiver (10) for receiving a data burst transmitted by a transmitter, wherein the data burst comprises a first section which has been modulated on the transmitter side using a first modulation method, and a second section which has been transmitted after the first section and which has been modulated on the transmitter side using a second modulation method, and the radio receiver (10) has a first reception path (12) for processing the first section and a second reception path (13) for processing the second section.

[0006] EP 2 469 717 A2 discloses a software radio receiver (11) used to acquire digital measured values ​​(17) via a signal processor (15) from demodulated and digitized data reception signals (16). This receiver can be operated in power-saving mode or with an increased range. In the latter case, a significant portion of the detection algorithms is relocated to a programmable or application-specific digital logic module (18) connected upstream of the signal processor (15). The otherwise bypassed function of the digital logic module is enabled by activating its configuration memory (22) by opening a bypass switch (19).

[0007] EP 3 002 560 B1 discloses a battery-operated stationary terminal (or sensor arrangement) for implementing wireless unidirectional transmission. The terminal comprises a sensor for detecting sensor data and for providing a sensor data packet based on the sensor data. By means of a device for generating data packets, the sensor data packet is divided into at least three data packets, each of the data packets being shorter than the sensor data packet itself. In addition, the sensor arrangement comprises a device for transmitting data packets, which is intended to transmit the data packets at a data rate of less than 50 kbit / s and at a time interval over a communication channel. Due to the low data rate compared to conventional data rates of 100 kbit / s, the signal-to-noise ratio at a data receiver (concentrator) can be reduced.In addition, the data packets are channel-coded by the data packet generation device in such a way that only a portion of the data packets is required to decode the sensor data packet. Thus, the use of such a terminal device increases the transmission range from the terminal device to the concentrator. However, the use of such a terminal device cannot improve the data transmission quality during transmission from the concentrator to the terminal device.

[0008] The object of the present invention is therefore to provide a radio receiver, in particular for a generic terminal, with improved data transmission quality and at the same time optimized power consumption. Solution to the task

[0009] The above object is achieved by a radio receiver according to claim 1. Advantageous embodiments of the invention are mentioned in the further claims.

[0010] A radio receiver according to the invention can be a radio receiver of the SDR type. Within the meaning of the invention, the SDR type encompasses concepts for high-frequency transmitters and receivers in which smaller or larger portions of the signal processing are implemented using software. For this purpose, the radio receiver comprises a receiving device (e.g., a radio chip) that receives the data in the form of at least one data packet or a portion thereof (partial data packet) or a data stream at a specific data rate and makes it available for further processing. In particular, the data stream can be a continuous or semi-continuous (i.e., interrupted) data stream.

[0011] By diverting the data in operating mode A within the receiving device and feeding it to a microcontroller, by the microcontroller or receiving device decimating the data by selecting only a portion from the sample set, and by the microcontroller temporarily storing the decimated data in a memory and making it available for further processing, data can be fed for further processing without requiring significant computing power from the microcontroller and without resampling. This requires comparatively little electrical energy, thus placing only a minimal load on the self-sufficient power source. This improves data transmission quality while simultaneously reducing or optimizing power consumption.

[0012] Conveniently, the receiving device includes a filter that filters the data before it is fed to the microcontroller, thus reducing unnecessary computing operations on the part of the microcontroller. As a result, data transmission quality is further improved and energy consumption is reduced.

[0013] Furthermore, the microcontroller can decimate the data by ignoring individual samples from the sample set, i.e., discarding them, and selecting the samples based on an integer decimation factor. This reduces the number of samples transmitted, which can also reduce the bandwidth for transmitting the data between the receiving device and the microcontroller. The sampling rate thus represents the maximum possible unfiltered bandwidth between the receiving device and the microcontroller and preferably corresponds to an integer factor of the bandwidth used (filtered) after the filter.

[0014] It has proven particularly advantageous if the bandwidth of the data provided to the microcontroller or the bandwidth used after the filter is preferably less than 200 kHz, preferably less than 100 kHz and particularly preferably less than 50 kHz.

[0015] Because different sampling rates can be set on the microcontroller for different bandwidths, data transmission can be adapted to different or abruptly changing transmission conditions. The radio system can support different data rates, for example, to adapt to abruptly changing transmission conditions. Different data rates therefore require different sampling rates and thus bandwidths. This further improves data transmission quality.

[0016] A clock generator is preferably provided, preferably a quartz crystal or an oscillator with an RF quartz crystal or quartz crystal. The sampling rate is preferably determined by the clock frequency (or quartz frequency) of the clock generator. The clock generator can also serve as the clock generator of the analog-to-digital converter, so that the latter can be clocked differently by changing the clock frequency or by selecting a clock generator with a specific clock frequency. The clock frequency is set or selected, taking the decimation factor into account, in such a way that the desired sampling rate is achieved. This prevents complex resampling by the microcontroller.

[0017] It has proven particularly advantageous if the clock frequency of the clock generator is between 20 MHz and 50 MHz, preferably between 23 MHz and 25 MHz, 38 MHz and 40 MHz or 47 MHz and 49 MHz, particularly preferably 24 MHz, 39 MHz or 48 MHz.

[0018] The sampling error that occurs during sampling can be advantageously modified by selecting the clock frequency of the clock generator. Preferably, the clock frequency is reduced.

[0019] It is particularly expedient if the error of the clock generator or the quartz after the change of the clock frequency is less than 10 ppm, preferably less than 5 ppm, particularly preferably less than 3 ppm.

[0020] For convenience, operating mode A can be switched on and off by the radio receiver. This offers the advantage that the reception, forwarding, and further processing of data can be performed selectively via operating mode A, and can also be switched on and / or off during operation, allowing flexible response to changes in the transmission or processing sequence. This significantly improves data transmission quality and processing reliability.

[0021] According to the invention, in addition to operating mode A, an operating mode C is provided, in which the data is processed by a microprocessor or a logic or digital receiving circuit that is connected downstream of the receiving device and / or is part of the receiving device. It is particularly advantageous if the radio receiver is designed such that it can switch between operating mode A and operating mode C. This can be achieved by means of a switching device that, according to the invention, is an integral part of the receiving device.

[0022] Preferably, the transmission of data between the receiving device and the microcontroller takes place piece by piece, i.e. step by step, with time intervals being provided between the transmission steps of the data in which no transmission takes place.

[0023] According to a preferred embodiment, the microcontroller can enter standby or sleep mode during time intervals in which no data is being transmitted, in order to reduce energy consumption during these periods. This allows for significant energy savings and thus, for example, increases the operating time or durability of a battery-operated, energy-autonomous device.

[0024] For practical purposes, the microcontroller can also be configured to decode the data. This eliminates the need for an additional decoder.

[0025] Alternatively or additionally, it is also possible for the microcontroller to be designed to process higher layers (particularly of the OSI layer model). For example, the microcontroller can also take over program and / or process functions of the end device, such as sensor control or the evaluation of sensor readings. This eliminates the need for an additional microcontroller to control the sensors, significantly reducing energy consumption and manufacturing costs.

[0026] Conveniently, the receiving device, the microcontroller, and / or the decoder can be designed as a common structural unit. It has proven particularly advantageous if the receiving device, the microcontroller, and / or the decoder are designed as an integrated circuit (IC). This results in the advantage that it can be installed easily and particularly cost-effectively in / on the radio receiver.

[0027] After entering the receiving device, the data is processed using the I / Q method (in-phase / quadrature method), meaning that, according to the invention, the data is digital I / Q data. This can be achieved, for example, by splitting the analog input signal into two signal components, with one signal component being generated with the original phase position (I data) and the other signal component being generated with a reference frequency phase-shifted by 90° (Q data).

[0028] The SDR-type radio receiver is intended for use in an energy-autonomous, preferably long-term energy-autonomous, environment. Energy-autonomous or long-term energy-autonomous within the meaning of the invention refers in particular to an operating mode in which the radio receiver or the terminal device comprising the radio receiver operates without an external energy supply and can carry out or maintain operation independently. The energy required for operation is preferably obtained from an energy storage device or an energy source. A battery is preferably provided as the energy source, which is installed within the radio receiver or the terminal device and optionally encapsulated in a dust- and watertight manner. In particular, the battery capacity is less than 20 Ah.Furthermore, means for generating electrical energy (energy harvesting) can also be provided, whereby the electrical energy required for operation is obtained, in particular, from air flow, ambient lighting, ambient temperature, or vibrations (e.g., through piezoelectric effects). Advantageously, a combination of battery and energy harvesting can also be provided, which allows for further optimization of power consumption, particularly in the present SDR concept.

[0029] Furthermore, the present invention claims a radio receiver of the SDR type for use in an energy-autonomous, preferably in a long-term energy-autonomous environment, with a receiving device which receives the data in the form of at least one data packet or a part thereof or in a data stream at a specific data rate (and / or at a specific sampling rate) and makes it available for further data processing. The data is fed to a microprocessor or a digital receiving circuit (logic) of the receiving device in an operating mode B. The data is then filtered by the microprocessor or the digital receiving circuit and then decimated by selecting a part from the sample set by the microprocessor or the digital receiving circuit. In practice, the decimation can be carried out, for example, by the microprocessor and the algorithm or signal processing (e.g.Decoding, demodulation, and / or the like) can be performed by the microcontroller. Alternatively or additionally, the microprocessor can also perform the algorithms or signal processing.

[0030] Conveniently, operating mode B can be switched on and off by the radio receiver. According to the invention, in addition to operating mode B, operating mode C is also provided, whereby the radio receiver can switch between operating mode B and operating mode C using the switching device. According to the invention, the data is I / Q data.

[0031] Another co-claimed radio receiver is a radio receiver of a type in which the signal processing is implemented at least substantially, but preferably exclusively, by hardware (e.g., as a prefabricated hardware module). Accordingly, it is explicitly not an SDR-type radio receiver. This radio receiver can, for example, be designed entirely as an application-specific integrated circuit (ASIC).

[0032] The function of the radio receiver can therefore no longer be changed via software. The use of such a radio receiver can significantly reduce manufacturing costs. The radio receiver comprises a clock generator, in particular a quartz crystal. By selecting the clock generator with an appropriate clock frequency, the sampling error is changed, in particular reduced. Consequently, the sampling error can be determined or influenced by selecting the clock frequency or the clock generator with a specific clock frequency. The radio receiver can preferably also be designed such that it can be operated in operating modes A, B, and / or C.

[0033] In addition, the present invention claims a communication system for transmitting data between at least one concentrator and several, in particular a plurality of, energy-autonomous terminal devices. Each terminal device comprises a radio receiver with a receiving device, which receives the data from the concentrator in the form of at least one data packet, preferably a plurality of individual data packets, at a specific data rate (and / or at a specific sampling rate) and makes it available for further data processing. Furthermore, a radio receiver according to the invention is provided as the radio receiver, which branches off the data in an operating mode A within the receiving device and feeds it to a microcontroller at a preferably definable sampling rate. The microcontroller or the receiving device decimates the data by selecting a portion from the sample set.The microcontroller then temporarily stores the decimated data in a memory and makes it available for further processing, for example. Alternatively or additionally, the radio receiver can also feed the data to a microprocessor or a digital receiving circuit in an operating mode B, and the data can be filtered by the microprocessor or digital receiving circuit and then decimated by selecting a portion from the sample set. Description of the invention based on exemplary embodiments

[0034] Advantageous embodiments of the present invention are explained in more detail below with reference to the drawing figures. They show: Fig. 1 shows a simplified schematic representation of a communication system consisting of several terminal devices and a concentrator; Fig. 2 shows a simplified schematic representation of data that is sent in the form of several data packets; Fig. 3 shows a simplified schematic representation of a radio receiver according to the prior art; Fig. 4 shows a simplified schematic representation of a first embodiment of the radio receiver according to the invention; Fig. 5 shows a simplified schematic representation of a further embodiment of the radio receiver according to the invention; Fig. 6 shows a simplified schematic representation of a further embodiment of the radio receiver according to the invention; Fig. 7 shows a simplified schematic representation of a further embodiment of the radio receiver according to the invention; Fig. 8 shows a simplified schematic representation of a further embodiment of the radio receiver according to the invention;Fig. 9 shows a simplified schematic representation of different operating modes; Fig. 10 shows a simplified schematic representation of a further embodiment of the radio receiver according to the invention, and Fig. 11 shows a simplified schematic representation of a further embodiment of the radio receiver according to the invention.

[0035] Fig. 1shows a communication system according to the invention, in which several terminal devices 11, each with an integrated radio receiver 10 of the SDR (Software Defined Radio) type, communicate wirelessly with a transmitting and receiving unit 13 of a data collector 12. The terminal devices 11 can be, for example, consumption measuring devices, such as gas, water, heat, or energy meters, sensor units, such as level sensors or temperature measuring devices, or other sensor nodes, e.g., of an IoT (Internet of Things) application. The receiving device 1 can be configured as a radio chip, SoC (System-on-Chip), SoS (System-on-Silicon), SIP (System-in-Package), or the like. The terminal device 11 or the receiving device 1 is expressly not a gateway. The data collector 12 is designed in such a way that it can transmit the data 2 to the terminal devices 11 via the transmitting and receiving unit 13 and / or receive it from them.

[0036] The data 2 can be, for example, operating data or program update data or firmware update data, which are transmitted in particular from the data collector 12 to the terminal devices 11. The data collector 12 can receive the data 2, for example, from a higher-level central unit (not shown in the figures), store it in a data memory 14 and then send it to the terminal devices 11. The data 2 are, as in Fig. 2 shown, transmitted in the form of at least one data packet, preferably a plurality of data packets 2a.

[0037] In Fig. 3A generic radio receiver 110 known from the prior art is shown. The data 2 or data packets 2a are received and demodulated in an operating mode C by a receiving device 101 of the radio receiver 110 as an analog input signal. An analog-to-digital converter (not shown in the figures) is provided to convert the analog input signal into a digital data stream. A microprocessor 115 assigned to or connected downstream of the receiving device 101 serves for further processing and / or forwarding of the data 2. Furthermore, the radio receiver 110 has an oscillator or clock generator, which serves to determine the frequency used.

[0038] In Fig. 4An embodiment of the radio receiver 10 according to the invention is shown. The radio receiver 10 comprises a receiving device 1 and a microcontroller 3 and is preferably designed as a common structural unit, such as an integrated circuit (IC). According to the invention, the data 2 or data packets 2a, which are received as an analog signal, are branched off within the receiving device 1 and fed to the microcontroller 3 via an interface 1a. The receiving device 1 prepares the data in such a way that complex computing operations of the microcontroller 3 are reduced or even prevented and no significant deterioration, e.g., due to aliasing, occurs. This is achieved by first digitizing the data 2 by means of the analog-to-digital converter (not shown in the figures), which is preferably arranged within the receiving device 1, and then filtering it via a filter 6 of the receiving device 1.The digitized data is made available to the microcontroller 3 with a bandwidth that is the same or lower than the sampling rate, e.g., less than 50 kHz. The filter 6 then pre-filters the data 2 in such a way that the microcontroller 3 no longer needs to perform any filtering. The sampling rate describes the frequency with which the analog signal (a continuous-time signal) is sampled in one second, i.e., measured and converted into a discrete-time signal. For example, a value of 2 kHz or 4 kHz indicates that 2000 or 4000 samples are taken within one second, respectively. The sampling rate to the microcontroller 3 specifies the bandwidth, i.e., the sampling rate represents the maximum adjustable unfiltered bandwidth between the receiving device 1 and the microcontroller 3.For example, with a sampling rate of 20 kHz, a maximum bandwidth of 20 kHz is theoretically possible, but due to the filtering of filter 6 with a bandwidth of only 10 kHz, 3 is transmitted to the microcontroller (factor = 2).

[0039] The bandwidth during the transmission of data 2 from the receiving device 1 to the microcontroller 3 is thus equal to or lower than the sampling rate. This can be achieved, in particular, by the microcontroller 3 decimating the data 2 within a decimation unit 7 using a definable decimation factor N, i.e., the microcontroller 3 selects a portion from the sample set supplied by the receiving device 1. The decimation factor N is preferably an integer, such as 2, 3, or 4. For example, with a decimation factor N=2, the microcontroller 3 omits every second sample, so that the bandwidth is a factor of 2 smaller than the sampling rate.

[0040] Alternatively or in addition to the filter 6, the microcontroller 3 may also have a filter 8, as shown in Fig. 5shown. The microcontroller 3 can then store or temporarily store the decimated data in a memory 4, e.g. in blocks, in order to make it available for further processing, for example. The quartz oscillator 5 serves as a clock generator for the frequency processing and the carrier frequency, as well as for clocking the analog-to-digital converter. Either an external unit or a structure functionally associated with the receiving device 1 can be provided as the clock generator. The sampling rate is determined in particular by changing the clock frequency of the quartz oscillator 5 accordingly or by selecting the quartz oscillator 5 according to its clock frequency in order to clock the analog-to-digital converter accordingly. The clock frequency is determined in such a way that the quartz oscillator 5 specifies the desired sampling rate together with the divider or the decimation factor N.Additional filtering on the microcontroller 3 side or energy-consuming resamples are therefore not necessary.

[0041] After entering the receiving device 1, the data 2 is processed using the I / Q method (in-phase quadrature method), i.e., it is converted into I / Q data (digital data). This is achieved by splitting the analog input signal into two signal components, with one signal component being demodulated with the original phase position (I data) and the other signal component being demodulated with a reference frequency phase-shifted by 90° (Q data). The I / Q data is then passed from the receiving device 1 to the microcontroller 3. The microcontroller 3 can then further process the data within the framework of an algorithm or use it for signal processing.

[0042] The mode of operation, as in Fig. 4 and Fig. 5The first operating mode A, for example, can be switched on and off in the radio receiver 10 during operation. In addition to the operating mode A, the operating mode C can also be provided, which Fig. 4 and 5 is shown by the dashed arrow. In this embodiment of the radio receiver 10, operating mode A and operating mode C can be selected or switched between using a selection or switching device 9.

[0043] The design of the radio receiver according to Fig. 6is operated using an operating mode C. For this purpose, the receiving device 1 comprises a microprocessor 15, which can alternatively also be designed as a digital receiving circuit. The microprocessor 15 is part of an RF front-end with an A / D converter (not shown in the figures for the sake of clarity). In addition, the microprocessor 15 can comprise the filter 6 and its own memory, in particular a RAM memory 16. Alternatively or additionally, as in Fig. 7 As shown, a common (RAM) memory 18 may be provided, which the microcontroller 3 and the microprocessor 15 can access, e.g., via a BUS system. Furthermore, an additional operating mode may also be provided, which Fig. 6 and 7as shown by way of example using the dashed lines and arrows. Switching between operating mode B and the additional operating mode can optionally also be performed during operation using the switching device 9.

[0044] Fig. 8shows a further alternative embodiment of the present invention, in which the microprocessor 15 of the receiving device 1 comprises the filter 6 and additionally has a decimation unit 17, i.e. the microprocessor 15 filters and decimates the data before making it available to the microcontroller 3 for signal processing and / or storing it in the memory 18. Equipping the microcontroller 3 with a filter 8 and a decimation unit 7 is optional here. Preferably, the microcontroller 3 has greater efficiency for the required work steps or is more powerful than the microprocessor 15. However, the algorithms or signal processing can also be carried out by the microprocessor 15, provided that it already has the required processing efficiency.

[0045] Furthermore, Fig. 9Different operating modes I, II, and III of the radio receiver 10 are shown. The receiving device 1 or the microprocessor 15 first performs filtering using the filter 6. The filter 6 can, in particular, be a high-pass, low-pass, or band-pass filter. If the filtering for decimation has been carried out sufficiently well, the data can be transmitted to the microcontroller 3 according to operating mode I, which decimates them by the decimation factor N (e.g., 2 or 4) using the decimation unit 7 by only using every Nth sample and discarding the remaining samples. The microcontroller 3 can then perform the algorithm or signal processing.In the event that the filtering for decimation could not be carried out sufficiently well, the data is first filtered in the microcontroller 3 using the filter 8 in accordance with operating mode II in order to obtain at least sufficient filtering, and then decimated by the decimation unit 7. Furthermore, the data can also be filtered according to operating mode III by the microprocessor 15 or a digital receiving circuit of the receiving device 1 via the filter 6 and then decimated by the decimation 17 of the microprocessor 15. The decimated data are then transmitted to the microcontroller 3 for algorithms or signal processing, or the algorithms or signal processing can be carried out immediately by the microprocessor 15. In particular, operating modes I and II can be implemented, for example, via operating mode A, and operating mode III, for example, via operating mode B.

[0046] In Fig. 10A further radio receiver 210 according to the invention is shown, which is a radio receiver of a type in which the signal processing is implemented exclusively by hardware. The radio receiver 210 is designed entirely as an application-specific integrated circuit (ASIC). Furthermore, a clock generator, in particular a quartz oscillator 5, is provided. In this case, the sampling error is changed, in particular reduced, by selecting the clock generator based on its clock frequency. Preferably, the selection of the clock generator can already take place during the manufacturing process. Furthermore, the radio receiver 210 can also be designed according to Fig. 11be designed such that it can implement operating mode A as well as additionally operating mode C (dashed arrow). As an alternative to the externally connected quartz oscillator 5, the radio receiver 210 can also comprise an internal clock generator, such as an integrated oscillator circuit, as a clock generator. In a practical manner, the present invention also encompasses embodiments of the radio receiver 210 (not shown) that are designed to implement operating modes A, B and / or C and / or operating modes I, II and / or III, in particular in the manner described above.

[0047] The disclosure content also expressly includes combinations of individual features (sub-combinations) as well as possible combinations of individual features of different embodiments not shown in the drawing figures. LIST OF REFERENCE SYMBOLS

[0048] 1Receiving device 1aInterface 2Data 2aData packet 3Microcontroller 4Memory 5Quartz 6Filter 7Decimation unit 8Filter 9Switching device 10Radio receiver 11Terminal device 12Concentrator 13Transmitting and receiving unit 14Data memory 15Microprocessor 16RAM memory 17Decimation 18Common memory 101Receiving device 105Quartz oscillator 110Radio receiver 115Microprocessor 210Receiving facility

Claims

1. Radio receiver (10) for use in an environment that is self-sufficient in terms of energy over the long term, wherein the radio receiver (10) comprises a receiving device (1) which receives data (2) in the form of at least one data packet or a portion thereof or a data stream at a certain data rate and provides said data for further data processing, characterized in that the radio receiver (10) comprises a microcontroller (3), wherein, in an operating mode A that can be selected via a switchover device (9), the received, or received and filtered, data (2) are diverted within the receiving device (1) and the data (2) are supplied in the form of I / Q data to the microcontroller (3) at a sampling rate which can be defined, the microcontroller (3) or the receiving device (1) decimates the data in the operating mode A by selecting a portion from the set of samples, and the microcontroller (3) buffers the decimated data in a memory (4, 18) in the operating mode A and provides said data for further processing, wherein an operating mode C that can be selected via the switchover device (9) is provided in addition to the operating mode A, in which operating mode C the data are processed by a microprocessor (15) or a logic unit or digital receiving circuit that is connected downstream of the receiving device (1) and / or is part of the receiving device (1).

2. Radio receiver (10) according to Claim 1, wherein, in an operating mode B that can be selected via the switchover device (9), the received, or received and filtered, data (2) are supplied to the microprocessor (15) or to the digital receiving circuit, and the data (2) are filtered by the microprocessor (15) or the digital receiving circuit in the operating mode B and are then decimated by selecting a portion from a set of samples.

3. Radio receiver (10) according to Claim 1 or 2, which is of the SDR type and / or which is characterized in that a clock generator, in particular a crystal oscillator (5), is provided, and in that preferably the sampling rate is defined by the clock frequency of the clock generator.

4. Radio receiver (210) according to Claim 1 or 2, which is of a type in which the signal processing is implemented at least mainly, preferably entirely, by hardware, wherein a clock generator, in particular a crystal oscillator (5), is provided, and the sampling error is modified, in particular reduced, by selecting the clock generator on the basis of its clock frequency.

5. Radio receiver according to one of the preceding claims, characterized in that the receiving device (1) comprises a filter (6) that filters the data (2) before supplying them to the microcontroller (3), wherein provision is made, in particular, for the bandwidth at which the data (2) are supplied to the microcontroller (3) after the filter (6) to be preferably less than 200 kHz, preferably less than 100 kHz and particularly preferably less than 50 kHz.

6. Radio receiver according to one of the preceding claims, characterized in that the microcontroller (3) comprises a filter (8) that filters the data (2) before decimation.

7. Radio receiver according to one of the preceding claims, characterized in that the data (2) are decimated by the microcontroller (3) by the microcontroller (3) disregarding individual samples of the set of samples supplied by the receiving device (1), and the samples being selected on the basis of an integer decimation factor.

8. Radio receiver according to one of the preceding claims, characterized in that different sampling rates can be defined at the microcontroller (3) for different bandwidths.

9. Radio receiver according to one of the preceding claims, characterized in that the clock frequency of the clock generator is between 20 MHz and 50 MHz, preferably between 23 MHz and 25 MHz, 38 MHz and 40 MHz or 47 MHz and 49 MHz, particularly preferably 24 MHz, 39 MHz or 48 MHz.

10. Radio receiver according to one of the preceding claims, characterized in that the error in the clock frequency of the clock generator is less than 10 ppm, preferably less than 5 ppm, particularly preferably less than 3 ppm.

11. Radio receiver according to one of the preceding claims, characterized in that the operating mode A and / or the operating mode B can be enabled and disabled.

12. Radio receiver according to one of the preceding claims, characterized in that an operating mode C is provided in addition to the operating mode A or the operating mode B, in which operating mode C the data (2) are processed by a microprocessor (15) or a digital receiving circuit of the receiving device (1) before being transferred to the microcontroller (3), and it is possible to switch between the operating mode A or operating mode B and the operating mode C.

13. Radio receiver according to one of the preceding claims, characterized in that the data (2) are transferred between the receiving device (1) and the microcontroller (3) in steps, and time intervals in which no transfer takes place are provided between the transfer of the data, wherein provision is made, in particular, for the microcontroller (3) to shift into a sleep mode in the time intervals in which no data (2) are transferred.

14. Radio receiver according to one of the preceding claims, characterized in that the microcontroller (3) is configured to decode the data (2).

15. Radio receiver according to one of the preceding claims, characterized in that the microcontroller (3) is configured to process also higher layers in addition to processing and storing the data (2).

16. Radio receiver according to one of the preceding claims, characterized in that the receiving device (1) and the microcontroller (3) are embodied as a common structural unit, in particular as an integrated circuit.

17. Radio receiver according to one of the preceding claims, characterized in that the radio receiver (10, 210) comprises an energy source for supplying energy, in particular a battery having a capacity of less than 20 Ah.

18. Communication system for transferring data (2) between at least one concentrator (12) and a plurality of, preferably a multiplicity of, terminals (11) that are self-sufficient in terms of energy, wherein each terminal (12) comprises a radio receiver (10, 210) having a receiving device (1), the receiving device (1) receives the data (2) from the concentrator (12) in the form of at least one data packet or a portion thereof or a data stream at a certain data rate and provides said data preferably for further data processing, characterized in that a radio receiver (10, 210) according to at least one of the preceding claims is provided as the radio receiver.