Near-healing procedure according to a hyperatmospheric method in a diffusion-promoting environment

Description

BACKGROUND Field

[0001] Embodiments of the present disclosure generally relate to integrated circuit fabrication methods, and in particular, to correcting seam defects in trenches or vias.Description of the Related Art

[0002] Many obstacles exist in the further miniaturization of semiconductor components. One such obstacle is the filling of metal interconnects, which affects the yield of modern CMOS devices. Metal interconnect signal lines make contact to lower conductive layers of the integrated circuit through vias that are formed in an insulating layer. It is desirable to fill the contact and interconnect with the metal that is used to form the interconnect layer so as to insure optimal operation of the device.

[0003] Conductive metals, such as copper, are presently the materials of choice for the fabrication of interconnect lines in integrated circuits. Conventional techniques used to fill interconnect lines generally include physical vapor deposition, PVD, or atomic layer deposition, ALD, of a barrier material, followed by a liner and then either copper reflow or electroplating.

[0004] When using conventional techniques, problems arise in the interconnect lines from the accumulation of relatively large grains of material at the upper surface of an insulating layer, as well as the accumulation of impurities within the conductive bulk. The accumulation of such grains at the edges of the contact via or interconnect can block or otherwise obstruct the contact or interconnect prior to completely filling the contact or interconnect, resulting in the formation of voids, seems, and uneven structures within the contact or interconnect. The aforementioned problem is particularly acute as integrated circuits are fabricated using smaller geometries.

[0005] The smaller contacts that are used in smaller geometry devices, such as contacts or interconnects in the tens of nanometers or less range, necessarily have a larger aspect ratio (i.e., relationship of feature height to width) than do larger geometry devices, thereby exacerbating the contact-filling or interconnect-filling difficulties described above. For example, unduly large voids can result in line resistance and contact resistance that are appreciably higher than designed. In addition, thinner regions of the conductive material adjacent to the contact or interconnect fill region will be subject to electro migration, which can result in the eventual opening of the circuits and failure of the device.

[0006] WO 2015 / 196081 A1describe removing seams and voids in metal interconnects and associated techniques and configurations. An interconnect structure formed by depositing a metal may be further coupled with other similarly configured interconnect structures. The metal may be a non-copper metal having a melting point that is greater than a melting point of copper (e.g., greater than 1085°C). For example, the metal may be composed of ruthenium (Ru), molybdenum (Mo), tungsten (W) and / or cobalt (Co), equivalents, or combinations thereof. In some embodiments, the metal 304 may be composed of rhenium (Re), iron (Fe), osmium (Os), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pd), platinum (Pt), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr) and / or technetium (Tc), equivalents, or combinations thereof. The metal may be exposed to a temperature ranging from 300°C to 800°C for a time period ranging from 5 minutes to a couple of hours, under atmospheric pressure (~1 atm), in the presence of forming gas comprising hydrogen. Further, for example, the pressure may range from 1 atm to 10 atm or the hydrogen concentration may be greater than 5% by volume in some embodiments.

[0007] JP 2010 080949 describes a copper film annealing method which can improve reliability of copper wiring by reducing an electric resistance of copper wiring, stabilizing it, and removing an impurity. The annealing method may have an amount of hydrogen added that is preferably at least 0.01% by weight, more preferably at least 0.04% by weight, and particularly preferably at least 0.1% by weight, based on the amount of carbon oxide.

[0008] To address the above issues, other materials and deposition techniques have been considered. When using other fill techniques such as chemical vapor deposition, CVD, cyclical deposition / treat processes are employed. One approach utilizes multiple cycles of deposition and anneal in attempt to repair seams and cavities in the conductive material in low-to-sub atmospheric pressures process regimes. This approach results in extremely slow process time, and attempts to reduce process time have resulted in unsatisfactory resistivity. In other approaches, the deposited metal is subjected to extremely high pressures, such as 700 bar to 2000 bar, or more, wherein 1 bar = 0.1 MPa, in attempt to repair defects in the conductive material. The exerted pressure forces the deposited metal into the undesired voids within the deposited film. However, subsequent thermal post treatment to correct grain boundary defects or other defects results in partial or full reformation of the void. In addition, the pressures utilized in conventional approaches may result in physical damage to low-k dielectric materials adjacent the interconnect.

[0009] Therefore, this is a need for an improved method of correcting seam defects.SUMMARY

[0010] According to the present invention, a method of treating a substrate is provided as described in claim 1. Preferred embodiments of the inventions are provided in the dependent claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0011] So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only exemplary embodiments. Figure 1 is a flow diagram of a method for processing a substrate. Figure 2A is a schematic sectional view a substrate having interconnects that include one or more defects from a gap-fill process. Figure 2B is a schematic sectional view of the substrate of Figure 2A after processing.

[0012] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.DETAILED DESCRIPTION

[0013] Aspects of the disclosure include methods of treating a substrate to remove one or more of voids, seams, or grain boundaries from an interconnect formed on the substrate. The method includes heating the substrate in an environment pressurized at a pressure of 12 bar to 15 bar.

[0014] Figure 1 is a flow diagram of a method 100 for processing a substrate, according to one embodiment of the disclosure. Figure 2A is a schematic sectional view of a substrate having interconnects that include one or more defects from a gap-fill process. Figure 2B is a schematic sectional view of the substrate of Figure 2A after processing. To facilitate explanation of aspects of the disclosure, Figures 2A and 2B will be explained in conjunction with Figure 1.

[0015] Method 100 begins at operation 101. In operation 101, a substrate 210a is positioned in a process chamber. The substrate 210a includes one or more trenches 211 (two are shown) having a conductive material 212 deposited therein to form interconnects. The conductive material 212, which comprises cobalt or ruthenium, is a metal, which may be deposited by CVD, PVD, ALD, plating, or other deposition methods. During deposition of the conductive material 212, one or more of a seam 213, a void 214, or grain boundaries 215 may form. The seams 213, the voids 214, and the grain boundaries 215 negatively affect performance of the interconnects by increasing electrical resistance of the interconnects.

[0016] In operation 102, the substrate 210a is exposed to a hydrogen-containing atmosphere at a predetermined pressure. The hydrogen-containing environment includes hydrogen gas and one or more non-reactive gases, such as diatomic nitrogen or argon. Hydrogen is present within a range of 3.5 atomic percent to 4.5 atomic percent. In one example, hydrogen is present at 4 atomic percent. It is contemplated that a lower atomic percentage of hydrogen may dictate longer processing times or elevated temperatures, while higher atomic percentages of hydrogen may dictate the use of additional hardware, such as interlocks. In another example, deuterium may be used in place of, or in combination with, hydrogen in the atomic percentages described above.

[0017] The presence of hydrogen in the atmosphere of the process chamber weakens the surface bounds of the conductive material 212 to facilitate flow of the conductive material 212 into the voids 214. A supra-atmospheric pressure (e.g., a pressure greater than atmospheric pressure) is maintained in the process chamber while exposing the substrate 210a to the hydrogen-containing environment. The pressure within the process chamber is maintained within a range of 12 bar to 15 bar, wherein 1 bar = 0.1 MPa. The application of increased pressure in the presence of the hydrogen-containing environment facilitates movement of the conductive material 212 into the voids 214. In addition, the application of increased pressure may facilitate introduction of hydrogen into seam 213, the void 214, or even along the grain boundary 215, to remove contaminants trapped therein. Contaminants may be present as a result of the deposition process of the conductive material 212, or from sources within the process chamber. The presence of the contaminants within the conductive material 212 may further increase electrical resistance.

[0018] In operation 103, the substrate 210a is heated to a predetermined temperature. The predetermined temperature is 250 degrees Celsius to 400 degrees Celsius, such as 300 degrees Celsius to 400 degrees Celsius, for example, 400 degrees Celsius. It is contemplated that temperatures above about 400 degrees Celsius may adversely the structure of the substrate 210a adjacent to the conductive material 212. For example, excess temperatures may physically disrupt material adjacent the conductive material 212, resulting in leakage of electrical current. In one example, the temperature of the substrate remains below the melting point of the conductive material 212. Even though the melting point of the conductive material 212 may not be reached in aspects described herein, the elevated temperature in the presence of the elevated pressure and the hydrogen gas still facilitates atomic movement of the conductive material 212. Thus, filling of the voids 214 is promoted.

[0019] The increased temperature, in combination with the increased pressure and the hydrogen-containing environment, facilitate movement of the conductive material 212 into voids 214, while simultaneously healing or repairing any seams 213, reducing grain boundaries 215, and increasing grain size. The removal of seams 213, voids 214, and grain boundaries 215 occurs in a single operation after complete deposition of the conductive material 212.

[0020] In contrast, one known approach uses cyclical treatment / deposition processes, in which a small amount of material is deposited in a trench, such as about 20 angstroms to about 100 angstroms, and then the material is treated. This previously-attempted approach is very inefficient and time consuming due to the number of processes required. In addition, the treatment process of such an approach is a multiple step process, further increasing the number of operations which are performed.

[0021] In the multi-cycle treatment process, the substrate is first exposed to high temperatures to weaken the conductive material and merge grains through multi-iteration deposition and treatment cycles, which is very time consuming. Alternatively, the conductive material is subjected to high temperatures after subjecting the conductive material to high pressures (to close a void), which allows the voids to reopen or reform. The very high pressures utilized in previous approaches result in damage to the substrate adjacent the conductive material, due to the excessive force applied to the conductive material and transferred to the substrate.

[0022] However, the inventors of the present disclosure have discovered that pressures within a range of 12 bar to 15 bar, in combination with simultaneous elevated temperatures and hydrogen gas, provides significant improvements over existing approaches. Specifically, seams and voids are repaired, and grain boundaries are reduced, in a single operation which does not subject the substrate 210a to undesirably elevated pressures. Notably, the pressure within a void 214 is about 1×10 -8< bar when formed by a PVD process, and the inventors have determined that a pressure within a range of 12 bar to about 15 bar, is sufficient to facilitate repair of seams 213 and voids 214. Thus, the extremely high pressures of conventional approaches, and the undesired consequences thereof, are avoided by aspects of the disclosure. Additionally, unlike existing approaches, the aspects described herein can repair seam, void, and grain defects after completely depositing the conductive material 212. Thus, aspects described herein are not subject to cyclical deposition-treatment, resulting in reduced process time per substrate.

[0023] Figure 2B schematically illustrates the substrate 210b after operation 103. As illustrated, method 100 has removed the grain boundaries 215, resulting in a single grain structure. Additionally, method 100 has also removed the seams 213 and the voids 214. The resulting conductive material 212 has a lower resistance than the conductive material illustrated in Figure 2A.

[0024] Figure 1 illustrates a method of treating a substrate; however, additional embodiments are also contemplated. In another aspect, operations 102 and 103 may occur simultaneously or in reverse order.

[0025] Benefits of the aspects of the disclosure include reduced processing time since seams, voids, and grain boundaries can be corrected in a single operation, rather than in multiple cycles as occurs in existing processes. Additionally, aspects described herein can be performed using less expensive hardware as compared to hardware configured for significantly higher pressures, since significantly lower pressures are utilized in aspects of the disclosure. Additionally, the enhanced flow conditions of conductive metals when processed as described herein may facilitate the use of thinner liners, thus reducing materials expenses and allowing smaller geometries. In some instances, it is contemplated that the liner may be completely excluded. Aspects of the disclosure should not be limited to examples described herein, and may be applied to any instance of metal fill, such as 3D-NAND gate fill, CMOS logic gate fill, bit lines for memory devices, and the like.

[0026] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the scope determined by the claims that follow.

Claims

1. A method of treating a substrate, comprising: positioning the substrate (210a) in a process chamber, the substrate having an interconnect formed thereon, the interconnect including a conductive material having one or more of a seam (213) or a void (214) therein, the conductive material comprising cobalt or ruthenium; heating the substrate (210a) to a temperature of 250 degrees Celsius to 400 degrees Celsius; and exposing the substrate to hydrogen-containing atmosphere at a pressure of1.2 MPa to 1.5 MPa, wherein the hydrogen-containing atmosphere includes hydrogen present within a range of 3.5 atomic percent to 4.5 atomic percent.

2. The method of claim 1, wherein the interconnect further comprises grain boundaries, wherein the hydrogen-containing atmosphere further comprises diatomic nitrogen or argon.

3. The method of claim 2, wherein the substrate (210a) is heated to a temperature within a range of 300 degrees Celsius to 400 degrees Celsius.

4. The method of claim 3, further comprising reducing the grain boundaries and healing the seam (213) or void (214).

5. The method of claim 1, wherein the substrate (210a) is heated to a temperature of 300 degrees Celsius to 400 degrees Celsius.

6. The method of claim 5, wherein the hydrogen-containing atmosphere further comprises diatomic nitrogen or argon.

7. The method of claim 5, further comprising healing the seam (213) or void (214).

8. The method of claim 5, wherein the interconnect further comprises grain boundaries.

9. The method of claim 8, further comprising reducing the grain boundaries.

10. The method of any of claims 1 or 5, further comprising: forming the interconnect on the substrate (210a) prior to positioning the substrate in the process chamber.

11. The method of claim 10, wherein the hydrogen-containing atmosphere further comprises diatomic nitrogen.

12. The method of claim 10, wherein the hydrogen-containing atmosphere is driven into the seam (213) or void (214) via pressure to remove contaminants from within the seam or void.