STORAGE WITH A MATRIX OF RESISTIVE STORAGE CELLS AND CORRESPONDING INTERFACE CONNECTION METHOD

Description

TECHNICAL FIELD

[0001] The technical field is that of microelectronics, more particularly that of resistive memories.

[0002] The invention relates more particularly to a memory comprising a matrix of resistive cells and an electrical device for interfacing this matrix. TECHNOLOGICAL BACKGROUND

[0003] New types of non-volatile memory, called resistive memory, or sometimes ReRAM (from the acronym for "Resistive Random Access Memory"), have been developed in recent years. A memory of this type generally comprises an array of memory cells, sometimes called "memory points", each storing a piece of data, for example a binary piece of data. The binary data in question is represented by the resistance level, either high or low, of the memory cell in question. The data stored in such a memory cell can also be data that can take more than two different values ​​(for example four different values, the data then grouping two bits), in the case of a "multi-level" memory cell. In this case, the memory cell has a resistance equal to one of its resistance levels (the number of which is greater than two), a level which is associated with the value stored in the cell.

[0004] Different technologies are possible for producing memory cells. For example, these may be filament-type memory cells, comprising an active layer in which an electrically conductive filament is either broken or, on the contrary, reformed to vary the resistance level of the memory cell, during write cycles and then resetting of this cell (SET operations, when the filament is reformed, and RESET operations, when the filament is broken again). Such a filament-type memory cell may, for example, be an OxRam type cell (according to the English acronym for "Oxide Random Access Memory"), or a CB-RAM type cell (according to the English acronym for "Conductive Bridge Random Access Memory").The resistive memory cells in question can also be PCRAM (for "Phase Change Random Access Memory") type cells, in which an amorphous-crystalline phase change is accompanied by a change in the resistance of the cell.

[0005] In any case, to access the data stored in one of the cells of the matrix, that is to say to read this cell, one technique consists of applying a reading voltage V' to the cell in question, and measuring the electric current which, in response, crosses the cell. The current value then provides information on the state, either highly resistive or low resistive, of the memory cell. In practice, the reading voltage is applied between, on the one hand, the row of the matrix where the cell to be read is located, and, on the other hand, the column of the matrix where this cell is located.

[0006] The memory cells in question are sometimes of the "1S1R" type, that is to say comprising, in series: a "1S" stage, acting as a selector and a "1R" stage corresponding to the memory element itself, in which the data is stored (in the form of the resistance level of this element). The resistive memory element is the part of the memory cell where the data is stored (in a non-volatile manner), in the form of the resistive state (high or low) of this element. As indicated above, this memory element can be of the filamentary type (OxRAM or CBRAM), or phase change. When a sufficient voltage is applied to the terminals of the memory cell, the selector becomes conductive, thus making it possible to read the state of the "1R" memory element.The selector is generally made in a so-called "backend" part of the electronic chip including the memory, that is to say in a part of this chip made during a second phase of manufacturing of the chip (the memory elements can also be made during this second phase, the entire matrix being part of the "backend"). Such a "1S1R" structure has the advantage of being able to be manufactured by a backend type technology, with stacking of the memory cell and selector matrices. Furthermore, from an electrical point of view, this structure makes it possible to inject a current density which is generally higher than with a traditional frontend technology based on transistors or diodes. This makes it possible to obtain a higher memory density.

[0007] But during such a reading operation, it is sometimes necessary to wait a certain time between the instant t' o when the reading voltage V' is started to be applied, and the moment when the selector switches to its conductive state. However, the corresponding delay is partly unpredictable, likely to vary from one cell to another, and from one reading to another: in some cases, the switching can take place almost instantaneously, after only one or a few nanoseconds, while in other cases, the switching may only occur around thirty or forty nanoseconds after the application of the reading voltage. This phenomenon is sometimes "incubation".

[0008] To be able to properly read the memory cell in question, the reading voltage is then applied in the form of a square pulse, of relatively long duration τ' lect (longer than the maximum value expected for the incubation time). Depending on the case, the instant from which the selector becomes conductive can be located either at the start of this pulse (case of instant t' 2 , on the figure 1 ), or rather at the end of it (case of instant t' 1 , on the figure 2 ).

[0009] When the selector switches to its state at the start of the read pulse, for example at time t' 2 , an electric current i' lect flows through the memory cell for a significant duration (i.e.: for almost the entire duration of the read pulse). This results in significant power consumption, and can also cause a form of alteration or small-scale mechanical stress (a "stress") within the memory element 1R.

[0010] Phenomena comparable to the incubation phenomenon just presented, for which there is a partly unpredictable delay before a change in conductive or resistive state, can also occur during writing operations (or, in other words, programming) of such a memory cell.

[0011] Furthermore, document US2013 / 329484A1 describes a device and a method for carrying out the initialization step of OxRAM type memory cells, this so-called “forming” step consisting of forming the filament for the first time. The “forming” step is carried out in a controlled manner, thanks to the use of a “forming” capacitor. SUMMARY

[0012] In this context, we propose a memory comprising: a matrix of resistive memory cells with: row electrical tracks, column electrical tracks, and resistive memory cells located at the intersections between the row electrical tracks and the column electrical tracks, each memory cell being connected between, on the one hand, one of the row electrical tracks and, on the other hand, one of the column electrical tracks, the memory comprising an interfacing device for interfacing said matrix, the interfacing device comprising at least one conversion capacitor, a voltage measuring device connected to the terminals of the conversion capacitor, an electrical source, a first switch, a second switch and a control module, the interfacing device being configured to execute the following steps: step a): connecting the conversion capacitor to the source by means of the second switch to charge the conversion capacitor,then step b): disconnecting the conversion capacitor from the source, and connecting the conversion capacitor between one of the row electrical tracks and one of the column electrical tracks, by means of the first switch, then acquiring a reading result voltage, across the conversion capacitor, by means of the voltage measuring device, then determining a resistive state of said cell by the control module, on the basis of said reading result voltage.

[0013] The conversion capacitor is therefore a reading capacitor, allowing an electrical voltage to be applied to a cell to be read, allowing the cell to be read, while limiting the electrical energy likely to be consumed during this reading. The state of the memory cell to be read is determined from the reading voltage in question, present at the terminals of the capacitor after it has been connected to this cell (in practice, after it has discharged, in part, in this cell).

[0014] In step b), the conversion capacitor is disconnected from the source, and connected between the row electrical track and the column electrical track in question, by means of the first switch, to carry out a conversion between: on the one hand, a resistive state of the memory cell which is located at the intersection of said row electrical track and said column electrical track, and, on the other hand, a charge level of the conversion capacitor. By charge level, we mean the quantity of electrical charges stored in the conversion capacitor, or, equivalently, the electrical voltage across its terminals.

[0015] This arrangement, with this conversion capacitor which plays a sort of intermediary role between the electrical source and the matrix, has the advantage of allowing a well-controlled conversion between the two quantities mentioned above (resistive state on the one hand, and charge level on the other), with a natural limitation of energy transfers during this conversion since the energy initially stored in the capacitor is limited (independently of possible latency times in this conversion).

[0016] This allows in particular to better control the energy consumption associated with such a conversion (by limiting it to a pre-established fixed value), as well as the energy which passes through the memory cell (energy which can be a source of premature aging, or stress of the memory cell, if it is too high).

[0017] As mentioned above, the conversion capacitor is used here to perform reading operations. The conversion in question then corresponds to a modification of the charge level of the capacitor, that is to say of the electrical voltage at its terminals, according to the resistive state of the memory cell read. In this case, the capacitor is initially charged by the electrical source, which is then disconnected from the capacitor (thanks to the second switch). The capacitor is then connected to the matrix (between one of the rows and one of the columns, thanks to the first switch).

[0018] If the memory element of this cell is in its highly resistive state, the conversion capacitor will discharge little, and will thus maintain a fairly high voltage. On the contrary, if the memory element is in its low resistive state, the conversion capacitor will discharge into the memory cell, and the voltage across its terminals will drop. The final voltage, across the conversion capacitor, then provides information on the data stored in the memory cell in question.

[0019] And the electrical energy consumed during this reading operation is constant, limited (intrinsically limited by the energy initially stored in the conversion capacitor).

[0020] In particular, for memory cells of the “1S1R” type, the electrical energy consumed during the reading operation is independent of the instant at which the “1S” selector becomes conductive, after the connection of the capacitor (previously charged) to the cell to be read. This is illustrated by the figure 2 . The instant to is the instant at which the conversion capacitor, previously charged, is connected to the terminals of the memory cell to be read. After a certain incubation time, the selector of this cell becomes conductive, at the instant t 1 . This is accompanied by a sudden increase in the current i 1 , delivered by the capacitor and which crosses the cell. Then this current decreases, due to the discharge of the capacitor.

[0021] If the selector switch occurs earlier, at time t 2 , the energy that will be consumed (and dissipated in the memory cell) will remain the same as that consumed during a late switch, since it is limited by the energy initially stored in the capacitor, and by its discharge.

[0022] The problem of overconsumption mentioned above, due to the necessary consideration of the incubation phenomenon (taken into account via a sufficiently long reading duration) is therefore avoided thanks to this conversion capacitor, used in a way as an intermediary for reading the cell.

[0023] The electrical energy consumed during such a reading operation is not only independent of the instant of switching of the selector, but it can also be made lower than the energy which would be consumed, on average, with reading under constant voltage, as will be shown by the example embodiment described below, by way of illustration, with reference to the figure 15 .

[0024] In addition to the features mentioned above, the memory just presented may have one or more of the following optional features, considered individually or in any technically conceivable combination: the interfacing device comprises an additional resistor connected in series with the conversion capacitor; the additional resistor is greater than a row resistance of the row or column electrical track; the conversion capacitor has a capacitance greater than an overall parasitic capacitance, this overall parasitic capacitance being representative of an effective electrical capacitance of the part of the matrix corresponding to said row electrical track and to said column electrical track; the capacitance of the conversion capacitor is between two times and thirty times the overall parasitic capacitance; the control module configured to control the first and second switches so as to execute steps a) and b) mentioned above;the control module is configured to control said switches so as not to connect the conversion capacitor simultaneously to said source and to said row and column electrical tracks; the control module is further configured to: in step a), control the second switch or the source so as to charge the conversion capacitor up to a given initialization voltage, then in step b), control the first and second switches so as to disconnect the source from the conversion capacitor and then connect the conversion capacitor between said row electrical track and said column electrical track for a predetermined memory cell reading duration, before acquiring the reading result voltage;each memory cell comprises a memory element having at least one highly resistive state and one low resistive state, as well as a selector arranged in series with the memory element, the selector being electrically conductive when a voltage across its terminals is greater than a given threshold, and being electrically insulating otherwise; By resistive state of the memory cell, we mean the resistive state (highly resistive or low resistive) of the memory element of the memory; when a voltage between a low voltage threshold and a high voltage threshold is applied to the terminals of the memory cell: if the memory element is in its low resistive state, then the selector becomes electrically conductive and the memory cell then has a low memory resistance, while if the memory element is in its highly resistive state, then the selector remains electrically insulating and the memory cell then has a high memory resistance;said initialization voltage is greater than said low voltage threshold, multiplied by a charge distribution compensation coefficient; said initialization voltage is less than said high voltage threshold, multiplied by said coefficient; the charge distribution compensation coefficient is equal to the sum of the capacitance of the conversion capacitor and the overall parasitic capacitance, divided by the capacitance of the conversion capacitor; the reading time is greater than: a high total effective resistance, multiplied by the overall parasitic capacitance, the high total effective resistance being a total effective resistance into which the conversion capacitor discharges when it is connected to said row electrical track and to said column electrical track, the memory cell, located at the intersection of this row and this column, having its high memory resistance;the read duration is greater than the total effective resistance high, multiplied by said overall parasitic capacitance, and further multiplied by the natural logarithm of one plus the capacitance of the conversion capacitor divided by the overall parasitic capacitance; the total effective resistance high is equal to the sum of said additional resistance with the inverse of the sum of the inverse of a leakage resistance of the matrix with the inverse of said memory resistance high; the selector is electrically conductive provided further that an electric current flowing through the selector remains greater than the holding current;the additional resistance is such that a total low effective resistance of the memory is less than said initialization voltage divided by the selector holding current, the total low effective resistance being the total effective resistance into which the conversion capacitor discharges when it is connected to said row electrical track and to said column electrical track, the memory cell, located at the intersection of this row and this column, having its low memory resistance; the additional resistance is such that the total low effective resistance of the memory is greater than said initialization voltage divided by a programming current of said memory element; the additional resistance is such that the total low effective resistance of the memory is, furthermore, less than said low voltage threshold divided by the selector holding current;the total low effective resistance is equal to the sum of: said additional resistance with the inverse of the sum of the inverse of the leakage resistance of the matrix with the inverse of said low memory resistance; the conversion capacitor is located on or under the matrix of memory cells and extends parallel to the matrix (in line with it), the matrix and the conversion capacitor being superimposed on each other; the conversion capacitor occupies a surface area smaller than the surface area occupied by the matrix of memory cells; the conversion capacitor does not extend beyond the surface area occupied by the matrix of memory cells; the memory elements of the memory cells are of the OxRAM type (i.e.: made from conductive oxide), or of the CB-RAM type, or of the PCRAM type. ;

[0025] Another aspect of the invention relates to a method of interfacing a memory as described above, comprising the following steps: step a): connecting the conversion capacitor to the source by means of the second switch to charge the conversion capacitor, then step b): disconnecting the conversion capacitor from the source, and connecting the conversion capacitor between one of the row electrical tracks and one of the column electrical tracks, by means of the first switch, then acquiring a reading result voltage, across the conversion capacitor, by means of the voltage measuring device, then determining a resistive state of said cell by the control module, on the basis of said reading result voltage.

[0026] In particular, it can be provided that, the memory comprising a voltage measuring device connected to the terminals of the conversion capacitor: in step a), the second switch, or the source, is controlled so as to charge the conversion capacitor up to a given initialization voltage, in step b), the first and second switches are controlled so as to disconnect the source from the conversion capacitor, then so as to connect the conversion capacitor between said row electrical track and said column electrical track, for a predetermined memory cell reading duration, before acquiring the reading result voltage.

[0027] The invention and its various applications will be better understood by reading the following description and examining the accompanying figures. BRIEF DESCRIPTION OF THE FIGURES

[0028] The figures are presented for information purposes only and in no way limit the invention. [ Fig. 1 ] There figure 1schematically represents a read voltage pulse applied to a resistive memory cell to read it, as well as a read current flowing through the cell, in response to this pulse. Fig. 2 ] There figure 2 schematically represents a current pulse passing through a memory cell during a reading operation carried out by means of an interfacing device implementing the teachings of the invention. Fig. 3 ] There figure 3 schematically represents a memory comprising a matrix of memory cells as well as the interfacing device in question. Fig. 4 ] There figure 4 is a schematic, perspective detail view of part of the matrix of the figure 3 . [ Fig. 5 ] There Figure 5 schematically represents current-voltage characteristics for any of the memory cells in the array of the figure 3 . [ Fig. 6 ] There figure 6schematically represents a distribution of threshold voltages, for the memory cells of the figure 3 . [ Fig. 7 ] There figure 7 is an equivalent electrical diagram modeling the electrical behavior of a part of the memory during a read operation of one of the cells. [ Fig. 8 ] There figure 8 illustrates a so-called "V / 2" matrix polarization configuration used during read operations. Fig. 9 ] There figure 9 shows the time evolution of the voltage across a memory conversion capacitor, during a read operation from a high resistive state. [ Fig. 10 ] There figure 10 shows in particular the temporal evolution of the voltage at the terminals of the cell read, during the reading operation corresponding to the figure 9 . [ Fig. 11 ] There figure 11 shows the time evolution of the voltage across the conversion capacitor during a reading operation from a low resistive state. [ Fig. 11B ] There Figure 11B shows an oscillation phenomenon that can occur in certain cases, during a reading operation from a low resistive state. [ Fig. 12 ] There figure 12 represents how the ratio between the area occupied by the matrix and the area occupied by the conversion capacitor varies, depending on the dimension of the matrix. Fig. 13 ] There figure 13 shows how the width of a reading window varies, depending on the capacitance of the conversion capacitor. Fig. 14 ] There figure 14 shows how the memory response time varies during a read operation, and how the energy consumed during this operation varies, depending on the capacity of the conversion capacitor. Fig. 15 ] There figure 15 shows values ​​of energy consumed during a reading operation carried out either using the interface device of the figure 3 , either in a conventional manner. DETAILED DESCRIPTION

[0029] The present invention relates in particular to a memory 1, such as that shown in the figure 3 , which comprises a matrix 2 of resistive memory cells 20 arranged in n rows and m columns.

[0030] The matrix 2 comprises n row electrical tracks L 1 ,...,L i ,...,L n , and m column electrical tracks C 1 ,...,C i ,...,C m , for example metallic. The memory cells 20, numbering m×n, are located at the intersections between the row electrical tracks and the column electrical tracks.

[0031] Each memory cell 20 is connected between, on the one hand, one of the row electrical tracks and, on the other hand, one of the column electrical tracks. Thus, to apply an electrical voltage V (for example a reading voltage) to one of the memory cells, located at the intersection between one of the row electrical tracks, L i , and one of the column electrical tracks, C j , this electrical voltage is applied between, on the one hand, the track L i , and on the other hand the track C j . The cell in question, located at the intersection of these two tracks L i and C j , is identified by the reference sign 20S, on the figure 3 From an electrical point of view, everything happens as if a first terminal of this memory cell were connected to track L i , its second terminal being connected to track C j .

[0032] The matrix 2, and more generally the memory 1, can be produced by planar techniques, in the form of a stack of several etched and functionalized layers. As shown in the figure 4 , the column electrical tracks can then be located in a lower layer while the row electrical tracks are located in an upper layer (or vice versa), the memory cells 20 (also called memory points) then extending between this lower layer and this upper layer. This type of matrix is ​​often called a “crossbar” type matrix, in this technical field.

[0033] Each memory cell 20 comprises a memory element 22 whose resistance can be electrically adjusted: either at a low resistance level, during a write operation generally called "SET", or at a high resistance level, during another write operation generally called "RESET" (sometimes considered a reset operation).

[0034] In its low resistive state, the resistive element 20 has a low electrical resistance noted R SET RRAM , and in its highly resistive state, it has a high electrical resistance noted R RESET RRAM The write operations in question are sometimes called programming operations in this technical field.

[0035] Data can be written and stored in each memory cell 20, this data being represented by the resistance level of the memory element 22. Here, the data in question is binary data, and the memory cells are programmed so as to place their respective memory elements 22 either in their high resistive state or in their low resistive state.

[0036] However, as a variant, more than two distinct resistance levels could be used for each memory element ("multi-level" elements), so as to store in each cell data capable of taking more than two different values. The present technology, based in particular on a specific conversion capacitor, is presented below in the case of two-level memory elements but it can also be applied to multi-level memory cells as mentioned above.

[0037] Here, the memory cells 20 are of the “1S1R” type, that is to say that they comprise, in addition to the memory element 22, a selector 21 arranged in series with the memory element 22 ( figure 4 ). From an electrical point of view, the selector 21 and the memory element are connected in series, one after the other, between the two corresponding tracks L i , C j . The selectors 21 can be produced in a so-called "backend" part of the electronic chip comprising the memory 1.

[0038] Different technologies are possible to produce the selector 21. It may be, for example, a selector of the MIEC type, according to the English acronym for "Mixed lonic Electronic Conduction", of the MIT type ("metal-insulator transition switch") or of the OTS type (for "Ovonic Threshold Switch") which are threshold switches made from films of amorphous alloys of chalcogenides, such an alloy being composed of a non-oxygen chalcogen element (S, Se, Te), in alloy with elements such as Ge, Si, Sb, As, Al, Zn, Ga. They can be doped with light elements such as B, C, N, O, P (with dopant concentrations which may be greater than 1 atomic %).

[0039] Here, the selectors 21 are of the OTS type.

[0040] The selector 21 becomes electrically conductive when the voltage across its terminals becomes greater than a selector threshold voltage. V th Sel , and which is electrically insulating otherwise. By electrically conductive, we mean that it then presents an electrical resistance R ON Sel low, for example less than 30 kiloohms, or even less than 3 kiloohms. When the voltage across its terminals is lower than the threshold voltage in question, the electrical resistance of the selector is significantly higher, for example by a factor of 10 4< , or 10 5< (and it varies according to the voltage, in general), and the selector is electrically insulating. By electrically insulating, we mean that it has a high electrical resistance, for example greater than 1 megohm, or even 3 megohms. The selector, when it is electrically conductive, may in particular have a resistance lower than the low electrical resistance R SET RRAM of the memory element 22, while when it is electrically insulating, it can have a resistance greater than the high electrical resistance R RESET RRAM of this element.

[0041] For the type of selector considered here (OTS), the selector 21 is electrically conductive when the voltage across its terminals is greater than the selector threshold voltage V th Sel , and further provided that the current i flowing through the selector remains greater than a holding current I h .

[0042] There Figure 5 shows current-voltage characteristics for the memory element 22 alone, and for the complete memory cell 20 (memory element 22 + selector 21). In this case, the memory element 22 is of the OxRAM type, here.

[0043] In this figure, the electric current i flowing through the element considered (expressed in arbitrary units) is represented as a function of the voltage U applied to its terminals (also in arbitrary units). The measurement points i 1R,SET and i 1R,RESET correspond to the memory element 22 alone, respectively in its low resistive state and in its high resistive state. The measurement points i 1R1S,SET and i 1R1S,RESET correspond to the entire memory cell, when the memory element 22 is, respectively, in its low resistive state and in its high resistive state.

[0044] When the memory element 22 is in its low resistive state and the selector 21 has not yet switched to its conductive state, the resistance of the memory element, R SET RRAM (for example of the order of tens of kilohms) is significantly smaller than that of the selector (the resistance of the selector, just below the selector threshold voltage V th Sel , is typically of the order of a megohm). Most of the voltage U applied to the memory cell 20 is therefore found at the terminals of the selector 21 (the voltage U is mainly distributed at the terminals of the selector). Thus, when this voltage becomes higher than the selector threshold voltage V th Sel , the overall resistance of the memory cell switches and the cell then has a low memory resistance R cell ON = R SET RRAM + R ON sel . On the Figure 5 , the low voltage threshold V th SET , o is therefore equal to, or at least close to, the selector threshold voltage V th Sel .

[0045] When the memory element 22 is in its highly resistive state, its resistance R RESET RRAM is closer to the resistance of the selector 21 just before switching. The voltage U applied to the memory cell is then distributed between the selector and the memory element, so that a voltage U barely higher than V th Sel is no longer sufficient to switch the selector to its conductive state. In practice, as long as the voltage U is below a high voltage threshold V th RESET , o , the selector then remains blocked. Above V th RESET , o , not only does the selector switch into its conductive state, but, in addition, the memory element is in some way rewritten, switching to its low-resistive state (whereas it was initially in its high-resistive state). When the voltage U remains lower than V th RESET , o , the memory cell has a high memory resistance R cell OFF , equal to the sum of the electrical resistance R RESET RRAM of the memory element 22 in its highly resistive state, and of a resistance of the selector 21 in the blocked state (which, under these conditions, can be expressed as U / I th , where I th is the “threshold” current which crosses the selector for a voltage just below the threshold V th Sel ) .

[0046] In any case, for the complete memory cell 20, when the voltage U is between the low voltage threshold V th SET , o , and the high voltage threshold V th RESET , o , it presents a resistance which is either R cell ON , either R cell OFF , depending on the low or high resistive state of the memory element, and which is therefore representative of the data (0 or 1) stored in the memory cell. A voltage in this range thus allows reading of this data, without risk of rewriting the cell during this reading (or at least with a low risk of rewriting, or, in other words, erasure).

[0047] The different memory cells 20 of the matrix may, from the point of view of their operating characteristics (voltage thresholds, resistance levels, etc.), present a certain disparity with respect to each other, whether immediately after the manufacture and commissioning of the memory, or later, due to different aging between cells. In any case, when controlling the memory 1, it is desirable to take this disparity into account.

[0048] There figure 6 schematically represents the way in which the low voltage threshold and the high voltage threshold are distributed among the different cells of matrix 2. In this figure, the voltages are represented on the abscissa, while the proportion of cells having a given low or high voltage threshold is represented on the ordinate, corresponding to the voltage value in question.

[0049] In this figure, in the distribution of low voltage thresholds, the largest of these thresholds is identified by the reference V th SET . Throughout the following, the expression "low voltage threshold" also designates the quantity V th SET . Similarly, in the distribution of high voltage thresholds, the smallest of these thresholds is identified by the reference V th RESET , and, throughout the following, the expression “high voltage threshold” designates the quantity V th RESET .

[0050] Given this distribution, a reading voltage between V th SET And V th RESET clearly allows any of the memory cells in the matrix to be read without the risk of rewriting it (or at least with a low risk of rewriting).

[0051] In any case, whatever the type of selector used, each memory cell 20 is such that, here, when a voltage between: a low threshold voltage, in this case the low voltage threshold V th SET , and a high threshold voltage, in this case the high voltage threshold V th RESET , then: the state, highly resistive or low resistive of the resistive element 22 is not modified, and the memory cell 20 has either its high memory resistance R cell OFF , or its low memory resistance R cell ON , depending on the state, highly resistive or low resistive, of the resistive element 22.

[0052] The memory 1 comprises, in addition to the matrix 2, an interfacing device 3 for interfacing said matrix 2.

[0053] The interfacing device 3 here makes it possible to address such or such memory cell of the matrix, that is to say to connect it electrically (by a system of switches) to an electrical circuit for controlling the cell, in order to interact with it.

[0054] More particularly, the interfacing device 3 comprises at least ( figure 3 ) : a conversion capacitor 4, a first switch 5, arranged in the interfacing device for, on command: either connecting the conversion capacitor 4 between one of the row electrical tracks Li and one of the column electrical tracks C j of the matrix 2, or disconnecting the conversion capacitor from said electrical tracks L i , C j , an electrical source, 7, and a second switch 6 arranged in the interfacing device for, on command: either connecting the electrical source to the terminals of the conversion capacitor, or disconnecting the source 7 from the conversion capacitor 4.

[0055] Switches 5 and 6 are, for example, transistors. Source 7 is capable of charging conversion capacitor 4. This is a voltage source (e.g., produced in the form of a voltage regulator, itself electrically powered). Alternatively, it could be a current source, or any source capable of delivering an arbitrary current and voltage. First switch 5 is connected between conversion capacitor 4 and one of the row electrical tracks, or one of the column electrical tracks of the matrix. Second switch 6 is connected between the conversion capacitor and source 7.

[0056] Conversion capacitor 4 allows conversion between: on the one hand, a resistive state of the memory cell 20S to which the conversion capacitor 4 is connected, and on the other hand, a charge state of the capacitor, translated by a voltage across the terminals of the capacitor.

[0057] This arrangement, with this conversion capacitor 4 which plays a sort of intermediary role between the source 7 and the matrix 2, has the advantage of allowing a well-controlled conversion between the two quantities mentioned above (resistive state on the one hand, and charge state on the other), with a natural limitation of the energy transfers during this conversion since the energy initially stored in the capacitor is limited (the capacitor having a limited electrical capacity).

[0058] This allows in particular to better control the energy consumption associated with such a conversion (by limiting it to a pre-established fixed value), as well as the energy which passes through the memory cell (energy which can be a source of premature aging, or stress of the memory cell, if it is too high).

[0059] Moreover, as shown, the interfacing device 3 comprises a control module 10 arranged to control the first and second switches 5, 6, the control module being configured to control these switches so as not to connect the conversion capacitor 4 simultaneously to the source 7 and to said row and column electrical tracks L i , C j , precisely so that the conversion capacitor 4 fully plays its role as intermediary between the source 7 and the cell 20S addressed by the interfacing device 3.

[0060] The control module 10 is implemented for example in the form of an electrical circuit, for example a programmable electrical circuit, which delivers control signals for the switches, according to a predetermined time sequence. The control module 10 is for example integrated on the same electronic chip as the matrix, as are the other components of the interface module 3.

[0061] As can be seen on the figure 3 , the interfacing device 3 also comprises an additional resistor R add , here. This resistor is connected in series with the conversion capacitor 4, between this capacitor and the row electrical track L i (alternatively, it could be connected between the conversion capacitor and the column electrical track C j , for example).

[0062] This additional resistance makes it possible, in particular, by the choice of its value, to limit the maximum electrical current delivered by the conversion capacitor in the matrix, which makes it possible to control the electrical exchanges even better when controlling the matrix. The additional resistance is notably greater than the line resistance of the row or column electrical track L i , C j . The additional resistance R add is produced here in the form of a dedicated electrical component (made of resistive material). Alternatively, this resistance could however be the internal resistance (effective resistance) of the first switch 5 in its on state.

[0063] The structure of the interfacing device 3, as shown in the figure 3 , is now described in more detail.

[0064] A first terminal 11 of the conversion capacitor 4 is connected to the electrical track of column C j , via an electrical ground M. The electrical track of column C j is electrically connected to ground M, and the first terminal 11 of the conversion capacitor is also electrically connected to this electrical ground.

[0065] A second terminal 12 of the conversion capacitor 4 is connected to the electrical line track L i , via the additional resistor R add and the first switch 5. In this case, the additional resistor R add is electrically connected between, on the one hand, the second terminal 12 of the capacitor, and, on the other hand, an intermediate terminal 13. The first switch is electrically connected between this intermediate terminal 13 on the one hand and the electrical line track L i on the other hand.

[0066] A first terminal 14 of the source 7 is connected to the ground M, while a second terminal 15 of this source is connected to the intermediate terminal 13, via the second switch 6 (the second switch 6 is connected between the second terminal 15 of the source on the one hand, and the intermediate terminal 13 on the other hand).

[0067] The interfacing device 3 also comprises a voltage measuring device 8, connected between the first and second terminals 11, 12 of the conversion capacitor 4. This device is capable of measuring the voltage across the terminals of the conversion capacitor 4, or at least capable of comparing it with a given predetermined threshold. It is connected to the control module 10 and is capable of communicating to it the result of this voltage measurement, or of this comparison.

[0068] As a person skilled in the art will be able to appreciate, different variants, compatible with the function of the conversion capacitor 4 mentioned above, can be made to the conversion device 3. Thus, the roles of the row and column electrical tracks L i and C j could be reversed for example (the column electrical track then being connected to the conversion capacitor by the first switch, while the row electrical track would then be connected to the ground M). It could also be provided to connect the second switch 6 between the second terminal 15 of the source 7 and the second terminal 12 of the capacitor, for example, rather than connecting it between the second terminal 15 of the source 7 and the intermediate terminal 13.

[0069] The interfacing device 3 can in particular be used, as here, to carry out operations for reading the memory cells of the matrix.

[0070] For this, the control module 10 is configured (e.g. programmed) to perform the following operations: controlling the first and second switches 5, 6 to connect the source 7 to the conversion capacitor 4, the conversion capacitor then being disconnected from the row and column electrical tracks L i and C j (one of its two terminals however being able to remain connected to one of these tracks), so as to charge the conversion capacitor to a given initialization voltage V init<, then controlling the first and second switches 5, 6 to disconnect the source 7 from the conversion capacitor 4 and connect the conversion capacitor between the row electrical track L i and the column electrical track C j , the conversion capacitor then remaining connected between these two electrical tracks for a predetermined memory cell reading duration, t meas , then acquiring a reading result voltage VR , across the conversion capacitor 4, by means of the voltage measuring device 8.

[0071] The reading result voltage, acquired by the voltage measuring device 8, can be measured by the voltage measuring device 8 (which then delivers a value, for example in the form of logical, digital data), or more simply compared to a given threshold (which constitutes a simplified form of measurement), the result then taking the form of a high or low electrical signal, depending on the result of the comparison, for example.

[0072] If the memory element 22 of the selected memory cell 20S (located at the intersection of L i and C j ) is in its highly resistive state, the selector will not switch to its conductive state, and the conversion capacitor 4 will discharge very little during the reading time t meas , thus maintaining a high voltage. On the contrary, if the memory element is in its low resistive state, the selector will switch to its conductive state, and the conversion capacitor 4 will discharge into the low memory resistance R cell ON , the voltage at its terminals then drops significantly ( figure 11 ). The reading result voltage VR, finally measured at the terminals of the conversion capacitor 4, therefore provides information on the data (0 or 1) stored in the memory cell in question.

[0073] And, as explained in the section entitled "Summary", the electrical energy consumed during this reading operation is intrinsically limited, regardless of the moment at which the selector switches to its conductive state. This makes it possible in particular to overcome the problems due to the incubation phenomenon mentioned above.

[0074] In the following, we will present operating characteristics (response time, voltage values, etc.), expected for the interfacing device 3 during such a reading operation, within the framework of a slightly simplified modeling of this operation corresponding to the equivalent electrical diagram of the figure 7 .

[0075] We will then present criteria for sizing the components of the interfacing device (capacitance C c of the conversion capacitor 4, value of the additional resistance R add , etc.) which, taking into account the operating characteristics in question, are well suited for this reading operation.

[0076] A numerical example of implementation will then be presented, as well as an illustration of the influence of the value of the capacity C c on the performance of the memory and the size of the device. Modeling

[0077] There figure 7 represents an equivalent electrical diagram of the memory 1, during a reading operation of the memory cell 20S. In addition to the components (4 to 8) of the interfacing device 3, presented above, this figure shows a model representing in a simplified manner the electrical behavior of the memory cell 20S read, and that of the rest of the matrix 2.

[0078] The memory cell is modeled by: a set of three resistors R line , R OTS and R RRAM connected in series with each other, this set being connected between the ground M and the first switch 5, and a capacitor having a parasitic capacitance C by , connected in parallel with this set of resistors.

[0079] The resistance R line is the electrical resistance of the electrical tracks L i and C j . In practice, it is significantly smaller than R OTS and R RRAM which are, respectively, the resistance of the selector 21 and the resistance of the memory element 22.

[0080] The rest of the matrix is ​​represented by a matrix leakage resistor, R mat leak , and an overall parasitic capacitance C par tot connected in parallel with the leakage resistor, the assembly being connected between ground M and the first switch 5.

[0081] The overall parasitic capacitance C par tot is representative of an effective electrical capacitance of the part of the matrix 2 which includes the row and the column of memory cells 20 corresponding to the row electrical track L i and to the column electrical track C j , without the memory cell 20S (located at the intersection of this row and this column). It is therefore the effective parasitic capacitance of the (m+n-1) memory cells in question.

[0082] The capacity of these cells must be taken into account to determine the electrical behavior of the memory (for example, response times), even if these cells are not read during the reading operation in question. Indeed, when reading a particular cell of the matrix, the other cells are also polarized (so as not to leave them at a floating potential), but in such a way as to apply a voltage to them which remains lower than the reading voltage (so as not to switch their selectors to the conductive state). A matrix polarization configuration called "V / 2" is shown schematically on the figure 8. We can clearly see that, in this configuration, the (m+n-2) cells of row L i and column C j , other than the targeted 20S cell, are polarized under a voltage V / 2, while the 20S cell is polarized under a voltage V. And as these (m+n-2) cells are polarized, powered, their capacity must be taken into account to determine the electrical response (in particular the response time) of the whole.

[0083] In this case, for this polarization configuration, the overall parasitic capacitance C par tot can be evaluated as (m+n-1)×C by . Note that m+n-1 is the total number of cells (including the 20S cell) that comprise row L i and column C j . For other polarization configurations (e.g., the configuration called "V / 3" in the literature), the expression for C par tot may however be different.

[0084] As for the leakage resistance R mat leak ,we consider here that it is given by the following relation: R mat leak = I leak Vleak + 1 Rline + 1 R RESET RRAM × m + n − 2 − 1 where I leak is a leakage current of a cell of the matrix subjected to the voltage V leak (for example V / 2).

[0085] Furthermore, in this model, we neglect: the parasitic capacitance of the circuitry external to the matrix, the influence of the current on the resistance of the selector (also called OTS in the following) in its on state (conductor); this resistance, R ON sel , is assumed to be constant, the influence of the evolution of the voltages (during the discharge of the conversion capacitor) on the leakage currents; constant and maximum currents are considered (worst case).

[0086] We also assume: as already indicated, a matrix polarization configuration of type "V / 2", that the leakage currents come only from the (m+n-1) partially selected cells, that only one memory cell is read at a time. Operating characteristics

[0087] In this context, we determined, for the reading operation described above, the evolution over time t: of the voltage U 4 across the conversion capacitor 4, of the voltage U SET< 20 and U RESET< 20 across the memory cell 20S, and of the current i 20 which flows through the cell 20S.

[0088] The temporal evolution of these quantities is represented schematically on the figures 9 to 11 .

[0089] On the figure 9 , we can see the evolution over time t of the voltage U 4 when the memory element of the 20S cell is in its highly resistive state (RESET).

[0090] The conversion capacitor 4 has been previously charged, to an initial voltage V init , by the source 7. The source is then disconnected (using the second switch 6). Then, at time to , at the end of a first phase (phase “1”, in the figures), the conversion capacitor 4 is connected to the matrix by closing the first switch 5.

[0091] The electrical charge initially contained in the conversion capacitor 4 is then distributed between this capacitor and the parasitic capacitances mentioned above. During this second phase (phase “2” in the figures), the voltage U RESET< 20 at the terminals of the memory cell 20S increases progressively ( figure 10 ) while the voltage U 4 decreases, these two voltages finally reaching the same equilibrium voltage V eq .

[0092] This equilibrium voltage V eq , fixed by the charge distribution in question, is therefore expressed as: V eq = V init 1 1 + C par tot / C c

[0093] The duration t eq to reach this equilibrium voltage is expressed as: t eq = − ln 1 − V eq / V init × R tot OFF . C par tot Or R tot OFF is a high total effective resistance into which the conversion capacitor 4 discharges.

[0094] The resistance R tot OFF is therefore expressed here as: R tot OFF = 1 / 1 / R leak mat + 1 / R ′ cell OFF + R add Or R ′ cell OFF is the sum of the high memory resistance R cell Off of the cell and the line resistance R line (the latter being generally negligible, in practice).

[0095] It can be expressed as: R cell OFF = V init I th + R RESET RRAM + R line Or V init / I th is an estimate of the resistance of the selector 21, in its blocked state, under these operating conditions.

[0096] Then, for a third phase (phases “3” and “4” on the figure 9 ), the voltage across the conversion capacitor 4 gradually decreases (as does that, U RESET< 20 , across the cell 20S), due to the current leaks mentioned above.

[0097] At the end of the measurement time t meas , the reading result voltage VR is then equal to a voltage V read RESET , which, assuming that t meas is greater than t eq , can be expressed as: V read RESET = V eq × 1 − exp − t meas / τ off Or τ off = R tot OFF × C c + C par tot is the response time of the RC circuit equivalent to the memory, in this situation.

[0098] On the figure 11 , we can see the evolution over time t of the voltage U 4 when the memory element of the 20S cell is in its low resistive state (SET).

[0099] The conversion capacitor 4 is pre-charged to the initial voltage V init , as described above, during the first phase (phase “1”, in the figures). At time to , at the end of the first phase, the conversion capacitor 4 is connected to the matrix by closing the first switch 5.

[0100] As in the case of a highly resistive memory element, the electrical charge initially contained in the conversion capacitor 4 begins to be distributed between this capacitor and the parasitic capacitances during a second phase (phase “2” in the figures), the voltage U SET < 20 at the terminals of the memory cell 20S gradually increasing towards the equilibrium voltage V eq . ( figure 10 ).

[0101] But, since the resistive element 22 is in its low resistive state, when the voltage U SET < 20 reaches the low voltage threshold V th SET , the selector 21 switches to its conductive state, thus initiating a third phase, “3”, of rapid discharge of the conversion capacitor.

[0102] The duration t ch of the second phase is expressed as: t ch = − ln 1 − V th SET / V init × R tot OFF . C par tot

[0103] During the third phase, the conversion capacitor 4 discharges quickly into the memory cell 20S, which has the low memory resistance R cell ON . This discharge continues as long as the current i 20 flowing through the cell remains greater than the holding current I h . When i 20 becomes less than or equal to I h ​​, the selector switches back to its blocked state and the current i 20 is greatly reduced, which marks the end of the third phase.

[0104] The maximum value I max reached by the current i 20 , at the beginning of the third phase (i.e.: just after the selector switches to its conductive state), can be expressed as I max = V init / R tot ON , Or R tot ON is a low total effective resistance into which the conversion capacitor 4 discharges.

[0105] The resistance R tot ON can be expressed as R tot ON = 1 / 1 / R leak mat + 1 / R ′ cell ON + R add Or R ′ cell ON is equal to the sum of the low memory resistance R cell ON of the cell, and the line resistance R line (the latter being generally negligible, in practice): R ′ cell ON = R cell ON + R line = R ON sel + R SET RRAM + R line

[0106] Various precautions must be taken regarding the maximum current I max.

[0107] First of all, it is desirable that the maximum current I max be less than a programming current of the cell, I prog , beyond which there is a risk of modifying the resistive state of the memory element 22, which results in: V init / R tot ON < I prog

[0108] The additional resistance R add allows, in a particularly convenient way, to adjust the value of the total effective low resistance R tot ON , in order to satisfy condition (F1) above. This possibility of adjustment of R tot ON thanks to the additional resistance R add is particularly interesting for an OxRAM type memory, like the one described here, for which the maximum reading current is often quite close to the programming current.

[0109] It is also desirable that the maximum current I max be greater than the holding current I h , to effectively switch the selector to its conductive state, i.e. V init / R tot ON > I h

[0110] More generally, it is interesting that the discharge current is high (without exceeding I prog ), to discharge the conversion capacitor as much as possible before re-blocking the selector. This in fact allows a substantial drop in the voltage across the capacitor, and therefore a greater difference between the reading result voltage for a highly resistive state and for a low resistive state.

[0111] It is also desirable to discharge the conversion capacitor to a minimum to avoid oscillations between the conversion capacitor and the memory cell. Indeed, if the conversion capacitor is not sufficiently discharged when the selector relocks, this capacitor will then charge (by charge distribution) the parasitic capacitances of the memory, thus causing the voltage across the cell to return to a value higher than V th SET and thus causing the selector to switch back to its conductive state, which will cause the conversion capacitor to discharge until the selector is re-blocked, and so on until the conversion capacitor is sufficiently discharged, its residual charge no longer allowing it to reach V th SET at the terminals of the memory cell. This oscillation phenomenon is illustrated in the Figure 11B, which shows the evolution over time t of U 4 and i 20 , as well as of the voltage U 21 across the terminals of the selector 21 alone, and of the voltage U 22 across the terminals of the memory element 22 alone. These oscillations are undesirable, if only because they lengthen the reading operation. To avoid them, it is desirable to reach, at the end of the first discharge (when the selector relocks), a sufficiently low voltage across the conversion capacitor, which results in: R tot ON < V th SET / I h

[0112] Again, adjusting the value of the additional resistor R add allows you to conveniently adjust the value of R tot ON so as to satisfy this condition.

[0113] As for the duration t dis of the third phase, it can be expressed as: t dis = − ln I h × R tot ON V th SET × τ ON Or τ ON = R tot ON × C c + C par tot is the response time of the RC circuit equivalent to the memory, in this situation.

[0114] At the instant of re-blocking of the selector, at the end of the third phase, the conversion capacitor presents at its terminals a voltage V read SET which can be expressed as: V read SET = V th SET . exp − t dis / τ ON = I h × R tot ON

[0115] To obtain the lowest possible reading result voltage, it is desirable to wait until the end of this third phase before disconnecting the conversion capacitor from the matrix and measuring the voltage across its terminals. It is therefore desirable that the reading time t meas be greater than the sum of t ch and tdis: t meas > t meas , min = t ch + t dis

[0116] We can even predict that the reading duration t meas is greater than the sum of the duration t meas,min and an expected maximum incubation duration t incub .

[0117] A fourth phase"4" of the read operation begins when the selector switches back to its blocked state, and ends at the end of the read duration t meas , when the read capacitor is disconnected from the matrix (in order to measure the read result voltage, during a fifth phase "5").

[0118] Here, it is considered that, during the fourth phase, the voltage drop across the conversion capacitor due to leakage currents is negligible. Indeed, the electrical voltage applied to line L i is then greatly reduced (due to the prior discharge of the capacitor).

[0119] The reading result voltage VR finally obtained at the end of the fourth phase is therefore equal to, or at least close to, the voltage V read SET at the end of the third phase.

[0120] Finally, the difference ΔV R between: the read result voltage VR for a memory element in its highly resistive state, and the read result voltage VR for a memory element in its low resistive state is then expressed as Δ V R = V read RESET − V read SET . Sizing

[0121] In view of the expected operation for memory 1, it appears useful to size the components of the interfacing device 3 in accordance with the conditions given below.

[0122] The interest of these sizing conditions is illustrated by the analysis of the operation made above, on the basis of the simplified electrical model of the memory presented above. But, as will appear to those skilled in the art, the behaviors and general trends thus illustrated are not limited to the framework of the simplified analysis in question, and the sizing conditions in question are of interest beyond the framework of this simplified electrical model.

[0123] First of all, we can note that, in order to be able to reach (at the terminals of the 20S cell) a voltage higher than the low voltage threshold V th SET , at the end of phase “2” of charge distribution (and thus be able to read the memory cell properly), it is desirable that the initial voltage V init< and the capacitance C c of the conversion capacitor 4 satisfy the following condition: V init ≥ V th SET × α Or α = C c + C par tot / C c is a load distribution compensation coefficient.

[0124] Furthermore, to avoid the risk of rewriting the memory cell when reading it, it is desirable to check the following condition (so that the voltage across the cell remains below the high voltage threshold V th RESET ) : V init ≤ V th RESET × α

[0125] To be able to work with an initial voltage V init< which is not excessively high, if possible of the same order of magnitude as the voltage thresholds of the memory cells (in other words, to have a coefficient α which is not too high), it is therefore desirable that the capacitance C c of the conversion capacitor is higher, and even significantly higher than the overall parasitic capacitance C par tot . This is also desirable for the entire operation of memory 1. The figure 13shows more precisely, for an example, the influence of the capacitance value C c on the width ΔV R of the “window” between high and low reading voltages, showing that it is desirable to choose the capacitance C c sufficiently large (compared to C par tot ) to obtain a sufficiently wide reading window.

[0126] On the other hand, considerably increasing the value of Cc would be unfavorable from the point of view of the minimum duration t meas,min of the reading operation, and in terms of electrical energy consumed (Cf: figure 14 ), without significantly improving the width ΔV R of the reading window (Cf: saturation effect of ΔV R , on the figure 13 )

[0127] For the capacitance C c , choose for example a value between two times and thirty times the overall parasitic capacitance C par tot allows us to obtain a good compromise between these different constraints.

[0128] As for the additional resistance R add , it is preferably chosen so that the total effective resistance low R tot ON either less than V init< divided I h (condition F2 given above), or even less than V th SET / I h (condition F3 given above - which makes it possible to avoid an oscillatory regime), and greater than V init< divided I prog (condition F1 - which makes it possible to limit the risks of rewriting when reading).

[0129] For the record, the total effective low resistance R tot ON is the total effective resistance into which the conversion capacitor 4 discharges when connected to the memory cell 20S, the cell having its low memory resistance R cell ON (ie: memory element in its low resistive state, and selector in its conductive state). The total effective low resistance R tot ON can be expressed approximately, as a function of the additional resistance R add to be adjusted, as: R tot ON = 1 / 1 / R leak mat + 1 / R cell ON + R add

[0130] Finally, as for the reading duration t meas , it can be chosen in practice so as to satisfy condition F4 given above. Numerical examples

[0131] An example of sizing the components of the interfacing device 3 is given below, for illustration purposes, in a case where the matrix of memory cells, of the OxRAM type, has the following characteristics: resistance of the memory element in the SET state: R SET RRAM = 10 kΩ , resistance of the memory element in the RESET state: R RESET RRAM = 100 kΩ , selector resistance (OTS type) in the on state: R ON sel = 1 kΩ , selector holding current: I h = 100µA, programming current: I prog = 200µA, low voltage threshold V th SET = 3,5 V , high voltage threshold V th RESET = 4 V , selector threshold current: It h = 1 µA, V / 2 type polarization configuration, with, for partially selected cells, V leak = V th SET / 2 = 1,75 V , leakage current at V / 2: I leak =10 -8< A, matrix dimensions: m × n = 128x128, and elementary parasitic capacitance (for a cell) C par = 0.5fF.

[0132] The conditions mentioned above, relating to the characteristics of the interfacing device 3, can then be satisfied by choosing the following values, for example: conversion capacitor capacity: C c =2pF, initial voltage: 3.72 V < V init< < 4.26 V, satisfied here by choosing V init< = 4 V, low total effective resistance: 17,5 k Ω < R tot ON < 35 kΩ , which can be obtained for example with R add = 14.2 kΩ (which then corresponds to a maximum current I max = 139 µA).

[0133] Furthermore, with these parameters the minimum reading time t meas,min is 178 ns, with t ch =160 ns and t dis =18 ns. The intrinsic duration of the reading operation itself, which is t dis =18 ns, is therefore short (on the other hand, the charging time of the parasitic capacitances, t ch , is rather long, and it would be interesting to reduce it).

[0134] By then choosing t meas = 200 ns, we obtain the following values ​​for the reading result voltage: V read RESET = 3,8 V , V read SET = 2,5 V , and a reading window ΔV R =1.3V.

[0135] In this example, the charging time of the parasitic capacitances t ch is much greater than the intrinsic reading time t dis . To reduce t ch , the value of the parasitic capacitances can be reduced (or, to a lesser extent, the initial voltage V init ). A total reading time of less than 50ns can, for example, be envisaged by using the same parameters as above, but by reducing the value of the elementary parasitic capacitance C par to 0.1fF. In this case, the charging time of the parasitic capacitances is t ch = 32 ns while t dis = 17 ns, allowing a minimum reading time of 49 ns and a reading window of approximately 1.4V for a reading time t meas = 50ns.

[0136] There figure 12 represents the ratio S 2 / S 4 between the surface S 2 occupied by the matrix 2 and a surface S4 occupied by the conversion capacitor 4, as a function of the number n of rows of the matrix, for a square matrix (n=m).

[0137] In terms of spatial density of memory points (for the matrix), and capacitance per unit area (for the conversion capacitor), the data from the figure 12 correspond to typical characteristics of a manufacturing process with fine engraving (with a pitch between lines of, for example, between 20 and 40 nanometers).

[0138] Furthermore, the capacity value C c corresponding to the surface S 4 is the smallest value of C c allowing the satisfaction of condition F5 given above, under the same conditions as for the complete numerical example presented above (in particular, for V init =4V).

[0139] As can be seen in this figure, except for very small matrices, the ratio S 2 / S 4 is greater than 1 (for the numerical example given above, it is equal to 10, for example). The conversion capacitor thus produced therefore occupies a smaller surface area than that of the matrix.

[0140] It can then be made on or under the matrix, directly above it, without extending beyond the surface occupied by matrix 2. This allows the conversion capacitor to be integrated as close as possible to the matrix, and without increasing the size of memory 1.

[0141] The increase in the ratio S 2 / S 4 with the dimension n, visible on the figure 12 , can be explained as follows. The surface area S2 of the matrix increases as n 2< , while the overall parasitic capacitance C par tot , and therefore the minimum value of the capacitance C c , increase as n (more precisely, proportionally, as 2n-1), so that the ratio S 2 / S 4 finally increases with n.

[0142] On the figures 13 And 14, we have represented values ​​obtained for the reading window ΔV R (expressed in volts, V) the discharge time t dis (in nanoseconds), and the energy E consumed during a reading operation of a SET state (expressed in joules), as a function of the value of the capacitance C c of the conversion capacitor (in Farads). These values ​​are obtained under the same conditions as for the complete numerical example presented above (in particular, C par =0.5fF, for these figures).

[0143] As already mentioned, we see that the reading window ΔV R increases advantageously when C c increases, but that this is also accompanied by an increase in the discharge time t dis (“intrinsic” reading time), and in the energy E consumed.

[0144] There figure 15 watch : the energy E is consumed during a reading operation of a SET state (in Joules) for the particular interfacing device 3 which has just been presented, and the energy E' consumed during a reading operation of a SET state (in Joules) for a conventional interfacing device, in which the reading would be carried out by applying a constant reading voltage (see the figure 1 ), in this case equal to 4V.

[0145] The four energy values ​​E, given respectively for C c =1, 2, 3 and 4 pF, are those corresponding to the curve of the figure 14 .

[0146] For the energy E', 4 curves are represented, associated respectively with a reading current I read of 100, 120, 150 and 200 microamperes. For each of these curves, the energy E' is represented as a function of an average duration in the on state t ON . This duration corresponds to the average time during which the memory cell (and in particular its selector) is conductive.

[0147] For example, if the incubation time mentioned above fluctuates, from one cell and from one reading to another, between 0 ns and 50 ns, a reading pulse ( figure 1 ) for at least 50ns, which leads to an average duration in the on state t ON of approximately 25ns (this is a very schematic example, but in any case, in practice, t ON is typically between ten and a few tens of ns). In this case, we can clearly see that the energy values ​​E' obtained by a conventional reading technique are higher than the energy E consumed with the interfacing device 3 which has just been presented, for the value C c =2pF mentioned above. And this conclusion remains valid for the different values ​​of t ON considered, possibly even if it means adapting the value of Cc.

[0148] In addition to the memory 1 which has just been described, the invention relates to a method of interfacing such a memory 1, comprising the following steps: controlling the first and second switches 5, 6 to connect the source 7 to the conversion capacitor 4, the conversion capacitor then being disconnected from said row and column electrical tracks L i , C j , so as to charge the conversion capacitor 4 up to the initialization voltage V init , then controlling the first and second switches 5, 6 to disconnect the source 7 from the conversion capacitor 4 and connect this capacitor between said row electrical track L i and said column electrical track C j .

[0149] This method may in particular be a reading method, in which: the first and second switches 5, 6 are for disconnecting the source 7 from the conversion capacitor 4 and connecting the capacitor between said row electrical track L i and said column electrical track C j , during the memory cell reading duration t meas mentioned above, the method then comprising a step of acquiring the reading result voltage VR at the terminals 11, 12 of the conversion capacitor 4, by means of the voltage measuring device 8.

[0150] This method can then comprise a step of determining the data (0 or 1, for example) stored in the memory cell 20S, as a function of the reading result voltage VR.

Claims

1. Memory (1) comprising: - a matrix (2) of resistive memory cells (20) with: ∘ line electrical tracks (L1, Li, Ln), ∘ column electrical tracks (C1, Cj, Cm), and o resistive memory cells (20) located at the crossings between the line electrical tracks (L1, Li, Ln) and the column electrical tracks (C1, Cj, Cm), each memory cell (20) being connected between, on the one hand, one of the line electrical tracks and, on the other hand, one of the column electrical tracks, - the memory (1) comprising an interfacing device (3) for interfacing said matrix (2), the interfacing device comprising at least one conversion capacitor (4), a voltage measuring device (8) connected to the terminals of the conversion capacitor (4), an electrical source (7), a first switch (5), a second switch (6) and a control module (10), the interfacing device (3) being configured to execute the following steps: o step a): connecting the conversion capacitor (4) to the source (7) by means of the second switch (6) to charge the conversion capacitor (4), then o step b): - disconnecting the conversion capacitor (4) from the source (7), and connecting the conversion capacitor (4) between one of the line electrical tracks (Li) and one of the column electrical tracks (Cj), by means of the first switch (5), then - acquiring a read result voltage (VR), at the terminals (11, 12) of the conversion capacitor (4), by means of the voltage measuring device (8), then - determining a resistive state of said cellule (20S), by the control module (10), based on said read result voltage (VR).

2. Memory (1) according to the preceding claim, wherein the interfacing device (3) comprises an additional resistor (Radd) connected in series with the conversion capacitor (4).

3. Memory (1) according to one of the preceding claims, wherein the conversion capacitor (4) has a capacitance (Cc) greater than a global parasitic capacitance ( C par tot ), this global parasitic capacitance being representative of an effective electrical capacitance of the portion of the matrix (2) corresponding to said line electrical track (Li) and to said column electrical track (Cj).

4. Memory (1) according to one of the preceding claims, wherein the control module (10) is configured to control the first and second switches (5, 6) in such a way as to execute steps a) and b).

5. Memory (1) according to claim 4, wherein the control module (10) is further configured to: - In step a), control the second switch (6), or the source (7), in such a way as to charge the conversion capacitor (4) to a given initialisation voltage (Vinit), - In step b), control the first and second switches (5,6) in such a way as to disconnect the source (7) from the conversion capacitor (4), then to connect the conversion capacitor (4) between said line electrical track (Li) and said column electrical track (Cj), during a predetermined memory cell reading time (tmeas), before the acquisition of said read result voltage (VR).

6. Memory (1) according to one of the preceding claims, - wherein each memory cell (20) comprises a memory element (22) having at least one high resistive state (RESET) and one low resistive state (SET), as well as a selector (21) arranged in series with the memory element (22), the selector being electrically conductive when a voltage at its terminals is greater than a given threshold ( V th Sel ), and being electrically insulating otherwise, - and wherein, when a voltage (U), applied at the terminals of the memory cell (20), is comprised between a low voltage threshold ( V th SET ) and a high voltage threshold ( V th RESET ): o if the memory element (22) is in its low resistive state (SET), then, the selector becomes electrically conductive and the memory cell (20) then has a low memory resistance ( R cell ON ), o while if the memory element (22) is in its high resistive state (RESET), then, the selector remains electrically insulating and the memory cell (20) then has a high memory resistance ( R cell OFF ).

7. Memory (1) according to claims 5 and 6, wherein said initialisation voltage (Vinit) is: - Greater than said low voltage threshold ( V th SET ), multiplied by a load balancing compensation coefficient (α), and - Less than said high voltage threshold ( V th RESET ), multiplied by said coefficient (α), - the load balancing compensation coefficient (α) being equal to the sum of the capacitance of the conversion capacitor (Cc) and of a global parasitic capacitance ( C par tot ), divided by the capacitance of the conversion capacitor (Cc), with global parasitic capacitance ( C par tot ) being representative of the effective electrical capacitance of the portion of the matrix (2) corresponding to said line electrical track (Li) and to said column electrical track (Cj).

8. Memory (1) according to claim 7, wherein the reading time (tmeas) is greater than: a high total effective resistance ( R tot off ), multiplied by said global parasitic capacitance ( C par tot ), the high total effective resistance ( R tot off ) being a total effective resistance in which the conversion capacitor (4) discharges when it is connected to said line electrical track (Li) and to said column electrical track (Cj), the memory cell (20S), located at the crossing of this line and of this column, having its high memory resistance ( R cell OFF ).

9. Memory (1) according to claims 2, 5 and 6, - wherein the selector (21) is electrically conductive with the further condition that an electrical current (i) that passes through the selector (21) remains greater than a holding current (Ih), - and wherein the additional resistor (Radd) is such that a low total effective resistance ( R tot ON ) of the memory is less than said initialisation voltage (Vinit) divided by the holding current (ih) of the selector, the low total effective resistance ( R tot ON ) being the total effective resistance in which the conversion capacitor (4) discharges when it is connected to said line electrical track (Li) and to said column electrical track (Cj), the memory cell (20S), located at the crossing of this line and of this column, having its low memory resistance ( R cell ON ).

10. Memory (1) according to claim 9, wherein the additional resistor (Radd) is such that the low total effective resistance ( R tot ON ) of the memory is, furthermore, less than said low voltage threshold ( V th SET ) divided by the holding current (ih) of the selector.

11. Memory (1) according to one of the preceding claims, wherein the conversion capacitor (4) is located above or below the matrix (2) of memory cells (20) and extends parallel to the matrix (2), the matrix (2) and the conversion capacitor (4) being superimposed on each other.

12. Method for interfacing a memory (1) in accordance with any of the preceding claims, comprising the following steps: - step a): connecting the conversion capacitor (4) to the source (7) by means of the second switch (6) to charge the conversion capacitor (4), then - step b): o disconnecting the conversion capacitor (4) from the source (7), and connecting the conversion capacitor (4) between one of the line electrical tracks (Li) and one of the column electrical tracks (Cj), by means of the first switch (5), then ∘ acquiring a read result voltage (VR), at the terminals (11, 12) of the conversion capacitor (4), by means of the voltage measuring device (8), then ∘ determining a resistive state of said cell (20S), by the control module (10), based on said read result voltage (VR).

13. Method according to the preceding claim, the memory (1) comprising the voltage measuring device (8) connected to the terminals (11, 12) of the conversion capacitor (4), wherein: - in step a), the second switch (6), or the source (7), is controlled in such a way as to charge the conversion capacitor (4) to a given initialisation voltage (Vinit), - in step b), the first and second switches (5,6) are controlled in such a way as to disconnect the source (7) from the conversion capacitor (4), then in such a way as to connect the conversion capacitor (4) between said line electrical track (Li) and said column electrical track (Cj), during a predetermined memory cell reading time (tmeas), before the acquisition of said read result voltage (VR).