GNSS SIGNAL SYSTEM AND RECEIVER

Description

Technical field

[0001] The description relates to the field of navigation, that is the ability of a device to determine a user position, velocity (speed) and attitude (i.e., 3D direction). The disclosed invention refers to techniques for providing navigation information, for instance using GNSS receivers in multiple frequency bands.Description of the related art

[0002] A currently leading technology for positioning applications is GNSS (Global Navigation Satellite System), which is conventionally used in navigation systems including navigation and telematics.

[0003] A GNSS comprises a plurality of RF receivers, each RF receiver configured to operate in a different frequency band, providing a multi-band multi-constellation positioning receiver.

[0004] For instance, GNSS constellations comprise GPS, Galileo, Glonass, BeiDou, NAVIC (former IRNSS) and QZSS, in L1, L2, L5 and E6 frequency bands.

[0005] As the receivers may be part of an integrated circuit (IC), area footprint and performance of these components are relevant figures of merit.

[0006] More specifically, the invention relates to a system according to the preamble of claim 1, which is known, for instance, from CN 210 351 144 U. Documents US 2012 / 026039 A1 and US 2006 / 176215 A1 are also of interest for the invention.Object and summary

[0007] An object of the disclosed invention is to contribute in reducing an area footprint and increasing performance of the RF receivers in GNSS systems. Such an object is achieved by means of a system having the features set forth in claim 1 that follows. A further object of the disclosed invention relates to a corresponding receiver, such as a GNSS receiver having the features set forth in claim 9 that follows.

[0008] The claims are an integral part of the technical teaching provided herein. Further details of the disclosed invention are provided in the dependent claims.Brief description of the several views of the drawings

[0009] One or more embodiments will now be described, by way of non-limiting example only, with reference to the annexed Figures, wherein: Figure 1 is a diagram exemplary of a system as per the present disclosure, Figure 2 is a diagram exemplary of a portion of the system exemplified in Figure 1, Figures 3A, 3B and 3C are diagrams exemplary of principles underlying one or more embodiments, Figure 4 is a diagram exemplary of frequency bands used in possible applicative scenarios.

[0010] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.

[0011] The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.

[0012] The edges of features drawn in the figures do not necessarily indicate the termination of the extent of the feature.Detailed description

[0013] In the ensuing description, one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments of this description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of embodiments will not be obscured.

[0014] Reference to "an embodiment" or "one embodiment" in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as "in an embodiment" or "in one embodiment" that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment.

[0015] Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

[0016] The drawings are in simplified form and are not to precise scale.

[0017] Throughout the figures annexed herein, like parts or elements are indicated with like references / numerals unless the context indicates otherwise, and for brevity a corresponding description will not be repeated for each and every figure.

[0018] The references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.

[0019] For the sake of simplicity, in the following detailed description a same reference symbol may be used to designate both a node / line in a circuit and a signal which may occur at that node or line.

[0020] A navigation receiver operates by down converting to quasi baseband the input signal received from the satellites, which is transmitted at a plurality of radio-frequency bands, using a local oscillator to step down the input frequency and allow a baseband digital management of the satellite information.

[0021] With reference to Figure 1, which diagrammatically shows a GNSS Global Navigation Satellite System) system (such as, for example, Global Positioning System (GPS), Global'naya Navigatsionnaya Sputnikovaya Sistema (GLONASS), Galileo System, or other types of satellite-based positioning systems, such global satellite positioning system comprises a constellation of a number N of satellites SC 1 -SC N and at least a receiving apparatus 10.

[0022] The receiving apparatus 10 comprises an antenna RX, an analog receiving module AFE (Analog Front End), provided with a radiofrequency (RF) stage 12, and an analog-digital converter 14 (ADC), which can be implemented by hardware modules.

[0023] The receiving apparatus 10 may be provided with a central processing unit, memories (mass memory and / or working storage) and respective interfaces (not shown in figures), comprising a microprocessor or microcontroller, for running the software resident in it.

[0024] The following embodiments are described in a non-limiting way referring to the GPS technology, however the teachings of the present disclosure can be applied also to other satellite positioning systems.

[0025] When the receiving apparatus 10 operates, the antenna RX receives a plurality of signals s 0 ,...,s N from one or more satellites SC 0 -SC N of the constellation of satellites operating in GNSS system. For example, these signals can be modulated on at least one carrier signal having a carrier frequency F c .

[0026] For the sake of simplicity, one or more embodiments are discussed in the following with references to an exemplary case in which a signal S RF having a plurality of spectral portions in a variety of frequency bands, such an example being purely exemplary and in no way limiting.

[0027] As exemplified in Figure 1, a system 10 for receiving and processing GNSS signals in a plurality of radiofrequency (briefly, RF) bands comprises: an antenna RX configured to receive a RF input signal S RF , e.g., a RF input signal S RF , having a spectral content in a plurality of distinct and separate frequency bands; a RF front-end circuit block 12 coupled to the receiver antenna RX to receive the RF input signal S RF therefrom, the RF signal being a (e.g., frequency) modulated signal that occupies a total bandwidth of BW (in Hertz); a local oscillator OSC configured to produce an oscillating signal OSC, a phase-locked loop (briefly, PLL) 11 coupled to the local oscillator OSC and comprising a voltage-controlled oscillator (briefly, VCO) coupled to the RF front-end 12, the PLL 11 configured to provide a VCO signal VO having a further frequency F VCO and a local oscillator LO1 having a LO signal frequency that is a fraction of the VCO signal frequency Fvco, e.g., F LO1 =F VCO / 4.

[0028] As exemplified in Figure 1, the PLL 11 is configured to provide a signal which is an integer multiple of a fundamental frequency set for the GNSS standard (e.g., with f0=1.023MHz equal to the GNSS frequency, the PLL 11 may provide the VCO signal VO at a frequency about 6.285 GHz, with the local oscillator signal LO1 at a local oscillator frequency about 1571.375 MHz).

[0029] As exemplified herein, the RF front-end 12 is configured to provide a set of processed signals I1, Q 1 , I 2 , Q 2 , I 3 , Q 3 .

[0030] For the sake of simplicity, one or more embodiments are discussed in the following mainly with respect to an arrangement comprising a number of three spectral portions or frequency bands in which the RF signal S RF is analyzed, such a number of frequency bands being purely exemplary and in no way limiting.

[0031] As exemplified in Figure 1, the set of processed signals I 1 , Q 1 , I 2 , Q 2 , I 3 , Q 3 comprises: a first pair of processed signals I 1 , Q 1 for a first frequency band of the RF signal S RF , the first pair of processed signals I 1 , Q 1 comprising a first signal I 1 and a second signal Q 1 as a quadrature version of the first signal I 1 , a second pair of processed signals I 2 , Q 2 for a second frequency band of the RF signal S RF , the second pair of processed signals I 2 , Q 2 comprising a third signal I 2 and a fourth signal Q 2 as a quadrature version of the third signal I 2 , a third pair of processed signals I 3 , Q 3 for a third frequency band of the RF signal S RF , the third pair of processed signals I 3 , Q 3 comprising a fifth signal I 3 and a sixth signal Q 3 as a quadrature version of the fifth signal I 3 .

[0032] As exemplified in Figure 1, the system 10 further comprises analog-to-digital converter (briefly, ADC) circuitry 14 coupled to the front-end 12 and configured to apply analog-to-digital conversion to the set of processed signals I 1 , Q 1 , I 2 , Q 2 , I 3 , Q 3 .

[0033] For instance, the ADC circuitry 14 comprises: a first pair of ADC circuits 140, 141 configured to receive the first pair of signals I 1 , Q 1 , the first pair of ADC circuits 140, 141 comprising a first ADC circuit 140 configured to apply ADC processing to the first signal I 1 and a second ADC circuit 141 configured to apply ADC processing to the second signal Q 1 , a second pair of ADC circuits 142, 144 configured to receive the second pair of signals I 2 , Q 2 , the second pair of ADC circuits 142, 144 comprising a third ADC circuit 142 configured to apply ADC processing to the third signal I 2 and a fourth ADC circuit 144 configured to apply ADC processing to the fifth signal Q 2 , a third pair of ADC circuits 146, 148 comprising a fifth ADC circuit 146 configured to apply ADC processing to the fifth signal I 3 and a sixth ADC circuit 148 configured to apply ADC processing to the sixth signal Q 3 .

[0034] As exemplified in Figure 1, the ADC circuitry 14 receives a sampling signal Fs and applies ADC conversion to the pairs of signals I 1 , Q 1 , I 2 , Q 2 , I 3 , Q 3 via sampling such signals at a frequency of the sampling signal Fs, in a manner per se known to those of skill in the art.

[0035] For instance, the sampling signal frequency Fs may be a fraction of the frequency of the VCO signal VO, e.g., F s =VCO / 6=1047.583MHz.

[0036] For instance, after the ADC processing 14 is applied, the ADC converted data has a frequency that is a fraction of the sampling signal frequency Fs, e.g., Fs / 8=130.945MHz=128*f0.

[0037] As exemplified in Figure 1, the ADC circuitry 14 produces ADC converted signals S 1 , S 2 , S 3 , e.g., digital signals indicative of the contents in respective frequency bands of the RF signal S RF .

[0038] As exemplified in Figure 1, the system 10 further comprises: a first (e.g., programmable) frequency divider 13 coupled to the PLL 11 to receive the local oscillator signal LO1 therefrom, the first frequency divider 13 configured to apply frequency division (e.g., using a first programmable scaling factor K) to the local oscillator signal LO1, providing an adequate clock signal to the GNSS base band processor 16; a second frequency divider 15 coupled to the PLL 11 to receive the local oscillator signal LO1 therefrom, the second frequency divider 15 configured to apply frequency division (e.g., using a second programmable scaling factor H) to the local oscillator signal LO1, providing a clock signal CK2 to further processing circuitry (e.g., an ARM processor); and a base band processor 16 coupled to the ADC circuitry 14 to receive the ADC-converted signals S 1 , S 2 , S 3 therefrom and coupled to the first frequency divider 13 to receive the GNSS clock CK1 therefrom, the base band processor 16 configured to perform GNSS signal processing based on the ADC-converted signals S 1 , S 2 , S 3 and on the GNSS clock CK1 in a manner per se known.

[0039] For instance, the VCO in the PLL 11 produces a signal VO at a VCO frequency F VCO = 6144*f0 = 6.285GHz where f0 is the fundamental GNSS frequency (e.g., f0)=1.023MHz).

[0040] For instance, the local oscillator has a LO frequency F LO1 which is a fraction of the VCO frequency (e.g., F LO1 =VCO / 4=1536*f0=1.5713GHz).

[0041] For instance, the first clock CK1 has a frequency F CK1 which is a fraction of the local oscillator frequency, e.g., F CK1 =F LO1 / K.

[0042] For instance, the scaling factor K of the first frequency divider 13 may have the exemplary values illustrated in Table I provided at the end of the description, which is exemplary of possible relationships between scaling factor K and local oscillator frequency, with factor of multiplication n indicating the integer multiple of the fundamental GNSS frequency.

[0043] For instance, it may be preferable to use of signals whose frequency is a multiple of the fundamental GNSS frequency f0 so as to facilitate processing of ADC converted data and of software library development.

[0044] For instance, the possibility to vary the clock frequency in a programmable manner facilitates current saving in case the system is used to process a subset of the incoming GNSS signals.

[0045] As exemplified in Figure 2, the RF front end 12 comprises: a quadrature demodulator or I / Q mixer CH0 (known per se) coupled to the antenna RX (optionally, via a low-noise amplifier) to receive the RF signal S RF and coupled to the PLL 11 to receive the local oscillator signal LO1 therefrom; the quadrature demodulator CH0 comprises a phase-shifter 20, a first "in-phase" mixer 21 and a second "quadrature" mixer 22, where the first mixer 21 of the quadrature demodulator 21, 22 provides a first "in-phase" component I of the (optionally, amplified) RF signal S RF by mixing the RF signal with the local oscillator signal LO1 while the second mixer 22 of the quadrature demodulator CH0 provides a second "quadrature" component Q of the (optionally, amplified) RF signal S RF by mixing the RF signal S RF with a quadrature version of the local oscillator signal LO1, that is phase-shifted by 90 degrees via phase-shifter 20; a first signal processing channel CH1 coupled to the quadrature demodulator CH0 to receive the in-phase I and quadrature Q components of the RF signal S RF , the first signal processing channel CH1 configured to apply a first signal processing to the in-phase I and quadrature Q components of the RF signal S RF to provide the first pair of processed signals I 1 , Q 1 ; a second signal processing channel CH2 coupled to the quadrature demodulator 20, 21, 22 to receive the in-phase I and quadrature Q components of the RF signal S RF and coupled to the PLL 11 to receive the local oscillator signal LO1 therefrom, the second signal processing channel CH2 configured to apply a second signal processing to the in-phase I and quadrature Q components of the RF signal S RF and to the local oscillator LO1 to provide the second pair of processed signals I 2 , Q 2 ; and a third signal processing channel CH3 coupled to the quadrature demodulator 20, 21, 22 to receive the in-phase I and quadrature Q components of the RF signal S RF and coupled to the PLL 11 to receive the signal VO from the voltage-controlled oscillator VCO in the PLL 11, the third signal processing channel CH3 configured to apply a third signal processing to the in-phase I and quadrature Q components of the RF signal S RF and to the VCO signal VO to provide the third pair of processed signals I 3 , Q 3 .

[0046] As appreciable to those of skill in the art, the modulated RF signal may be expressed as: S RF t = S t cos 2 π F c t + φ + IM t cos 2 π 2 F LO1 − F c t + σ where: F c is a carrier frequency of the RF signal S RF , ϕ is a first initial phase, σ is a second initial phase, F LO1 is a frequency of the local oscillator signal LO1, S(t) is the desired signal component, and IM(t) is the image signal component.

[0047] As exemplified in Figures 3A and 3B, both in case the carrier frequency Fc is greater than the local oscillator frequency F LO1 and vice versa, the desired signal component S is superimposed on the carrier frequency FC while the image signal component IM is superimposed at a frequency twice the local oscillator minus the carrier frequency (e.g., 2*F LO1 -F C ).

[0048] As exemplified in Figure 3C, after mixing the RF signal S RF in the quadrature mixer 20, 21, 22, both the desired signal component S and the image signal IM are displaced towards an "intermediate frequency" (briefly, IF) F IF1 which is in a range of frequencies between base band and radio frequency, e.g., F IF1 =Fc-F LO1 . For instance, in-phase component I and quadrature component Q are at this intermediate frequency IF and are indicative of the desired signal component S and of the image signal component IM.

[0049] As exemplified in Figure 2, each of the processing chains is configured to generate an IF signal by processing and combining intermediate signals in phase I and in quadrature Q so as to delete the contribution of the image signal I with respect to the IF signal displaced at the IF frequency as exemplified in Figure 3C.

[0050] For instance, the in-phase component I may be expressed as: I = S t cos 2 πF IF1 t + φ − ϑ + IM t cos 2 πF IF1 t + σ − ϑ while the quadrature component Q may be expressed as: Q = S t sin 2 πF IF1 t + φ − ϑ − IM t sin 2 πF IF1 t + σ − ϑ where FIF1 is the first intermediate frequency, ϕ is a first signal phase, Θ is a second signal phase.

[0051] As exemplified in Figure 2, the first signal processing chain CH1 comprises: a first buffer 210 having a first buffer input node coupled to the first mixer 21 to receive the in-phase component I and a second buffer input node coupled to the second mixer 22 to receive the quadrature component Q, the first buffer 210 configured to provide a first IF signal IF1 based on the I and Q components provided by the quadrature demodulator 20, 21, 22, and a first variable gain amplifier (briefly, VGA) 212 coupled to the first buffer 210 to receive the first IF signal IF1 and to apply variable gain amplification 212 thereto (and, optionally, also anti-alias filtering), providing the first processed signal I 1 and the second processed signal Q 1 of the first pair of processed signals I 1 , Q 1 .

[0052] As exemplified in Figure 2, the second signal processing chain CH2 comprises: a second buffer 220 having a first buffer input node coupled to the first mixer 21 to receive the in-phase component I and a second buffer input node coupled to the second mixer 22 to receive the quadrature component Q; a filtering stage 222, such as a polyphase filter (e.g., a Hartley or Weaver filter, known per se), configured to apply signal filtering to the I and Q components provided by the quadrature demodulator 20, 21, 22; for instance, the filtering stage 222 may be tuned to remove the image signal of GNSS signals in a first frequency band selected out of L5, E5a and B2a frequency bands; an adder stage 224 configured to combine therebetween the filtered I / Q components, providing a second IF signal IQ2 as a superposition of the filtered I / Q components; a LO frequency divider 225 coupled to the PLL 11 to receive the local oscillator signal LO1 therefrom, the LO frequency divider 225 being configured to apply frequency division (e.g., via a programmable scaling factor M) to the local oscillator signal LO1, providing a second LO signal LO2 having a second LO frequency F LO2 that is a fraction of the local oscillator frequency F LO1 (e.g., F LO2 =F LO1 / M); a second quadrature demodulator 226, 227, 228, comprising a 90° phase-shifter 228, a second "in-phase" mixer 226 and a second "quadrature" mixer 227, where the second in-phase mixer 226 of the second quadrature demodulator 226, 227, 228 provides a first "in-phase" component I 2 of the second IF signal IF2, mixing the second IF signal IF2 with the second local oscillator signal LO2, while the second quadrature mixer 226 of the quadrature demodulator 226, 227, 228 provides a second "quadrature" component Q 2 of the second IF signal IF2, mixing the second IF signal IF2 with a quadrature version of the second local oscillator signal LO2, that is phase-shifted by 90 degrees via phase-shifter 226; and a second VGA 229 coupled to the second quadrature mixer 226, 227, 228 and configured to receive the image and quadrature signals from the second quadrature demodulator 226, 227, 228, the second VGA 229 configured to provide the third I 2 and fourth Q 2 processed signals.

[0053] For instance, document Fayrouz. Haddad, Lakhdar Zaid, Wenceslas Rahajandraibe, Oussama Frioui: "Polyphase Filter Design Methodology for Wireless Communication Applications", Salma Ait Fares, Mobile and Wireless Communications, Network layer and circuit level design, IntechOpen, pp.219-246, 2010, doi: 10.5772 / 7707 hal-01895400 discusses a filter stage 222 suitable for use in one or more embodiments.

[0054] For instance, the signal IQ2 comprises the signal at the first intermediate frequency FIF1 cleaned from the image signal and may be expressed as: IQ 2 t = S t cos 2 π F IF1 t + φ + IM t cos 2 π 2 F LO1 − F IF1 t + σ where F LO1 is the frequency of the local oscillator signal LO1.

[0055] As exemplified in Figure 2, the off-loop frequency divider 235 is used to bring the signal components I, Q at the first intermediate frequency IF1 down to a further reduced intermediate frequency IF2, e.g., with IF2=IF1-LO2. This may facilitate further signal processing by the subsequent A / D converter circuitry 14, for instance.

[0056] For instance, an in-phase signal I IF2 and a quadrature signal Q IF2 produced by the second down-conversion stage 226, 227, 228, can be expressed as: I IF2 = S t cos 2 πF IF2 t + φ − ϑ + IM t cos 2 πF IF2 t + σ − ϑ Q IF 2 = − S t sin 2 πF IF2 t + φ − ϑ + IM t sin 2 πF IF2 t + σ − ϑ where F IF2 is the second intermediate frequency, e.g., F IF2 =|F IF1 |-|F LO2 |.

[0057] As exemplified in Figure 2, the third signal processing chain CH3 comprises: a third buffer 230 having a first buffer input node coupled to the first in-phase mixer 21 to receive the in-phase component I and a second buffer input node coupled to the second mixer 22 to receive the quadrature component Q; a third filtering stage 232, such as a polyphase filter as in the case of the second filtering stage 222 but tuned to work in a different frequency (e.g., for GNSS signals in a second frequency band selected out of L2 and BW3 frequency bands), configured to apply signal filtering to the I and Q components provided by the quadrature demodulator 20, 21, 22; a further adder stage 234 configured to combine therebetween the filtered I / Q components, providing a third IF signal IQ3 as a superposition of the filtered I / Q components; a VCO frequency divider 235 coupled to the PLL 11 to receive the VCO signal VO therefrom, the VCO frequency divider 235 being configured to apply frequency division (e.g., via a programmable scaling factor G) to the VCO signal VO, providing a third LO signal LO3 having a third frequency F LO3 that is a fraction of the VCO frequency F LO3 (e.g., F LO3 =F LO2 / G); a third quadrature demodulator 236, 237, 238, comprising a 90° phase-shifter 238, a third "in-phase" mixer 236 and a third "quadrature" mixer 238, where the third in-phase mixer 236 of the third quadrature demodulator 236, 237, 238 provide a third "in-phase" component I 3 of the third IF signal IF3, mixing the third IF signal IF3 with the third local oscillator signal LO3, while the third quadrature mixer 236 of the quadrature demodulator 236, 237, 238 provides a third "quadrature" component Q IF3 , mixing the third IF signal IQ3 with a quadrature version of the third local oscillator signal LO3, that is phase-shifted by 90 degrees via phase-shifter 236; and a third VGA 239 coupled to the third quadrature mixer 236, 237, 238 and configured to receive the image I IF3 and quadrature Q IF3 signals from the third quadrature demodulator 236, 237, 238, the third VGA 239 configured to provide the fifth I 3 and sixth Q 3 processed signals.

[0058] As exemplified herein, the third filtering stage 232 is configured to filter the image signal from the second IF signal at the second intermediate frequency signal IF2, producing the signal IQ3 as a result.

[0059] For instance, the VCO frequency divider 235 uses a scaling factor G about 18 or 20, providing the third LO signal LO3 with a third LO frequency F LO3 which is a fraction G of the frequency of VCO, e.g., F LO3 =F VCO / G=F VCO / 18 or F VCO / 20.

[0060] It is noted that the phase shifters 20, 226 and 236 exemplified in Figure 2 are purely exemplary an in no way mandatory, as in one or more embodiments the signals LO1, LO2, LO3 can be provided (e.g., by respective divider blocks) as a pair of phase-shifted signals in quadrature therebetween.

[0061] As exemplified in Figure 2, the scaling factor G of the VCO divider 235 is an even integer number so as to provide the local oscillator to the third quadrature mixer 236, 237, 238.

[0062] For instance, the presence of the VCO divider 235 facilitates obtaining signals I3, Q3 which have a lower intermediate frequency F IF3 with respect to the signals I, Q provided by the first quadrature mixer 20, 21, 22, e.g., I F3 <I F1 . This facilitates further processing by the A / D converter circuitry 14, for instance.

[0063] As exemplified herein, a system 12 comprises: an input node S RF configured to receive a set of global navigation satellite system, GNSS signals S 0 , S N transmitted from a plurality of GNSS satellites SC 0 , SC N over a set of carrier frequencies f 1 , f 11 , f 2 , f 3A1 , f 3A2 , f 3B1 , f 3B2 , Fc; a phase-locked loop, PLL 11 configured to provide a first local oscillator signal LO1 and a voltage-controlled oscillator, VCO signal VO; a first quadrature demodulator CH0 coupled to the input node and to the PLL, the first quadrature demodulator CH0 configured to apply quadrature demodulation processing 20, 21, 22 to the set of GNSS signals based on the local oscillator signal received from the PLL, the first quadrature demodulator providing a first set of in-phase signals I and a first set of quadrature signals Q as a result.

[0064] For instance, in-phase signals of the first set of in-phase signals and quadrature signals of the first set of quadrature signals have a first intermediate frequency F IF1 lower than carrier frequencies of the set of carrier frequencies of GNSS signals of the set of GNSS signals.

[0065] As exemplified herein, the system further comprises: a first signal processing chain CH1 coupled to the first quadrature demodulator to receive the set of in-phase signals and the set of quadrature signals, the first signal processing chain comprising a first variable gain amplifier, VGA 212 coupled to the first quadrature demodulator, the VGA configured to apply a first variable gain amplification to the first set of in-phase signals and to the first set of quadrature signals, providing a first in-phase signal component I 1 and a first quadrature signal component Q 1 as a result; a second signal processing chain CH2 coupled to the first quadrature demodulator to receive the first set of in-phase signals and the first set of quadrature signals and coupled to the PLL to receive the first local oscillator signal, the second signal processing chain comprising: a first polyphase filter 222 configured to apply polyphase filtering to the first set of in-phase signals and to the first set of quadrature signals, producing a first set of filtered in-phase signals and a first set of filtered quadrature signals as a result; a first adder 224 coupled to the first polyphase filter to receive the first set of filtered in-phase signals and the first set of filtered quadrature signals, the first adder configured to provide a first sum signal IQ 2 as a sum of the first set of filtered in-phase signals and the first set of filtered quadrature signals, a first frequency divider 225 configured to apply frequency division to the first local oscillator signal, producing a second local oscillator signal LO2 as a result, wherein the second local oscillator signal has a second local oscillator frequency that is a fraction of the frequency of the local oscillator signal; a second quadrature demodulator 226, 227, 228 coupled to the adder and to the first frequency divider, the second quadrature demodulator 226, 227, 228 configured to apply second quadrature demodulation processing to the first sum signal, providing, based on the second local oscillator signal, a second set of in-phase signals and a second set of quadrature signals, the second set of in-phase signals and the second set of quadrature signals having a second intermediate frequency IF2 lower than the first intermediate frequency, and a second VGA 229 configured to apply a second variable gain amplification to the second set of in-phase signals and to the second set of quadrature signals, the second VGA configured to produce a second in-phase signal component I 2 and a second quadrature signal component Q 2 as a result; a third signal processing chain CH3 coupled to the first quadrature demodulator to receive the set of in-phase signals and the set of quadrature signals and coupled to the PLL to receive the VCO signal, the third signal processing chain comprising: a second polyphase filter 232 configured to apply second polyphase filtering to the first set of in-phase signals and to the first set of quadrature signals, producing a second set of filtered in-phase signals and a second set of filtered quadrature signals as a result; a second adder 234 coupled to the second polyphase filter to receive the second set of filtered in-phase signals and the second set of filtered quadrature signals therefrom, the second adder configured to provide a second sum signal IQ 3 as a sum of the second set of filtered in-phase signals and the second set of filtered quadrature signals; a second frequency divider 235 configured to apply a second frequency division to the VCO signal, producing a third local oscillator signal LO3 as a result, wherein the third local oscillator signal has a third local oscillator frequency that is a fraction of the frequency of the VCO signal; a third quadrature demodulator 236, 237, 238 coupled to the second adder and to the second frequency divider, the third quadrature demodulator 236, 237, 238 configured to apply third quadrature demodulation processing to the second sum signal, providing, based on the third local oscillator signal, a third set of in-phase signals and a third set of quadrature signals, the third set of in-phase signals and the third set of quadrature signals having a third intermediate frequency IF3 lower than the second intermediate frequency, and a third VGA 239 configured to apply a third variable gain amplification to the third set of in-phase signals and to the third set of quadrature signals, the third VGA configured to produce a third in-phase signal component I 3 and a third quadrature signal component Q 3 as a result.

[0066] As exemplified herein, the first local oscillator signal has a first local oscillator frequency that is fraction of the frequency of the VCO signal.

[0067] As exemplified herein, the first frequency divider is configured to apply frequency division using a first programmable frequency division factor.

[0068] As exemplified herein, the second frequency divider is configured to apply frequency division using a second programmable frequency division factor, preferably programmable in a range 18 to 20.

[0069] As exemplified herein, GNSS signals of the set of GNSS signals transmitted from a plurality of GNSS satellites over a set of carrier frequencies comprise signals transmitted over frequency bands distinct and separate BW1, BW2, BW3A, BW3B.

[0070] As exemplified herein, GNSS signals of the set of GNSS signals transmitted from a plurality of GNSS satellites over the set of carrier frequencies comprise at least two of: a first GNSS signal S 0 transmitted over a first carrier frequency f 1 , f 11 , a second GNSS signal S N transmitted over a second carrier frequency f 2 , the second carrier frequency higher than the first carrier frequency, a third GNSS signal S RF transmitted over a third carrier frequency f 3A1 , f 3A2 , f 3B1 , f 3B2 higher than the second carrier frequency.

[0071] As exemplified herein, the first set of in-phase signals and the first set of quadrature signals comprise at least one image signal component, and the first polyphase filter is configured to filter at least one image signal component of the first set of in-phase signals and of the first set of quadrature signals, producing the first set of filtered in-phase signals and the first set of filtered quadrature signals exempt from at least one image signal component as a result.

[0072] As exemplified herein, the first set of in-phase signals and the first set of quadrature signals comprise at least one image signal component and the second polyphase filter is configured to filter at least one image signal component of the first set of in-phase signals and the first set of quadrature signals, producing the second set of filtered in-phase signals and the second set of filtered quadrature signals exempt from at least one image signal component as a result.

[0073] As exemplified herein, a (e.g., RF) receiver 100 comprises: a system 12 as per the present disclosure, an antenna RX configured to receive the set of GNSS signals and coupled to the to the input node of the system to provide the received set of GNSS signals thereto, a set of analogue-to-digital converter, ADC, circuits 14 coupled to the first signal processing chain, the second signal processing chain and to the third signal processing chain, the set of ADC circuits configured to apply analogue-to-digital conversion to the first in-phase component, the first quadrature component, the second in-phase component, the second quadrature component, the third in-phase component and the third quadrature component, providing a set of digital signal components as a result.

[0074] As exemplified herein, the receiver comprises a baseband circuit block 16 coupled to the set of ADC circuits 14, the base stand circuit block configured to apply baseband signal processing to the set of digital signals received from the set of ADC converters.

[0075] As exemplified herein, the set of ADC converter circuits is configured to apply the analog-to-digital conversion based on a sampling signal Fs having a sampling frequency that is a multiple of a fundamental GNSS frequency.

[0076] As exemplified in Figure 4, the system exemplified in Figures 1 and 2 can be used to process signals which have a carrier frequency band F C that may fall in a variety of frequency bands such as, for instance: a first frequency band BW1 comprising signals that fall in a first frequency range f 1 -f 11 , e.g., between 1559 MHz and 1606 MHz; a second frequency band BW2, e.g., centered around a second frequency band f 2 , such as a frequency about 1176 MHz; a third frequency band BW3A in a third frequency range, e.g., f 3A1 -f 3A2 between 1200 MHz and 1250 MHz, such as 1207.14 MHz, for instance; a fourth frequency band BW3B in a fourth frequency range f 3B1 -f 3B2 , such as between 1258 MHz and 1289 MHz, for instance.

[0077] For instance, GNSS signals S 0 ,...,S N may be transmitted and received from satellites in a variety of known GNSS constellations using any of these frequency bands BW1, BW2, BW3A, BW4A.

[0078] For instance, the first signal processing chain CH1 may be suitable to process a RF signal received in the first frequency band BW1, e.g., from a first set of GNSS constellation of satellites L1CA, E1, L1C, B1C, B1I, LOF1, L1OC and / or any other signal in these frequency bands.

[0079] For instance, the second signal processing chain CH2 may be suitable to process a RF signal received in the second frequency band BW2, e.g., from a second set of constellations L5, B2a, E5a.

[0080] For instance, the third signal processing chain CH3 may be suitable to process a RF signal S RF received in the third frequency band BW3A (e.g., from a third set of constellations L2C, B2b, B2l, E5b, L3OC) or in the fourth frequency band BW3B (e.g., from a fourth set of constellations L2OC, L2OF, B3l, E6).

[0081] Table II provided at the end of the description exemplifies settings of the first signal processing chain CH1, such as carrier frequency Fc, bandwidth BW, VCO signal frequency F VCO , first local oscillator signal frequency F LO1 and intermediate frequency IF1 which may be used to process signals from a variety of constellations configured to transmit signals over frequency bands (e.g., L1c / a, L1C, E1, B1I, B1C, LOF1) in the first bandwidth BW1.

[0082] Table III provided at the end of the description exemplifies settings of the second signal processing chain CH2, such as carrier frequency Fc, bandwidth BW, VCO signal frequency F VCO , first local oscillator signal frequency F LO1 , second LO signal frequency F LO2 , scaling factor M, intermediate frequency IF2 and maximum frequency Max F which may be used to process signals from a variety of the constellations configured to transmit signals over frequency bands (e.g., L5, such as GPS and others, B2a, E5a) in the second bandwidth BW2.

[0083] Table IV provided at the end of the description exemplifies settings of the third signal processing chain CH3, such as carrier frequency Fc, bandwidth BW, VCO signal frequency F VCO , first local oscillator signal frequency F LO1 , third local oscillator signal frequency F LO3 , scaling factor G, third intermediate frequency IF3 and maximum frequency Max F which may be used to process signals from a variety of constellations configured to transmit over frequency bands (e.g., L2C, B2b, B2l, E5b) in the third bandwidth BW3A.

[0084] Table V provided at the end of the description exemplifies of the third signal processing chain CH3 such as carrier frequency F C , bandwidth BW, VCO signal frequency F VCO , first local oscillator signal frequency F LO1 , third local oscillator signal frequency F LO3 , scaling factor G, third intermediate frequency IF3 and maximum frequency Max F which may be used to process signals from a variety of constellations configured to transmit over frequency bands (e.g., alternative constellations L2OC, L2OF, B3l, E6) in the fourth bandwidth BW3B.

[0085] Table VI provided at the end of the description is exemplary of combinations of constellations and respective names of channels that may be used to process signals received from such exemplary combinations of constellations.

[0086] As exemplified in Table VI, the system as exemplified in Figures 1 and 2 provides flexibility to deal with a wide variety of application scenarios, as those listed in the Table VI are purely exemplary an in no way limiting.

[0087] It will be otherwise understood that the various individual implementing options exemplified throughout the figures accompanying this description are not necessarily intended to be adopted in the same combinations exemplified in the figures. One or more embodiments may thus adopt these (otherwise non-mandatory) options individually and / or in different combinations with respect to the combination exemplified in the accompanying figures.

[0088] Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described by way of example only, without departing from the extent of protection. The extent of protection is defined by the annexed claims. TABLE IK LO1 / K 2^n * f0 6256*f0n = 812128*f0n = 72464*f0n = 64832*f0n = 59616*f0n = 4 TABLE II Constell. frequency bandF C [MHz]BW [MHz]F VCO [MHz]F LO1 [MHz]IF1 [MHz]Max F [MHz]L1C / A orLIC1575.422.0466285.51571.3754.0455.068E11575.424.0926285.51571.3754.0456.091B1I1561.0984.0926285.51571.375-10.27712.323B1C1575.4232.7366285.51571.3754.04520.413LOF116027.8756285.51571.37530.62534.5625 TABLE III Constell. name or frequency bandF C [MHz]BW [MHz]F VCO [MHz]F LO1 [MHz]IF1 [MHz]MF LO2 [MHz]IF2 [MHz]Max F [MHz]GPS - L51176.4520.466285.51571.375394.9254392.84382.0812512.31125E5A1176.4520.466285.51571.375394.9254392.84382.0812512.31125B2A1176.4520.466285.51571.375394.9254392.84382.0812512.31125IRNSS - L51176.452.0466285.51571.375394.9254392.84382.081253.10425 TABLE IV Constell. frequency bandF C [MHz]BW [MHz]F VCO [MHz]F LO1 [MHz]IF1 [MHz]GF LO3 [MHz]IF3 [MHz]Max F [MHz]L2C1227.61.0236285.51571.375343.77518349.19445.4194445.930944E5b1207.1420.466285.51571.375364.23518349.1944-15.040625.27056B211207.146285.51571.375364.23518349.1944-15.0406B2B1207.1420.466285.51571.375364.23518349.1944-15.040625.27056LCF212466.1256285.51571.375325.37518349.194423.8194426.88194L2CC1248.062.0466285.51571.375323.31518349.194425.8794426.90244L3CC1202.0252.0466285.51571.375369.3518349.1944-20.155621.17856 TABLE V Constell. frequency bandF C [MHz]BW [MHz]F VCO [MHz]F LO1 [MHz]IF1 [MHz]GF LO3 [MHz]IF3 [MHz]Max F [MHz]L2C1227.61.0236285.51571.375343.77520314.275-29.530.0115E6I1278.7510.236285.51571.375292.62520314.27521.6526.765B3I1268.5220.466285.51571.375302.85520314.27511.4221.65 TABLE VI L1C / AL2CLOF1LOF2E1E5bB1IB21CH1, CH 31575.421227.6160212461575.421207.141561.091207.14L1C / A or L1CL2CLOF1LOF2E1E5bB1IB1CB2IB2BCH1, CH31575.421575.421227.6160212461575.421207.141561.091575.421207.141207.14L1C / AL5E1E5AB1IB2AL5CH1, CH21575.421176.451575.421176.451561.091176.451176.45L1C / A or L1CL5E1E5AB1I or B1CB2AL5CH1, CH21575.421575.421176.451575.421176.451561.09 1575.421176.451176.45L1C / A or L1CL2CE1E6IB1I or B1CB3ICH1, CH31575.421575.421227.61575.421278.751561.091575.421268.52L1C / AL2CL5E1E5BE5AB1IB2IB2ACH1, CH2, CH31575.451227.61176.451575.421207.141176.451561.091207.141176.45L1C / A or L1CL2CL5E1E5BE5AB1I or B1CB2I or B2BB2ACH1, CH2, CH31575.421575.421227.61176.451575.421207.141176.451561.091575.421207.141207.141176.45L1C / A or L1CL2CL5E1E6IE5AB1I or B1CB3IB2ACH1, CH2, CH31575.421575.421227.61176.451575.421278.751176.451561.091575.421268.521176.45L1CL2CL5L1OCL2OCL3OCCH1, CH2, CH31575.421227.61176.451600.991248.061202.02

Claims

1. A system (10), comprising: an input node (SRF) configured to receive a set of global navigation satellite system, GNSS signals (S0, SN) transmitted from a plurality of GNSS satellites (SC0, SCN) over a set of carrier frequencies (f1, f11, f2, f3A1, f3A2, f3B1, f3B2, Fc); a phase-locked loop, PLL (11) configured to provide a first local oscillator signal (LO1) and a voltage-controlled oscillator, VCO signal (VO); a first quadrature demodulator (CH0) coupled to the input node (SRF) and to the PLL (11), the first quadrature demodulator (CH0) configured to apply quadrature demodulation processing (20, 21, 22) to the set of GNSS signals (S0, SN) based on the local oscillator signal (LO1) received from the PLL (11), the first quadrature demodulator (CH0) providing a first set of in-phase signals (I) and a first set of quadrature signals (Q) as a result, wherein in-phase signals of the first set of in-phase signals (I) and quadrature signals of the first set of quadrature signals (Q) have a first intermediate frequency (FIF1) lower than carrier frequencies of the set of carrier frequencies (f1, f11, f2, f3A1, f3A2, f3B1, f3B2, FC) of GNSS signals of the set of GNSS signals (S0, SN), characterized in that the system (10) comprises: a first signal processing chain (CH1) coupled to the first quadrature demodulator (CH0) to receive the set of in-phase signals (I) and the set of quadrature signals (Q), the first signal processing chain (CH1) comprising a first variable gain amplifier, VGA (212) coupled to the first quadrature demodulator (CH0), the VGA (212) configured to apply a first variable gain amplification to the first set of in-phase signals (I) and to the first set of quadrature signals (Q), providing a first in-phase signal component (I1) and a first quadrature signal component (Q1) as a result; a second signal processing chain (CH2) coupled to the first quadrature demodulator (CH0) to receive the first set of in-phase signals (I) and the first set of quadrature signals (Q) and coupled to the PLL (11) to receive the first local oscillator signal (LO1), the second signal processing chain (CH2) comprising: a first polyphase filter (222) configured to apply polyphase filtering to the first set of in-phase signals (I) and to the first set of quadrature signals (Q), producing a first set of filtered in-phase signals and a first set of filtered quadrature signals as a result; a first adder (224) coupled to the first polyphase filter (222) to receive the first set of filtered in-phase signals and the first set of filtered quadrature signals, the first adder (224) configured to provide a first sum signal (IQ2) as a sum of the first set of filtered in-phase signals and the first set of filtered quadrature signals, a first frequency divider (225) configured to apply frequency division to the first local oscillator signal (LO1), producing a second local oscillator signal (LO2) as a result, wherein the second local oscillator signal (LO2) has a second local oscillator frequency that is a fraction of the frequency of the local oscillator signal (LO1); a second quadrature demodulator (226, 227, 228) coupled to the first adder (224) and to the first frequency divider (225), the second quadrature demodulator (226, 227, 228) configured to apply second quadrature demodulation processing to the first sum signal (IQ2), providing, based on the second local oscillator signal (LO2), a second set of in-phase signals and a second set of quadrature signals, the second set of in-phase signals and the second set of quadrature signals having a second intermediate frequency (IF2) lower than the first intermediate frequency (IF1, FIF1), and a second VGA (229) configured to apply a second variable gain amplification to the second set of in-phase signals and to the second set of quadrature signals, the second VGA (229) configured to produce a second in-phase signal component (I2) and a second quadrature signal component (Q2) as a result; a third signal processing chain (CH3) coupled to the first quadrature demodulator (CH0) to receive the set of in-phase signals (I) and the set of quadrature signals (Q) and coupled to the PLL (11) to receive the VCO signal (VO), the third signal processing chain (CH3) comprising: a second polyphase filter (232) configured to apply second polyphase filtering to the first set of in-phase signals (I) and to the first set of quadrature signals (Q), producing a second set of filtered in-phase signals and a second set of filtered quadrature signals as a result; a second adder (234) coupled to the second polyphase filter (232) to receive the second set of filtered in-phase signals and the second set of filtered quadrature signals therefrom, the second adder (234) configured to provide a second sum signal (IQ3) as a sum of the second set of filtered in-phase signals and the second set of filtered quadrature signals; a second frequency divider (235) configured to apply a second frequency division to the VCO signal (VO), producing a third local oscillator signal (LO3) as a result, wherein the third local oscillator signal (LO3) has a third local oscillator frequency that is a fraction of the frequency of the VCO signal (VO); a third quadrature demodulator (236, 237, 238) coupled to the second adder (234) and to the second frequency divider (235), the third quadrature demodulator (236, 237, 238) configured to apply third quadrature demodulation processing to the second sum signal (IQ3), providing, based on the third local oscillator signal (LO3), a third set of in-phase signals and a third set of quadrature signals, the third set of in-phase signals and the third set of quadrature signals having a third intermediate frequency (IF3) lower than the second intermediate frequency (IF2), and a third VGA (239) configured to apply a third variable gain amplification to the third set of in-phase signals and to the third set of quadrature signals, the third VGA (239) configured to produce a third in-phase signal component (I3) and a third quadrature signal component (Q3) as a result.

2. The system (10) according to claim 1, wherein the first local oscillator signal (LO1) has a first local oscillator frequency that is fraction of the frequency of the VCO signal (VO).

3. The system (10) according to claim 1 or claim 2, wherein the first frequency divider (225) is configured to apply frequency division using a first programmable frequency division factor.

4. The system according to any of the previous claims, wherein the second frequency divider (235) is configured to apply frequency division using a second programmable frequency division factor, programmable in a range 18 to 20.

5. The system (10) according to any of the previous claims, wherein GNSS signals of the set of GNSS signals (S0, SN) transmitted from a plurality of GNSS satellites (SC0, SCN) over a set of carrier frequencies (f1, f11, f2, f3A1, f3A2, f3B1, f3B2, FC) comprise signals transmitted over frequency bands distinct and separate (BW1, BW2, BW3A, BW3B).

6. The system (10) according to any of the previous claims, wherein GNSS signals of the set of GNSS signals (S0, SN) transmitted from a plurality of GNSS satellites (SC0, SCN) over the set of carrier frequencies (f1, f11, f2, f3A1, f3A2, f3B1, f3B2, FC) comprise at least two of: a first GNSS signal (S0) transmitted over a first carrier frequency (f1, fn), a second GNSS signal (SN) transmitted over a second carrier frequency (f2), the second carrier frequency (f2) higher than the first carrier frequency, a third GNSS signal (SRF) transmitted over a third carrier frequency (f3A1, f3A2, f3B1, f3B2) higher than the second carrier frequency (f2).

7. The system (10) according to any of the previous claims, wherein: the first set of in-phase signals (I) and the first set of quadrature signals (Q) comprise at least one image signal component, and the first polyphase filter (222) is configured to filter the at least one image signal component of the first set of in-phase signals (I) and of the first set of quadrature signals (Q), producing the first set of filtered in-phase signals and the first set of filtered quadrature signals exempt from at least one image signal component as a result.

8. The system (10) according to any of the previous claims, wherein: the first set of in-phase signals (I) and the first set of quadrature signals (Q) comprise at least one image signal component, and the second polyphase filter (232) is configured to filter at least one image signal component of the first set of in-phase signals (I) and the first set of quadrature signals (Q), producing the second set of filtered in-phase signals and the second set of filtered quadrature signals exempt from at least one image signal component as a result.

9. A receiver (100), comprising: a system (10) according to any of the previous claims, an antenna (RX) configured to receive the set of GNSS signals (S0, SN) and coupled to the to the input node (SRF) of the system (10) to provide the received set of GNSS signals thereto, a set of analogue-to-digital converter, ADC, circuits (14), coupled to the first signal processing chain (CH1), the second signal processing chain (CH2) and to the third signal processing chain (CH3), the set of ADC circuits (14) configured to apply analogue-to-digital conversion to the first in-phase component (I1), the first quadrature component (Q1), the second in-phase component (I2), the second quadrature component (Q2), the third in-phase component (I3) and the third quadrature component (Q3), providing a set of digital signal components as a result.

10. The receiver (100) according to claim 9, comprising a baseband circuit block (16) coupled to the set of ADC circuits (14), the base stand circuit block (16) configured to apply baseband signal processing to the set of digital signals received from the set of ADC converters (14).

11. The receiver (100) according to claim 9 or claim 10, wherein the set of ADC converter circuits (14) is configured to apply the analog-to-digital conversion based on a sampling signal (FS) having a sampling frequency that is a multiple of a fundamental GNSS frequency.