METHOD FOR MANUFACTURING A SUPRAL CONDUCTING ELECTRONIC DEVICE WITH AT LEAST ONE JOFET

Description

TECHNICAL FIELD

[0001] The invention relates to the field of electronic devices with one or more superconducting qubits, and more particularly with gatemon-type qubit(s). The invention advantageously applies to the production, in a semiconductor layer, of such a device. STATE OF THE PRIOR ART

[0002] In a superconducting qubit, the qubit takes the form of the state of a superconducting current that crosses a very thin barrier, relying on the Josephson effect. There are several types of superconducting qubits: flux, phase, or charge qubits. In these different types of qubits, the idea is to create a superposition of two distinct states of a current oscillating at high frequency and crossing the Josephson junction in a superconducting loop. The oscillation is made possible by the fact that the loop integrates the equivalent of an inductance and a resistance. The oscillation of the current is activated by the application of microwaves with frequencies between 5 and 10 GHz and transmitted by conductive and physical means. The state of the qubit corresponds to the resonance phase of the current or to the direction of the current, measured by a magnetometer or by coupling to a microwave resonator.

[0003] In a gatemon qubit, the Josephson junction can be realized by a Josephson junction field-effect transistor, also called a JoFET for "Josephson Field Effect Transistor" or JJ-FET for "Josephson Junction Field Effect Transistor". Such a transistor has a gate arranged above a channel semiconductor region extending between superconducting source and drain regions.

[0004] A disadvantage of making this type of qubit is that the superconducting regions are generally made from materials that are not compatible with the semiconductor technologies conventionally used in microelectronics.

[0005] Document US 2021 / 296557 A1 discloses a masked implantation method similar to the present application for producing a superconducting qubit in which superconductivity is obtained by implantation of a semiconductor. However, the consecutive steps of claim 1 are not disclosed by US 2021 / 296557 A1. In particular, these steps of claim 1 are aimed at producing a gate in order to obtain a gatemon-type qubit.

[0006] Similarly, the structure obtained by the method of US 2021 / 226114 A1 does not comprise a grid and, consequently, document US 2021 / 226114 A1 does not disclose corresponding steps for producing a grid. Moreover, in the structure of US 2021 / 226114 A1, the two superconducting electrodes are arranged one on top of the other. Therefore, in the structure of US 2021 / 226114 A1, there is not a first region covered by a protective dielectric potion arranged between two regions implanted by dopants as defined by claim 1.

[0007] The method of US 2021 / 384405 A1 comprises a doped region 204 disposed between two undoped regions. Moreover, there is no disclosure of a subsequent deposition of a protective dielectric layer or of the following steps defined by claim 1.

[0008] The article Casparis et al.: "Superconducting Gatemon Qubit based on a Proximitized Two-Dimensional Electron Gas", XP081148608, DOI: 10.1038 / S41565-018-0207-Y proposes a structure of a gatemon-type qubit and a method for producing it. However, the superconducting regions of the structure as seen in Casparis et al. are made of aluminum. Therefore, there are no steps of implanting the regions of a semiconductor into regions arranged in a manner defined by claim 1.

[0009] The article Daubriac et al.: "Superconducting Polycrystalline Silicon Layer Obtained by Boron Implantation and Nanosecond Laser Annealing", ECS Journal of Solid State Science and Technology, vol. 10, no. 1, page 14004, XP093006638, DOI: 10.1149 / 2162-8777 / abdc41 describes obtaining a superconducting region in a semiconductor by doping, but there is no disclosure of the steps of claim 1.

[0010] Document FR 3 088 483 A1 discloses a JoFET having superconducting regions 19a, 19b based on silicide. However, these regions 19a, 19b are formed by reaction of the semiconductor layer 4 with the metal layer 17. Thus, there is no step of implantation of the dopants, a reaction between two layers as written by FR 3 088 483 A1 being distinct from an implantation of the dopants in a material by a beam of particles. STATEMENT OF THE INVENTION

[0011] An aim of the present invention is to propose a method for producing an electronic device with superconducting qubit(s) including at least one JoFET, which can be implemented with techniques used in the field of semiconductors.

[0012] For this, the present invention proposes a method for producing an electronic device with superconducting qubit(s) including at least one JoFET formed by implementing the steps of: producing, on at least one semiconductor layer, at least one protective dielectric portion arranged on at least a first region of the semiconductor layer; implanting dopants in second regions of the semiconductor layer, adjacent to the first region and such that the first region is arranged between the second regions; depositing a protective dielectric layer covering at least the protective dielectric portion and the second regions; exposing the protective dielectric layer to at least one laser pulse; removing at least a portion of the protective dielectric layer covering the second regions; removing the protective dielectric portion; producing at least one electrostatic control grid on the first region; and wherein the materials and thicknesses of the protective dielectric portion and the protective dielectric layer, as well as the duration and power of said at least one laser pulse, are chosen such that the superposition of the protective dielectric portion and the protective dielectric layer on the first region prevents said at least one laser pulse from reaching the first region, and that the presence of the protective dielectric layer alone on the second regions allows said at least one laser pulse to reach the second regions and to melt the semiconductor of the second regions which forms, after cooling, a recrystallized semiconductor material having superconducting material properties.

[0013] Thus, this method proposes the production of an electronic device with one or more superconducting qubits including one or more JoFETs produced in a semiconductor layer. More particularly, the method according to the invention proposes producing the superconducting regions of the JoFET(s) by applying the principle of pulsed laser induced epitaxy or PLIE for "Pulsed Laser Induced Epitaxy", which consists of carrying out an implantation of dopants in the semiconductor material corresponding for example to silicon of a Bulk (massive) or SOI (silicon on insulator) substrate. The semiconductor material in which the implantation of dopants has been carried out is then subjected to one or more laser pulses melting the semiconductor material. The cooling of the semiconductor material causes its recrystallization which gives it superconducting properties.

[0014] In the method according to the invention, at least one protective dielectric portion and one protective dielectric layer are judiciously chosen and produced to allow both the melting by laser pulse(s) of the semiconductor in which the dopants are implanted to form superconducting regions, and to protect from the laser pulse(s) at least a first region of the semiconductor layer intended to form the junction between the superconducting regions.

[0015] The protective dielectric portion may comprise SiN, and the protective dielectric layer may comprise SiN and / or SiCO and / or SiO 2 .

[0016] The protective dielectric portion may be made by first depositing a layer of dielectric material on the semiconductor layer, then etching this layer such that at least a remaining portion of this layer forms the protective dielectric portion.

[0017] The choice of materials and thicknesses of the protective dielectric portion and the protective dielectric layer can be made: by choosing the material and the thickness of the protective dielectric layer such that the protective dielectric layer has a reflectivity, with respect to the wavelength of said at least one laser pulse, of less than or equal to 10%, or less than or equal to 15%, then by choosing the material and the thickness of the protective dielectric portion such that the superposition of the protective dielectric portion and the protective dielectric layer has a reflectivity, with respect to the wavelength of said at least one laser pulse, of greater than or equal to 50%, or greater than or equal to 55%.

[0018] The process can be as follows: the protective dielectric layer is deposited conformally, and the removal of at least a portion of the protective dielectric layer covering the second regions is achieved by implementing an anisotropic etching of the protective dielectric layer such that remaining portions of the protective dielectric layer form lateral dielectric spacers arranged against lateral flanks of the protective dielectric portion.

[0019] The method may further comprise, between the production of the protective dielectric portion and the implantation of the dopants in the second regions: conformal deposition of a second dielectric layer covering at least the protective dielectric portion and the second regions; anisotropic etching of the second dielectric layer such that remaining portions of the second dielectric layer cover lateral flanks of the protective dielectric portion and are arranged on the first region (and more precisely on edges of the first region); semiconductor epitaxy on the second regions; and the deposited protective dielectric layer may also cover the remaining portions of the second dielectric layer.

[0020] The epitaxially grown semiconductor complements the existing semiconductor of the second regions and is part of these second regions.

[0021] In the above case: the protective dielectric layer may be deposited conformally, and the removal of at least a portion of the protective dielectric layer covering the second regions may be achieved by implementing an anisotropic etching of the protective dielectric layer, the remaining portions of the protective dielectric layer forming, with the remaining portions of the second dielectric layer, lateral dielectric spacers arranged against lateral flanks of the protective dielectric portion, or the removal of at least a portion of the protective dielectric layer may correspond to a total removal of the protective dielectric layer.

[0022] The method may further comprise, between the production of the protective dielectric portion and the implantation of the dopants in the second regions: conformal deposition of a third dielectric layer covering at least the protective dielectric portion and the second regions, and the thickness of which is at least equal to that of the subsequently formed protective dielectric layer; anisotropic etching of the third dielectric layer such that remaining portions of the third dielectric layer cover lateral flanks of the protective dielectric portion and are arranged on the first region (these remaining portions of the third dielectric layer then have a dimension, corresponding to the thickness of the third dielectric layer, which is at least equal to the thickness of the subsequently formed protective dielectric layer); and may further comprise, between the implantation of the dopants in the second regions and the deposition of the protective dielectric layer, a removal of the remaining portions of the third dielectric layer.

[0023] In this case, the method may further comprise, between the removal of at least a portion of the protective dielectric layer covering the second regions and the removal of the protective dielectric portion, the production of lateral dielectric spacers against remaining portions of the protective dielectric layer, and the production of the electrostatic control grid may be preceded by a removal of the remaining portions of the protective dielectric layer.

[0024] The semiconductor layer may correspond to a surface layer of a semiconductor-on-insulator type substrate, for example of the SOI (silicon-on-insulator) type.

[0025] In this case, the dopants can be implanted throughout the entire thickness of the semiconductor layer, or the dopants can be implanted in only a portion of the thickness of the semiconductor layer.

[0026] Dopants can correspond to boron atoms implanted with a dose between 1.10 16< and 9.10 17< at / cm 2< .

[0027] The method may further comprise, before producing the protective dielectric portion, producing isolation trenches through at least part of the thickness of the semiconductor layer, and the steps subsequently implemented may form several JoFETs electrically isolated from each other by the isolation trenches.

[0028] The steps implemented can form several JoFETs electrically coupled in series via second regions common to two of said JoFETs.

[0029] The method may further comprise the production, in the semiconductor layer, of spin qubit devices and / or CMOS type devices and / or at least one Andreev chain comprising other regions (i.e. distinct from the second regions) of recrystallized semiconductor having superconducting material properties.

[0030] Throughout the document, the term "on" is used without distinction of the orientation in space of the element to which this term relates. For example, in the characteristic "on a face of the first substrate", this face of the first substrate is not necessarily oriented upwards but can correspond to a face oriented in any direction. Furthermore, the arrangement of a first element on a second element must be understood as being able to correspond to the arrangement of the first element directly against the second element, without any intermediate element between the first and second elements, or as being able to correspond to the arrangement of the first element on the second element with one or more intermediate elements arranged between the first and second elements.

[0031] Throughout the document, the term "layer" is used to refer to a single layer, but also to a superposition of several distinct layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The present invention will be better understood by reading the description of exemplary embodiments given for purely indicative and non-limiting purposes with reference to the appended drawings in which: THE figures 1 to 11 represent a first method for producing an electronic device with superconducting qubit(s) including at least one JoFET, the subject of the present invention; the figure 12 represents an alternative embodiment of an electronic device with superconducting qubit(s) including at least one JoFET; the figures 13 to 23 represent a second method for producing an electronic device with superconducting qubit(s) including at least one JoFET, the subject of the present invention; the figures 24 to 33represent a third method for producing an electronic device with superconducting qubit(s) including at least one JoFET, the subject of the present invention; the figures 34 to 36 represent different examples of the realization of electronic devices with superconducting qubit(s) integrated on a semiconductor substrate in which other types of semiconductor devices have been produced.

[0033] Identical, similar or equivalent parts of the different figures described below bear the same numerical references so as to facilitate the transition from one figure to another.

[0034] The different parts represented in the figures are not necessarily on a uniform scale, to make the figures more readable.

[0035] The different possibilities (variants and embodiments) must be understood as not being mutually exclusive and can be combined with each other. DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

[0036] A first method for producing an electronic device 100 with superconducting qubit(s) including at least one JoFET 102 is described below in connection with the figures 1 to 11 . In the example described in connection with these figures, the device 100, visible on the figure 10 , has several JoFETs 102, and two of these JoFETs 102 are visible.

[0037] In this first method, the device 100 is made from a solid substrate 104, or bulk, of semiconductor, here silicon (other semiconductors are possible, such as for example germanium or SiGe).

[0038] In a first step, STI (Shallow Trench Isolation) type isolation trenches 106 are made in the substrate 104, delimiting the regions of the substrate 104 in which each of the JoFETs 102 will be made. The steps implemented to make the trenches 106 are similar to those conventionally implemented when making MOSFET transistors electrically isolated by such trenches.

[0039] A layer 108 of dielectric material is then deposited on the substrate 104, also covering the trenches 106 (see figure 1 ). In the embodiment described here, the layer 108 comprises SiN and its thickness E 1 is between 25 nm and 60 nm. The choice of the thickness and material of the layer 108 is described later.

[0040] The layer 108 is then etched so that remaining portions of this layer 108 form protective dielectric portions 110 which will subsequently serve to preserve the parts of the substrate 104 covered by these portions 110 with respect to an implantation of dopants and an exposure to a laser beam. These portions 110 also form dummy gates occupying, on the substrate 104, locations on which the gates of the JoFETs 102 will subsequently be made. These portions 110 have a critical dimension which will determine the gate length of the JoFETs 102. This critical dimension is denoted “CD” on the figure 2 and is for example between 20 nm and 50 nm.

[0041] A cleaning step is implemented after the production of portions 110.

[0042] A dopant implantation step is then implemented through the surface of the substrate 104 on which the portions 110 rest. In the embodiment described here, the implanted dopants are boron atoms. The dose with which this implantation is implemented is for example between 1.10 16< and 9.10 17< at / cm 2< . The energy with which this implantation is implemented is chosen as a function of a desired thickness E 2 in which the dopant atoms are implanted. This thickness E 2 is for example between 5 nm and 25 nm. The arrows visible on the figure 3 symbolically represent the direction of implantation of the dopant atoms in the substrate 104.

[0043] During this implantation step, the regions of the substrate 104 covered by the portions 110, called first regions 112, are protected and the doping atoms are not implanted in these first regions 112. Thus, the thickness and the material of the layer 108 are chosen so that the portions 110 obtained from this layer make it possible to obtain this protection.

[0044] The dopant atoms are, on the other hand, implanted in the regions of the substrate 104 not covered by the portions 110, called second regions 114. With this implantation, the semiconductor of the second regions 114 becomes amorphous. The thickness E 2 corresponds to the thickness of these second regions 114. In addition, with this implantation step, the lateral flanks of the portions 110 are arranged plumb with, or are aligned with, the edges of the second regions 114 and the first regions 112. In the structure obtained visible on the figure 3, two second regions 114 are adjacent to each first region 112 which is arranged between these two second regions 114.

[0045] After this implantation of dopants in the second regions 114, the structure can again undergo a cleaning step.

[0046] A protective dielectric layer 116 is then deposited conformally over the entire structure, i.e. by covering the portions 110 (the upper faces and the lateral flanks of the portions 110), the insulation trenches 106 and the second regions 114 (see figure 4). In the embodiment described here, the layer 116 comprises SiCO or SiOz or SiN, and its thickness E 3 is between 15 nm and 40 nm. The choice of the thickness and the material of the layer 116 is made in such a way that a subsequent step of exposing the structure produced to one or more laser pulses melts the material of the second regions 114, which is covered only by the layer 116, but not the material of the first regions 112, which is covered by the portions 110 and the layer 116.

[0047] The structure produced is then exposed to one or more laser pulses which melt the material of the second regions 114. By using for example a laser emitting wavelengths in the ultraviolet range, for example 193 nm, 248 nm, 308 nm or 355 nm, the pulse durations can typically be between approximately 20 ns and 200 ns, preferably between approximately 60 ns and 180 ns. The associated energy density ranges are then typically between approximately 0.1 and 2 J / cm 2< , more particularly between approximately 0.3 and 1.5 J / cm 2< . Note that for the same result, a lower density will be necessary if the pulse duration is low.After being exposed to the laser pulse(s) (dose for example between 0.6 and 2 J / cm 2 < , for laser with wavelength equal to 308 nm), the molten amorphous semiconductor of the second regions 114 recrystallizes, after cooling, into a semiconductor material having superconducting material properties. In the embodiment described here, the recrystallized material corresponds to Si:B which has superconducting properties when the percentage of boron atoms is greater than approximately 4 or 5%. Furthermore, depending on the nature of the material located under the implanted second regions 114 (semiconductor in the case of a bulk substrate, or a buried oxide in the case of an FDSOI substrate), the recrystallized semiconductor of the second regions 114 is polycrystalline or monocrystalline.

[0048] When exposing the structure to the laser pulse(s), the superposition of the portions 110 and the layer 116 prevents the laser beam used from penetrating to the first regions 112. The semiconductor of the first regions 112 is therefore not modified by the laser used to confer superconducting properties to the semiconductor of the second regions 114.

[0049] The layer 116 is then etched anisotropically in order to remove the parts of the layer 116 located on the isolation trenches 106, the second regions 114 and on the tops of the portions 110, while retaining portions 120 of the layer 116 covering the lateral flanks of the portions 110 and which are intended to form the lateral spacers around the future gates of the JoFETs 102.

[0050] Alternatively, and in particular when the material of the layer 116 is not suitable for forming the desired lateral spacers, it is possible to completely etch the layer 116, then deposit one or more new layers of materials over the entire structure, then anisotropically etch this or these new layers of materials in order to retain only the parts of this or these new layers arranged covering the lateral sides of the portions 110 and forming the future lateral spacers of the gates of the JoFETs 102.

[0051] A siliciding of the second regions 114 is then implemented. This siliciding is for example implemented using nickel. The presence of the portions 120 makes it possible to obtain a good positioning of the silicide portions 122 obtained with respect to the future gates of the JoFETs 102, that is to say spaced by a non-zero distance from these future gates (see figure 6 ).

[0052] At least one other dielectric layer 124 is then deposited over the entire structure. This layer 124 comprises, for example, SiOz, or corresponds to a superposition of an oxide and a dielectric material called “low-k”, or with low permittivity. The thickness of the layer 124 is greater than the thickness E 1 of the portions 110. A mechanical-chemical planarization with a stop on the portions 110 is then implemented (see figure 7 ).

[0053] The portions 110 are then removed by selective etching with respect to the materials of the portions 120 and the layer 124 (see figure 8). In the embodiment described here, this etching may correspond to a wet etching carried out with a solution of H 3 PO 4 making it possible to etch the SiN of the portions 110 selectively with respect to the SiOz or the SiCO of the portions 120 and the SiOz of the dielectric layer 124 or the Si (or SiGe) of the zones 112. The removal of the portions 110 forms empty spaces 126 surrounded by the portions 120.

[0054] The gates of the JoFETs 102 are then produced. For this, a cleaning step is implemented, followed by a step of producing at least one layer of gate dielectric deposited conformally against the walls of the empty spaces 126 (bottom walls and side walls) and on the layer 124, then the deposition of one or more electrically conductive materials in the remaining volume of the empty spaces 126 on the layer 124 with a thickness sufficient to fill the remaining volume of the empty spaces 126. For example, the layer of gate dielectric may correspond to a layer of SiO 2 formed by thermal oxidation or by deposition, or a “High K” dielectric material, or with a high dielectric permittivity, such as for example HfOz. According to one example, the electrically conductive materials deposited to form the gates of the JoFETs 102 correspond to a layer of TiN covered with a thicker layer of tungsten.

[0055] A chemical-mechanical planarization is then implemented in order to remove the parts of the gate dielectric layer and the electrically conductive materials located outside the empty spaces 126, thus forming the gates 128 of the JoFETs 102, these gates 128 being located on the first regions 112 (see figure 9 ).

[0056] The production of the device 100 is completed by depositing at least one PMD (pre-metallic dielectric) layer 130, comprising for example SiOz, on the entire structure produced, then by etching contact holes through this layer 130, and also through the layer 124 for some of these holes. The etched holes are then filled with one or more electrically conductive materials, forming electrical contacts 132 connected to the silicide portions 122 (these electrical contacts 132 pass through the layers 124 and 130) and to the gates 128 (these electrical contacts 132 pass only through the layer 130). The completed device 100 is visible on the figure 10 . A top view of one of the two JoFETs 102 of the device 100 is visible in the figure 11 .

[0057] In the previously described method example, the JoFETs 102 are electrically isolated from each other by the isolation trenches 106. As an alternative or in combination of these JoFETs 102, the steps of this method can realize several JoFETs 102 electrically connected in series via second regions 114 which are common to two neighboring JoFETs 102. Such a configuration is visible on the figure 12 on which three JoFETs 102 electrically coupled in series with each other are shown. On the example of the figure 12 , no electrical contact is connected to the second modified portions 118 common to two neighboring JoFETs 102.

[0058] As indicated previously, prior to the implementation of the depositions of the layers 108 and 116, the thickness and the material of these layers 108 and 116 are chosen so that the step of exposing the structure to one or more laser pulses melts the material of the second regions 114, which is covered only by the layer 116, but not the material of the first regions 112, which is covered by the portions 110 of the layer 108 and the layer 116.

[0059] For this, the thickness and the material of the layer 116 are firstly chosen so that this layer has a low reflectivity, for example less than or equal to approximately 15%, or less than or equal to approximately 10%, with respect to the wavelength of the laser used to melt the semiconductor of the second regions 114. According to a first particular exemplary embodiment, when the laser used to melt the semiconductor of the second regions 114 has a wavelength equal to 308 nm, a low reflectivity with respect to this laser is obtained with a layer 116 comprising SiN and a thickness E 3 of between 25 nm and 35 nm, for example equal to 30 nm.According to a second particular exemplary embodiment, when the laser used to melt the semiconductor of the second regions 114 also has a wavelength equal to 308 nm, the layer 116 may comprise SiOz and a thickness E 3 of between 30 nm and 40 nm, for example equal to 35 nm.

[0060] After choosing the thickness and material of the layer 116, the thickness and material of the layer 108 are chosen so that the superposition of the materials of the layers 108, 116 on the first regions 112 has a high reflectivity, for example greater than or equal to approximately 50%, or greater than or equal to approximately 55%, with respect to the wavelength of the laser used to melt the semiconductor of the second regions 114 and thus protects the first regions 112 so that the material of the first regions 112 does not melt when exposed to this laser. It should be noted that by thus choosing the thickness and material of the layer 108, the semiconductor of the first regions 112 is also preserved from the implantation of dopants implemented to obtain the second regions 114.According to the first particular embodiment example indicated above, the layer 108 may also comprise SiN and a thickness E 1 of between 25 nm and 45 nm. According to the second particular embodiment example indicated above, the layer 108 may also comprise SiN and a thickness E 1 of between 50 nm and 60 nm.

[0061] A second method of producing an electronic device 100 with superconducting qubit(s) including at least one JoFET 102 is described below in connection with the figures 13 to 23 . In the example described in connection with these figures, the device 100 comprises several JoFETs 102, and two of these JoFETs 102 are visible in these figures.

[0062] In this second method, the device 100 is made from a substrate of the semiconductor on insulator type, here SOI (silicon on insulator). Advantageously, this substrate is of the FDSOI type (completely deserted silicon on insulator, or completely depleted silicon on insulator). This substrate comprises a massive layer 134, or support layer, on which is arranged a buried dielectric layer 136, or BOX. A surface layer of semiconductor 138, here silicon, is arranged on the buried dielectric layer 136. The thickness E 4 of the surface layer 138 is advantageously less than or equal to approximately 12 nm, or even less than or equal to approximately 7 nm.

[0063] As in the first production method previously described, STI type isolation trenches 106 are made in the substrate (through layers 138 and 136, and part of the thickness of layer 134), delimiting the regions of the substrate in which each of the JoFETs 102 will be made.

[0064] The layer 108 of dielectric material is then deposited on the substrate, also covering the trenches 106, and is then etched so as to form the portions 110 which will serve to delimit the first and second regions 112, 114 which will be obtained in the surface layer 138 (see figure 13 ). The layer 108 is for example similar to that previously described for the first production method. A cleaning step is implemented after the production of the portions 110.

[0065] Another dielectric layer, called for example the second dielectric layer, comprising for example SiOz, is then deposited conformally over the entire structure, i.e. on the substrate, the trenches 106 and the portions 110 (upper and side walls). Anisotropic etching is then carried out in order to keep only the remaining portions 140 of this second dielectric layer, these portions 140 covering the side flanks of the portions 110 and being intended to form or form part of the lateral spacers of the JoFETs 102 (see figure 14 ).

[0066] In the example described here, in which the substrate is of the FDSOI type, to obtain good operation of the device 100, the method is implemented such that the first regions 112 have a thickness different from that of the second regions 114. More particularly, so that the gates 128 can achieve good electrostatic control of the conductivity of the first regions 112, these first regions 112 are produced with a thickness less than or equal to approximately 12 nm, or even less than or equal to approximately 7 nm. On the other hand, so that the second regions 114 have good superconducting properties, the second regions 114 are produced with a thickness greater than or equal to approximately 15 nm, or greater than or equal to approximately 20 nm.

[0067] To obtain this difference in thickness between the first and second regions 112 and 114, a step of epitaxy of semiconductor (silicon in the example described here) is implemented in order to grow this semiconductor in the parts of the layer 138 not covered by the portions 110 and 140 until reaching a thickness subsequently making it possible to obtain second regions 114 having the desired superconducting properties. According to an exemplary embodiment, this epitaxy step is implemented so as to grow a thickness of semiconductor comprised between approximately 5 nm and 25 nm, which makes it possible to obtain a total thickness E 5 of semiconductor, at the level of the future regions of semiconductor intended to be melted, comprised between approximately 17 nm and 30 nm. On the figure 15, the semiconductor obtained by implementing this growth step is designated by the reference 142. Due to the presence of the portions 140 around the portions 110, the semiconductor 142 is not in contact with the portions 110, which will make it possible, at the end of the method, to obtain second regions 114 distant from the gates 128, that is to say which are not in contact with the gates 128.

[0068] A cleaning step is implemented after this epitaxy.

[0069] As in the first method previously described, a dopant implantation step is then implemented. The parts of the layer 138 covered by the portions 110 and 140 are protected and the dopant atoms are not implanted in these parts of the layer 138 forming the first regions 112. The dopant atoms are, however, implanted in the second regions 114 of the layer 138 not covered by the portions 110 and 140. With this implantation step, the outer lateral edges (those which are not in contact with the portions 110) of the portions 140 are arranged plumb with, or are aligned with, the edges of the second regions 114 and the first regions 112.

[0070] In the example of realization visible on the figure 16, the dopant atoms are not implanted throughout the thickness of the layer 138. Thus, parts 144 of the layer 138 (symbolically delimited from the first regions 112 by dotted lines) present under the second regions 114 are preserved from the implantation of dopants implemented and will subsequently serve as a crystal seed during the recrystallization of the molten semiconductor of the second regions 114, which will allow the recrystallized semiconductor of the second regions 114 to be monocrystalline due to the monocrystalline nature of the semiconductor of the parts 144 of the layer 138 present under the second regions 114.

[0071] Alternatively, it is possible for the dopant atoms to be implanted throughout the thickness of the layer 138. In this case, the second regions 114 extend from the surface of the layer 138 on which the portions 110 and 140 rest to the buried dielectric layer 136 (see figure 17). In this case, the recrystallized material of the second regions 118 will be polycrystalline because the semiconductor recrystallizes on the dielectric material of the layer 136.

[0072] The rest of the process is described considering that the following steps are implemented from the structure shown in the figure 16 , that is to say by having kept the parts 144 of the layer 138 under the second regions 114. These steps would however be implemented in an identical manner if the dopants were implanted throughout the thickness of the layer 138.

[0073] After this implantation, the structure can again undergo a cleaning step. The protective dielectric layer 116 is then deposited conformally over the entire structure, as previously described for the first method. As in the first method, the thickness E 3 and the material of the layer 116 are chosen so that a subsequent step of exposing the structure produced to one or more laser pulses melts the material of the second regions 114, which is covered only by the layer 116, but not the material of the first regions 112, which is covered by the portions 110, 140 and the layer 116. Alternatively, it is possible that the layer 116 is not deposited conformally, because due to the presence of the portions 140, parts of the layer 116 may subsequently be retained or not to form, with the portions 140, the lateral spacers around the gates 128.

[0074] The produced structure is then exposed to one or more laser pulses which melt the material of the second regions 114 (see figure 19 ). After being exposed to the laser pulse(s), the molten amorphous semiconductor of the second regions 114 recrystallizes into a semiconductor material (here monocrystalline due to the presence of the monocrystalline semiconductor portions 144 under the molten semiconductor of the second regions 114) having superconducting material properties.

[0075] Layer 116 is then etched either completely as shown in the figure 20, or as previously described in the first method, that is to say by retaining parts of the layer 116 covering the lateral flanks of the portions 110 and which are intended to form, with the portions 140, the lateral spacers around the future gates of the JoFETs 102. It is also possible to completely etch the layer 116, then to deposit one or more new layers of materials on the entire structure, then to anisotropically etch this or these new layers of materials in order to retain only the parts of this or these new layers covering the lateral flanks of the portions 140 and forming, with the portions 140, the lateral spacers.

[0076] As in the first method, a siliciding of the second regions 114 is then carried out (see figure 20 ).

[0077] The dielectric layer 124 is then deposited over the entire structure, then a mechanical-chemical planarization with stopping on the portions 110 is then implemented (see figure 21 ).

[0078] The portions 110 are then removed by selective etching with respect to the materials of the lateral spacers, formed by the portions 140, and the dielectric layer 124 (see figure 22 ). The removal of the portions 110 forms the empty spaces 126 surrounded by the portions 140.

[0079] As in the first method, the gates 128 of the JoFETs are then made in the empty spaces 126 (see figure 23 ).

[0080] The production of the device 100 is completed as in the first method previously described, that is to say by depositing at least one PMD dielectric layer on the entire structure produced, by etching the contact holes and by filling these holes with one or more electrically conductive materials to form the electrical contacts 132 connected to the silicide portions 122 and to the gates 128.

[0081] As for the first method, this second method can be applied to produce a device 100 comprising several JoFETs 102 electrically connected in series by their second regions 114 common to two neighboring JoFETs 102.

[0082] A third method of producing an electronic device 100 with superconducting qubit(s) including at least one JoFET 102 is described below in connection with the figures 24 to 33. In the example described in connection with these figures, the device 100 comprises several JoFETs 102, and two of these JoFETs 102 are visible in these figures.

[0083] As in the first method, a bulk substrate 104 is used. The isolation trenches 106 are first made in the substrate 104, delimiting the regions of the substrate in which each of the JoFETs 102 will be made.

[0084] The layer 108 is then deposited on the substrate 104, also covering the trenches 106, and is then etched so as to form the portions 110 intended to be arranged on the first regions 112 of the substrate 104 (see figure 24 ). The layer 108 is for example similar to that previously described for the first and second production methods. A cleaning step is implemented after the production of the portions 110.

[0085] A dielectric layer, called for example the third dielectric layer and comprising for example SiOz, is then deposited in a conformal manner over the entire structure, i.e. on the substrate 104, the trenches 106 and the portions 110 (upper and side walls). The thickness of this third dielectric layer is at least equal to that of the protective dielectric layer 116 which will be formed subsequently. Anisotropic etching is then carried out in order to retain only the remaining portions 146 of this layer which cover the side walls of the portions 110 and which form temporary side spacers (see figure 25). The thickness E 6 of the remaining portions 146 of the third deposited dielectric layer is equal to that of the final lateral spacers intended to be produced subsequently so that the portions 146 occupy, on the substrate 104, the locations which will subsequently be occupied by the final lateral spacers of the gates 128 of the JoFETs 102. This thickness E 6 is less than or equal to the initial thickness of the third deposited dielectric layer. Furthermore, this thickness E 6 is chosen to be equal to the thickness E 3 of the protective dielectric layer 116 which will be used subsequently during the process. This thickness E 6 is for example equal to approximately 15 nm.

[0086] A cleaning step is implemented after etching the dielectric layer forming the portions 146.

[0087] As in the first method previously described, a dopant implantation step is then implemented. The first regions 112 of the substrate 104 covered by the portions 110 and 146 are protected and the dopant atoms are not implanted in these first regions 112. The dopant atoms are, on the other hand, implanted in the second regions 114 of the substrate 104 not covered by the portions 110 and 146. With this implantation step, the outer lateral edges (those which are not in contact with the portions 110) of the portions 146 are arranged plumb with, or are aligned with, the edges of the second regions 114, and the inner lateral edges (those in contact with the portions 110) of the portions 146 are arranged plumb with, or are aligned with, the edges of the first regions 112 (see figure 26 ).

[0088] As shown in the figure 27, the portions 146 are then removed, for example by implementing wet etching using an HF solution when these portions 146 comprise SiO 2 .

[0089] After this implantation, the structure can undergo a further cleaning step. The layer 116 is then deposited conformally over the entire structure, as previously described for the first and second methods (see figure 28 ). As previously, the thickness E 3 and the material of the second layer 116 are chosen so that a subsequent step of exposing the structure produced to one or more laser pulses melts the semiconductor of the second regions 114, which is covered only by the layer 116, but not the material of the first regions 112, which is covered by the portions 110 and the second layer 116.

[0090] The structure produced is then exposed to one or more laser pulses which melt the semiconductor of the second regions 114 (see figure 29 ). After being exposed to the laser pulse(s), the molten amorphous semiconductor of the second regions 114 recrystallizes, after cooling, into a semiconductor material having superconducting material properties. The semiconductor of the first regions 112 previously covered by the portions 146 and which is covered only by the layer 116 is also protected from this or these laser pulses due to the significant thickness of material of the layer 116 present on these semiconductor portions.

[0091] The layer 116 is then etched anisotropically so as to preserve parts of this layer 116 covering the lateral sides of the portions 110 and which are intended to form the lateral spacers around the future gates of the JoFETs 102. As a variant, and as is the case in the example shown in the figure 30 , another layer of material is deposited over the entire structure, then etched anisotropically in order to retain only parts 148 of this or these new layers covering the lateral sides of the portions 116 and intended to form the future lateral spacers of the gates 128 of the JoFETs 102.

[0092] As previously, a siliciding of the second regions 114 is then implemented (see figure 30 ).

[0093] The dielectric layer 124 is then deposited over the entire structure, then a mechanical-chemical planarization with stopping on the portions 110 is then implemented (see figure 31 ).

[0094] The portions 110 and 120 are then removed by selective etching with respect to the materials of the lateral spacers, formed by the portions 148, and the dielectric layer 124 (see figure 32 ). This etching corresponds for example to a wet etching carried out with a solution of H 3 PO 4 when the portions 110 and 120 comprise SiN. The removal of the portions 110 and 120 forms the empty spaces 126 surrounded by the portions 148.

[0095] As in the previous methods, the gates 128 of the JoFETs 102 are then made in the empty spaces 126 (see figure 33 ).

[0096] The production of the device 100 is completed as in the first and second methods previously described, that is to say by depositing at least one PMD dielectric layer on the entire structure produced, by etching the contact holes and by filling these holes with one or more electrically conductive materials to form the electrical contacts 132 connected to the silicided regions 122 and to the gates 128.

[0097] As for the first method, this third method can be applied to produce a device 100 comprising several JoFETs 102 electrically connected in series by the second regions 114 which are common to two neighboring JoFETs 102.

[0098] Alternatively, this third method could be implemented from a semiconductor-on-insulator type substrate such as that used in the second method previously described, possibly applying the different implementation variants previously described for the second method.

[0099] Whatever the method implemented, the device 100 obtained can be co-integrated, on the same substrate, with other types of devices in the semiconductor field.

[0100] For example, the figure 34 represents a device 100 comprising one or more superconducting qubits including at least one JoFET 102 (only one JoFET 102 is visible on the figure 34 ) made in the semiconductor substrate 104, and also comprising CMOS type devices, i.e. FET type transistors. On the figure 34, a transistor 202 of the “Gate Last” type, that is to say whose gate was produced after the production of the lateral spacers and the removal of a temporary gate, and a transistor 204 of the “Gate First” type, that is to say whose gate was produced by depositing layers prior to the rest of the transistor, produced in the substrate 104 are visible.

[0101] According to another example, the figure 35 represents a device 100 comprising one or more superconducting qubits including several JoFETs 102 electrically coupled in series by second regions 114 common to two of the JoFETs 102 and produced in the semiconductor substrate 104, and also comprising an Andreev chain 206 produced from superconducting regions 208 for example obtained by implementing the steps producing the second regions 114 of the JoFETs 102.

[0102] According to another example, the figure 36represents a device 100 comprising one or more superconducting qubits including at least one JoFET 102 (only one JoFET 102 is visible on the figure 36 ) made in the semiconductor substrate 104, and also comprising spin qubit devices 210.

Claims

1. A method for fabricating out an electronic device (100) with superconductor qubit(s) including at least one JoFET (102) formed by the implementation of the steps of: - making, over at least one semiconductor layer (104, 138), at least one protective dielectric portion (110) arranged over at least one first region (112) of the semiconductor layer (104, 138); - implanting dopants in second regions (114) of the semiconductor layer (104, 138), adjacent to the first region (112) and such that the first region (112) is arranged between the second regions (114) ; - depositing a protective dielectric layer (116) covering at least the protective dielectric portion (110) and the second regions (114) ; - exposing the protective dielectric layer (116) to at least one laser pulse; - removing at least one portion of the protective dielectric layer (116) covering the second regions (114); - removing the protective dielectric portion (110); - making at least one electrostatic control gate (128) over the first region (112); and wherein the materials and the thicknesses of the protective dielectric portion (110) and of the protective dielectric layer (116), as well as the duration and the power of said at least one laser pulse, are selected such that the superposition of the protective dielectric portion (110) and of the protective dielectric layer (116) over the first region (112) prevents said at least one laser pulse from reaching the first region, and that the presence of the protective dielectric layer (116) alone over the second regions (114) enables said at least one laser pulse to reach the second regions (114) and melt the semiconductor of the second regions which forms, after cooling, a recrystallised semiconductor material having superconductor material properties.

2. The method according to claim 1, wherein the protective dielectric portion (110) includes SiN, and wherein the protective dielectric layer (116) includes at least one of: SiN, SiCo, SiO2.

3. The method according to any of the preceding claims, wherein the selection of the materials and of the thicknesses of the protective dielectric portion (110) and of the protective dielectric layer (116) is carried out: - by selecting the material and the thickness of the protective dielectric layer (116) such that the protective dielectric layer (116) has a reflectivity, for the wavelength of said at least one laser pulse, lower than or equal to 15%, then - by selecting the material and the thickness of the protective dielectric portion (110) such that the superposition of the protective dielectric portion (110) and of the protective dielectric layer (116) has a reflectivity, for the wavelength of said at least one laser pulse, higher than or equal to 50%.

4. The method according to the preceding claims, wherein: - the protective dielectric layer (116) is conformally deposited, and - the removal of at least one portion (116) of the protective dielectric layer covering the second regions (114) is carried out by implementing an anisotropic etching of the protective dielectric layer such that remaining portions (120) of the protective dielectric layer (116) form lateral dielectric spacers arranged against sidewalls of the protective dielectric portions (110).

5. The method according to any of the claims 1 to 3, further including, between the making of the protective dielectric portion (110) and the implantation of the dopants in the second regions: - conformal deposition of a second dielectric layer covering at least the protective dielectric portion and the second regions (114); - anisotropic etching of the second dielectric layer such that remaining portions (140) of the second dielectric layer cover sidewalls of the protective dielectric portion (110) and are arranged over the first region (112) ; - a semiconductor epitaxy (142) over the second regions; and wherein the deposited protective dielectric layer also covers the remaining portions (140) of the second dielectric layer.

6. The method according to claim 5, wherein: - the protective dielectric layer (116) is conformally deposited, and the removal of at least one portion of the protective dielectric layer (116) covering the second regions (114) is carried out by implementing an anisotropic etching of the protective dielectric layer (116), remaining portions (140) of the protective dielectric layer forming, with the remaining portions of the second dielectric layer, lateral dielectric spacers arranged against sidewalls of the protective dielectric portion (110), or - the removal of at least one portion of the protective dielectric layer (116) corresponds to a total removal of the protective dielectric layer (116).

7. The method according to any of the claims 1 to 3, further including, between the making of the protective dielectric portion (110) and the implantation of the dopants in the second regions (114): - conformal deposition of a third dielectric layer covering at least the protective dielectric portion (110) and the second regions (114), and whose thickness is equal at least to that of the protective dielectric layer (116) formed subsequently; - anisotropic etching of the third dielectric layer such that remaining portions (146) of the third dielectric layer cover sidewalls of the protective dielectric portion and are arranged over the first region (112); and further including, between the implantation of the dopants in the second regions (114) and the deposition of the protective dielectric layer (116), a removal of the remaining portions (146) of the third dielectric layer.

8. The method according to claim 7, further including, between the removal of at least one portion of the protective dielectric layer (116) covering the second regions (114) and the removal of the protective dielectric portion (110), making of lateral dielectric spacers (148) against remaining portions (120) of the protective dielectric layer (116), and wherein the making of the electrostatic control gate (128) is preceded by a removal of the remaining portions (120) of the protective dielectric layer (116).

9. The method according to any of the preceding claims, wherein the semiconductor layer (138) corresponds to a superficial layer of a semiconductor-on-insulator type substrate.

10. The method according to claim 9, wherein the dopants are implanted within all the thickness of the semiconductor layer (138), or wherein the dopants are implanted within only one portion of the thickness of the semiconductor layer (138).

11. The method according to any of the preceding claims, wherein the dopants correspond to boron atoms implanted with a dose between 1.1016 and 9.1017 at / cm2.

12. The method according to any of the preceding claims, further including, before the making of the protective dielectric portion (110), the making of isolation trenches (106) through at least one portion of the thickness of the semiconductor layer (104, 138), and wherein the steps implemented afterwards form several JoFETs (102) electrically isolated from each other by the isolation trenches (106).

13. The method according to any of the preceding claims, wherein the implemented steps form several JoFETs (102) electrically coupled in series via second regions (114) common to two of said JoFETs (102).

14. The method according to any of the preceding claims, further including the making, in the semiconductor layer (104, 138), of devices with spin qubits (210) and / or CMOS-type devices (202, 204) and / or at least one Andreev chain (206) including other regions (208) of a recrystallised semiconductor having superconductor material properties.