Encapsulation substrate and encapsulation process embedded in a power chip
Patent Information
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- SHENNAN CIRCUITS
- Filing Date
- 2024-08-06
- Publication Date
- 2026-06-10
AI Technical Summary
Current packaging techniques for third-generation semiconductor materials, such as SiC and GaN, fail to realize their full potential due to long signal transmission paths, significant electrical performance loss, and large space occupation, as chips are packaged outside the substrate and connected via pins, leading to inefficient integration and miniaturization.
A power chip embedded package substrate method where the bare chip and rigid substrate are integrated into a through groove of a first chip board, with an insulation layer covering the chip, and blind holes providing 3D vertical interconnections for direct signal fan-out, reducing transmission paths and allowing space for more components.
This method reduces signal transmission loss and frees up space for additional components, facilitating module integration and miniaturization by embedding the chip within the substrate, enhancing thermal conductivity and electrical performance.