METHOD AND DEVICE FOR ERROR CORRECTION IN RESISTIVE STORAGE OR FLASH STORAGE

Description

Domaine technique

[0001] The invention lies in the field of resistive memories or flash memories, and relates more particularly to a method and a device for improving error correction in such memories. Etat de la technique

[0002] Resistive Random Access Memory (RRAM) is a non-volatile memory technology characterized by high operating speed, low power consumption, and a long lifespan. For these reasons, resistive memory is among the most promising memory technologies for replacing both RAM and current non-volatile memory such as flash memory.

[0003] There are several resistive memory technologies. These include conductive-bridging random-access memory (CBRAM), oxide-based random-access memory (OxRAM), and phase-change memory (PCM).

[0004] Resistive memory is composed of a multitude of resistive memory cells arranged in rows and columns to form a matrix. An RRAM memory cell has at least one resistive element whose electrical conductance can be modified.

[0005] One factor limiting their widespread adoption in the market remains the significant error rates during read operations. The error rate, or BER (Bit Error Rate), is impacted by shifts in the HRS (High Resistance State) or LRS (Low Resistance State) values ​​of the resistors programmed into the memory. The article by B. Giraud et al., "Benefits of Design Assist Techniques on Performances and Reliability of an RRAM Macro" - DOI: 10.1109 / IMW56887.2023.10145984, describes this known phenomenon in more detail.

[0006] It is also worth noting that even though NAND flash memory technology is mature and continues to dominate the market for electronic memories used in mass storage devices, these memories can also suffer from a significant error rate when attempting to store multiple bits per cell and / or when subjected to a large number of write / erase cycles. The IDC white paper by N. Sundby and D. Taylor, "Beyond Capacity: Storage Architecture Choices for the Modern Datacenter," published by IDC Analyze the Future, explores these points.

[0007] A known solution to address a high error rate affecting a memory of one of these types is to use error-correcting code or ECC protection.

[0008] Error-correcting code can be implemented by adding an ECC encoder and decoder inside or near the memory controller. Generally, a memory controller is the electronic circuit whose function is to translate requests, usually from a host electronic system, to read or write to memory systems.

[0009] The general principle of data encoding with ECC is to add check bits to the data bits using an encoder. The check bits are calculated from the data bits, and together they form a codeword. During decoding with an ECC decoder, the presence of the check bits allows for the detection and correction of errors affecting both the data bits and the check bits.

[0010] The code words of a binary and linear ECC can be defined through the following equation: H ⋅ v = 0 Or vis a vector corresponding to a codeword, and where H corresponds to a parity matrix which includes only binary values ​​('0' or '1') and in which each column is different from the other columns, and includes at least one value other than 0.

[0011] When reading data from memory, each code word that is read (i.e., each vector) v is verified by evaluating the value of the matrix product H · v .

[0012] The result of this operation is a binary vector called a "syndrome". If the syndrome is a zero vector, i.e., each bit of the vector is equal to zero, the codeword is considered correct. Conversely, a non-zero syndrome indicates the presence of at least one error in the codeword.

[0013] Furthermore, if a syndrome can identify the positions of the erroneous bits, the codeword can be corrected.

[0014] In the presence of high error rates, one solution is to use increasingly powerful ECCs, i.e. allowing to correct more and more erroneous bits in a codeword.

[0015] However, this leads to an increasingly significant additional cost in terms of surface area, i.e. the storage area for the check bits, and in terms of latency and surface area (consumption) of the ECC decoder.

[0016] Also, faced with the problem of error correction in resistive or flash memories, there is a need for a solution that overcomes the various disadvantages of known solutions, in particular the disadvantages related to latency and the surface area of ​​the ECC decoder.

[0017] The present invention addresses this need.

[0018] US2021 / 143836 describes an error correction method. When an uncorrectable error is detected, the weak bits are inverted in several steps. In each step, the bits to be inverted are determined by an inversion threshold. Résumé de l'invention

[0019] The invention relates to a device for reducing the cost of circuits used for error correction affecting words read from memories protected by an error-correcting code (ECC).

[0020] The invention is particularly relevant to resistive memories and flash memories protected by an error-correcting code that allows the correction of at least two erroneous bits per code word stored in memory.

[0021] The device of the invention relates to an ECC decoder, which advantageously offers a smaller footprint implementation and improved latency performance.

[0022] In general, for an ECC capable of correcting up to r erroneous bits per codeword obtained during a memory read operation, the device according to the invention combines a correction module capable of correcting up to r-1 erroneous bits per codeword, and a detection module capable of verifying the number of erroneous bits per codeword.

[0023] More specifically, the detection module is designed to detect if the initial codeword contains a maximum of r-1 erroneous bits, and, otherwise, initiate a sequence of decoding operations on a succession of words, each of which contains a single bit reversed with respect to the initial code word.

[0024] A check is then performed to verify whether the number of erroneous bits in the version of the codeword with a one-bit inversion has become correctable, i.e., whether the number of erroneous bits has fallen below rOnce this condition is met, the codeword can be corrected.

[0025] Thus, the principle of the invention is based on the implementation and use of an ECC decoder with less functional complexity, smaller surface area and reduced latency, than an ECC decoder composed of a single combinational module.

[0026] To achieve the desired goal, an error correction device for codewords is proposed, a codeword comprising a data word formed of data bits and including check bits, the device performing the steps of the error correction process in codewords according to claim 10. The device of the invention comprises a combination of means or modules including (a) means for receiving a codeword with potential errors, the word being read from a memory protected by an error-correcting code having a maximum correction capacity of rerroneous bits per codeword.

[0027] The device of the invention further comprises (b) a decoding module which includes: - means for generating a binary vector or syndrome for the received codeword or for a version of the codeword with a one-bit inversion, a one-bit inversion codeword being a codeword derived from the received codeword in which the value of a single bit is inverted; and - correction means for generating, from the syndrome, an error vector enabling correction of up to r-1 erroneous bits.

[0028] The device of the invention further includes (c) an evaluation module for determining the number of erroneous bits in a codeword, which includes: - detection means for detecting, from the syndrome, whether the number of erroneous bits in the received codeword or in a version of the codeword with a one-bit inversion, is greater than or equal to r- means of analysis to decide on a bit inversion operation; and - means of inversion to reverse a bit in the code word.

[0029] The device of the invention further includes (d) output means for delivering an error-vector-corrected data word when the number of erroneous bits in the received codeword, or in a version of the codeword with a one-bit inversion, is less than r.

[0030] According to one aspect of the invention, the means for generating a syndrome make it possible to evaluate the value of a matrix product H · v Or H corresponds to a parity matrix, and where v is a vector corresponding to a received codeword or a codeword with inversion.

[0031] In one embodiment, the correction means include a combination of logic gates to generate an error vector, each bit of the error vector being an input to an exclusive-OR gate of the output means.

[0032] In one implementation, the detection means include a combination of logic gates to generate a signal indicating the presence of at most r-1 erroneous bits in the received codeword or in a codeword with one bit reversed, said signal being an input to the analysis means.

[0033] According to one aspect of the invention, the analysis means comprise a state machine driven by the output of the detection means and the output of the inversion means, said state machine allowing to determine whether a new decoding cycle is to be performed by the error correction device, and to command the inversion means to invert a single bit in the received code word.

[0034] In one embodiment, the evaluation module further includes parity calculation means for generating a total parity signal, said total parity signal enabling the analysis means, in combination with the signal received from the detection means, to detect the presence of an uncorrectable error.

[0035] In an implementation, the correction methods are designed according to logical optimization methods allowing the processing of data of the type " don't care "

[0036] In one embodiment, the means for generating syndromes are designed to generate oversized syndromes having a number of bits greater than the number of verification bits of the codeword.

[0037] Another object of the invention covers an FPGA or ASIC type electronic system comprising a resistive memory or a flash memory, an ECC encoder and an error correction device according to the invention.

[0038] The invention also addresses a method for correcting errors in code words, a code word comprising a data word formed of data bits and including check bits.

[0039] The process of the invention comprises steps consisting of: receive a codeword with potential errors, the codeword being read into a memory protected by an error-correcting code having a maximum correction capacity of r erroneous bits per codeword; in a first decoding cycle: perform a decoding of the received codeword; determine if the codeword contains a number of erroneous bits less than or equal to r-1; and if not, invert a data bit in the codeword to generate a version of the codeword with a one-bit inversion; repeat a new decoding cycle with the previous steps for each version of the codeword with a one-bit inversion that is generated, as long as the number of erroneous bits is greater than r-1 or a maximum number of bits to be inverted is reached, the one-bit inversion step consisting in each new cycle of restoring the value of the bit inverted in the previous cycle to its initial state, and inverting the value of a new bit in the received codeword;and deliver a corrected data word if the number of erroneous bits in the received codeword or in a version of the codeword with a one-bit inversion is less than r. ;

[0040] In one embodiment, the process includes, before the step of determining whether the codeword contains a number of erroneous bits less than r, a total parity calculation step to determine the presence of uncorrectable errors in the codeword.

[0041] Advantageously, the method of the invention is implemented in an electronic system of the FPGA or ASIC type comprising a resistive memory or a flash memory, an ECC encoder and an error correction device according to the invention. Description des figures

[0042] Features, details and advantages of the invention will become apparent from the description provided with reference to the accompanying drawings given by way of example, which represent, respectively: There figure 1 illustrates an example of the architecture of an error correction device according to the invention; The figure 2 illustrates the steps of an error correction process implemented by a device according to the figure 1 ; There figure 3 illustrates an architectural variant of an error correction device according to the invention with detection of uncorrectable errors; The figure 4 illustrates the steps of an error correction process implemented by a device according to the figure 3 ; There figure 5 shows a table comparing gains in area and clock period for different types of ECC and circuits implementing devices according to the invention; The figure 6 shows a graph of the average number of additional decoding cycles (clock cycles) vs the error rate per bit for prior art decoders and decoders according to the invention. Description détaillée de l'invention

[0043] There figure 1 illustrates an embodiment of an error correction device 100 according to the invention, also referred to as an ECC decoder, and which can be used with an ECC allowing the correction of a maximum of r erroneous bits per codeword read from a resistive memory or a flash memory.

[0044] This device can be implemented in an architecture that typically integrates a host electronic system, a memory controller, and memory (resistive or flash).

[0045] The host can consist of one or more processor cores, a microcontroller, a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC).

[0046] The memory controller manages the read and write operations in memory. It includes an ECC encoder and decoder implemented according to the described embodiment variants.

[0047] In variant embodiments, the error-correcting code can be of type DEC (“Double Error Correction”), DEC-TED (“Double Error Correction-Triple Error Correction”), TEC (“Triple Error Correction”), TEC-QED (“Triple Error Correction-Quadruple Error Detection”), QEC (“Quadruple Error Correction”) or QEC-QED (“Quadruple Error Correction-Quintuple Error Detection”).

[0048] There figure 1 shows the functional blocks of device 100 of the invention, and the data flows circulating between the different blocks.

[0049] The device according to the invention for correcting errors in codewords, where a codeword comprises a data word formed of data bits and including check bits, comprises: means 110 for receiving a codeword with potential errors, the codeword being read from a resistive memory or flash memory, the memory being protected by an error-correcting code having a maximum correction capacity of r erroneous bits per codeword; a decoding module comprising: - means 130 for generating a binary vector or syndrome for the received codeword or for a codeword with a one-bit inversion from the received codeword, a one-bit inversion codeword being a codeword obtained from the received codeword where the value of a single bit is inverted; and - correction means 140 for generating, from the syndrome, an error vector capable of correcting up to r-1erroneous bits in the data word; an evaluation module to determine the number of erroneous bits in the codeword which includes: - detection means 150 to detect, from the syndrome, whether the number of erroneous bits in the received codeword or in a codeword with a bit inversion is greater than or equal to r ; - analysis means 170 for deciding whether to invert a bit in the codeword; - inversion means 120 for inverting a bit in the codeword; output means 160 for delivering a corrected data word when the number of erroneous bits in the received codeword or in a codeword with a bit inversion is less than r.

[0050] The ECC 100 decoder receives as input a codeword containing potential programming, storage, or read errors (i.e., erroneous bits). Each bit of the received codeword passes through an exclusive-OR (XOR) logic gate 110. Each XOR gate is controlled by a bit from an inversion vector derived from inversion means 120.

[0051] In one embodiment, the inversion means include a shift register 120 for storing an inversion vector having a number of bits equal to the number of bits in the codeword minus r-1. Among these bits, at most one bit can be equal to 1 in order to invert the value of at most one bit in the input word of the ECC decoder.

[0052] A code word output from the input logic gates 110 is addressed to a decoding module consisting of means 130 to generate a binary vector or syndrome for the received word.

[0053] A word received as input to the syndrome 130 generator is a codeword with potential errors that has or has not undergone a single-bit inversion, depending on the value of the inversion vector.

[0054] At initialization, all bits of the inversion vector are initialized to zero such that each bit of the received codeword that passes through an XOR 110 gate retains its initial value.

[0055] At each decoding iteration, all bits of the inversion vector are shifted one position with a 0 or 1 input to the flip-flop located at the input of the shift register, i.e., at the opposite end from the shift direction. The input value 1 is used only for the first shift operation to produce an inversion vector with a single value of 1 and a version of the codeword called the "codeword with a one-bit inversion," which is sent to the syndrome generator.

[0056] The syndrome 130 generator implements multiplication operations to perform matrix multiplication. H · v of equation (1), where the vector v is a codeword with potential errors, either received as input by reading from memory, or a codeword with a bit inversion generated during a subsequent decoding cycle.

[0057] From the syndrome, an error vector generator 140 generates a control bit for each data bit, the set of control bits being the error vector.

[0058] Each data bit can be corrected using a two-input 160 exclusive-or (XOR) logic gate, one input for the bit to be corrected and another input driven by the corresponding control bit in the error vector.

[0059] Thus the output of the syndrome generator 130 is an input of the correction means 140 which are arranged to generate an error vector allowing to correct up to r-1 bits of erroneous data in the word output of the module 110.

[0060] In an advantageous embodiment, the correction means 140 are designed with design tools that allow Boolean logic optimizations in order to handle inputs of type " don't care » (DC) also referred to as "whatever" entries.

[0061] Such optimization methods are described for example in the article "Synthesis of Irregular Combinational Functions with Large Don't Care Sets" by V. Gherman et al. (DOI: 10.1145 / 1228784.1228856).

[0062] The notion of DC is defined in conjunction with incompletely specified Boolean functions, i.e., f : {0 , 1} N< → {0,1, X} Or Xrepresents an undefined value that can take the value 0 or 1, in the case of a hardware implementation of f. Combinations of N bits, y ∈ {0, 1} N< in the domain of definition of f which are mapped to X , are called DC.

[0063] Advantageously, in the presence of a large number of DCs, It becomes possible to obtain hardware implementations of a function f that are more optimized in terms of latency, area or dissipated power.

[0064] Thus, a large number of DCs can be identified for the functions implemented by the correction module 140 (and by similarity by the correction module 340 of the variant of the figure 3 ).

[0065] In this way, all the syndromes generated for errors that affect r And r+1 bits, can be considered as data of type DC because in these cases, the ECC decoder output is not used. This particular type of DC is considered to be DCs observational studies.

[0066] In one alternative embodiment, the number of DCs For correction methods 140 (and 340), it can be further increased by generating oversized syndromes using syndrome generator 130 (and by similarity using syndrome generator 330). figure 3 ), i.e., syndromes having a number of bits greater than the number of verification bits of the codeword.

[0067] Such oversized syndromes can be generated by adding redundant rows to the parity matrix. H e.g. lines that are linear combinations of already existing lines. For each additional bit added to the syndromes, the number of possible combinations at the input of module 130 (or 330) is multiplied by 2.

[0068] In such a process, only the number of DCs can increase because the value of each redundant syndrome bit is defined by the values ​​of the non-redundant syndrome bits. Therefore, for each combination of non-redundant syndrome bits, there is only one possible combination of redundant syndrome bits, and no other combination of redundant syndrome bits can be realized. All combinations of syndrome bits that contain non-realizable values ​​of redundant syndrome bits are considered to be DCs said to be controllability.

[0069] Returning to the figure 1 , the output of the syndrome generator is also an input of the detection means 150 of the evaluation module.

[0070] The detection means are arranged to allow, through the evaluation of the syndrome, the detection of r or r+1 erroneous bits in the code word output from module 110.

[0071] The output of module 150 is used by a state machine 170 or (FSM) acronym "Finite State Machine" in English.

[0072] The state machine determines whether a new decoding cycle should be performed by the ECC decoder.

[0073] The FSM drives the 120 shift register via signals START And EN. During the first decoding cycle, if at least r erroneous bits are detected in the codeword received at the input of device 100 (and at the output of module 110, with the inversion vector in its initial state, all values ​​at 0), the two signals START And EN When set to 1, the FSM forces the start of a new decoding cycle. The first bit of register 120 is set to 1. This inverts the bit of the received codeword entering the first XOR gate. Simultaneously, a new decoding cycle is performed with the version of the codeword whose first bit is inverted.

[0074] At each subsequent decoding cycle, the signal START is reset to 0 and the signal EN is maintained at 1, and this as long as a number r Or r+1 erroneous bits are detected, i.e., until the cycle where decoding becomes successful. The signal EN allows you to reset all bits of register 120 to zero.

[0075] Thus, after each unsuccessful decoding cycle, i.e. where the detection module 150 indicates the presence of at least r erroneous bits in the version of the word output from module 110, the value 1 is advanced one position in register 120 so that another bit of the word input to device 100 is reversed.

[0076] The iterative decoding process stops either when the detection module 150 indicates a maximum number of r-1 erroneous bits (i.e., a number of errors that can be corrected by the error vector), or when the value 1 is assigned to the bit in the last position in the shift register 120.

[0077] Each decoding cycle can be executed in a clock cycle that controls device 100.

[0078] After the positive decoding cycle, a correction of erroneous data bits in the output word version of input module 110 is performed using exclusive-or gates 160, the gates being driven by the bits of the error vector generated by module 140.

[0079] From the outside of the device, the cessation of the decoding process is indicated by a signal Ready generated at the output of the FSM.

[0080] There figure 2 illustrates the steps of an error correction process according to the invention that can be implemented by a device according to the figure 1 .

[0081] The 200 method is applied when reading from a memory protected by an ECC capable of correcting up to r bits per codeword, and it allows for improved error correction.

[0082] The process begins with step 210, receiving a code word which may potentially contain erroneous bits.

[0083] In a subsequent step 220, the process allows a first decoding of the code word 220, and allows verification in a subsequent or simultaneous step 230 if the number of erroneous bits is less than or equal to r-1.

[0084] If the number of erroneous bits is at most r-1, the process allows the correction of the erroneous bits and allows a corrected word to be delivered at step 270.

[0085] Depending on the embodiment, the process allows either the entire corrected codeword to be delivered, or only the corrected data bits (for reduced ECC decoder implementations).

[0086] Returning to step 230, if the number of erroneous bits is greater than r-1, the process initiates a new decoding cycle for a version of the codeword where only one bit is inverted. The process includes a step 240 in which one bit of the initially received codeword is inverted.

[0087] During the execution of a new decoding cycle, apart from the first execution, the process allows the bit that was inverted during the previous execution to be returned to its initial value.

[0088] Thus, with each execution of step 240, a new bit of the code word is reversed.

[0089] The process continues the execution of new decoding cycles (branch non of 250) as long as the number of erroneous bits is not less than or equal to r-1, or as long as a maximum number of bits to be reversed in the initially received word is not reached.

[0090] When the maximum number is reached, the process generates at step 260 a signal indicating an uncorrectable error.

[0091] The error correction method according to the invention allows, for an ECC circuit capable of correcting r erroneous bits per codeword, that it can handle up to r-1 erroneous bits in one decoding cycle.

[0092] Thus, advantageously, the process of the invention implemented on an optimized device such as that of the figure 1 or with implementation variants, makes it possible to reduce the latency and the area of ​​the error correction logic.

[0093] There figure 3 illustrates an architectural variant of an error correction device according to the invention, which includes additional means for performing a total parity calculation.

[0094] The 300 device can be used with an ECC that allows correction of up to r erroneous bits and detection of r+1 erroneous bits per codeword.

[0095] In this variant, it is assumed that the detection of r+1 The protection against erroneous bits is ensured by using codewords with a total parity bit added, which allows the resulting codewords to be all even or odd.

[0096] Different functional blocks are identical to the blocks of the figure 1 and no detailed description is provided, which can be taken from the previous description. Thus, blocks or modules 310 to 360 of the figure 3 are respectively identical to modules 110 to 160 of the figure 1 .

[0097] The 300 system also includes a 380 module for total parity assessment.

[0098] Module 380 is designed to select a syndrome bit that corresponds to the total parity of the word output from module 310, in the syndrome calculated by syndrome generator 330, and send a total parity signal to state machine 370.

[0099] In one embodiment, the syndrome bit corresponding to total parity can be calculated from all the input bits of the syndrome generator 330 using an XOR gate tree having all these bits as input.

[0100] In the variant of the figure 3 The 370 state machine is very similar to that of the architecture in figure 1 , the difference being that during the first decoding cycle, the FSM 370 uses the total parity signal generated at the output of the 380 module to identify the presence of an uncorrectable error that affects r+1 bits.

[0101] This variant allows us to take advantage of the fact that a code word with r erroneous bits have a different total parity than a codeword with r+1 erroneous bits, while the output of module 350 remains the same in both cases.

[0102] Thus, in the event that an uncorrectable error is indicated during the first decoding cycle, no further decoding cycle is initiated and a signal is generated at the output of the FSM 370 indicating the presence of an uncorrectable error.

[0103] There figure 4 illustrates the steps of an error correction process that can be implemented by a device according to the figure 3 .

[0104] The 400 process is applied when reading from a memory protected by an ECC capable of correcting up to r bits per codeword and detect r+1 erroneous bits per codeword.

[0105] Several steps are identical to the steps of the figure 2 and no detailed description is given, which can be taken from the previous description. Thus, steps 410, 430, 440, 450, 460 and 470 are respectively identical to steps 210, 230, 240, 250, 260 and 270 of process 200.

[0106] After receiving a codeword potentially containing erroneous bits in step 410, the subsequent decoding step 420 identifies the presence of uncorrectable errors in the codeword, such as errors that affect r+1 bits.

[0107] The result of this detection of uncorrectable errors is processed in step 425. In the case where a number of r+1 erroneous bits, the process continues with a step 460 to signal the presence of uncorrectable errors in the code word.

[0108] If no uncorrectable errors are detected, the process continues with step 430.

[0109] Then, according to the result of step 430, the process continues by setting up a loop of decoding cycles on codeword versions with a single bit inversion, according to steps (440, 450) and in accordance with the corresponding steps (240, 250) described for process 200.

[0110] According to different embodiments of processes 200 and 400, the step (240, 440) of reversing a single bit in the codeword at each decoding cycle, can consist either of applying a unitary reversal only on the data bits of the codeword initially received at step 210 or 410, or of applying a unitary reversal on all bits (data bits and check bits) less r-1 bits of the codeword received at step 210 or 410.

[0111] In one embodiment of a BCH-type ECC (acronym for the initials of the authors Bose, Ray-Chaudhuri, and Hocquenghem), the detection modules 150 and 350 respectively of the figures 1 And 3These methods can be implemented using a technique described in the paper entitled "Encoding and Error-Correction Procedures for the Bose-Chaudhuri Codes" by W.W. Peterson (DOI: 10.1109 / TIT.1960.1057586). This paper introduces matrices called Peterson matrices for BCH-type ECCs. If the ECC can correct up to r error bits per codeword, the Peterson matrix Mr+1 is singular, i.e., its determinant is equal to 0, if the number of error bits in a codeword is less than or equal to r-1. The Peterson matrix Mr+1 is singular if the number of error bits in a codeword is equal to r or r+1.

[0112] The process of figure 4 can then be adapted to detect an error that affects r bits by evaluating the determinant of the Peterson matrix M r and the total parity of the received word (equal to r modulo 2 if all codewords are even), and to detect an error that affects r+1 bits by evaluating the determinant of the Peterson matrix M r+1 and the total parity of the received word (equal to r+1 modulo 2 if all codewords are even).

[0113] There figure 5 illustrates the gains in area and clock cycles of different types of ECCs and circuits implementing error correction devices according to architectures such as those proposed in figure 1 or in figure 3 .

[0114] The state-of-the-art ECCs considered are of the BCH type and allow the correction of a maximum of 3 erroneous bits per codeword ( r=3) on codewords with 32, 64 or 128 bits of data. The codes considered are identified as TEC (acronym for "triple-error correction") or TEC-QED (acronym for "triple-error correction and quadruple-error detection"), depending on whether the detection of 4 erroneous bits is ensured or not.

[0115] The calculation of gains, clock period reduction, and logic area reduction is performed relative to decoders implemented according to solutions presented in the paper entitled "A Low-Complexity Three-Error-Correcting BCH Decoder with Applications in Concatened Codes" by J. Freudenberger, M. Rajab, and S. Shavgulidze (DOI: 10.30420 / 454862002). All decoders were synthesized using the Synopsis Design Compiler tool in 28nm FDSOI technology.

[0116] The iterative decoding cycle error correction approach makes it possible, for example, to reduce the clock period by up to -20% for 32-bit TEC codes, alongside reductions in the logic area by up to -45%.

[0117] There figure 6 illustrates on a graph the average number of additional decoding cycles "cycle overhead" according to the error rate per bit "RBER", for prior art decoders and decoders according to the invention.

[0118] According to the invention, additional decoding cycles are introduced only if the received codeword contains a maximum number of correctable error bits. Prior art decoding (labeled "all errors") requires additional decoding cycles as soon as the received codeword contains a single error bit. The number of additional cycles is at least equal to (a) the number of data bits plus (b) the maximum number of correctable error bits minus (c) the actual number of error bits. It can be noted that the proposed solution (labeled "largest errors") offers a significant advantage, and its additional decoding cycle (clock) cost becomes negligible as the RBER decreases.

[0119] For RBERs below 10⁻⁴, this overhead falls below 2 × 10⁻⁷, 2 × 10⁻⁷, and 2 × 10⁻⁵ respectively for TEC codes with 32, 64, and 128 bits of data. The entries under the label "all errors" correspond to the overhead of one known method presented in the paper entitled "Step-by-step decoding of the Bose-Chaudhuri-Hocquenghem codes" by J. Massey (DOI: 10.1109 / TIT. 1965.1053833).

[0120] In this prior art approach, although there is a bit inversion, this method is strictly different from the method of the invention with respect to (a) correcting codewords affected by fewer than r errors and (b) correcting remaining errors once a first erroneous bit is corrected in the case of r erroneous bits.

[0121] In this so-called "step-by-step" approach, additional erroneous bits are initially injected into the check bits to reach a maximum of r erroneous bits. The process then inverts one bit at a time and, after decoding, verifies whether the number of erroneous bits has decreased. If the number of erroneous bits has decreased, the process identifies that the inverted bit is erroneous. The process then continues to invert and test all the data bits one by one. This results in a very large number of cycles to be performed as soon as an error is encountered.

[0122] Conversely, according to the methods and devices of the invention, if a maximum number of erroneous bits are not detected, the correction takes place in a single cycle (yes branches of steps 230 and 430). This presents a major advantage, verified and illustrated on the figure 6 .

[0123] The present description illustrates a preferred, but not limiting, implementation of the invention. Examples are chosen to facilitate a clear understanding of the principles of the invention and its practical application, but are by no means exhaustive and should enable those skilled in the art to make modifications and implementation variations to the different circuits while maintaining the same principles. In alternative embodiments, each functional module for encoding, counting, comparing, and inverting can be implemented by a dedicated module such as an ASIC.

[0124] The invention can be implemented using hardware and / or software elements. It can be available as a computer program product executed by a dedicated processor or by a memory controller of a storage system, and which includes code instructions to execute the steps of the processes in their various embodiments.

Claims

1. Error correction device for in code words, a code word comprising a data word formed by data bits and comprising verification bits, the device carrying out the steps of the error correction method in code words according to claim 10, and comprising: - means (110) for receiving a code word with potential errors, the word being read in a protected memory by an error correction code which has a maximum correction capacity of r erroneous bits per code word; - a decoding module comprising: - means (130) for generating a binary vector or syndrome for the code word received or for a version of the code word with inversion of a bit, a code word with inversion of a bit being a word originating from the code word received wherein the value of a single bit is inverted; - correction means (140) for generating from the syndrome an error vector which enables up to r - 1 erroneous bits to be corrected; - an evaluation module for determining the number of erroneous bits in a code word, comprising: - detection means (150) for detecting, based on the syndrome, if the number of erroneous bits in the code word received or a version of the code word with inversion of a bit is greater than or equal to r; - analysis means (170) in order to decide on a bit inversion operation; - inversion means (120) for inverting a bit in the code word; - output means (160) for issuing a data word corrected by the error vector when the number of erroneous bits in the code word received or in a version of the code word with bit inversion is less than r.

2. Device according to claim 1, wherein the means for generating a syndrome enable the value of a matrix product H · v to be evaluated, wherein H corresponds to a parity matrix, and where v is a vector corresponding to a code word received or to a code word with inversion.

3. Device according to claim 1 or 2, wherein the correction means (140) comprise a combination of logic gates in order to generate an error vector, each bit of the error vector being an input of an exclusive-or gate of the output means (160).

4. Device according to any one of claims 1 to 3, wherein the detection means (150, 350) comprise a combination of logic gates in order to generate a signal which indicates the presence of a maximum of r-1 erroneous bits in the code word received or in a code word with inversion of a bit, the signal being an input of the analysis means.

5. Device according to any one of claims 1 to 4, wherein the analysis means comprise a status machine (170) which is controlled by the output of the detection means and the output of the inversion means, the status machine enabling it to be determined whether a new decoding cycle should be carried out by the error correction device, and enabling the inversion means to be controlled to carry out the inversion of a single bit in the code word received.

6. The device according to any one of claims 1 to 5, wherein the evaluation module further comprises parity calculation means (380) which enable a total parity signal to be generated, the total parity signal enabling the analysis means (370) in combination with the signal received from the detection means (350) to detect the presence of a non-correctable error.

7. Device according to any one of claims 1 to 6, wherein the correction means (140, 340) are configured in accordance with logical optimization methods which enable data of the type « don't care » to be processed.

8. The device according to any one of claims 1 to 7, wherein the means for generating syndromes are configured to generate oversized syndromes which have a number of bits greater than the number of verification bits of the code word.

9. An electronic system of the FPGA or ASIC type comprising a resistive memory or a flash memory, an ECC encoder and an error correction device according to any one of claims 1 to 8.

10. Error correction method in code words, a code word comprising a data word formed by data bits and comprising verification bits, the method comprising steps of: - (210) receiving a code word with potential errors, the word being read in a protected memory by an error correction code which has a maximum correction capacity of r erroneous bits per code word; - in a first decoding cycle: - (220) carrying out a decoding of the code word received; - (230) determining whether the code word contains a number of erroneous bits less than or equal to r-1; - (240) if not, inverting a data bit in the code word in order to generate a version of the code word with inversion of a bit; - repeating a new decoding cycle with the preceding steps (220) to (240) for each version of the code word with inversion of a bit which is generated as long as the number of erroneous bits is greater than r - 1 or a maximum number of bits to be inverted is reached, the inversion step of a bit involving with each new cycle setting the value of the bit inverted during the preceding cycle back to its initial state and inverting the value of a new bit in the code word received; and - transmitting a corrected data word if the number of erroneous bits in the code word received or in a version of the code word with bit inversion is less than r.

11. Method according to claim 10, comprising prior to step (430) determining whether the code word contains a number of erroneous bits less than r, a step (425) of total parity calculation which enables the presence of a non-correctable error in the code word to be determined.

12. Method according to claim 10 or 11, implemented in an electronic system of the FPGA or ASIC type, comprising a resistive memory or a flash memory, an ECC encoder and an error correction device according to any one of claims 1 to 8.