Semiconductor component

Abstract

The invention relates to a semiconductor component (2). The semiconductor component (2) comprises a circuit carrier (S) having a first conductor layer (CU1), in which a first conductor path (F1) is formed. The semiconductor component (2) comprises a first thyristor chip (C1) which has, on its upper face, an anode contact (A10) and a gate contact (G10) and, on its lower face, a cathode contact (K10), wherein the cathode contact (K10) of the first thyristor chip (C1) is placed on the first conductor path (CU1, F1) such that an electrical connection is established between the cathode contact (K10) and the first conductor path (CU1, F1). The semiconductor component (2) also comprises a second thyristor chip (C2) which has, on its upper face, a cathode contact (K2) and a gate contact (G2) and, on its lower face, an anode contact (A2), wherein the anode contact (A2) of the second thyristor chip (C2) is placed on the first conductor path (CU1, F1) such that an electrical connection is established between the anode contact (A2) and the first conductor path (CU1, F1). The semiconductor element (2) also comprises at least one electrically conductive connection element (22, D), which electrically connects the anode contact (A10) of the first thyristor chip (C1) to the cathode contact (K2) of the second thyristor chip (C2). The first conductor path (CU1, F1) thus establishes an electrical connection between the cathode contact (K10) of the first thyristor chip (C1) and the anode contact (A2) of the second thyristor chip (C2).

Description

[0001] Description

[0002] semiconductor component

[0003] The present invention relates to a semiconductor component having two thyristor chips; it also relates to a power semiconductor module having such a semiconductor component.

[0004] In semiconductor switching devices, such as soft starters, an anti-parallel circuit of two thyristors can be used as a semiconductor switch for switching an alternating current, see, for example, DE102016214419A1 (Siemens AG) 08.02.2018. For this purpose, the cathode of a first thyristor chip must be connected to the anode of a second thyristor chip; further electrical connections must also be established in the anti-parallel circuit.

[0005] It is known to implement these electrical connections between thyristors using bonding wires, see, for example, W02008 / 071134A1 (Siemens AG) June 19, 2008 and DE102008031297A1 (Siemens AG) January 14, 2010. To handle the currents occurring in a power semiconductor module, several parallel bonding wires may be required for each electrical connection, which in many cases also have to be routed and bonded at an angle. This makes it difficult to create an antiparallel connection of two thyristors.

[0006] One object of the present invention is to simplify the manufacture of an antiparallel circuit of two thyristors. Another object of the present invention is to provide a thyristor circuit that is easier to manufacture.

[0007] This object is achieved according to the invention by a semiconductor component having the features specified in claim 1. The semiconductor component has a circuit carrier which has a first conductor track in a first conductor layer. The circuit carrier can alternatively also be referred to as a "substrate". The circuit carrier can be designed as a so-called DCB (= Direct Copper Bonding). A DCB is a sandwich consisting of two conductor layers, e.g. copper or aluminum layers or layers, and an insulating layer in between, e.g. a ceramic layer. In comparison to conventional circuit boards, such as epoxy circuit boards, such as a ceramic layer, such a DCB allows considerably higher temperatures for the components to be carried, in particular the power semiconductors. The first conductor track can be divided into two parts, e.g.The first conductor layer may have been formed into electrically insulated line and connection structures using a structuring process such as photolithography in semiconductor technology. The first conductor track of the first conductor layer is therefore an electrically conductive surface arranged on an electrically insulating layer of a circuit carrier, which is electrically insulated from other conductor tracks of the first conductor layer. These conductor tracks serve as line structures and as contact surfaces for electronic components. The entirety of the conductor tracks of a circuit carrier forms a circuit layout on the insulating carrier layer.

[0008] The semiconductor component has a first thyristor chip which has an anode contact and a gate contact on its top side and a cathode contact on its bottom side. The first thyristor chip is placed with its cathode contact on the first conductor track in such a way that there is an electrical connection between the cathode contact and the first conductor track. The first conductor track has a planar first contact surface against which the cathode contact of the first thyristor chip rests. In particular, the cathode contact is electrically connected to the first contact surface via a soldered connection, so that a low-ohmic electrical transition with, at the same time, a low thermal resistance is produced. The electrical connection, e.g. in the form of soldering, also ensures that the first thyristor chip is mechanically fixed to the first conductor track of the first conductor layer.

[0009] The semiconductor component has a second thyristor chip which has a cathode contact and a gate contact on its top side and an anode contact on its bottom side. The second thyristor chip is placed with its anode contact on the first conductor track in such a way that there is an electrical connection between the anode contact and the first conductor track. The first conductor track has a second flat contact surface against which the anode contact of the second thyristor chip rests. In particular, the anode contact is electrically connected to the second contact surface via a soldered connection, so that a low-ohmic electrical transition with, at the same time, a low thermal resistance is produced. The electrical connection, e.g. in the form of soldering, also ensures that the second thyristor chip is mechanically fixed to the first conductor track of the first conductor layer.

[0010] The thyristor chips are thyristors designed as microchips. The thyristor chips are also referred to simply as thyristors in this description. The individual thyristor chips can be plate- or disk-shaped. They each have two main terminals, namely a cathode contact and an anode contact, and a control electrode terminal, namely a gate contact. One of the main terminals and the control electrode terminal are located on the top side of the thyristor chip, and the other main terminal is located on the bottom side of the thyristor chip.

[0011] Such a thyristor chip is, in particular, packageless. Essentially, such a thyristor chip consists of the semiconductor chip itself, the so-called "die." The die contains contact surfaces for bonding, i.e., for electrically contacting the electrodes of the thyristor chip. The compact design allows a low-resistance connection of the thyristor chip to the conductor layer while simultaneously maintaining low thermal resistance for cooling the thyristor chip.

[0012] The semiconductor component has at least one electrically conductive connecting element, in particular a metal element, e.g. made of copper or aluminum, which electrically connects the anode contact of the first thyristor chip to the cathode contact of the second thyristor chip. In addition, the first conductor track of the first conductor layer establishes an electrical connection between the cathode contact of the first thyristor chip and the anode contact of the second thyristor chip. Bonding wires, stamped parts or any type of metal pieces can be used as the at least one electrically conductive connecting element; in principle, any electrically conductive element that can be electrically connected to the anode and cathode contacts can be used.The arrangement of the electrically conductive connecting elements, in particular the course of the bonding wires, in the semiconductor component for producing the necessary electrical connections of the semiconductor component is referred to for the sake of simplicity as the "bonding pattern", even if the more general term "connecting element pattern" would be more correct in this case.

[0013] The invention is based on the discovery that the use of two different thyristor chips—a first thyristor chip with the cathode at the bottom and a second thyristor chip with the cathode at the top—significantly simplifies the bonding pattern and thus the fabrication of an antiparallel circuit of two thyristors. The position of the anode contact and cathode contact of the first thyristor chip is reversed compared to the position of the second thyristor chip.

[0014] The invention enables the implementation of the antiparallel connection of the thyristors with a greatly simplified bonding pattern. The number of electrically conductive connecting elements, in particular the bonding wires to be drawn, is significantly reduced. The electrically conductive connecting elements only need to be arranged on the top side of the chips. The path of the electrically conductive connecting elements is also straightened; for example, bonding with a straight path of the bonding wires is possible.

[0015] The invention enables simpler bond wire placement and a reduction in the number of bond wires, leading to a reduction in bonding costs. The simplified bond pattern also frees up installation space, allowing larger semiconductors to be placed in a given package.

[0016] Advantageous embodiments and further developments of the invention are specified in the dependent claims.

[0017] According to a preferred embodiment of the invention, the semiconductor component has an input contact and an output contact. By means of these two contacts, the semiconductor component can be switched into an electrical circuit where the semiconductor component acts as a switch. The output contact is electrically connected to the anode contact of the second thyristor chip by the first conductor track of the first conductor layer. The semiconductor component also has at least one electrically conductive connecting element, e.g. at least one bonding wire, which electrically connects the input contact to the anode contact of the first thyristor chip. One advantage of this is that the electrical connections required for the operation of the semiconductor component are produced using electrically conductive connecting elements, e.g. bonding wires, and using conductor tracks of the first conductor layer, which result in a simple bonding pattern.

[0018] According to a preferred embodiment of the invention, the semiconductor component has a first control contact and a second control contact. The control contacts can be designed as contacting surfaces that are arranged on a carrier layer of the circuit carrier. They can be designed as conductor tracks of the first conductor layer, e.g. copper or aluminum fields that are arranged on a carrier layer of the circuit carrier and are electrically insulated from other conductor tracks of the first conductor layer. The semiconductor component also has at least one control wire that electrically connects the first control contact to the gate contact of the first thyristor chip. And the semiconductor component has at least one control wire that electrically connects the second control contact to the gate contact of the second thyristor chip.One advantage is that the electrical connections required for the operation of the semiconductor component are made using electrically conductive connecting elements, e.g. bonding wires, which result in a simple bond pattern.

[0019] According to a preferred embodiment of the invention, the semiconductor component has a third control contact. The control contact can be designed as a contacting area that is arranged on a carrier layer of the circuit carrier. It can be designed as a conductor track of the first conductor layer, e.g. a copper or aluminum field that is arranged on a carrier layer of the circuit carrier and is electrically insulated from other conductor tracks of the first conductor layer. And the semiconductor component has at least one auxiliary wire that electrically connects the third control contact to the cathode contact of the second thyristor chip. One advantage here is that the electrical connections required for the operation of the semiconductor component are produced with bond wires that result in a simple bonding pattern.

[0020] According to a preferred embodiment of the invention, the semiconductor component has a fourth control contact, which is electrically connected to the cathode contact of the first thyristor chip by the first conductor track of the first conductor layer. The fourth control contact can be formed as a contacting surface of the first conductor track. One advantage of this is that the electrical connections required for the operation of the semiconductor component are established with conductor tracks of the first conductor layer, resulting in a simple bond pattern.

[0021] A further preferred embodiment of the invention is a power module, short for: power semiconductor module, with a semiconductor component according to one of the embodiments described above. A power semiconductor module is an electrical device which, with the aid of semiconductor components, can convert electrical energy as efficiently as possible into the form required by various applications and can reliably control the power flow via suitable circuits. The power module according to the invention has, in addition to a semiconductor component according to the invention, a heat sink, a housing and a potting compound, e.g. a plastic.In this case, the circuit carrier of the semiconductor component has, in addition to the first conductor layer arranged on the upper side of the circuit carrier, a second conductor layer arranged on the underside of the circuit carrier and a middle layer electrically insulating the two aforementioned conductor layers from one another.

[0022] The circuit carrier can be a DCB; the two conductor layers can be copper or aluminum layers and the middle layer a ceramic layer. The possible designs of a DCB are sufficiently known to those skilled in the art and need not be explained further here. The semiconductor component is arranged on the heat sink and housed in the housing, which is filled with the potting compound. Power semiconductor modules are installed in housings to insulate them from environmental influences. These housings protect the module from mechanical damage, moisture and other harmful external influences. The housing is usually potted with a filling compound, which serves as an electrical insulation layer and at the same time as a mechanical holder.The result is a plastic body in which the electrical and / or electronic parts and components are completely embedded and from which only the electrical supply and discharge lines of the power module protrude.

[0023] According to a preferred embodiment of the power module, connecting layers are arranged between the thyristor chips and the first conductor layer, and between the heat sink and the second conductor layer. These connecting layers can be layers of solder or other electrically conductive materials. The connecting layers provide mechanical fixation and an electrical and thermal connection between the connected components.

[0024] According to a preferred embodiment of the power module, the input contact and the output contact of the semiconductor component are each electrically connected through the encapsulating compound to a first and second contacting device, respectively, which are arranged outside the housing. The power module thus comprises a plastic body in which the electrical and / or electronic parts and components are completely embedded and from which only the electrical supply and discharge lines of the power module protrude.

[0025] In the following, the invention is explained with the aid of the accompanying drawing. It shows schematically and not to scale

[0026] Fig. 1 is a circuit diagram of a thyristor pair;

[0027] Fig. 2 shows a section through a conventional power module;

[0028] Fig. 3 is a circuit diagram and a bond diagram of a conventional thyristor pair;

[0029] Fig. 4 shows a section through a conventionally connected thyristor pair; Fig. 5 shows a circuit diagram and a bonding diagram of a thyristor pair according to the invention;

[0030] Fig. 6 shows a section through a thyristor pair connected according to the invention;

[0031] Fig. 7 shows a section through a power module according to the invention according to a first embodiment; and

[0032] Fig. 8 shows a section through a power module according to the invention according to a further embodiment.

[0033] Fig. 1 shows a schematic circuit diagram of a component comprising an antiparallel-connected thyristor pair Tl.1, Tl.2, which can be connected to the two poles of an AC voltage source via contact pieces L1, L2 of the component. The thyristors Tl.1, Tl.2 can each be implemented as a semiconductor chip C1, C2. The thyristors Tl.1, Tl.2 each have an anode A1, A2, a cathode K1, K2, and a gate electrode G1, G2. A control unit can turn on both thyristors Tl.1, Tl.2 by applying a current to the gate electrodes G1, G2, i.e., convert them from a blocking initial state to a conducting state. Turning on a thyristor by applying this gate current is referred to as "firing." Once triggered, the thyristors remain conductive even without an applied gate current until the current flowing through the conductive thyristor reaches a minimum value, the so-called gate current.Holding current, falls below.

[0034] In conventional antiparallel-connected thyristor pairs Tl.l, TI.2, two thyristors of the same type TI with the same structure are used: the cathode K1, K2 is in the same position on both thyristor chips Tl.l, TI.2, e.g., at the top of the chip. In contrast, in an antiparallel-connected thyristor pair according to the invention, two thyristors of different types T10, TI with different structures are used: a first thyristor chip C1, T10 has its cathode K1 at the bottom, and a second thyristor chip C2, TI has its cathode K2 at the top, i.e., mirrored to the first thyristor chip C1, T10.

[0035] Fig. 2 shows a section through a conventional power semiconductor module 4 in which a conventional anti-parallel connected thyristor pair Tl. l, Tl. 2 is installed. The power semiconductor module has a typical hybrid power electronic structure with several power semiconductor components C1, C2 combined on a substrate / circuit carrier and interconnected. The power semiconductor module 4 is equipped with at least one semiconductor component C1, C2 which has an anti-parallel connected thyristor pair Tl. l, Tl. 2. The power semiconductor module 4 can also have further semiconductor components, such as, for example, GTOs (= Gate Turn-Off Thyristor), MCTs (= MOS-Controlled Thyristor), power diodes, IGBTs (= Insulated Gate Bipolar Transistor) or MOSFETs (= Metal Oxide Semiconductor Field Effect Transistor). A module 4 can also contain other circuit components, e.g.passive components and sensors. The semiconductor components of a conventional power semiconductor module 4 are commercially available components and are therefore not described in detail below.

[0036] The power semiconductor module 4 contains a base plate P . In the example shown, the base plate P is connected by means of a heat-conducting layer I to a heat sink KK, which can have cooling fins in order to dissipate the heat generated by the semiconductor elements. The illustration of cooling fins on the heat sink KK in Fig. 2 has been omitted for the sake of simplicity. Another advantageous embodiment would be, for example, a liquid cooler. The heat-conducting layer I can consist of a TIM (= Thermal Interface Material), which improves the thermal coupling between the base plate P and the heat sink KK. The base plate P is fastened to the heat sink KK by a fastening device B; the closest possible contact between the base plate P and the heat sink KK supports the dissipation of heat from the semiconductor components C1, C2.

[0037] The base plate P is preferably made of a material with good thermal conductivity, e.g., a metal such as aluminum or copper, or a metal / matrix composite such as aluminum-silicon carbide (AlSiC) or copper-silicon carbide (CuSiC). A base plate P made of a metal-ceramic composite (AlSiC, CuSiC) can be easily combined with cooling structures KK made of the same composite or the corresponding metal (Al, Cu).

[0038] In the structure shown, the power semiconductor components Cl, C2 are mounted on a circuit carrier S. The circuit carrier S forms an electrical insulation between the semiconductor components Cl, C2 and the base plate P and also has good thermal conductivity in order to dissipate the heat of the semiconductor components Cl, C2 to the base plate P. The circuit carrier S can have a ceramic layer CC, with aluminum nitride (AIN), aluminum oxide (Al2O3), beryllium oxide (BeO), silicon carbide (SiC) or silicon nitride (SiN) being preferred materials.Due to their high thermal conductivity and thermal expansion coefficient, ceramic circuit carriers S, so-called DCB substrates, are preferably used. These consist of a ceramic insulator CC such as aluminum oxide or aluminum nitride, on each of whose two sides a thin layer of pure copper is applied, namely a first conductor layer CU1 on an upper side of the ceramic layer CC and a second conductor layer CU2 on an underside of the ceramic layer CC, as shown in Fig. 2. The connection of the circuit carrier S to the base plate P is made via a solder layer V.

[0039] On its upper side facing the semiconductor components C1, C2, the circuit carrier S has metallized conductor tracks F1, F2, F3, F4, which are structured according to circuit requirements: in the present example, the conductor tracks F1 to F4 comprise an input contact L1, an output contact L2, a first conductor track F1, and a second conductor track F2. The conductor tracks F1 to F4 were formed by subdividing the first conductor layer G1, which was arranged on the upper side of the ceramic layer CG.

[0040] The electronic semiconductor components Cl, C2 are mechanically and electrically connected to the conductor tracks Fl to F4; these electrical connections can be made by solder layers V. Instead of the solder layers V between the semiconductor components Cl, C2 and the circuit carrier S, another material-fit connection or fastening can also be used which ensures good electrical and thermal contact, for example via an intermediate layer in the form of a metal plate. Electrical connections between the conductor tracks Fl to F4 and the semiconductor components Gl, C2 are made by bonding wires D.

[0041] The power semiconductor module 4 further comprises a housing H, which is sealed by the base plate P and thus forms a housing interior. Plastic housings are common. In addition to plastic, the housing H can also be made of another dielectric, particularly a ceramic. Ceramics are inexpensive and resistant and, for electrical insulators, have good thermal conductivity. This thermal conductivity is important for dissipating the generated heat.

[0042] For mutual electrical insulation of the components of the power semiconductor module 4 and for sealing the circuit structure against the outside atmosphere, the housing H is at least partially potted with a potting compound M in the direction of the base plate P. Typically, the housing volume is filled with potting compound M to such an extent that it evenly surrounds the semiconductor components C1, C2 and the usual standard specifications are met. The connections 51, 52 of the power semiconductor module 4 are led out of the potted housing H via the contacts L1, L2 of the circuit carrier S and solder layers V at suitable points in order to provide external connections of the power semiconductor module 4.

[0043] Fig. 3 shows a circuit diagram in part a and a bond diagram in part b of a conventional semiconductor component with an antiparallel-connected thyristor pair. The circuit diagram (Fig. 3a) shows two identically designed thyristors Tl.1, Tl.2, connected in antiparallel. The cathode K1, K2 is located at the same position on the top side of the chip for both thyristor chips Tl.1, Tl.2. The gate G1, G2 is located at the same position on the top side of the chip for both thyristor chips Tl.1, Tl.2. The anode A1, A2 is located at the same position on the bottom side of the chip for both thyristor chips Tl.1, Tl.2.

[0044] The two thyristor chips Tl.l, TI.2 are interconnected as follows: the input contact LI of the circuit is connected to the cathode K1 of the first transistor chip Tl.l by means of a first bond connection 11. The anode A1 of the first transistor chip Tl.l is connected to the cathode K2 of the second transistor chip TI.2 by means of a second bond connection 12. The cathode K1 of the first transistor chip Tl.l is connected to the anode A2 of the second transistor chip TI.2 by means of a third bond connection 13. The cathode K2 of the second transistor chip TI.2 is connected to the output contact L2 by means of a fourth bond connection 14.

[0045] The bonding image (Fig. 3b) shows a top view of a conventionally connected thyristor pair. Eight electrically insulated conductor tracks are formed from the copper layer, which is arranged as the first conductor layer GUI on the ceramic layer CC of the circuit carrier, using a structuring process: the input contact LI of the semiconductor component forms a third conductor track F3. The first transistor chip CI, Tl.1 is arranged with its anode contact A1 on a first conductor track F1. The second transistor chip C2, Tl.2 is arranged with its anode contact A2 on a second conductor track F2. And the output contact L2 of the semiconductor component forms a fourth conductor track F4. In addition, a first control contact 31 forms a fifth conductor track F5, a second control contact 32 a sixth conductor track F6, a third control contact 33 a seventh conductor track F7, and a fourth control contact 34 an eighth conductor track F8.

[0046] The interconnection of the two thyristor chips Tl.l, TI.2 is as follows: The third conductor track F3, i.e. the input contact LI of the circuit, is connected to the cathode K1 of the first transistor chip Tl.l by means of a first bond connection 11. The first conductor track F1, to which the anode A1 of the first transistor chip Tl.l is soldered, is connected to the cathode K2 of the second transistor chip TI.2 by means of a second bond connection 12. The cathode K1 of the first transistor chip Tl.l is connected to the second conductor track F2, to which the anode A2 of the second transistor chip TI.2 is soldered, by means of a third bond connection 13. The cathode K2 of the second transistor chip TI.2 is connected to the fourth conductor track F4, i.e. the output contact L2 of the circuit, by means of a fourth bond connection 14.

[0047] The fifth conductor track F5, which forms a first control contact 31 (auxiliary cathode) of the circuit, is supplied with the potential of the cathode K1 of the first transistor Tl.l by means of a first auxiliary wire 16, the first auxiliary wire 16 being connected at a first end to the anode A2 of the second transistor Tl.2, which is at the potential of the cathode K1 of the first transistor Tl.l. At another end, the first auxiliary wire 16 is connected to the first control contact 31, from which an electrical connection can be established to a control device for controlling the first thyristor Tl.l. The first control contact 31, via which energy from the main circuit can be made available to the control device, is used to control the gate G1 of the first transistor chip Tl.l. A first control wire 15 runs from the sixth conductor track F6, which forms a second control contact 32 of the circuit, to the gate G1 of the first thyristor Tl.l.

[0048] From the seventh conductor track F7, which forms a third control contact 33 of the circuit, a second control wire 17 runs to the gate G2 of the second thyristor TI.2.

[0049] The eighth conductor track F8, which forms a fourth control contact 34 (auxiliary cathode) of the circuit, is supplied with the potential of the cathode K2 of the second transistor TI.2 by means of a second auxiliary wire 18, the second auxiliary wire 18 being connected at a first end to the anode A1 of the first transistor Tl.1, which is at the potential of the cathode K2 of the second transistor TI.2. At another end, the second auxiliary wire 18 is connected to the fourth control contact 34, from which an electrical connection can be made to a control device for controlling the second thyristor TI.2. The fourth control contact 34, via which energy from the main circuit can be made available to the control device, is used to control the gate G2 of the second transistor chip TI.2.

[0050] To handle the currents occurring in the power semiconductor component C1, C2, several parallel bonding wires are required per electrical connection 11, 12, 13, 14, which must also be routed and bonded at an angle. This makes it difficult to create an antiparallel connection of two thyristors with a bonding pattern as shown in Fig. 3b using wire bonding.

[0051] Fig. 4 shows a section of two conventionally interconnected thyristors T1, T2 according to the circuit / bonding diagram of Fig. 3. The two thyristor chips C1, C2 have the same structure, ie each has an anode contact A1, A2 arranged on the underside of the chip, a cathode contact K1, K2 arranged on the top side of the chip, and a gate contact G1, G2 arranged on the top side of the chip. Between the contacts on the top and bottom sides there is a semiconductor layer structure 1, which is also of the same design for both thyristor chips C1, C2.

[0052] The first thyristor chip Cl, Tl.l is arranged on the first conductor track Fl. The anode contact Al arranged on the underside of the first thyristor chip Gl, Tl.l is electrically and mechanically connected to the first conductor track Fl by means of a solder layer V. The cathode contact Kl and the gate contact Gl are arranged on the upper side of the first thyristor chip Gl, Tl.l.

[0053] The second thyristor chip C2, TI. 2 is arranged on the second conductor track F2. The anode contact A2 arranged on the underside of the second thyristor chip C2, TI. 2 is electrically and mechanically connected to the second conductor track F2 by means of a solder layer V. The cathode contact K2 and the gate contact G2 are arranged on the top side of the second thyristor chip C2, TI. 2.

[0054] With regard to the electrical connection of the two thyristor chips C1, C2 by bonding wires D, reference is made to the description of Fig. 3b.

[0055] Fig. 5 shows in part a a circuit diagram and in part b a bonding diagram of a semiconductor component according to the invention with an anti-parallel connected thyristor pair C1, C2. The circuit diagram (Fig. 5a) shows two differently designed thyristors T10, T11 which are anti-parallel connected to one another. The cathode K10 of the first thyristor chip T10 is on the underside of the chip, whereas the cathode K2 of the second thyristor chip T11 is on the top side of the chip. The anode A10 of the first thyristor chip T10 is on the top side of the chip, whereas the anode A2 of the second thyristor chip T11 is on the underside of the chip. The gate G10 of the first thyristor chip T10 as well as the gate G2 of the second thyristor chip T11 are on the top side of the respective chip.

[0056] The two thyristor chips T10, TI are connected as follows: the input contact LI of the circuit is connected to the anode A10 of the first transistor chip T10 by means of a first bond connection 21. The anode A10 of the first transistor chip T10 is connected to the cathode K2 of the second transistor chip TI by means of a second bond connection 22. The anode A2 of the second transistor chip TI is connected to the output contact L2 by means of a third bond connection 23. The cathode K10 of the first transistor chip T10 is connected to the anode A2 of the second transistor chip TI by means of a connection 24, which is not a bond wire connection. Instead of bond wires, the electrical connections 21, 22, 23 can also be made using other connecting elements.

[0057] The bonding image (Fig. 5b) shows a plan view of a thyristor pair C1, C2 connected according to the invention. Six electrically insulated conductor tracks have been formed from the copper layer, which is arranged as a first conductor layer GUI on the ceramic layer CC of the circuit carrier, by a known structuring process: Both transistor chips C1, C2 are arranged on a first conductor track Fl: the first transistor chip C1, T10 is arranged with its cathode contact K10 on the first conductor track Fl, whereas the second transistor chip C2, T10 is arranged with its anode contact A2 on the first conductor track Fl. A fourth control contact 44 as well as the output contact L2 of the semiconductor component are also placed on the first conductor track Fl. The input contact LI of the semiconductor component forms a second conductor track F2.In addition, a first control contact 41 forms a third conductor track F3, a second control contact 42 forms a fourth conductor track F4, and a third control contact 43 forms a fifth conductor track F5. The two thyristor chips T10, TI are connected as follows: The second conductor track F2, i.e. the input contact LI of the circuit, is connected to the anode A10 of the first transistor chip T10 by means of a first bond connection 21. The first conductor track Fl, which is designed as a copper layer, onto which the cathode K10 of the first transistor chip T10 and the anode K2 of the second transistor chip TI are soldered, connects the cathode K10 of the first transistor chip T10 to the anode K2 of the second transistor chip TI. The anode A10 of the first transistor chip T10 is connected to the cathode K2 of the second transistor chip TI by means of a second bond connection 22.The anode A2 of the second transistor chip TI is connected to the output contact L2 of the circuit via the first conductor track Fl. Instead of bonding wires, the electrical connections 21, 22 can also be made with other connecting elements.

[0058] An electrical connection to a control unit for controlling the first thyristor T10 can be established from the fourth control contact 44, which is formed as a projection of the first conductor track F1 and is at the potential of the cathode K10 of the first transistor T10. The fourth control contact 44, via which energy from the main circuit can be made available to the control unit, is used to control the gate G10 of the first transistor chip T10.

[0059] From the third conductor track F3, which forms a first control contact 41 of the circuit, a first control wire 25 runs to the gate G10 of the first thyristor T10.

[0060] From the fourth conductor track F4, which forms a second control contact 42 of the circuit, a second control wire 26 runs to the gate G2 of the second thyristor TI.

[0061] The potential of the cathode K2 of the second transistor TI is supplied to the fifth conductor track F5, which forms a third control contact 43 of the circuit, by means of an auxiliary wire 27, the auxiliary wire 27 being connected at a first end to the cathode K2 of the second transistor TI. At another end, the auxiliary wire 27 is connected to the third control contact 43, from which an electrical connection can be established to a control device for controlling the second thyristor TI. The third control contact 43, via which energy from the main circuit can be made available to the control device, is used to control the gate G2 of the second transistor chip TI.

[0062] In order to be able to handle the current intensities occurring in the power semiconductor component C1, C2, several bonding wires running in parallel are required for each electrical connection 21, 22. However, the inventive design of the thyristors and the anti-parallel connection results in a greatly simplified bonding pattern in which the total number of wires to be drawn is significantly reduced and bonding only has to take place on the top side of the chips. In addition, the invention enables the bonding wires to run straight. This makes it considerably easier to produce an anti-parallel circuit of two thyristors with a bonding pattern according to Fig. 5b by means of wire bonding. The inventive arrangement of the thyristor chips also makes it easier to produce electrical connections using connecting elements other than bonding wires: the connecting elements can, among other things, run in a straight line.

[0063] As an alternative to the embodiment shown in Fig. 5b, the output contact L2 of the semiconductor component can also be designed as a conductor track separated from the first conductor track Fl, which is electrically connected to the first conductor track Fl by an electrical connecting element, e.g. one or more bonding wires. This alternative embodiment is advantageous, for example, when the first conductor track Fl and the conductor track of the output contact L2 separated therefrom are to be located at different heights relative to the plane of the ceramic layer CC. Fig. 6 shows a section through two thyristors T10, TI interconnected according to the invention in accordance with the circuit / bonding diagram of Fig. 5. The two thyristor chips Cl , C2 have a different structure : The cathode K10 of the first thyristor chip Cl , T10 is on the underside of the chip , whereas the cathode K2 of the second thyristor chip C2 , T1 is on the top side of the chip .The anode A10 of the first thyristor chip C1, T10 is on the top side of the chip, whereas the anode A2 of the second thyristor chip C2, T10 is on the bottom side of the chip. The gate G10 of the first thyristor chip C1, T10 and the gate G2 of the second thyristor chip C2, T10 are both on the top side of the respective chip. Between the contacts on the top side and the bottom side there are respective semiconductor layer structures 1, 10, which are also designed differently for the two thyristor chips C1, C2.

[0064] The first thyristor chip Cl, T10 is arranged on the first conductor track Fl. The cathode contact K10 arranged on the underside of the first thyristor chip Cl, T10 is electrically and mechanically connected to the first conductor track Fl by means of a solder layer V. The anode contact A10 and the gate contact G10 are arranged on the top side of the first thyristor chip Cl, T10.

[0065] The second thyristor chip C2, TI is also arranged on the first conductor track Fl. The anode contact A2 arranged on the underside of the second thyristor chip C2, TI is electrically and mechanically connected to the first conductor track Fl by means of a solder layer V. The cathode contact K2 and the gate contact G2 are arranged on the top side of the second thyristor chip C2, TI.

[0066] With regard to the electrical connection of the two thyristor chips C1, C2 by bonding wires D, reference is made to the description of Fig. 5b. Fig. 7 shows a section of a power module 4 according to the invention according to a first embodiment, in which a thyristor pair T10, T11 connected in antiparallel according to the invention is installed.

[0067] The power semiconductor module has a typical hybrid power electronics structure with several power semiconductor components C1, C2 combined on a substrate / circuit carrier and interconnected. The equipment of the power semiconductor module 4 comprises at least one semiconductor component C1, C2, which has an anti-parallel connected thyristor pair T10, T12. The power semiconductor module 4 can have further semiconductor components, such as GTOs, MCTs, power diodes, IGBTs or MOSFETs. A module 4 can also contain other wiring components, e.g. passive components and sensors. The semiconductor components of a conventional power semiconductor module 4 are commercially available components and are therefore not described in more detail below.

[0068] The power semiconductor module 4 contains a base plate P . In the example shown, the base plate P is connected by means of a heat conducting layer I to a heat sink KK, which can have cooling fins in order to dissipate the heat generated by the semiconductor elements. The illustration of cooling fins on the heat sink KK in Fig. 7 has been omitted for the sake of simplicity. Another advantageous embodiment would be, for example, a liquid cooler. The heat conducting layer I can consist of a TIM, which improves the thermal coupling between the base plate P and the heat sink KK. The base plate P is fastened to the heat sink KK by a fastening device B; the closest possible contact between the base plate P and the heat sink KK supports the dissipation of heat from the semiconductor components C1, C2.

[0069] The base plate P is preferably made of a material with good thermal conductivity, e.g., a metal such as aluminum or copper, or a metal / matrix composite such as aluminum-silicon carbide (AlSiC) or copper-silicon carbide (CuSiC). A base plate P made of a metal-ceramic composite (AlSiC, CuSiC) can be easily combined with cooling structures KK made of the same composite or of the associated metal (Al, Cu).

[0070] In the structure shown, the power semiconductor components Cl, C2 are constructed on a circuit carrier S. The circuit carrier S forms an electrical insulation between the semiconductor components Cl, C2 and the base plate P and also has good thermal conductivity in order to dissipate the heat from the semiconductor components Cl, C2 to the base plate P. The circuit carrier S can have a ceramic layer CC, with aluminum nitride (AIN), aluminum oxide (A12O3), beryllium oxide (BeO), silicon carbide (SiC) or silicon nitride (SiN) being preferred materials.Due to their high thermal conductivity and coefficient of thermal expansion, ceramic circuit carriers S, so-called DCB substrates, are preferably used. These consist of a ceramic insulator CC such as aluminum oxide or aluminum nitride, on each of whose sides a thin layer of pure copper is applied, namely a first conductor layer CU1 on an upper side of the ceramic layer CC and a second conductor layer CU2 on an underside of the ceramic layer CC, as shown in Fig. 7. The connection of the circuit carrier S to the base plate P is made via a solder layer V.

[0071] The circuit carrier S has, on its upper side facing the semiconductor components Cl, C2, a first conductor layer CU1 which is structured into a plurality of conductor tracks Fl and F2 according to circuit requirements: in the present example, the conductor tracks comprise, in addition to a first conductor track Fl, a second conductor track with the input contact LI. The conductor tracks Fl and F2 were formed by structuring the first conductor layer CU1, which was arranged on the upper side of the ceramic layer CC. The electronic semiconductor components Cl, C2 are mechanically and electrically connected to the conductor tracks Fl, F2; these electrical connections can be produced by solder layers V. Instead of the solder layers V between the semiconductor components Cl, C2 and the circuit carrier S, another material-fit connection orA suitable fastening method is one which ensures good electrical and thermal contact, for example via an intermediate layer in the form of a metal plate. Electrical connections between the conductor tracks Fl, F2 and the semiconductor components Cl, C2, as well as between the semiconductor components Cl, C2, are made by bonding wires D. Instead of bonding wires, these electrical connections can also be made by other connecting elements.

[0072] The power semiconductor module 4 further comprises a housing H, which is sealed by the base plate P and thus forms a housing interior. Plastic housings are common. In addition to plastic, the housing H can also be made of another dielectric, particularly a ceramic. Ceramics are inexpensive and resistant and, for electrical insulators, have good thermal conductivity. This thermal conductivity is important for dissipating the generated heat.

[0073] For the mutual electrical insulation of the components of the power semiconductor module 4 and for sealing the circuit structure against the outside atmosphere, the housing H is at least partially potted in the direction of the base plate P with a potting compound M. Typically, the housing volume is filled with potting compound M until it evenly surrounds the semiconductor components C1, C2 and the usual standard specifications are met. The connections 51, 52 of the power semiconductor module 4 are led out of the potted housing H via the contact surfaces L1, L2 of the circuit carrier S and solder layers V at suitable points in order to provide external connections of the power semiconductor module 4. Fig. 8 shows a section through a power module 4 according to the invention in accordance with a further embodiment. In contrast to the structure shown in Fig. 7, the structure shown in Fig.8 shown structure of the power module 4 the base plate P, the heat conducting layer I and the fastening devices B .

[0074] Circuit carrier S is only attached to the heat sink KK via a connecting layer V.

Claims

Patent claims 1. Semiconductor component (2) comprising: - a circuit carrier (S) with a first conductor layer (GUI) in which a first conductor track (Fl) is formed, - a first thyristor chip (CI) having an anode contact (A10) and a gate contact (G10) on its upper side and a cathode contact (K10) on its lower side, wherein the first thyristor chip (CI) is placed with its cathode contact (K10) on the first conductor track (GUI, Fl) in such a way that an electrical connection exists between the cathode contact (K10) and the first conductor track (GUI, Fl), - a second thyristor chip (C2) which has a cathode contact (K2) and a gate contact (G2) on its upper side and an anode contact (A2) on its lower side, wherein the second thyristor chip (C2) is placed with its anode contact (A2) on the first conductor track (GUI, Fl) in such a way that an electrical connection exists between the anode contact (A2) and the first conductor track (GUI, Fl), and - at least one electrically conductive connecting element (22, D) which electrically connects the anode contact (A10) of the first thyristor chip (CI) to the cathode contact (K2) of the second thyristor chip (C2), wherein the first conductor track (GUI, Fl) establishes an electrical connection between the cathode contact (K10) of the first thyristor chip (CI) and the anode contact (A2) of the second thyristor chip (C2).

2. Semiconductor component (2) according to claim 1, comprising: - an input contact (LI), - an output contact (L2) which is electrically connected to the anode contact (A2) of the second thyristor chip (C2) by the first conductor track (GUI, Fl), and - at least one electrically conductive connecting element (21, D) which electrically connects the input contact (LI) to the anode contact (A10) of the first thyristor chip (Gl).

3. Semiconductor component (2) according to one of the preceding claims, comprising: - a first control contact (41), - a second control contact (42), - at least one control wire (25, D) which electrically connects the first control contact (41) to the gate contact (G10) of the first thyristor chip (CI), and - at least one control wire (26, D) which electrically connects the second control contact (42) to the gate contact (G2) of the second thyristor chip (C2).

4. Semiconductor component (2) according to one of the preceding claims, comprising: - a third control contact (43), - at least one auxiliary wire (27, D) which electrically connects the third control contact (43) to the cathode contact (K2) of the second thyristor chip (C2).

5. Semiconductor component (2) according to one of the preceding claims, comprising a fourth control contact (44) which is electrically connected to the cathode contact (K10) of the first thyristor chip (Gl) by the first conductor track (GUI, Fl).

6. Semiconductor component (2) according to one of the preceding claims, wherein the at least one electrically conductive connecting element (22, D) is one or more elements from the following group: a bonding wire, a stamped part, a metal piece.

7. Power semiconductor module (4) with a semiconductor component (2) according to one of the preceding claims, further comprising: - a heat sink (KK), - a housing (H), - a potting compound (M), wherein the circuit carrier (S) of the semiconductor component has, in addition to the first conductor layer (GUI) on its upper side, a second conductor layer (CU2) on its underside and a middle layer (CG) electrically insulating the two conductor layers from one another, wherein the semiconductor component (2) is arranged on the heat sink (KK) and housed in the housing (H) which is filled with the potting compound.

8. Power semiconductor module (4) according to claim 7, wherein connecting layers (V) are arranged between the thyristor chips (Cl, C2) and the first conductor track (Fl) of the first conductor layer (GUI) and between the heat sink (KK) and the second conductor layer (CU2).

9. Power semiconductor module (4) according to one of claims 7 or 8, wherein the input contact (LI) and the output contact (L2) of the semiconductor component (2) are each electrically connected through the potting compound (M) to a first and second contacting device (51, 52), respectively, which are arranged outside the housing (H).

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