Method for producing coreless interposer
Patent Information
- Authority / Receiving Office
- EP · EP
- Patent Type
- Applications
- Current Assignee / Owner
- INPACK TECH - LLP
- Filing Date
- 2024-02-25
- Publication Date
- 2026-06-24
Smart Images
Figure IL2024050210_06092024_PF_FP
Abstract
Description
[0001] METHOD FOR PRODUCING CORELESS INTERPOSER
[0002] TECHNICAL FIELD
[0003] The present disclosure relates generally to semiconductor devices, and more particularly, to methods for manufacturing interconnecting structures and electrical interfaces.
[0004] BACKGROUND
[0005] Decreasing the size of semiconductor devices enhances their performance, due to decrease in the interconnecting length, which, in turn, leads to increasing speed of signals transferring, and decreasing the power consumption thereof. Existing manufacturing methods of semiconductor devices are generally based on packaging semiconductor dies / chips, and mounting thereof on a PCB. In order to allow electrical interconnection therebetween, an interposer is mounted between the PCB and the package. Hence, the interposer should coordinate small pads and fine-pitch interconnectors of semiconductor dies / chips with relatively large pads and coarse-pitch interconnectors of the PCB.
[0006] Currently, interposers are made of silicon, glass or organic cores equipped with vertical and horizontal electrical connections. The vertical electrical connections (vias) are typically formed by drilling holes through the substrate, and plating the holes with a conductive material, which, in turn, limits the obtained aspect ratio.
[0007] A recent approach to achieve a shorter interconnector length includes 2.5D or 3D interposers. However, formation of electrical connections in the 2.5D or 3D interposers requires drilling, yielding manufacturing difficulties, poor reliability, and limiting designs and complexity of vias patterns. An additional approach is manufacturing ultra-thin coreless interposers made of organic materials. These, however, suffer from high warpage, via-cracking, and a limited line / space resolution. SUMMARY
[0008] Aspects of the disclosure, according to some embodiments thereof, relate to semiconductor devices. More specifically, but not exclusively, aspects of the disclosure, according to some embodiments thereof, relate to a coreless interposer and methods for manufacturing thereof.
[0009] According to some embodiments, there is provided herein a coreless interposer interconnecting structure, the interposer including one or more layers, wherein each of the one or more layers including: one or more electrically conductive lines (e.g., regions, patterns, pads, and the like) configured to allow passing electrical signals, and an electrically insulating material configured to fill a gap between each of the one or more electrically conductive lines. According to some embodiments, the one or more electrically conductive lines are arranged in a predefined pattern. In some embodiments, the predefined pattern of each of the one or more layers may be different. According to some embodiments, the one or more layers are substantially vertically stacked, thereby enabling on-the-fly formation of vertical electrical connections between the electrically conductive regions.
[0010] Advantageously, in some embodiments, the vertical electrical connections (i.e., vias) of each of the one or more layers are substantially simultaneously formed.
[0011] Advantageously, in some embodiments, the vertical electrical connections are formed devoid of drilling, and therefore are not limited by the aspect ratio (i.e., height to diameter ratio) of the vertical electrical connections. As a result, in some embodiments, formation of vias with high density, complex patterns, and substantially unlimited via height is facilitated and achieved.
[0012] According to some embodiments, the coreless interposer may be flexible. According to some embodiments, the coreless interposer may be semi-rigid. According to some embodiments, the coreless interposer may be rigid. Each possibly is a separate embodiment.
[0013] According to some embodiments, an aspect ratio of the vertical electrical connections is substantially infinite / unlimited. According to some embodiments, there is provided herein a method for a system in a package manufacturing of an interconnecting structure (e.g., coreless interposer) configured for electrically communicating / coupling one or more integrated circuit packages / semiconductor dice to a circuit board, the method including: forming one or more electrically conductive lines (e.g., regions, pads, patterns and the like), filling one or more gaps between the one or more electrically conductive lines by an electrically insulating material, removing excess of the electrically insulating material, thereby obtaining a first layer of the interconnecting structure, and repeating the abovementioned steps to produce additional one or more layers of the interconnecting structure, wherein the additional one or more layers are stacked above the first layer, and thereby enabling on-the-fly formation of vertical electrical connections between the electrically conductive lines.
[0014] According to some embodiments, the one or more electrically conductive lines may be formed by photolithography.
[0015] According to some embodiments, the photolithography may include forming a seed layer, applying a resist on the seed layer, illuminating and developing the resist, filling one or more gaps between the developed resist with an electrically conducting material, removing the developed resist, and removing remnants of the seed layer, such that one or more electrically conducting lines of the electrically conducting material are formed.
[0016] According to some embodiments, the one or more electrically conductive lines may be formed by selective laser sintering.
[0017] According to some embodiments, removing the excess of the electrically insulating material may include planarizing using a surface planer tool / machine, thereby forming a substantially flat surface of the first and / or the additional one or more layers of the interconnecting structure.
[0018] According to some embodiments, the excess of the electrically insulating material may be removed until a portion of the first and / or the additional one or more layers of the interconnecting structure is exposed. According to some embodiments, the method may be devoid of drilling steps. According to some embodiments, the method may be devoid of etching steps.
[0019] According to some embodiments, an aspect ratio of the vertical electrical connections formed according to the disclosed method may be substantially unlimited.
[0020] According to some embodiments, the method may include curing and / or baking the electrically insulating material. According to some embodiments, the method may include thermally treating the electrically insulating material.
[0021] According to some embodiments, filling of the one or more gaps may include pouring / spreading the electrically insulating material over the one or more electrically conductive lines and the gaps therebetween.
[0022] According to some embodiments, the method may include forming at least the first layer of the interconnecting structure on a temporary carrier.
[0023] According to some embodiments, the electrically insulating material may be dielectric.
[0024] According to some embodiments, the electrically insulating material may include one or more polymers.
[0025] According to some embodiments, a line / space resolution of the conductive lines structure may be at least about 5 / 5 um.
[0026] According to some embodiments, the vertical electrical connections may include through- chip vertical electrical connections.
[0027] According to some embodiments, the interconnecting structure may be configured to allow electrical coupling between conductive pads sized about 100 x 100 um to conductive pads sized about 5 x 5 um or less.
[0028] Certain embodiments of the present disclosure may include some, all, or none of the above advantages. One or more other technical advantages may be readily apparent to those skilled in the art from the figures, descriptions, and claims included herein. Moreover, while specific advantages have been enumerated above, various embodiments may include all, some, or none of the enumerated advantages. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. In case of conflict, the patent specification, including definitions, governs. As used herein, the indefinite articles “a” and “an” mean “at least one” or “one or more” unless the context clearly dictates otherwise.
[0029] BRIEF DESCRIPTION OF THE FIGURES
[0030] Some embodiments of the disclosure are described herein with reference to the accompanying figures. The description, together with the figures, makes apparent to a person having ordinary skill in the art how some embodiments may be practiced. The figures are for the purpose of illustrative description and no attempt is made to show structural details of an embodiment in more detail than is necessary for a fundamental understanding of the disclosure. For the sake of clarity, some objects depicted in the figures are not drawn to scale. Moreover, two different objects in the same figure may be drawn to different scales. In particular, the scale of some objects may be greatly exaggerated as compared to other objects in the same figure.
[0031] In the figures:
[0032] Figure 1A schematically depicts a side view of an interconnecting structure, according to some embodiments;
[0033] Figure IB schematically depicts a top view of the interconnecting structure of Figure 1A, according to some embodiments;
[0034] Figure 1C schematically depicts a top view of each of one or more layers of the interconnecting structure of Figure 1A, according to some embodiments;
[0035] Figure 2 shows a flow chart of a method for manufacturing an interconnecting structure, such as a coreless interposer, according to some embodiments;
[0036] Figure 3 schematically illustrates an example of an additive manufacturing method for forming electrically conducting regions of an interconnecting structure, according to some embodiments; Figure 4 schematically illustrates an example of a semi-additive manufacturing method forming the electrically conducting regions of an interconnecting structure, according to some embodiments;
[0037] Figure 5 schematically illustrates an example of a semi-additive manufacturing method forming the electrically conducting regions of an interconnecting structure, according to some embodiments;
[0038] Figure 6 schematically illustrates an example of a method for producing an interconnecting structure, such as a coreless interposer, according to some embodiments.
[0039] Figure 7 illustrates an example of a cross-section view of an experimentally produced coreless interposer having four layers, according to some embodiments.
[0040] DETAILED DESCRIPTION
[0041] The principles, uses, and implementations of the teachings herein may be better understood with reference to the accompanying description and figures. Upon perusal of the description and figures present herein, one skilled in the art will be able to implement the teachings herein without undue effort or experimentation.
[0042] In the description and claims of the application, the words “include” and “have”, and forms thereof, are not limited to members in a list with which the words may be associated.
[0043] As used herein, the term “about” may be used to specify a value of a quantity or parameter (e.g. the length of an element) to within a continuous range of values in the neighborhood of (and including) a given (stated) value. According to some embodiments, “about” may specify the value of a parameter to be between 80 % and 120 % of the given value. For example, the statement “the length of the element is equal to about 1 m” is equivalent to the statement “the length of the element is between 0.8 m and 1.2 m”. According to some embodiments, “about” may specify the value of a parameter to be between 90 % and 110 % of the given value. According to some embodiments, “about” may specify the value of a parameter to be between 95 % and 105 % of the given value. As used herein, according to some embodiments, the terms “substantially” and “about” may be interchangeable.
[0044] As used herein, according to some embodiments, the terms “interface”, “interposer” and “interconnecting structure” may be interchangeable and refer to an electrical interface configured to enable electrical interconnection between devices or components thereof. According to some embodiments, the electrical interface may be configured for routing and / or rerouting electrical interconnection, e.g., spreading electrical interconnection between large pads to small pads. According to some embodiments, the interposer may be configured for allowing electrical interconnection between large pads formed on a printed circuit board (PCB) and small pads (e.g., having a small size / diameter and / or a small pitch size) formed on a package, dice, or any other components of integrated circuits.
[0045] According to some embodiments, the large pads may refer to pads having a large size, such as but not limited to, about 500 x 500 um or more, about 400 x 400 um or more, about 300 x 300 um or more. Each possibility is a separate embodiment. According to some embodiments, the large pads may refer to pads having a large pitch size, such as but not limited to, about 4 mm or more, about 3 mm or more, about 2 mm or more, about 1.4 mm or more. Each possibility is a separate embodiment. According to some embodiments, the small pads may refer to pads having a small size, such as but not limited to, about 4 x 4 um or less, about 5 x 5 um or less, about 7 x 7 um or less, about 10 x 10 um or less, about 12 x 12 um or less, about 15 x 15 um or less, about 20 x 20 um or less, about 25 x 25 um or less, about 30 x 30 um or less, about 40 x 40 um or less, about 50 x 50 um or less. Each possibility is a separate embodiment. According to some embodiments, the small pads may refer to pads having a small / fme pitch size (i.e., a distance between each conductive region / line), such as but not limited to, about 500 um or less, about 200 um or less, about 100 um or less, about 50 um or less, about 40 um or less, about 30 um or less, about 20 um or less, about 10 um or less, about 8 um or less, about 5 um or less, about 4 um or less, about 3 um or less, about 2.5 um or less. Each possibility is a separate embodiment.
[0046] According to some embodiments, the interposer may be used, among others, in integrated circuits, providing electrical communication between integrated circuit dies and a package / package substrate, such as ball grid array (BGA) packages, multi-chip modules, and the like. According to some embodiments, the interposer may be integrated in 3D integrated circuit die stacking.
[0047] According to some embodiments, the interposer may refer to logic interposers. According to some embodiments, the interposer may refer to logic and memory interposers. According to some embodiments, the interposer may refer to image sensor interposers, such as a complementary metal oxide semiconductor (CMOS) image interposer. According to some embodiments, the interposer may refer to memory stack interposers. According to some embodiments, the interposer may refer to power, RF, analogue integrated passive interposers. Each possibility is a separate embodiment.
[0048] As used herein, the term “coreless” may refer to a substrate-less structure, i.e., an interposer without an interposer substrate. According to some embodiments, the term “coreless interposer” may refer to an interposer devoid of a core / substrate layer.
[0049] As used herein, the term “package” may refer to any package type housing one or more semiconduction devices, dies, integrated circuits, memory devices, passive and / or active components, and the like, or any combination thereof.
[0050] As used herein, the terms “conductive lines” and “electrically conducting material regions”, “conductive regions” and “contact pads” and “conductive pattern” may, according to some embodiments, be used interchangeably and refer to any electrically conducting portions, such as conducting portions of a coreless interposer. According to some embodiments, the conductive lines may be made of or include metals, such as, but not limited to, copper, gold, silver, nickel, and the like, or any combination thereof. According to some embodiments, conductive regions are configured to electrically interconnect, rout and / or re-rout integrated circuit devices and / or components thereof, such as, but not limited to, microprocessors, memory devices, a chipset, a graphics device, one more dies, and the like, or any combination thereof. According to some embodiments, conductive line may refer to electrical traces. Additionally, or alternatively, in some embodiments, conductive lines may form a conducting pathway (vertical electrical connections) between one or more layers of the coreless interposer, as further elaborated elsewhere herein. According to some embodiments, the conductive lines may form various types of vias, such as, but not limited to, through-vias, tented vias, blind vias, buried vias, stacked vias, and the like, or any combination thereof. Each possibility is a separate embodiment. According to some embodiments, in contrast conventionally formed vias, the disclosed herein vias are formed devoid of drilling. According to some embodiments, in contrast to conventionally formed vias, the disclosed herein vias are form devoid of etching.
[0051] Reference is now made to Fig. 1A, which schematically depicts a side view of an interconnecting structure 100, to Fig. IB which schematically illustrates a top view thereof, and to Fig. 1C, which schematically illustrates a top view of each of the one or more layers of interconnecting structure 100, according to some embodiments.
[0052] According to some embodiments, interconnecting structure 100 includes a coreless interposer 102. According to some embodiments, coreless interposer 102 is configured to allow electrical interconnection of packages (e.g., a chip package), modules, systems, and the like, or any combination thereof. According to some embodiments, coreless interposer 102 may be used for electrically interconnecting a chip package to a printed circuit board (PCB), such as motherboard, central processing unit (CPU), and the like.
[0053] Advantageously, in some embodiments, a line / space resolution of coreless interposer 102 may be at least about 5 / 5 um. According to some embodiments, contact pitch (spatial separation between nearest vias) of coreless interposer 102 may be below about 5 um. According to some embodiments, contact pitch (spatial separation between nearest vias) of coreless interposer 102 may be below about 4 um. According to some embodiments, contact pitch (spatial separation between nearest vias) of coreless interposer 102 may be below about 3 um. According to some embodiments, contact pitch (spatial separation between nearest vias) of coreless interposer 102 may be below about 2.5 um.
[0054] According to some embodiments, coreless interposer 102 has a substrate-less structure. According to some embodiments, electrically conductive lines of coreless interposer 102 are formed devoid of drilling, etching, or otherwise penetrating thereof, thereby minimizing / preventing cracking or otherwise deforming thereof, while allowing increasing the density and the resolution of the electrically conductive lines (and of vias formed by the electrically conductive lines, as further elaborated elsewhere herein). According to some embodiments, coreless interposer 102 is a three-dimensional (3D) interposer. According to some embodiments, coreless interposer 102 may include a plurality of high-density of electrically conductive lines defined therein. According to some embodiments, coreless interposer 102 may include a plurality of ultra-thin and high- density vertical electrical interconnections formed therein. Advantageously, in some embodiments, coreless interposer 102 enables miniaturizing electronic devices while improving the interconnection, thereby improving the performance and decreasing the power consumption of the electronic devices.
[0055] According to some embodiments, interconnecting structure 100 may have an ultra-thin structure e.g. a thickness of about 50 um or lower. According to some embodiments, interconnecting structure 100 may have an ultra-thin structure e.g., a thickness of about 40 um or lower. According to some embodiments, interconnecting structure 100 may have an ultra-thin structure e.g., having a thickness of about 30 um or lower. According to some embodiments, interconnecting structure 100 may have an ultra-thin structure e.g., having a thickness of about 20 um or lower. According to some embodiments, interconnecting structure 100 may have an ultra-thin structure e.g., having a thickness of about 10 um or lower. According to some embodiments, interconnecting structure 100 may have an ultra-thin structure e.g., having a thickness in a range of about 5 to about 500 um. Each possibility is a separate embodiment. In some embodiments, interconnecting structure 100 may have any desired thickness (i.e., substantially unlimited height).
[0056] According to some embodiments, interconnecting structure 100 may have a multilayered structure (e.g. 2, 3, 4, 5, 6, 7 or more layers). Each possibility is a separate embodiment. According to some embodiments, thickness of each of the layers may be substantially the same. In some embodiments, each of the layers may have a different thickness.
[0057] According to some embodiments, interconnecting structure 100 is configured to electrically interconnect various types of packaging to the PCB, such as but not limited to, a ball grid array (BGA), land grid array (LGA), multi-chip module (MCM), a quad flat non-leaded package (QFN), system-in-package (SiP), package-on-package (PoP), fan-out wafer-level packaging (WLP), or any other type of packaging. According to some embodiments, interconnecting structure 100 may be used to electrically interconnect a single package to the PCB. According to some embodiments, interconnecting structure 100 may be used to electrically interconnect multiple packages to the PCB.
[0058] According to some embodiments, interconnecting structure 100 is configured to electrically interconnect microprocessors (e.g., single-core and / or multi-core processors), microcontrollers, memory chips (such as volatile memory, a non-volatile memory, and the like), logic chips, integrated circuits, any passive and / or active components or device, or any other electrical components, semiconductor devices, and the like, or any combination thereof.
[0059] According to some embodiments, coreless interposer 102 includes one or more layers. According to some embodiments, each of the one or more layers is stacked above a previous (bottom) layer. According to some embodiments, each of the or more layers include electrically insulating regions and electrically conducting regions.
[0060] According to some embodiments, each of the insulating regions is positioned between each of the electrically conducting regions, thereby preventing a (horizontal) current flow (i.e., shorts) between each of the plurality of conducting regions at a specific layer of the one or more layers. Put differently, the one or more layers are substantially vertically stacked, forming vertical electrical connections between insulating regions, thereby allowing vertical current flow through the one or more layers according to a predefined pattem / path.
[0061] Advantageously, in some embodiments, the structure of coreless interposer 102 enables on-the-fly formation of vertical electrical connections between the electrically insulating material. According to some embodiments, the vertical electrical connections of each of the one or more layers may be formed simultaneously. Advantageously, in some embodiments, the vertical electrical connections are formed devoid of drilling. Advantageously, in some embodiments, the vertical electrical connections are formed devoid of etching (e.g., chemical etching). Advantageously, the vertical electrical connections may be formed in any desired pattern and / or height, to facilitate routing the electrical signal. Advantageously, in some embodiments, the aspect ratio of the vertical electrical connections of coreless interposer 102 may be substantially infmite / unlimited.
[0062] According to some embodiments, and as depicted in Figs. 1A-C, the one or more layers of coreless interposer 102 may include four layers. According to some embodiments, and as depicted in Fig. 1A, a first layer 110 of the one or more layers includes a plurality of electrically conducting material regions 110a and a plurality of electrically insulating material regions 110b. According to some embodiments, and as depicted in Fig. 1A, each of a second layer 112, a third layer 114 and a fourth layer 116 of the one or more layers includes a plurality of electrically conducting material regions 112a, 114a and 116a and a plurality of electrically insulating material regions 112b, 114b and 116b, respectively. It may be understood that the number of the one or more layers of coreless interposer 102 may vary and include substantially any required number thereof. According to some embodiments, the number of the one or more layers may include, among others, 3, 4, 5, 6, 7, 8, 9, 10, 15, 20, 25, 30 or more layers. According to some embodiments, there is substantially no upper limit for the number of the one or more layers, as described in greater detail in Fig. 2.
[0063] According to some embodiments, and as depicted in Figs. 1A-C, plurality of electrically conducting material regions 110a of first layer 110 may include a first plurality of contact pads configured to electrically interconnect to a PCB. According to some embodiments, dimensions of each of the first plurality of contact pads may be about 100 um x 100 um. According to some embodiments, dimensions of each of the first plurality of contact pads may be in the range of about 100-500 um x 100-500 um. According to some embodiments, dimensions of each of the first plurality of contact pads may be in the range of about 50-500 um x 50-500 um. Each possibility is a separate embodiment.
[0064] According to some embodiments, the plurality of electrically conducting material regions 112a of second layer 112 may be configured for forming a desired pattern and / or size of vertical electrical connections. According to some embodiments, plurality of electrically conducting material regions 114a of third layer 114 may optionally include and / or serve as a redistribution layer (RDL) configured for rerouting the vertical electrical connections to desired locations. According to some embodiments, the plurality of electrically conducting material regions 116a of fourth layer 116 may include a second plurality of contact pads, wherein the second plurality of contact pads is configured to interconnect interposer 102 to a package. According to some embodiments, the dimensions of each of the second plurality of contact pads may be about 10 x 10 um or lower. According to some embodiments, dimensions of each of second plurality of contact pads may be about 8 x 8 um or lower. According to some embodiments, dimensions of each of second plurality of contact pads may be about 6 x 6 um or lower. According to some embodiments, dimensions of each of second plurality of contact pads may be about 5 x 5 um or lower. According to some embodiments, dimensions of each of second plurality of contact pads may be about 4 x 4 um or lower. According to some embodiments, dimensions of each of second plurality of contact pads may be about 2.5 x 2.5 um or lower. Each possibility is a separate embodiment.
[0065] According to some embodiments, lines and / or contact pads of the electrically conducting material regions may have a thickness of about 5-7 um or 3-6 um. According to some embodiments, the lines and / or pads may have a thickness of less than about 5 um.
[0066] According to some embodiments, electrically conducting material regions 110a / 112a / 114a / 116a may include or be in a form of contact pads. According to some embodiments, a form / shape of electrically conducting material regions 110a / 112a / 114a / 116a may include or be in a form of, among others, a circle, square, oblong, rectangle, rounded rectangle, chamfered rectangle, octagon, donut, n-sided polygon, and the like (when viewed from above), or any combination thereof. Each possibility is a separate embodiment. According to some embodiments, electrically conducting material regions 110a / 112a / 114a / 116a may include or be in a form of electrical lines.
[0067] According to some embodiments, vertical electrical connections may be in a form of or include, among others, through-vias, tented vias, blind vias, buried vias, stacked vias, and the like, or any combination thereof. Each possibility is a separate embodiment.
[0068] According to some embodiments, coreless interposer 102 may be flexible. According to some embodiments, coreless interposer 102 may be semi-rigid. According to some embodiments, coreless interposer 102 may be rigid. Each possibly is a separate embodiment. According to some embodiments, the rigid coreless interposer may have Shore D hardness values in a range of about 90D-100D. According to some embodiments, the rigid coreless interposer may have Shore D hardness values in a range of about 85D- 96D. According to some embodiments, the flexible coreless interposer may have Shore hardness values in a range of about 55D-75D. According to some embodiments, the flexible coreless interposer may have Shore hardness values in a range of about 60D-70D. According to some embodiments, the semi-rigid coreless interposer may have combined Shore D hardness values of the rigid and the flexible coreless interposers, i.e., may include combination of the rigid Shore D hardness and of the flexible Shore D hardness values of coreless interposers. As a non-limiting example, the semi -flexible coreless interposer may have regions of Shore hardness of about 96D and regions of about 65D. Alternatively, in some embodiments, the semi-rigid coreless interposer may substantially uniform hardness, such as but not limited to, Shore D hardness values in a range of about 65D- 85D.
[0069] Reference is made to Fig. 2, which is a flow chart 200 of a method for manufacturing an interconnecting structure, such as a coreless interposer, according to some embodiments.
[0070] According to some embodiments, at step 202, the method may include forming one or more electrically conducting regions. According to some embodiments, the one or more electrically conducting regions may include or be in the form of one or more conductive lines. According to some embodiments, the one or more electrically conducting regions may include or be in the form of contact pads. According to some embodiments, the one or more electrically conducting regions may be configured to form vias. According to some embodiment, the one or more electrically conducting regions may be formed according to a predefined pattern.
[0071] According to some embodiments, the one or more electrically conducting regions may be made of or include metals. According to some embodiments, the one or more electrically conducting regions may include copper, gold, silver, and the like. Each possibility is a separate embodiment. According to some embodiments, each of the one or more layers of the interposer may be made of or include different materials. According to some embodiments, each of one or more layers of the interposer may be made of or include the same materials (e.g., made of or include the same metal in each of the one or more layers). According to some embodiments, the one or more electrically conducting regions may be made of or include a mixture of conductive materials. According to some embodiments, the one or more electrically conducting lines may be made of or include a mixture of metals.
[0072] According to some embodiments, at step 202, the method may include forming one or more electrically conducting regions on a temporary carrier substrate. According to some embodiments, the temporary carrier substrate may be made of an inert material, such as, but not limited to, glass, stainless steel, SiC, AIN, polyimide, polyimide on glass and the like. According to some embodiments, the temporary carrier substrate may be rigid, semirigid or flexible. Each possibility is a separate embodiment.
[0073] According to some embodiments, the one or more electrically conducting regions may be formed by implementing an additive manufacturing method (step 202a), such as but not limited to, selective laser sintering, as elaborated in Fig. 3.
[0074] According to some embodiments, the one or more electrically conducting regions may be formed by implementing a semi-additive manufacturing method (step 202b), such as but as but not limited to, photolithography and / or electroplating, as further elaborated in Fig. 4 and Fig. 5.
[0075] According to some embodiments, at step 204, the method may include filling one or more gaps between the one or more electrically conducting regions with electrically insulating material. According to some embodiments, the filling may include pouring / spreading the electrically insulating material over the one or more electrically conducting regions and the one or more gaps therebetween.
[0076] According to some embodiments, the electrically insulating material may include dielectric materials. According to some embodiments, the electrically insulating material may include one or more polymers. According to some embodiments, the electrically insulating material may be made of or include polyimide. According to some embodiments, the electrically insulating material may be photosensitive. As a nonlimiting example, the electrically insulating material may be made of or include photo definable epoxy. According to some embodiments, the electrically insulating material may be photo-insensitive. According to some embodiments, the electrically insulating material may include a thickness to diameter ratio of at least about 5: 1. According to some embodiments, the thickness of the electrically insulating material layer be in the range of about 5-30 um. According to some embodiments, the electrically insulating material has a coefficient of thermal expansion (CTE) of about 15-20 ppm / °C.
[0077] According to some embodiments, the CTE of the electrically conducting regions may substantially match the CTE of the electrically insulating material, thereby facilitating the thermal management and heat dissipation generated by an electronic device away therefrom. It is understood by skilled in the art that insufficient heat transfer results in performance degradation of the electronic device or components thereof. Furthermore, thermal expansion mismatch may lead to an increased mechanical stress, which, in turn, may also lead to performance degradation.
[0078] According to some embodiments, each of one or more layers of the coreless interposer may be made of or include different electrically insulating materials. According to some embodiments, each of one or more layers of the coreless interposer may be made of or include same electrically insulating material.
[0079] According to some embodiments, at step 206, the method may optionally include thermally treating, curing and / or polymerizing the electrically insulating material fdling the one or more gaps between the one or more electrically conducting regions.
[0080] According to some embodiments, at step 208, the method may include removing excess of the electrically insulating material, thereby obtaining a first layer of the one or more layers of the interconnecting structure.
[0081] According to some embodiments, removing / scraping off the excess of the electrically insulating material may include planarizing using a surface planer device / machine, such that a substantially flat surface of the first layer (and / or of each of additional one or more layers) of the interconnecting structure is formed. According to some embodiments, the excess of the electrically insulating material may be removed until a portion of the electrically conducting material regions (e.g., surface or top layer of the electrically conducting material region) is exposed. According to some embodiments, at step 210, the method may include repeating the abovementioned steps (e.g., steps 202-208) to produce an additional one or more layers of the interconnecting structure. Put differently, the abovementioned steps may be repeated until the required number of the one or more layers is obtained (e.g., until the required height / depth of vertical electrical connections is achieved).
[0082] According to some embodiments, the repeating may include aligning the electrically conductive regions of a previous / bottom layer of the one or more layers with the additional layer of the one or more layers of the interconnection structure. According to some embodiments, the aligning may be performed according to fiducials / landmarks of the previous / bottom layer. According to some embodiments, alignment between the electrically conductive regions of each of the one more layers may be about 1 um or lower. According to some embodiments, alignment between the electrically conductive regions of each of the one more layers may be about 0.5 um or lower. Each possibility is a separate embodiment. In some embodiments, the method disclosed herein allows manufacturing coreless interposers having mismatch loss of less than about 10% or less than about 5%.
[0083] According to some embodiments, the method may optionally include a step 212 of removing the temporary carrier from the interconnecting structure.
[0084] According to some embodiments, the method may optionally include performing electrical measurements to test / verify at least a portion of the one or more layers during and / or after manufacturing of the interconnecting structure (step not shown).
[0085] According to some embodiments, the method provides an “on-the-fly” formation of vertical electrical connections between the electrically insulating material.
[0086] In some embodiments, the disclosed herein method is devoid of any drilling steps. In some embodiments, the method is devoid of mechanical drilling and / or laser drilling. Advantageously, the disclosed method is therefore not limited to a height to diameter aspect ratio of the via, as opposed to methods including drilling of the via which are prone to cracking of the interposer or parts thereof. Put differently, in some embodiments, the aspect ratio may be substantially infinite. Advantageously, due to the absence of height to diameter aspect ratio limitations, in some embodiments, there are substantially no upper limit of the number of the one or more layers stacked above each other, thereby allowing formation of vertical electrical connections (e.g., vias) between the electrically insulating material with substantially unlimited height / depth.
[0087] According to some embodiments, the predefined pattern of each of the one or more layers may be different. According to some embodiments, complex and high-density patterns may be obtained, regardless of the number of the one or more layers of the interposer. Advantageously, in some embodiments, the disclosed herein methods combine additive manufacturing techniques for producing the coreless interposer interconnecting structure, such that the interposer is produced either by semi-additive or by additive (e.g., fully additive) methods. Thereby, in some embodiments, allowing obtaining a wide range of patterns (e.g., interconnecting schemes) and vias architectures, and hence achieving the required signal routing, signal integrity, and power delivery, while facilitating thermal management therethrough. In some embodiments, complex patterns of the vertical electrical connections may be achieved substantially without reducing or limiting the resolution (i.e. the density of the electrically conducting regions) of the interposer. According to some embodiments, a line / space resolution of the interconnecting structure may be at least about 5 / 5 um.
[0088] In some embodiments, a coreless interposer manufactured according to the disclosed herein method may be compatible with military standard testing of 1000 cycles from - 45°C to +145°C. In some embodiments, a coreless interposer manufactured according to the disclosed herein method may be compatible with Joint Electron Device Engineering Council (JEDEC) standards, including testing of 1000 cycles from -25°C to +125°C.
[0089] In some embodiments, the method disclosed herein allows manufacturing coreless interposers having mismatch loss of less than about 10% or less than about 5%. In some embodiments, the method disclosed herein allows manufacturing coreless interposers having conducting material thickness variation of less than about 1 um or less than about 0.5 um. In some embodiments, the method disclosed herein allows manufacturing coreless interposers having interlayer contact resistivity lower than about I x lO'6ohm / cm2. Reference is made to Fig. 3, which schematically illustrates an example of an additive manufacturing method 302a for forming the electrically conducting regions (i.e., in step 202a in Fig. 2), according to some embodiments. According to some embodiments, the additive manufacturing method may include, among others, selective laser sintering (SLS) methods, such as but not limited to, direct SLS, direct metal laser sintering (DMLS), selective laser melting (SLM), metal lines 3D printing or any other additive manufacturing methods. According to some embodiments, the additive manufacturing method may include any type of directed energy deposition methods, powder-based fusion additive manufacturing methods, and the like, or any combination thereof. According to some embodiments, the additive manufacturing method may include micrometal additive manufacturing (MMAM) methods. Each possibility is a separate embodiment.
[0090] According to some embodiments, at step 302a- 1, the additive manufacturing method may include cleaning a carrier 304. According to some embodiments, carrier 304 may be a temporary carrier. Alternatively, in some embodiments, the carrier may be a nontemporary carrier.
[0091] According to some embodiments, cleaning carrier 304 may include performing plasma surface treatment. According to some embodiments, the plasma surface treatment may be performed by an atmospheric plasma. According to some embodiments, cleaning carrier 304 may include chemical etching (i.e., wet or dry etching) of the surface of the carrier. According to some embodiments, cleaning carrier 304 may include dry etching of the surface of carrier 304. According to some embodiments, cleaning carrier 304 may include ultrasonic cleaning. According to some embodiments, cleaning carrier 304 may include ozone treatment of the surface of the carrier. According to some embodiments, cleaning carrier 304 may include any combination of the abovementioned cleaning methods, or any other surface treatment / cleaning.
[0092] According to some embodiments, at step 302a-2, the additive manufacturing method may include coating the surface of carrier 304 with electrically conductive material. According to some embodiments, the electrically conductive material may be made of or include one or more metals. According to some embodiments, the electrically conductive material may include copper. According to some embodiments, the electrically conductive material may include gold, silver, and the like.
[0093] According to some embodiments, at step 302a-2, the additive manufacturing method may include spreading / coating carrier 304 with an ink coating 308, such as but not limited to, a copper ink coating. According to some embodiments, ink coating 308 may include a structural powder (i.e., a high-melting-point powder, such as metal), and a binder / solvent (i.e., a powder having a lower melting point than the structural powder). Put differently, in some embodiments, ink coating 308 may be made of or include a mixture of two or more powders. According to some embodiments ink coating 308 may include a mixture of conducting materials (e.g., a mixture of metals). It may be understood by one of skill in the art that different binders and / or solvents produce a metal ink with different viscosities, thereby affecting filling abilities thereof. According to some embodiments, the solvents may include, among others, water, ethylene glycol, diethylene glycol monomethyl ether, and the like. Each possibility is a separate embodiment.
[0094] According to some embodiments, the coating of carrier 304 with electrically conducting material may be performed by, among others, an ink spay coater, a slot-die coater, an ultrasonic spin-spay coater and the like, or any combination thereof. According to some embodiments, coating carrier 304 may include doctor blade coating, to facilitate formation of well-defined coating thickness.
[0095] According to some embodiments, step 302a-2 may include drying the ink coating 308. According to some embodiments, the drying may be performed, among others, by a blower, an oven, or the like.
[0096] According to some embodiments, at step 302a-3, the additive manufacturing may include performing selective laser sintering to form electrically conductive regions 310a according to a predefined pattern. According to some embodiments, a direct laser writer may be used for performing the selective laser sintering.
[0097] According to some embodiments, at step 302a-4, the additive manufacturing method may include washing or otherwise removing the non-sintered material (e.g., the non-sintered copper ink), thereby obtaining a pattern of the electrically conducting regions 310a. According to some embodiments, the pattern may include electrically conducting lines having a required width, length, and distance therebetween, as essentially disclosed herein.
[0098] According to some embodiments, method 302a may be devoid of material subtractions steps.
[0099] Reference is made to Fig. 4, which schematically illustrates an example of a semi-additive manufacturing method 402b for forming the electrically conducting regions (i.e., step 202a in Fig. 2), according to some embodiments.
[0100] According to some embodiments, the semi-additive method may be based on or include lithography manufacturing methods. According to some embodiments, the lithography methods may include, among others, maskless lithography methods. According to some embodiments, lithography may include, among others, X-ray, electron-beam and / or optical lithography (i.e., photolithography), and the like. Each possibility is a separate embodiment. According to some embodiments, lithography may include, among others, nanolithography, plasmonic-assisted lithography, laser interference lithography, nanosphere lithography, and the like. Each possibility is a separate embodiment.
[0101] According to some embodiments, semi-additive manufacturing method 402b may include photolithography.
[0102] According to some embodiments, at step 404b-l, the semi-additive method may include cleaning a carrier 404. According to some embodiments, cleaning carrier 404 may include performing plasma surface treatment. According to some embodiments, the plasma surface treatment may be performed by an atmospheric plasma. According to some embodiments, cleaning may include chemical etching (i.e., wet etching) of the surface of carrier 404. According to some embodiments, carrier cleaning may include dry etching of the surface of carrier 404. According to some embodiments, carrier cleaning may include ultrasonic cleaning (e.g., in different solutions, such as acetone, methanol, and the like). According to some embodiments, carrier cleaning may include ozone treatment of the surface of carrier 404. According to some embodiments, carrier cleaning may include any combination of the abovementioned cleaning methods, or any other surface treatment / cleaning . According to some embodiments, at step 402b-2, the semi-additive method may include applying a radiation-sensitive compound on carrier 404. According to some embodiments, the radiation-sensitive compound may include a resist, such as a positive resist (i.e., the formed pattern in the positive resist is the same as the pattern on the mask) or a negative resist (i.e., the formed pattern is reverse of the mask pattern). According to some embodiments, the resist may include a photoresist 408.
[0103] According to some embodiments, carrier 404 may be maintained in a spin coater for applying / spreading the photoresist thereon. According to some embodiments, carrier 404 may be positioned on a vacuum spindle for applying / spreading photoresist 408 thereon. According to some embodiments, carrier 404 may be rotated (e.g., for about 15 seconds, about 30 seconds, about 60 seconds, and the like), to facilitate obtaining uniform photoresist 408 coating. According to some embodiments, carrier 404 may optionally undergo a pre-patterning thermal treatment (e.g., soft baking), to remove solvent from photoresist 408 and / or to enhance adhesion to carrier 404.
[0104] According to some embodiments, at step 402b-3, the semi-additive method may include pattern transferring. According to some embodiments, step 402b-3 may be performed in a clean room illuminated with yellow light. According to some embodiments, step 402b- 3 may include exposing photoresist 408 to radiation, such as ultraviolet radiation, to transfer the desired pattern.
[0105] According to some embodiments, following completion of transferring the pattern, photoresist 408 may be removed from the unpattemed portions, such that a pattern of one or more insulating regions 410b is formed on carrier 404. According to some embodiments, a developer solution (e.g., metal-ion-free developer solution) may be used for removing the unexposed portions of negative tone photoresist and exposure of positive resist 408.
[0106] According to some embodiments, step 402b-3 may include performing a post-exposure baking before developing the pattern of one or more insulating regions 410b on carrier 404. According to some embodiments, step 402b-3 may include performing a hard baking of one or more insulating regions 410b, to facilitate solidifying the pattern of one or more insulating regions 410b.
[0107] According to some embodiments, step 402b-3 may include removing photoresist residue.
[0108] According to some embodiments, at step 402b-4, the semi-additive method may include applying electrically conducting material between one or more gaps between one or more insulating regions 410b. According to some embodiments, the electrically conducting material may be applied by electroplating (e.g., copper electroplating).
[0109] According to some embodiments, the one or more gaps between one or more insulating regions 410b define the regions and the dimensions of the electrically conducting material (i.e., of the electrically conducting regions 410a, such as lines, pads, vias, and the like) on the carrier. As a non-limiting example, in the semi-additive methods, the resolution of the electrically conducting lines of an interconnecting structure is defined by the resolution of the photoresist pattern (i.e., the minimum dimension that can be accurately transferred to the resist applied on the carrier) obtained by photolithography methods.
[0110] According to some embodiments, at step 402b-6, the semi-additive method may optionally include removing one or more insulating regions 410b. According to some embodiments, removing the photoresist may include any suitable removing method, such as, wet and / or dry etching, stripping, washing, and the like, or any combination thereof.
[0111] Reference is made to Fig. 5, which schematically illustrates an example of a semi-additive manufacturing method 502b for obtaining the electrically conducting regions (i.e., of step 202b in Fig. 2), according to some embodiments.
[0112] According to some embodiments, semi-additive method 502b may be based on or include lithography manufacturing methods. According to some embodiments, the lithography methods may include, among others, maskless lithography methods. According to some embodiments, lithography may include, among others, X-ray, electron-beam and / or optical lithography (i.e., photolithography), and the like. Each possibility is a separate embodiment. According to some embodiments, lithography may include, among others, nanolithography, plasmonic-assisted lithography, laser interference lithography, nanosphere lithography, and the like. Each possibility is a separate embodiment.
[0113] According to some embodiments, semi-additive method 502b may include photolithography .
[0114] According to some embodiments, at step 502b-l, the semi-additive method may include providing / obtaining a carrier substrate 504. According to some embodiments, carrier 504 may be a temporary carrier.
[0115] According to some embodiments, step 502b- 1 may include cleaning carrier 504. According to some embodiments, the carrier cleaning may include performing plasma surface treatment. According to some embodiments, the carrier cleaning may include chemical etching (i.e., wet etching) of the surface of carrier 504. According to some embodiments, the carrier cleaning may include dry etching of the surface of carrier 504. According to some embodiments, the carrier cleaning may include ultrasonic cleaning. According to some embodiments, the carrier cleaning may include ozone treatment, plasma treatment and the like, of the surface of the carrier. According to some embodiments, the carrier cleaning may include any combination of the abovementioned cleaning methods, or any other suitable surface treatment / cleaning.
[0116] According to some embodiments, at step 502b-2, the semi-additive method may include forming a seed layer 506 on carrier 504. According to some embodiments, seed layer 506 may be made of or include one or more metals. According to some embodiments, seed layer 506 may include TiW and Cu.
[0117] According to some embodiments, seed layer 506 may be formed by metallization processes. According to some embodiments, seed layer 506 may be formed by physical vapor deposition (PVD) methods, such as sputtering or thermal evaporation. According to some embodiments, seed layer 506 may be formed by chemical vapor deposition (CVD) methods, such as atomic layer deposition (ALD). Each possibility is a separate embodiment.
[0118] According to some embodiments, at step 502b-3, the semi-additive method may include applying of a radiation-sensitive compound on the seed layer 506. According to some embodiments, the radiation-sensitive compound may include a resist, such as a positive resist (i.e., the formed pattern in the positive resist is the same as the pattern on the mask) or a negative resist (i.e., the formed pattern is reverse of the mask pattern). According to some embodiments, the resist may include a photoresist 508.
[0119] According to some embodiments, carrier 504 may be positioned on a vacuum spindle while applying the photoresist. According to some embodiments, carrier 504 may be then rotated (e.g., for about 15 seconds, about 30 seconds, about 60 seconds, and the like), to facilitate obtaining a uniform coating of photoresist 506. According to some embodiments, the coated carrier 504 may optionally undergo a pre-patterning thermal treatment (e.g., baking), to remove solvent from photoresist 508 and / or to enhance adhesion of photoresist 508 to seed layer 506.
[0120] According to some embodiments, at step 502b-4, the semi-additive method may include photoresist illumination and development (pattern transferring). According to some embodiments, step 502b-4 may be performed in a clean room illuminated with a yellow light. According to some embodiments, step 502b-4 may include applying radiation, such as ultraviolet radiation, to transfer the desired pattern to photoresist 508, forming one or more electrically insulating regions 510b (i.e., photoresist pattern 510b).
[0121] According to some embodiments, following completing transferring the pattern, photoresist 508 may be removed from the unpattem portions, thereby exposing the pattern of one or more electrically insulating regions 510 formed on seed layer 506. According to some embodiments, the unpattemed photoresist may be removed by washing, sonicating, etching, and / or rinsing in a solution, plasma oxidation, and the like, or any combination thereof.
[0122] According to some embodiments, a second thermal treatment (e.g., post baking) may be optionally performed after developing the pattern on carrier 504. According to some embodiments, carrier 504 and the developed pattern may be dried in an ambient environment.
[0123] According to some embodiments, at step 502b-5, the semi-additive method may include filling one or more gaps between the electrically insulating material regions 510b with an electrically conducting material, such that one or more electrically conducting regions 510a are formed. According to some embodiments, one or more electrically conducting regions 510a may be formed by electroplating. As a non-limiting example, step 504b-5 may include copper electroplating.
[0124] According to some embodiments, at step 502b-6, the semi-additive method may include removing photoresist pattern 510b. According to some embodiments, photoresist pattern 510b may be removed by wet chemistry techniques. According to some embodiments, AZ 100 remover may be used for removing photoresist pattern 510b. According to some embodiments, AZ 920 remover may be used for removing photoresist pattern 510b. According to some embodiments, 1 -methyl -2 -pyrrolidone (NMP) remover may be used for removing photoresist pattern 510b. According to some embodiments, dimethyl sulfoxide (DMSO) may be used (e.g., by ultrasonic cleaning) for removing photoresist pattern 510b.
[0125] According to some embodiments, at step 502b-7, the semi-additive method may include removing seed layer 506 remnants between one or more electrically conducting regions 510a to prevent horizontal current flow between each of one or more electrically conducting regions 510a through each of the one or more layers of the interconnecting structure, thereby allowing vertical current flow (i.e., between each of the one or more layers of the core less interposer).
[0126] According to some embodiments, the remnants of seed layer 506 may be removed by etching or any other suitable removal technique.
[0127] Reference is made to Fig. 6, which schematically illustrates an example of a method 600 for producing a coreless interposer, according to some embodiments.
[0128] According to some embodiments, at step 602, the method may include forming a seed layer 601 on a carrier 603. According to some embodiments, step 602 may include sputtering one or more metals to obtain seed layer 601.
[0129] According to some embodiments, at step 604, the method may include applying a photoresist 605 onto carrier 603. According to some embodiments, photoresist 605 may be applied by using a spin coater, to facilitate homogeneous coating of photoresist 605. According to some embodiments, coated carrier 603 may optionally undergo soft baking, to remove solvent from photoresist 605 and / or to enhance adhesion to carrier 603.
[0130] According to some embodiments, at step 606, the method may include illumination and development of photoresist 605 (i.e., pattern transfer). According to some embodiments, following completing transferring the pattern, photoresist 605 may be removed from unexposed portions thereof, e.g., by washing, rinsing, and / or using developer solution. According to some embodiments, step 606 may optionally include a post-exposure baking before developing the photoresist pattern 607. According to some embodiments, step 606 may optionally include a hard baking of photoresist pattern 607 to facilitate solidification thereof. According to some embodiments, step 606 may optionally include removing remnants of photoresist 605.
[0131] According to some embodiments, at step 608, the method may include applying electrically conducting material between one or more gaps of photoresist pattern 607. According to some embodiments, the electrically conducting material may be applied by electroplating (e.g., copper electroplating), thereby forming one or more electrically conducting regions 609.
[0132] According to some embodiments, at step 610, the method may include removing photoresist pattern 607, e.g., rinsing, wet and / or dry etching, washing, and the like, or any combination thereof.
[0133] According to some embodiments, at step 612, the method may include removing seed layer 601 remnants between one or more electrically conducting regions 609.
[0134] According to some embodiments, at step 614, the method may include filling one or more gaps between the one or more electrically conducting regions with electrically insulating material 611.
[0135] According to some embodiments, at step 616, the method may include thermally treating, curing and / or polymerizing the electrically insulating material 611 filling the one or more gaps. According to some embodiments, at step 618, the method may include removing excess of the electrically insulating material 611, thereby obtaining a first layer of the one or more layers of the coreless interposer.
[0136] According to some embodiment, each of steps 620, 622, 624, 626, 628, 630, 632, 634, and 636 may be similar or identical to each of steps 602, 604, 606, 608, 610, 612, 614, 616, and 618, thereby obtaining a second layer of the one or more layers of the coreless interposer.
[0137] According to some embodiment, each of steps 638, 640, 642, 644, 646, 648, 650, 652, and 654 may be similar or identical to each of steps 602, 604, 606, 608, 610, 612, 614, 616, and 618, thereby obtaining a third layer of the one or more layers of the coreless interposer.
[0138] Similarly, according to some embodiment, each of steps 656, 658, 660, 662, 664, 666, 668, 670, and 672 may be similar or identical to each of steps 602, 604, 606, 608, 610, 612, 614, 616, and 618, thereby obtaining a fourth layer of the one or more layers of the coreless interposer. It may be understood by skilled in the art that the disclosed method allows manufacturing a coreless interposer having any required number of the one or more layers.
[0139] According to some embodiments, the photoresist pattern 607 of each of the first layer, the second layer, the third layer and the fourth may differ.
[0140] According to some embodiments, at step 674, the method may include removing the carrier from the coreless interposer.
[0141] EXAMPLES
[0142] Example 1
[0143] A coreless interposer 700 have been experimentally prepared by using copper to form the one or more electrically conducting lines, and SU-8 (GLM2060 SU8 by Gersteltec) to form the one or more electrically insulating regions, in accordance with some embodiments. Fig. 7 shows a cross-sectional side view obtained from a high-resolution scanning electron microscope (HR-SEM) using a focused ion beam (FIB) in a dual beam tool of coreless interposer 700 manufactured according to the process disclosed herein, specifically using the herein disclosed semi additive approach.
[0144] As shown in Fig. 7, coreless interposer 700 has four layers. A first layer 710 includes a plurality of electrically conducting lines 710a and a plurality of electrically insulating material regions 710b. As depicted in Fig. 7, each of a second layer 712, a third layer 714 and a fourth layer 716 of one or more layers of coreless interposer 700 includes a plurality of electrically conducting lines 712a, 714a and 716a, and a plurality of electrically insulating material regions 712b, 714b and 716b, respectively.
[0145] As depicted in Fig. 7, the thickness of each of plurality of electrically conducting lines 710a, 712a and 714a is substantially uniform and is about 5 um. The thickness of electrically conducting lines 716a of fourth layer 716 is about 7 um.
[0146] It is appreciated that certain features of the disclosure, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the disclosure, which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable sub-combination or as suitable in any other described embodiment of the disclosure. No feature described in the context of an embodiment is to be considered an essential feature of that embodiment, unless explicitly specified as such.
[0147] Although stages of methods, according to some embodiments, may be described in a specific sequence, the methods of the disclosure may include some or all of the described stages carried out in a different order. In particular, it is to be understood that the order of stages and sub-stages of any of the described methods may be reordered unless the context clearly dictates otherwise, for example, when a latter stage requires as input an output of a former stage or when a latter stage requires a product of a former stage. A method of the disclosure may include a few of the stages described or all of the stages described. No particular stage in a disclosed method is to be considered an essential stage of that method, unless explicitly specified as such. Although the disclosure is described in conjunction with specific embodiments thereof, it is evident that numerous alternatives, modifications, and variations that are apparent to those skilled in the art may exist. Accordingly, the disclosure embraces all such alternatives, modifications, and variations that fall within the scope of the appended claims . It is to be understood that the disclosure is not necessarily limited in its application to the details of construction and the arrangement of the components and / or methods set forth herein. Other embodiments may be practiced, and an embodiment may be carried out in various ways.
[0148] The phraseology and terminology employed herein are for descriptive purpose and should not be regarded as limiting. Citation or identification of any reference in this application shall not be construed as an admission that such reference is available as prior art to the disclosure. Section headings are used herein to ease understanding of the specification and should not be construed as necessarily limiting.
Claims
CLAIMSWhat is claimed is:
1. A method for system in a package manufacturing of an interconnecting structure configured for electrically communicating / coupling one or more integrated circuit package s / semiconductor dies to a circuit board, the method comprising: forming one or more electrically conductive lines; filling one or more gaps between the one or more electrically conductive lines by an electrically insulating material; removing excess of the electrically insulating material, thereby obtaining a first layer of the interconnecting structure; repeating the abovementioned steps to produce additional one or more layers of the interconnecting structure, wherein the additional one or more layers are stacked above the first layer, and thereby enabling on-the-fly formation of vertical electrical connections between the electrically conductive lines / pattems.
2. The method of claim 1, wherein the one or more electrically conductive lines are formed by photolithography.
3. The method of claim 2, wherein the photolithography comprising: forming a seed layer; applying a resist on the seed layer; illuminating and developing the resist; filling one or more gaps between the developed resist with an electrically conducting material; removing the developed resist; and removing remnants of the seed layer, such that one or more electrically conducting lines of the electrically conducting material are formed.
4. The method of claim 1, wherein the one or more electrically conductive lines are formed by selective laser sintering.
5. The method of any one of claims 1-4, wherein removing the excess of the electrically insulating material comprises planarizing using a surface planer tool / machine, thereby forming a substantially flat surface of the first and / or the additional one or more layers of the interconnecting structure.
6. The method of any one of claims 1-5, wherein the excess of the electrically insulating material is removed until a portion of the first and / or the additional one or more layers of the interconnecting structure is exposed.
7. The method of any one of claims 1-6, wherein the method is devoid of drilling steps.
8. The method of claim 7, wherein an aspect ratio of the vertical electrical connections is substantially unlimited.
9. The method of any one of claims 1-8, wherein the method comprises curing and / or baking the electrically insulating material.
10. The method of any one of claims 1-9, wherein filling of the one or more gaps between comprises pouring / spreading the electrically insulating material over the one or more electrically conductive lines and the gaps therebetween.
11. The method of any one of claims 1-10, wherein the electrically insulating material is dielectric.
12. The method of claim 11, wherein the electrically insulating material comprises one or more polymers.
13. The method of any one of claims 1-12, wherein a line / space resolution of the interconnecting conductive lines is at least about 5 / 5 um.
14. The method of any one of claims 1-13, wherein the method comprises forming at least the first layer of the interconnecting structure on a temporary carrier.
15. The method of claim 14, further comprising removing the temporary carrier.
16. The method of any one of claims 1-15, wherein the vertical electrical connections comprise through-chip vertical electrical connections.
17. The method of any one of claims 1-16, wherein the interconnecting structure is configured to allow electrical coupling between conductive pads sized about 100 x 100 um to conductive pads sized about 5 x 5 um or less.
18. A coreless interposer interconnecting structure, the interposer comprising one or more layers, each of the one or more layers comprising: one or more electrically conductive lines configured to allow passing the electrical signals, the one or more electrically conductive lines are arranged in a predefined pattern; an electrically insulating material configured to fill a gap between each of the one or more electrically conductive lines, wherein each of the one or more layers is substantially vertically stacked, thereby enabling on-the-fly formation of vertical electrical connections between the electrically conductive lines.
19. The coreless interposer of claim 18, wherein the predefined pattern of each of the one or more layers is different.
20. The coreless interposer of any one of claims 18-19, wherein the electrically insulating material comprises photo definable epoxy.
21. The coreless interposer of any one of claims 18-20, wherein an aspect ratio of the vertical electrical connections is substantially infinite.