Read-out circuit for reading out electric currents of10na and / or less, use of a read-out circuit, and method for reading out the read-out circuit

Abstract

The invention relates to a read-out circuit (100) for reading out electric currents of 10nA or less, wherein the read-out circuit assembly (100) comprises a capacitive current amplifier (10) and a temporally continuous incremental sigma-delta modulator (20) in the current mode. The invention additionally relates to a use of the read-out circuit and to a method for reading out the read-out circuit.

Description

[0001] Readout circuit for reading electrical currents of 10 nA and / or less and use of a readout circuit and method for reading the readout circuit

[0002] Description

[0003] The present invention relates to a readout circuit for reading electrical currents of 10nA or less and to a use of such a readout circuit and a method for reading such a readout circuit.

[0004] Readout circuits for reading electrical currents are known from the state of the art. For example, the publication by M. Bennati et al., "20.5 A Sub-pA AX Current Amplifier for Single-Molecule Nanosensors," 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009, pp. 348-349, 349a, doi: 10.1109 / ISSCC.2009.4977451, describes a circuit concept that operates on a voltage-controlled AZ converter (delta-sigma converter) with a noise floor of less than 150 fArms at 1 kHz and at room temperature. This circuit concept can be used for reading nanosensors, nanopores. The circuit blocks of the converter in this publication include a charge integrator followed by a CDS circuit that contributes to the reduction of 1 / f noise and offset and also acts as a sample-and-hold (S / H) circuit.The abbreviation CSD stands for "correlated double sampling." The preamplifier integrates the input current for 120 ps and then performs a reset for 8 ps. Therefore, the CDS block has a total sampling time of 128 ps, which limits the bandwidth to approximately 4 kHz. A switch sets the value of the feedback capacitor to operate with two different full-scale ranges: ±200 pA and ±5 nA. After the integrator output is sampled by the CDS block, the sampled value is subtracted at the end of the integration time. In summary, the input signal is integrated, then differentiated and sampled, producing a voltage output proportional to the input current. This publication discloses a separation between an analog front-end device (AFE) and a voltage-to-digital converter.The AFE converts the current input into a voltage using correlated double sampling (CDS). The voltage is then converted into a digital output by a voltage sigma-delta modulator. WO 2010 / 122293 A1 discloses a device for detecting an interaction of a molecular entity with a membrane protein in a lipid bilayer. The device comprises an array of sensor elements arranged to output an electrical signal dependent on the occurrence of the interaction. Furthermore, the device comprises a detection circuit with detection channels capable of amplifying an electrical signal from a sensor element. More sensor elements than detection channels are provided, and detection channels are selectively connected to sensor elements that have an acceptable performance quality in terms of forming a lipid bilayer and ensuring that an acceptable number of membranes are present.

[0005] When measuring very small currents in the pA range, as is often the case with nanopores and nanosensors, current measurement becomes challenging because the outputs consist of signals in the pA range or less, in the kHz range. Measuring these values ​​typically requires very low-noise front-end amplifiers.

[0006] For example, the integrator's output noise is typically sampled twice, so it doubles in correlated double sampling (CDS). Typically, a SH circuit design is required. The non-ideality of the SH circuit degrades signal quality and therefore requires careful design.

[0007] An object of the present invention is therefore to provide an improved readout circuit for reading electrical currents of 10 nA or less, in particular, extremely small electrical currents in the range of a few pA. A further object is to provide a readout circuit for reading electrical currents of 10 nA or less, in particular, extremely small electrical currents in the range of a few pA, which enables direct digitization of, in particular, extremely small electrical currents, i.e., of detected signals, without a significant increase in area or power consumption.

[0008] This object is achieved by a readout circuit according to claim 1, a use of the readout circuit according to claim 24, and a method according to claim 25. According to the proposal, the readout circuit for reading electrical currents of 10 nA and / or less comprises a capacitive current amplifier and a temporally continuous incremental sigma-delta modulator in current mode. With the proposed readout circuit, even the smallest currents in the pA range (pico-amperes) can be read out and further processed. In particular, these smallest currents in the pA range can be directly digitized. The proposed readout circuit does not require a CDS circuit.With the proposed readout circuit, the capacitive current amplifier and the continuous-time incremental sigma-delta modulator can be reset in current mode sequentially and separately from each other in such a way that background noise is not digitized with the actual signal and therefore not output as a digital signal. This background noise is caused by the resetting of the capacitive current amplifier. Since the resetting of the capacitive current amplifier occurs independently of the resetting of the continuous-time incremental sigma-delta modulator, the background noise, which is charge noise and constitutes a major part of the noise, is eliminated or even not converted into a digital signal.Other noise sources that are still digitized with the proposed circuit do not have a dominant noise component and are therefore negligible. The proposed readout circuit can also be used for larger electrical currents in the nA range. What is special about the proposed readout circuit, however, is its use for detecting electrical currents in the pA range. One advantage of the proposed circuit is, for example, that by eliminating one noise source (the main smoke source), smaller currents can be measured, making the proposed circuit suitable for detecting smaller and very small currents. For large currents, the proposed circuit allows for higher resolution or a larger background noise budget by using other components in the overall circuit.

[0009] A further aspect of the present invention relates to the use of a readout circuit according to the invention in a nanopore readout circuit, a digital X-ray image sensor readout circuit, a gas sensor readout circuit, or a readout circuit for electrochemical sensors. The readout circuit according to the invention can be used in many different sensor circuits to convert small or extremely small electrical currents detected by the sensors into a digital signal, so that the converted digital signal can be used for further evaluation. A further aspect of the present invention relates to methods for reading a readout circuit that detects electrical currents of 10 nA and / or less, wherein the readout circuit arrangement comprises a capacitive current amplifier and a temporally continuous incremental sigma-delta modulator in current mode.The method first comprises amplifying an input current Im , which is on the order of 10 nA or less, by an amplified current l . out The method then comprises converting the amplified current l ou t into a digital value Dout. The digital value can then be used for further evaluation. The input current is based on a current detected by a sensor. The sensor is therefore arranged upstream of a readout circuit according to the invention. In other words, the readout circuit is coupled to a sensor that measures, i.e., detects, the input current. The input current is finally converted by the readout circuit into the digital value, which can be used for further evaluation.

[0010] The technical teaching described herein enables the widely researched continuous-time incremental sigma-delta analog-to-digital converter to be used for measuring currents from 1 pA to 10 nA. In particular, a CDS (correlated double sampling) circuit is not required. The proposed readout circuit and the corresponding method are thus simplified and simultaneously improved, as the readout circuit itself is simplified. The technical teaching described herein offers an alternative to the widely used correlated double sampling circuit in charge integrators for measuring input current ranges from 1 pA to 10 nA.

[0011] It is understood that individual aspects described with reference to the readout circuit can also be implemented as a method step, and vice versa. Further details are discussed in the following figure description.

[0012] Preferred embodiments of the present invention are explained in detail below with reference to the accompanying drawings. They show:

[0013] Fig. 1 shows a readout circuit according to the invention;

[0014] Fig. 2 shows a readout circuit known from the prior art; Fig. 3 shows the readout circuit according to the invention according to Fig. 1 with more details;

[0015] Fig. 4 is a schematic representation of the operation of the readout circuit according to the invention;

[0016] Fig. 5 is a schematic representation of the signals of a readout of the readout circuit according to the invention;

[0017] Fig. 6. a representation of a simulation result of the power spectral density (PSD) and in-band noise (IBN) versus frequency using a time-continuous incremental second-order sigma-delta modulator;

[0018] Fig. 7 is a schematic representation of a use of the readout circuit according to the invention in detecting the electrical currents in a nanopore; and

[0019] Fig. 8 shows schematically the course of the method according to the invention for reading the readout circuit according to the invention.

[0020] Individual aspects of the invention described herein are described below in Figs. 1 and 3 to 8. In the present application, identical reference numerals refer to identical or equivalent elements, although not all reference numerals need to be shown again in all drawings if they are repeated. Fig. 2 shows a readout circuit known from the prior art to enable a direct comparison with the readout circuit according to the invention from Fig. 1.

[0021] Fig. 1 shows a readout circuit 100 according to the invention. The readout circuit 100 according to the invention for reading electrical currents of 10 nA and / or less comprises a capacitive current amplifier 10 and a temporally continuous incremental sigma-delta modulator 20 in current mode. In the present case, current mode refers to current operation of the temporally continuous incremental sigma-delta modulator 20. As indicated in Fig. 1, both the capacitive current amplifier 10 and the temporally continuous incremental sigma-delta modulator 20 can be reset. Resetting the capacitive current amplifier 10 is indicated by the symbol Rst-camp, where camp stands for capacitive amplifier and rst for reset.A reset of the temporally continuous incremental sigma-delta modulator 20 is indicated by the symbol Rsticw, where ICM is a well-known abbreviation for incremental delta-sigma modulator. A readout circuit 100 according to the invention for reading electrical currents of 10 nA or less is suitable for reading very small currents of only a few pA. The term "very small currents" here refers to electrical currents of a few pA (pico amperes). As can be seen in Fig. 1, the readout circuit 100 is coupled to a sensor 30. Here, the term "coupled" encompasses being connected via a cable. As shown in Fig. 1, the sensor 30 can be suitable for reading nanopores, or the sensor 30 is provided by the nanopore. In other words, the nanopore is the sensor 30. The nanopore can be used to detect specific molecules. For example, the sensor 30 has, in addition to an input capacitance Cin, a resistance Rp.Ore Furthermore, the nanopore can be described as a pore resistance Rp Ore and a capacitance Cin. The sensor 30 is not part of the readout circuit 100, which is why the sensor 30 is shown with dashed lines. It can also be seen from Fig. 1 that the capacitive current amplifier 10 of the readout circuit 100 receives an input current Im, the input current l in amplified and as amplified current l ou t to the temporally continuous incremental sigma-delta modulator 20. The temporally continuous incremental sigma-delta modulator 20 thus receives the amplified current l ou t and converts the amplified current l ou t into a digital value D ou t, which is used for further processing.

[0022] In this case, the capacitive current amplifier represents a preamplifier 10 or an AFE device (AFE for Analog Front End). Furthermore, the temporally continuous incremental sigma-delta modulator 20 represents an analog-to-digital converter.

[0023] Fig. 2 shows a readout circuit 100' known from the prior art, which comprises an integrator 10', a CDS stage 40' (CDS for correlated double sampling), an SH stage 50 (SH for sample and hold), and an analog-to-digital converter (ADC). According to the readout circuit 100' of Fig. 2, known from the prior art, the detected current l is output. in as a digital value.

[0024] Fig. 3 shows the readout circuit 100 according to the invention according to Fig. 1 in more detail. From Fig. 3 it can be seen that the capacitive amplifier 10 comprises a first capacitor Ci in addition to an operational amplifier OPi. A first switch Si(RstCamp) is arranged in parallel with the first capacitor Ci and the operational amplifier OPi. When the first switch Si(RstCamp) is closed, the capacitive amplifier 10 is reset. When the first switch Si(RstC am p) the recorded electrical input currents l are collected or integrated in .

[0025] Preferably, and as can be seen in Fig. 3, the current amplifier 10 is designed to receive an input current l in to amplify to produce an amplified current l outat an output of the capacitive current amplifier 10, and wherein the temporally continuous incremental sigma-delta modulator 20 is designed to receive the amplified current lout and to convert it into a digital value D out Description: The digital value Dout is output at an output of the time-continuous incremental sigma-delta modulator 20 to convert the digital value D out to be further processed or evaluated. Dout corresponds to a digital current value, which in turn corresponds to an averaged current value of a sampling interval.

[0026] The term "trained" is to be understood as "configured to do something." In this case, the terms "trained" or "configured" describe features that are not only suitable for performing the relevant steps / functions, but rather have been specifically designed for that purpose.

[0027] Preferably, and as can be seen in Fig. 3, the capacitive current amplifier 10 is designed to, upon receiving a first reset signal RST ca m P To initialize a reset of the capacitive current amplifier, the first switch Si(Rstc am p) is closed. During the current amplifier reset, the first switch Si(Rstc amp ) is therefore in the closed state. In the closed state of the first switch Si(Rstc amp ) a feedback capacitance Ci can be reset by discharging the feedback capacitance Ci.

[0028] Preferably, and as can be seen in Fig. 3, the temporally continuous incremental sigma-delta modulator 20 is configured to perform a modulator reset upon receiving a second reset signal RSTicM. The temporally continuous incremental sigma-delta modulator 20 has a second switch S2(Rsticw). To initiate a reset of the temporally continuous incremental sigma-delta modulator 20, the second switch S2(Rsticw) is closed. During the modulator reset, the second switch S2(Rsticw) is therefore in the closed state. When the second switch S2(Rsticw) is closed, the further capacitor C3 of the temporally continuous incremental sigma-delta modulator 20 can be reset by discharging the further capacitor C3.

[0029] A first pulse duration 12 of the first reset signal RST ca m Pand a second pulse duration 22 of the second reset signal RSTICM are temporally superimposed such that the first and second pulse durations 12, 22 start / begin at the same time at the beginning of the reset of the ICM. This can be seen, for example, in Fig. 4. Preferably, a first period duration of the capacitive amplifier 10 corresponds to a second period duration v of the temporally continuous incremental sigma-delta modulator 20. In other words, the period durations of the two reset signals RST ca m P and RSTICM are the same. However, the first and second pulse durations 12 and 22 of the two reset signals RST camp and RSTIC are different. In Fig. 4, the pulse duration of the first reset signal RST- cam P with TRST.CAMP and the pulse duration of the second reset signal RSTICM is designated with TRST.ICM. Both the reset signal RST camp as well as the reset signal RSTICM have a single period of TRST cM+T COn conversion, where conversion indicates a period, which specifies a conversion period (conversion period Tconversion or Tumwandiung) for digitizing the signal (conversion for conversion). In Fig. 4, the period T appears RS T,ICM to be twice as long as T RS T, CAMP, which may be but is not necessarily the case. Fig. 4 is not to scale. For example, the pulse duration T RS T,CAMP of the capacitive amplifier 19 is one microsecond and the pulse duration T RS T,ICM of the incremental sigma-delta modulator 20 can be two microseconds. The conversion time period Tconversion can be, for example, 8 microseconds. This would then result in a total period of 10 microseconds and thus a sampling rate of 100 kHz.

[0030] Fig. 4 shows a schematic representation of the operation of the readout circuit 100 according to the invention in the case of a coupling with the sensor 30. Signal amplitudes are plotted against time in Fig. 4. The reset signals RST camp and RSTICM are both digital signals. Their voltage levels are therefore either low or high. The low and high voltage values ​​depend on the digital supply voltages used. Overall, no units are required here because these are digital signals. High / High means true, and Low / Low means false, which is understandable to a person skilled in the art and therefore will not be explained further.

[0031] Preferably, the current amplifier 10 comprises an output capacitance C2 and at least one feedback capacitance Ci, wherein the amplified current l out is M times the input current Ln, where M is a ratio between the output capacitance C2 and the at least one feedback capacitance Ci. For example, the ratio is M=10 or M=9 or M=1 1 .

[0032] Preferably, the current amplifier 10 comprises at least one operational amplifier OP1, wherein the current amplifier 10 is designed to supply the input current l in to amplify by the current amplifier 10 being designed to amplify the input current l in via the at least one feedback capacitance Ci using the at least one operational amplifier OP1. See Fig. 3. The first switch Si(Rstc am p) of the current amplifier 10 is then in an open state, ie the first switch Si(Rst- Camp) is open during the integration of the at least one operational amplifier OP1. An output voltage V out,opi of at least one operational amplifier OP1 represents the integration of the input current. The output voltage V out The opi of at least one operational amplifier OP1 is also formed by the capacitance value of the output capacitance C2, which differentiates the voltage. Differentiating the voltage is understood as follows: The current flowing through a capacitance is equal to C*dv / dt! Where C is the value of the capacitance and v is the voltage difference across the capacitance! Dv / dt means the derivative of the voltage across the capacitance as a function of time. This is why it is also called voltage differentiation. The result is the output current l ou t be M times the input current, where M is the ratio between C2 and Ci.

[0033] Preferably, the readout circuit 100 is or can be coupled to a sensor 30, wherein the capacitive current amplifier 10 is configured to regulate a voltage detected by the sensor 30 in the case of coupling, in particular to reset it to a command voltage Vbias. The sensor 30 is not necessarily part of the readout circuit 100. Since the sensor 30 can be, for example, a nanopore or a gas sensor or another sensor, the sensor 30 is shown only with dashed lines in Fig. 1. As can be seen, for example, in Fig. 3, the sensor, in the case of coupling to the readout circuit 100, is connected to an input of the operational amplifier OP1 of the amplifier 10. Connection can be made via a cable or as a direct metal connection on a circuit board. The capacitive current amplifier 10 thus regulates the voltage across the sensor 30 and brings it to the command voltage V bias back.

[0034] Preferably, the current amplifier 10 comprises the first switch Si(Rstc am p), which is arranged in parallel with the feedback capacitance Ci, wherein a resetting of the capacitive current amplifier 10 is effected by closing the first switch Si(Rstc amp ) using the first reset signal RST camp , which has a first pulse width T RS T, camp. This is shown schematically in Fig. 4, for example. Here, the first pulse width TRST, camp is plotted against time. By closing the first switch Si(Rstc amp ) the at least one operational amplifier OPi brings the voltage across the feedback capacitance Ci and thus across the output capacitance C2 back to the command voltage Vbi a s.ln a summary of Figs. 3 to 5, this can be seen from the figures of the application.

[0035] Preferably, the temporally continuous incremental sigma-delta modulator 20 comprises at least one loop filter 21, a quantizer 24 and a digital filter 23, as can be seen, for example, in Fig. 3. The loop filter 21 comprises at least one second feedback capacitor C3, at least one loop filter switch S2(RSTI C M), a first feedback switch SFBI, a second feedback switch SFB2 and at least one integrator INTICM, wherein the loop filter 21, in particular with the components just mentioned, is designed to amplified current l out to receive and process. The at least one loop filter switch S2(RSTI C M) corresponds to the aforementioned second switch S2(RSTICM). The at least one loop filter switch S2(RSTICM) serves, when closed, to reset the temporally continuous incremental sigma-delta modulator 20.

[0036] Preferably, the loop filter 21 has a loop filter output, and the loop filter 21 is configured to provide an output voltage VHS at the loop filter output. The loop filter output is coupled to the quantizer 24 to sample the output voltage VHS at each clock edge of a clock signal CLK. Fig. 3 shows the coupling between the quantizer 24 and the loop filter 21, or between the quantizer 24 and the digital filter 23.

[0037] Preferably, the quantizer 24 has a quantizer output, and the quantizer 24 is configured to generate a feedback current I F B P, IFBPI to the loop filter 21 as a function of the output voltage VHS, in particular to feed it back, in order to regulate the output voltage VHS within a specific range. The specific range preferably corresponds to a supply voltage range, i.e., a range in which the supply voltage of the readout circuit 100 is located. The quantizer 24 is further configured to provide the amplified current lout, which corresponds to a digital bit stream, at the quantizer output.

[0038] Preferably, the digital filter 23 is coupled to the quantizer output and is designed to receive and filter the digital bit stream, wherein the digital filter 23 is designed to generate a digital value D after a conversion period has elapsed. ou t, which is associated with the digital bitstream. This can be seen in Fig. 3.

[0039] Preferably, the loop filter 21 comprises a switchable feedback current and one or more integrators, depending on the order of the temporally continuous incremental sigma-delta modulator 20. For example, only one integrator INTICM is shown in Fig. 3. The bit stream received by the quantizer 24 corresponds to the amplified current l ou t after passing through the loop filter 21. In other words, the amplified current l out at the output of the capacitive amplifier 10 is processed by the loop filter 21. The output voltage VHS of the loop filter 21 is sampled by the quantizer 24 at each clock edge of the clock signal CLK. The output of the quantizer 24 activates one of the feedback currents I FB P or l FBn as a function of the output voltage VHS- This regulates the output voltage VHS within a certain range and the output bit stream of the quantizer 24 represents the current lout. The bit stream is filtered by the digital filter 23 and at the end of the conversion time a digital output value D out generated.

[0040] Preferably, the resetting of the temporally continuous incremental sigma-delta modulator 20 is controllable by the second reset signal RSTICM, which has a second pulse width T RS T,ICM, as can be seen in Fig. 4. Resetting the temporally continuous incremental sigma-delta modulator 20 includes resetting all integrators of the loop filter 21 and resetting the digital filter 23 and stopping the feedback currents l F Bn, P by opening the corresponding switch S F B2, S F BI . The switches S F B2, SF BI are required for proper operation of the time-continuous incremental sigma-delta modulator 20.

[0041] The capacitive current amplifier 10 is designed to separate the noisy virtual ground of the first integrator INTICM of the incremental sigma-delta 20 from the sensitive input current l in The capacitive current amplifier 10 also reduces the noise requirements of the first integrator INTICM as well as the first feedback current IFB of the continuous-time incremental sigma-delta modulator 20. Furthermore, the capacitive current amplifier 10 is configured to provide the required bias voltage for the sensor 30.

[0042] Preferably, the first reset signal RST ca m Pof the current amplifier 10 and the second reset signal RSTICM of the temporally continuous incremental sigma-delta modulator 20 each have the same frequency, wherein the frequency defines a Nyquist sampling rate, in particular the first pulse duration 12 of the first reset signal RST ca m P and the second pulse duration 22 of the second reset signal RSTICM is temporally superimposed such that the pulse durations 12, 22 start at the same time, as can be seen, for example, in Fig. 4 and has already been described in more detail above, to which reference is made here. The term Nyquist sampling rate is a familiar term to a person skilled in the art and requires no further explanation.

[0043] Preferably, the readout circuit 100 is configured to execute the modulator reset after the current amplifier reset, in particular to execute the modulator reset after the current amplifier reset with a certain delay, wherein the certain delay is based on a settling time of an integrator 11 of the at least one operational amplifier OPi. In Fig. 4, the certain delay is not shown due to the limited representation options. The certain delay is calculated based on the settling time of the integrator 11 of the capacitive amplifier 10, wherein the certain delay is a function of the bandwidth BWINT of the at least one integrator 11 of the capacitive amplifier 10. The certain delay time is proportional to

[0044] Delay time = 5 / BWINT , where BWINT is the bandwidth of the integrator 11 of the capacitive amplifier 10, ie, the operational amplifier OPi, in rad / s. The time-continuous incremental sigma-delta modulator 20 converts the amplified current l ou t into a bit stream, whereby this amplified current does not depend on the initial voltage value at the feedback capacitance Ci or the output capacitance C2.

[0045] Preferably, the readout circuit 100, when coupled to the sensor 30, is designed to detect charge noise at a sensor input capacitance Cm of the sensor 30 when performing the current amplifier reset. In other words, the charge noise at the sensor input capacitance Cin of the sensor 30 is detected during the current amplifier reset RST CAMp of the current amplifier integrator is detected, ie while the switch SI (RSTCAMP) is switched on, i.e. closed. The switch SI (RSTCAMP) can be defined as a resistor R on When SI (RSTCAMP) is closed, the operational amplifier OPi now operates as a transimpedance amplifier with a feedback resistance of R on of SI (RSTCAMP) . A virtual ground of the operational amplifier OPi, ie the negative input, is noisy, and the noise depends on the noise of the resistor R onof the switch SI (RSTCAMP) and the voltage noise of the operational amplifier OPi. When the switch SI (RSTCAMP) is opened, the instantaneous noise amplitude at the negative input of the operational amplifier OPi is sampled at the capacitance Cin (see Fig. 3). In the present case, the term sensor 30 refers to a device for detecting a physical parameter. A physical parameter can be, for example, an electric current, a magnetic field, a voltage, or a mechanical or electrochemical force. After the amplifier reset of the integrator 11 of the capacitive current amplifier 10 is triggered, charge noise is detected or sampled at the input capacitance Cin. The charge noise is caused by the thermal noise of the on-resistance of the first switch Si(RST ca m P) and the input-referred voltage noise of the operational amplifier OPi. This charge noise also depends on the total input capacitance Cin.

[0046] Preferably, the readout circuit 100 is configured to first accumulate the charge noise on the input capacitance Cin and then integrate it via the feedback capacitance C1. The integration occurs after the settling time of the integrator 11 of the capacitive current amplifier 10 has elapsed. The settling time corresponds to the certain delay time and can therefore be calculated by delay time = 5 / BWINT.

[0047] Preferably, the readout circuit 100 is configured to integrate the charge noise via the feedback capacitance C1 during the modulator reset of the temporally continuous incremental sigma-delta modulator 20. As a result, a digital value 42 can finally be obtained for the charge noise, which is independent of the actual measured signal, as shown in Fig. 3. However, the digital value 42 of the charge noise is not included in the digital value 44 of the actual measured signal. In other words: an amplified charge noise is also stored in the output capacitance C2, but since the temporally continuous incremental sigma-delta modulator 20 is in the reset state during the integration of the charge noise, this charge noise is not included in the digital bit stream and thus in the digital value D outat the output of the digital filter 23. This is because the charge noise was not integrated via the feedback capacitance Cs of the first integrator INTICMJ of the temporally continuous incremental sigma-delta modulator 20.

[0048] Preferably, an effect of the charge noise of the at least one integrator INTICM of the temporally continuous incremental sigma-delta modulator 20 on the digital value D out due to the upstream capacitive current amplifier 10, is reduced to a negligible value. The charge noise that has accumulated on the total capacitance of the first integrator INTICM of the temporally continuous incremental sigma-delta modulator 20 is at the digital final value D out involved, but its effect is reduced to a negligible value when referenced back to the input due to the current amplifier.

[0049] Preferably, the readout circuit 100 is designed to separate the at least one integrator IntICM, 1 of the temporally continuous incremental sigma-delta modulator 20 from the sensor input capacitance Ci nto separate, whereby a bandwidth of the at least one integrator InticMj is capacitance-independent. A bandwidth of the readout circuit can be 100 kHz. In other words: The capacitive current amplifier 10 separates the first integrator INTIC J of the temporally continuous incremental sigma-delta modulator 20 from the sensor capacitance Cm, i.e., from the input capacitance Cm of the sensor 30 in the case of a coupling with the sensor 30. The sensor capacitance Cm can be large or can vary from one sensor to another. The sensor capacitance Cm is large in this case if it comprises up to 10 pF. As a result, the bandwidth of the first integrator of the sigma-delta INTICMJ is not affected by this changing capacitance, which is important for the stability of the modulator. A large input capacitance Cm reduces the bandwidth of the integrator 11 and thus the bandwidth of the current amplifier 10.This results in the integrator 11 needing more time to settle after the switch S1 is reset, which means that a larger pulse width of the reset signal RST. C amp is required. However, stability remains unaffected.

[0050] Preferably, a corner frequency of the readout circuit 100 corresponds to a reset frequency at which the current amplifier reset and the modulator reset occur, respectively. The overall bandwidth of the readout circuit 100 depends primarily on the signal transfer function of the digital filter 23, which depends on the structure of the temporally continuous incremental sigma-delta modulator 20 used. In all cases, however, the corner frequency is at the reset frequency. This means that an analog anti-aliasing filter is not required in this case. However, this anti-aliasing filter could be implemented by the capacitive current amplifier by tuning the bias current or by tuning the compensation capacitance of the operational amplifier OPi to change its transfer function.

[0051] Fig. 5 shows a schematic representation of the signals from a readout of the inventive readout circuit 100 during operation of the readout circuit 100. Voltage signals are shown as a time profile during operation of the readout circuit. The first feedback switch SFBI and the second feedback switch SFB2 are open during a reset of the capacitive amplifier 10 and a reset of the temporally continuous incremental sigma-delta modulator 20.

[0052] Upon receipt of a reset signal RST ca m P First, the switches Si(RST ca m P ) and S2(RSTI CM). Fig. 6 shows that an in-band noise (IBN) of almost 700 fARMs was achieved with an example implementation of the proposed readout circuit 100 using a second-order incremental sigma-delta modulator 20 running at a clock frequency of 20 MHz and a reset frequency of 100 kHz, corresponding to a total bandwidth of 50 kHz. The power spectral density PSD was calculated by first comparing the bit stream between two reset signals RST camp and RSTICM with a digital filter in the form of a cascade of digital integrators. In this case, this means that the bit stream is filtered between two reset signals RSTICM or between two reset signals RST campwas filtered with a digital filter in the form of a cascade of digital integrators. The power spectral density (PSD) is then calculated for the current values ​​resulting from the digital filter, and the noise was integrated over the 50 kHz bandwidth.

[0053] A further aspect of the present invention relates to the use of a readout circuit 100, as just described, in a nanopore readout circuit or in a digital X-ray image sensor readout circuit or in a gas sensor readout circuit or in a readout circuit for electrochemical sensors. Fig. 7, for example, shows a schematic representation of a use of the readout circuit 100 according to the invention in detecting the electrical currents in a nanopore 80. As shown in Fig. 7, a DNA strand 82 of a DNA molecule is guided through a nanopore 80 (DNA for deoxyribonucleic acid), whereby an electrical current in the pA range is generated, which is detected with the aid of the readout circuit 100 and finally digitized. The nanopore 80 as such is arranged in a double lipid membrane 84. The digital bit stream, which is in the form of the digital value D ouThe signal t finally output by the readout circuit 100 can be further processed or evaluated by an artificial intelligence K1. Of course, other suitable devices can also be used for further evaluation instead of a K1.

[0054] A further aspect of the present invention relates to a method for reading a readout circuit 100 that detects electrical currents of 10 nA and / or less. Such a method 800 is shown in Fig. 8. To carry out the method, a readout circuit 100 described herein is used. The readout circuit 100 comprises a capacitive current amplifier 10 and a temporally continuous incremental sigma-delta modulator 20 in current mode. In a step 810, the method comprises amplifying an input current 100, which is on the order of 10 nA or less, to generate an amplified current l outThis amplified input current is used to convert the amplified current lout into a digital value D in a step 820. out . To execute. This digital value D out can be further processed, for example by a Kl, as shown in Fig. 7.

[0055] Preferably, the method 800 comprises resetting the capacitive current amplifier 10 upon receiving a first reset signal RST ca m P, and resetting the temporally continuous incremental sigma-delta modulator 20 upon receiving a second reset signal RSTICM, wherein the resetting of the temporally continuous incremental sigma-delta modulator 20 is carried out after the resetting of the capacitive current amplifier 10. The delay time already described above can lie between the resetting of the capacitive current amplifier 10 and the resetting of the temporally continuous incremental sigma-delta modulator 20. Reference is hereby made to the above description.

[0056] Preferably, the method 800 comprises sampling an output voltage VHS at each clock edge of a clock signal CLK to regulate the output voltage VHS within a certain range; and / or receiving and filtering the amplified current lout and converting the filtered, amplified current l ou t after a conversion period into the digital value Dout . Furthermore, the method 900 preferably comprises regulating a detected voltage, in particular to a command voltage V bias , in the case of coupling with a sensor 30. Further preferably, in the case of coupling with the sensor 30, the method 900 comprises sampling charge noise at a sensor input capacitance Cin of the sensor 30 when performing the current amplifier reset; and / or first accumulating the charge noise on an input capacitance Cin of the sensor 30 and then integrating the charge noise across a feedback capacitance C1 of the capacitive current amplifier 10; and / or integrating the charge noise across the feedback capacitance C1 during the modulator reset of the temporally continuous incremental sigma-delta modulator 20.

[0057] The table (see below) summarizes a comparison of the present readout circuit 100 with the known state of the art by M. Bennati et al., "20.5 A Sub-pA X Current Amplifier for Single-Molecule Nanosensors," 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009, pp. 348-349, 349a, doi: 10. 1109 / ISSCC.2009.4977451.

[0058] A person skilled in the art understands that the device features described above can also be understood as method steps. A detailed repetition of the above description is omitted within the framework of the proposed method 900 in order to avoid redundancies. Advantages of the present technical teaching are furthermore as follows: The bit stream at the output of the quantizer 24 of the temporally continuous incremental sigma-delta modulator 20 represents the segment of the input current signal between two resets (cf. Figs. 3 and 4). This is more information-rich compared to a time-limited current sampling with correlated double sampling (CDS). In addition, the bit stream has a bandwidth equal to the clock frequency divided by two. This means that rapid current changes within the conversion time affect the bit stream. These rapid changes can, for example,represent characteristic molecular movements in DNA sequencing with nanopores that would otherwise not be captured by correlated double sampling. For example, when used as a nanopore readout circuit, an improvement in sequencing accuracy is expected when using the bit stream as the information source instead of discrete current samples, as generated by correlated double sampling.

[0059] Further advantages are:

[0060] The separation of the reset of the capacitive current amplifier 10 and the time-continuous incremental sigma-delta modulator 20 eliminates the KTC charge noise and other offset charges from the switch Si(RST ca m P ) such as charge injection and clock feed-through. The amplification reduces the noise requirements on the current sources. F Bn and IFB Pand also the noise requirements for the first integrator of the time-continuous incremental sigma-delta modulator 20

[0061] The capacitive amplifier 10 separates the sensor capacitance C from the at least one integrator INT I C MI of the temporally continuous incremental sigma-delta modulator 20, so that the bandwidth (GBW) of the at least one integrator INT icMi is constant.

[0062] No additional filter is required to prevent aliasing effects (anti-aliasing). Filtering is performed by the digital filter 23, ie GBW from the at least one integrator INT I C MI can be large to reduce the required reset time of the capacitive amplifier 10 and thus reduce the information loss.

[0063] A direct current-to-digital conversion takes place.

[0064] Easy scaling by adjusting capacities and power sources l F Bn and IFBP is possible, multiplexing is possible and the input channel can be switched on during the reset of the time-continuous incremental sigma-delta modulator 20 to avoid errors.

[0065] - -Manufacturing costs, the required space on a chip area and the power consumption or power consumption are reduced

[0066] The bitstream is richer in information! It's possible to perform no filtering at all and feed the bitstream directly into a KL.

[0067] The quantization noise, also called Q-noise, can always be set lower than the thermal noise so that the resolution is maintained.

[0068] Although some aspects have been described in connection with a device or system, it is understood that these aspects also represent a description of a corresponding method, so that a block or component of a device or system can also be understood as a corresponding method step or as a feature of a method step. For reasons of redundancy, a representation of the present invention in the form of method steps is omitted here.

[0069] In the foregoing Detailed Description, various features have been grouped together in examples in order to streamline the disclosure. This manner of disclosure should not be interpreted as intending that the claimed examples include more features than are expressly recited in each claim. Rather, as the following claims reflect, the subject matter may lie in fewer than all of the features of a single disclosed example. Accordingly, the following claims are hereby incorporated into the Detailed Description, with each claim being capable of standing as its own separate example.While each claim may stand as its own separate example, it should be noted that although dependent claims in the claims refer to a specific combination with one or more other claims, other examples also include a combination of dependent claims with the subject matter of any other dependent claim or a combination of any feature with other dependent or independent claims. Such combinations are intended to be encompassed unless it is stated that a specific combination is not intended. Furthermore, it is intended to encompass a combination of features of a claim with any other independent claim, even if that claim is not directly dependent on the independent claim.

Claims

Patent claims 1. Readout circuit (100) for reading out electrical currents of 10nA and / or less, wherein the readout circuit arrangement (100) comprises a capacitive current amplifier (10) and a temporally continuous incremental sigma-delta modulator (20) in current mode.

2. Readout circuit (100) according to claim 1, wherein the current amplifier (10) is designed to generate an input current l in to provide an amplified current lout at an output of the capacitive current amplifier (10), and wherein the temporally continuous incremental sigma-delta modulator (20) is designed to provide the amplified current l ou t and convert it into a digital value Dout.

3. Readout circuit (100) according to one of claims 1 or 2, wherein the capacitive current amplifier (10) is designed to perform a current amplifier reset upon receiving a first reset signal RSTcamp.

4. Readout circuit (100) according to one of claims 1 to 3, wherein the temporally continuous incremental sigma-delta modulator (20) is designed to perform a modulator reset upon receiving a second reset signal RSTicw.

5. Readout circuit (100) according to one of claims 1 to 4, wherein the current amplifier (10) comprises an output capacitance C2 and at least one feedback capacitance Ci, wherein the amplified current l ou t is M times the input current Im, where M is a ratio between the output capacitance C2 and the at least one feedback capacitance Ci.

6. Readout circuit (100) according to claim 5, wherein the current amplifier (10) comprises at least one operational amplifier OP1, wherein the current amplifier (10) is designed to adjust the input current l in to amplify, in that the current amplifier (10) is designed to adjust the input current l in via the at least one feedback capacitance Ci with the aid of the at least one operational amplifier OP1.

7. Readout circuit (100) according to one of claims 1 to 6, wherein the readout circuit (100) is or can be coupled to a sensor (30), wherein the capacitive current amplifier (10) is designed to regulate a voltage detected by the sensor (30) in the case of a coupling, in particular to reset it to a command voltage Vbias.

8. Readout circuit (100) according to one of claims 1 to 7, wherein the current amplifier (10) comprises a switch Si arranged in parallel with the feedback capacitance Ci, wherein a resetting of the capacitive current amplifier (10) is effected by closing the switch Si using the first reset signal RST C amp, which has a first pulse width T RS T, camp identifies, is carried out.

9. Readout circuit (100) according to one of claims 1 to 8, wherein the temporally continuous incremental sigma-delta modulator (20) comprises at least one loop filter (21), a quantizer (24) and a digital filter (23).

10. Readout circuit according to claim 9, wherein the loop filter (21) comprises at least one feedback capacitance C3, at least one loop filter switch S2, a first feedback switch SFB1, a second feedback switch SFB2 and at least one integrator INTICM.I, wherein the loop filter (21) is designed to amplified current l out to receive and process.

11. Readout circuit (100) according to one of claims 9 or 10, wherein the loop filter (21) has a loop filter output and the loop filter (21) is configured to provide an output voltage VHS at the loop filter output, wherein the loop filter output is coupled to the quantizer (24) to sample the output voltage VHS at each clock edge of a clock signal CLK.

12. Readout circuit (100) according to one of claims 9 to 11, wherein the quantizer (24) has a quantizer output, and the quantizer (24) is designed to generate a feedback current (IFB P , IFBH) depending on the output voltage VHS to the loop filter, in particular to feed it back in order to regulate the output voltage VHS within a certain range.

13. Readout circuit (100) according to claim 12, wherein the quantizer (24) is designed to provide the amplified current l at the quantizer output. ou t, which corresponds to a digital bitstream.

14. Readout circuit (100) according to one of claims 9 to 13, wherein the digital filter (23) is coupled to the quantizer output and is designed to receive and filter the digital bit stream, wherein the digital filter (23) is designed to output a digital value D after expiration of a conversion period out to spend.

15. Readout circuit (100) according to one of claims 4 to 14, wherein the resetting of the temporally continuous incremental sigma-delta modulator (20) is controllable by the second reset signal RSTICM, which has a second pulse width T RS T,ICM.

16. Readout circuit (100) according to one of claims 4 to 15, wherein the first reset signal RST ca m P of the current amplifier (10) and the second reset signal RSTICM of the temporally continuous incremental sigma-delta modulator (20) each have the same frequency, wherein the frequency defines a Nyquist sampling rate, in particular a first pulse duration (12) of the first reset signal RST C amp and second pulse duration (22) of the second reset signal RSTIC are superimposed in time such that the first and second pulse durations (12, 22) start at the same time.

17. Readout circuit (100) according to one of claims 4 to 16, wherein the readout circuit (100) is designed to carry out the modulator reset after the current amplifier reset, in particular to carry out the modulator reset after the current amplifier reset with a certain delay, wherein the certain delay is based on a settling time of an integrator (11) of the at least one operational amplifier OPi.

18. Readout circuit (100) according to claim 7, wherein the readout circuit (100) in the case of coupling with the sensor (30) is designed to, when executing the Current amplifier reset to sample a charge noise at a sensor input capacitance Cin of the sensor (30).

19. Readout circuit (100) according to claim 18, wherein the readout circuit (100) is designed to first accumulate the charge noise on the input capacitance Cin and then to integrate it via the feedback capacitance C1.

20. Readout circuit (100) according to claim 1, wherein the readout circuit (100) is configured to integrate the charge noise via the feedback capacitance C1 during the modulator reset of the temporally continuous incremental sigma-delta modulator (20).

21. Readout circuit (100) according to one of claims 2 to 20, wherein an effect of the charge noise of the integrator (INTICM.I) on the digital value D out because of the upstream current amplifier (10), in particular to a negligible value.

22. Readout circuit (100) according to one of claims 18 to 21, wherein the readout circuit (100) is designed to separate the at least one integrator lntlCM,1 from the sensor input capacitance Cin, whereby a bandwidth of the at least one integrator Inticrvi.i is capacitance-independent.

23. Readout circuit (100) according to one of claims 4 to 22, wherein a corner frequency of the readout circuit (100) corresponds to a reset frequency at which the current amplifier reset and the modulator reset take place.

24. Use of a readout circuit (100) according to one of claims 1 to 23 in a nanopore readout circuit or in a digital X-ray image sensor readout circuit or in a gas sensor readout circuit or in a readout circuit for electrochemical sensors.

25. Method for reading a readout circuit (100) which detects electrical currents of 10nA and less, wherein the readout circuit arrangement (100) comprises a capacitive current amplifier (10) and a temporally continuous incremental sigma-delta modulator (20) in current mode, the method comprising: Amplifying an input current Im , which is of the order of 10nA or less, to produce an amplified current l ou t to receive; and Converting the amplified current l ou t into a digital value D out ..

26. The method of claim 25, which comprises: Resetting the capacitive current amplifier (10) upon receipt of a first reset signal RST ca m P , Resetting the temporally continuous incremental sigma-delta modulator (20) upon receipt of a second reset signal RST I C M , wherein the resetting of the temporally continuous incremental sigma-delta modulator (20) is carried out after the resetting of the capacitive current amplifier (10).

27. A method according to any one of claims 25 to 26, which comprises: Sampling an output voltage VHS at each clock edge of a clock signal CLK to regulate the output voltage VHS within a specific range; and / or Receiving and filtering the amplified current l ou t and converting the filtered, amplified current l out after a conversion period into the digital value Dout.

28. A method according to any one of claims 25 or 27, which comprises: Regulating a sensed voltage, in particular to a command voltage V b ias, in case of coupling with a sensor.

29. The method of claim 28, comprising: in the case of coupling to the sensor (30), sampling a charge noise at a sensor input capacitance Cin of the sensor (30) when performing the current amplifier reset; and / or first accumulating the charge noise on an input capacitance Cin of the sensor (30) and then integrating the charge noise across a feedback capacitance C1 of the current amplifier (10); and / or integrating the charge noise across the feedback capacitance C1 during the modulator reset of the time-continuous incremental sigma-delta modulator (20).

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