Method and apparatus for decoding trace data

Abstract

A method and apparatus for decoding trace data output by monitoring circuitry configured to monitor execution of a program on a computing system are provided. The method includes receiving trace data including a sequence of packets from the computing system, identifying a first synchronization packet in a first predefined format, and identifying one or more further synchronization packets. The method also includes partitioning the sequence of packets into subsequences based on the identified synchronization packets, and decoding the plurality of subsequences.

Description

METHOD AND APPARATUS FOR DECODING TRACE DATATECHNICAL FIELD

[0001] The present disclosure relates to a method and apparatus for decoding encoded trace information from a computing system and, in particular, a method of decoding a sequence of trace packets using parallelization.BACKGROUND

[0002] Modern computing systems frequently execute highly complex software programs including millions or billions of individual instructions. During normal execution, a program will either step from one instruction to the next in the order the instructions are stored in the memory, or non-sequentially from one instruction to another instruction that does not immediately follow the original instruction. The computing system keeps track of which instruction is being executed using a program counter. The program counter is incremented to point to the next instruction once the current instruction has been fetched from memory.

[0003] It is possible to reconstruct the program flow of a program executed by a processor using a trace. A trace may be used to assist in program debugging or monitoring operations. In one arrangement, a trace interface may be used to output relevant information from the processor for tracking operations including instruction addresses, instruction type, and further data such as context information. A hardware encoder may be provided to receive the data from the trace interface. The hardware encoder compresses the data for transmission via a communication channel such a USB connection.

[0004] A decoder, which may be provided as software on an external computer, receives the trace packets and, with knowledge of the program binary, reconstructs the program counter values. This enables the decoder to restore the state of the computing system during program execution.

[0005] Today’s CPUs can easily retire 5-10 instructions per cycle per hardware thread. This provides that the amount of data output from the trace encoder grows rapidly over time. Conversely, the average decoding speed on a regular desktop CPU is approximately 32 million instructions per second (MIPS), peaking at a maximum of 54 MIPS. Decoding only a single second of trace packets from a 3 GHz hardware thread may therefore take up to 16 minutes.SUMMARY AND DESCRIPTION

[0006] The scope of the present invention is defined solely by the appended claims and is not affected to any degree by the statements within this summary.

[0007] The present embodiments may obviate one or more of the drawbacks or limitations in the related art. For example, a fast decoding method for decoding a trace from a computing system is provided.

[0008] The foregoing and other objects are achieved by the features of the independent claims. Further implementation forms are apparent from the dependent claims, the description, and the figures.

[0009] According to a first aspect, a computer-implemented method for decoding trace data output by monitoring circuitry in a computing system is provided. The monitoring circuitry is configured to monitor the execution of a program on the computing system. The method includes receiving trace data from the computing system.The trace data includes: a sequence of trace packets; a synchronization packet in a first predefined format at the start of the sequence of trace packets; and one or more further synchronization packets. Each of the one or more further synchronization packets includes either a synchronization packet in the first predefined format or a synchronization packet in a second predefined format. The second predefined formal is different than the first predefined format. The method includes: identifying the first synchronization packet in the first predefined format; identifying the one or more further synchronization packets; partitioning the sequence of trace packets into a plurality of subsequences based on the identified synchronization packets; and decoding the subsequences. The synchronization packets in the first predefined format are inserted into the sequence of trace packets periodically based on a predetermined parameter, and synchronization packets in the second predefined format are inserted into the sequence of trace packets in response to an event in the computing system.

[0010] The method according to the first aspect enables fast decoding by decomposing a sequence into subsequences that may be decoded separately. The sequence is decomposed by splitting the sequence at synchronization packets. Most of the synchronization packets are located periodically throughout the sequence and may be determined in constant time based on a predetermined parameter that determines the periodicity.

[0011] In a first implementation form of the method according to the first aspect, the parameter includes a predetermined number of packets between a previous synchronization packet and a subsequent synchronization packet in the first predefined format.

[0012] In a second implementation form, identifying the one or more further synchronization packets includes: determining an expected location of a subsequent synchronization packet in the first predefined format based on the predetermined parameter; and identifying the subsequent synchronization packet in either: a) the first pre-defined format, when the packet at the expected location is a synchronization packet in the first pre-defined format; or b) the second predefined format, when the packet at the expected location is not a synchronization packet in the first pre-defined format.

[0013] In a third implementation form, identifying a subsequent synchronization packet in the second predefined format includes evaluating the sequence of trace packets sequentially to identify the subsequent synchronization packet.

[0014] In a fourth implementation form, decoding the subsequences includes decoding at least two of the subsequences in parallel.

[0015] In a fifth implementation form, decoding the subsequences includes reconstructing the program flow execution based on data in the trace packets.

[0016] In a sixth implementation form, the event includes an interrupt or an exception.

[0017] According to a second aspect of the present embodiments, an apparatus for decoding trace data output by monitoring circuitry configured to monitor the execution of a program in a computing system is provided. The apparatus includes a decoding device configured to receive trace data from the computing system. The trace data includes: a sequence of trace packets; a synchronization packet in a first pre-defined format at the start of the sequence of trace packets; and one or more further synchronization packets where each of the one or more further synchronization packets includes either a synchronization packet in the first predefined format or a synchronization packet in a second predefined format. The second predefined format is different than the first pre-defined format. The decoding device is configured to: identify the first synchronization packet in the first predefined format; identify the one or more further synchronization packets; partition the sequence of trace packets into a plurality of subsequences based on the identified synchronization packets; and decode the subsequences. The synchronization packets in the first predefined format are inserted into the sequence of trace packets periodically based on a predetermined parameter, and synchronization packets in the second predefined format are inserted into the sequence of trace packets in response to an event in the computing system.

[0018] These and other aspects of the present embodiments will be apparent from the embodiments described below.BRIEF DESCRIPTION OF THE DRAWINGS

[0019] For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

[0020] Figure 1 shows a computing system with monitoring circuitry, according to an example.

[0021] Figure 2 shows a flow diagram of a method for decoding trace data, according to an example.

[0022] Figure 3 shows a simplified schematic diagram of a computing system, according to an example.DETAILED DESCRIPTION

[0023] Example embodiments are described below in sufficient detail to enable those of ordinary skill in the art to embody and implement the systems and processes herein described. It is important to understand that embodiments may be provided in many alternate forms and should not be construed as limited to the examples set forth herein.

[0024] Accordingly, while embodiments may be modified in various ways and take on various alternative forms, specific embodiments thereof are shown in the drawings and described in detail below as examples. There is no intent to limit to the particular forms disclosed. On the contrary, all modifications, equivalents, and alternatives falling within the scope of the appended claims should be included. Elements of the example embodiments are consistently denoted by the same reference numerals throughout the drawings and detailed description where appropriate.

[0025] The terminology used herein to describe embodiments is not intended to limit the scope. The articles “a,” “an,” and “the” are singular in that they have a single referent; however, the use of the singular form in the present document should not preclude the presence of more than one referent. In other words, elements referred to in the singular may number one or more, unless the context clearly indicates otherwise. The terms “comprises,” “comprising,” “includes,” and / or “including,” when used herein, specify the presence of stated features, items, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, items, steps, operations, elements, components, and / or groups thereof.

[0026] Unless otherwise defined, all terms including technical and scientific terms used herein are to be interpreted as is customary in the art. Terms in common usageshould also be interpreted as is customary in the relevant art and not in an idealized or overly formal sense unless expressly so defined herein.

[0027] Figure 1 is a simplified schematic diagram showing a computing system 100, according to an example. The computing system 100 may be used in conjunction with the other methods and systems described herein.

[0028] Computing system 100 includes system circuitry 110 that includes sub-blocks 120, 130, 140 representing core devices in the computing system 100. Core devices 120, 130, 140 may include one or more of: central processing units (CPUs), memory, input / output devices, secondary storage devices, graphical processing units (GPUs), custom logic, or any other type of suitable component. In other examples of computing systems, the system circuitry 110 may include more or fewer than the three core devices 120, 130, 140 shown in Figure 1.

[0029] The computing system 100 includes monitoring circuitry 150. The monitoring circuitry 150 is able to monitor the operation of the core devices 120, 130, 140. For example, monitoring circuitry 150 may be configured to trace instruction execution of a program executed on a core device. The monitoring circuitry 150 outputs a trace. The trace includes a sequence of trace packets that contain information for tracking program execution. The trace data is compressed for transmission off-chip via a communication channel 160 such as a USB connection. A decoder 170, which may be provided as software on an external computer 180, receives the trace packets and, with knowledge of the program binary, reconstructs program counter values. These decoding operations may be performed offline or online in real time.

[0030] The methods and systems described herein improve the efficiency of decoding trace packets through parallelization. A sequence of trace packets may be partitioned suchthat each subsequence is decoded independently, and the results are joined together at the end. This still produces a single, correct sequence of program counter values.

[0031] The partitioning of the sequence of trace packets occurs at specific points by exploiting synchronization. Synchronization is used to provide that an instruction trace is robust. The monitoring circuitry 150 is configured to insert synchronization packets that contain all the information the decoder needs to identify an instruction address. This enables the decoder to resync at specific points by aligning with the address in the synchronization packet.

[0032] The monitoring circuitry 150 may be configured to insert synchronization packets in different formats depending on the circumstances. A format of a packet refers to the organization of data within the packet. For example, packets generally begin with a packet header containing source and destination information and other identifying information, and a packet payload. In the context of the monitoring circuitry 150 and decoder, formats may be used to specify a subtype of synchronization packet, so that the decoder may correctly decode and interpret data in the packet.

[0033] In the examples described herein, the monitoring circuitry 150 is configured to insert synchronization packets in a first predefined format periodically. The period between inserted synchronization packets is based on a predetermined parameter. The parameter may be, for example, a number of packets between a previous synchronization packet and a subsequent synchronization packet in the first pre-defined format, or a number of clock cycles that have elapsed since the last synchronization packet. The monitoring circuitry 150 is further configured to insert synchronization packets in a second predefined format in response to an event in the computing system. The eventmay be an interrupt or an exception on the computing system during execution of the program being monitored by the monitoring circuitry 150.

[0034] Figure 2 is a block diagram of a computer implemented method 200 for decoding trace data output by monitoring circuitry 150 in computing system 100, according to an example. The method 200 may be implemented by the decoder 170 in software on external computing device 180, either in real-time or offline, as previously described.

[0035] At block 210, the method 200 includes receiving trace data from the computing system 100. The trace data includes a sequence of trace packets, a synchronization packet in the first predefined format at the start of the sequence of trace packets, and one or more further synchronization packets. Each of the one or more further synchronization packets includes either a synchronization packet in the first predefined format or a synchronization packet in the second predefined format, where packets in the first predefined format are inserted periodically by monitoring circuity 150 based on the predetermined parameter, and packets in the second predefined format are inserted into the sequence of trace packets by the monitoring circuitry in response to an event in the computing system.

[0036] At block 220, the method 200 includes identifying the first synchronization packet in the first predefined format. A decoder may locate the first synchronization packet by reading the sequence from the first packet.

[0037] At block 230, the method 200 includes identifying the one or more further synchronization packets. Identifying the further synchronization packets may include determining an expected location of a subsequent synchronization packet in the first predefined format based on the predetermined parameter. For example, when theparameter value specifies a number of packets between successive synchronization packets, the parameter value may be added to the location of the previous synchronization packet in the sequence of trace packets to determine the expected location of the next synchronization packet in the first predefined format. If the packet at the expected location is a synchronization packet in the first predefined format, then the next synchronization packet has been identified.

[0038] If the packet at the expected location of a synchronization packet in the first predefined formation is not a synchronization packet, then the decoder knows that there must have been a further synchronization packet between the previous synchronization packet and the packet at the expected location of the next synchronization packet in the first predefined format. For example, an event is to have occurred on the computing system 100 to trigger the monitoring circuitry 150 to insert a synchronization packet in the second predefined format in the sequence of trace packets. Therefore, the decoder may perform a linear search from the location of the previous synchronization packet in the sequence to identify the next synchronization packet, which is to be a synchronization packet in the second pre-defined format.

[0039] At block 240, the method 200 includes partitioning the sequence of trace packets into a plurality of subsequences based on the identified synchronization packets. The sequence is partitioned at each of the synchronization points as determined by the synchronization packets. At block 250, the method includes decoding each of the subsequences. Each subsequence of trace packets may be decoded independently and in parallel with the other subsequences. The complete program execution may be reconstructed from decoded subsequences combined with the address information from the synchronization packets.

[0040] The method 200 enables fast decoding through parallelization by exploiting synchronization packets. The average time complexity for locating synchronization packets is 0(1). This is because synchronization packets in the first predefined format are located at predictable positions in the sequence based on the parameter and are locatable in constant time 0(1). Synchronization packets in the second predefined format may be located with a linear search that has time complexity O(n). This therefore takes longer than the synchronization packets in the first predefined format; however, synchronization packets in the second predefined format are only output exceptionally by the monitoring circuitry 150 in response to an event on the computing system.

[0041] The present disclosure is described with reference to flow charts and / or block diagrams of the method, devices, and systems according to examples of the present disclosure. Although the flow diagrams described above show a specific order of execution, the order of execution may differ from that which is depicted. Blocks described in relation to one flow chart may be combined with those of another flow chart. In some examples, some blocks of the flow diagrams may not be necessary, and / or additional blocks may be added.

[0042] Each flow and / or block in the flow charts and / or block diagrams, as well as combinations of the flows and / or diagrams in the flow charts and / or block diagrams may be realized by machine readable instructions.

[0043] The machine-readable instructions may, for example, be executed by a general-purpose computer, a special purpose computer, an embedded processor, or processors of other programmable data processing devices to realize the functions described in the description and diagrams. For example, a processor or processing apparatus may execute the machine-readable instructions. Thus, modules of an apparatusmay be implemented by a processor executing machine-readable instructions stored in a memory, or a processor operating in accordance with instructions embedded in logic circuitry. The term 'processor' is to be interpreted broadly to include a CPU, processing unit, ASIC, logic unit, or programmable gate set, etc. The methods and modules may all be performed by a single processor or divided amongst a number of processors.

[0044] Such machine-readable instructions may also be stored in a computer readable storage that may guide the processing devices to operate in a specific mode. Figure 3 shows an example 300 of a processor 310 associated with a memory 320. The memory 320 includes computer readable instructions 330 that are executable by the processor 410.

[0045] The instructions 330 cause the processor 310 to receive trace data from a computing system. The trace data includes a sequence of trace packets, a synchronization packet in a first pre-defined format at the start of the sequence of trace packets, and one or more further synchronization packets. Each of the one or more further synchronization packets includes either a synchronization packet in the first predefined format or a synchronization packet in a second predefined format. The second predefined format is different than the first predefined format. The instructions 330 cause the processor to identify the first synchronization packet in the first predefined format, identify the one or more further synchronization packets, partition the sequence of trace packets into a plurality of subsequences based on the identified synchronization packets, and decode the plurality of subsequences. The synchronization packets in the first predefined format are inserted periodically based on a predetermined parameter into the sequence of trace packets, and synchronization packets in the second predefined format are inserted into the sequence of trace packets in response to an event in the computing system.

[0046] Such machine-readable instructions may also be loaded onto a computer or other programmable data processing devices, so that the computer or other programmable data processing devices perform a series of operations to produce computer-implemented processing; thus, the instructions executed on the computer or other programmable devices provide an operation for realizing functions specified by flow(s) in the flow charts and / or block(s) in the block diagrams.

[0047] Further, the teachings herein may be implemented in the form of a computer software product. The computer software product is stored in a storage medium and includes a plurality of instructions for making a computer device implement the methods recited in the examples of the present disclosure.

[0048] The present inventions may be embodied in other specific apparatus and / or methods. The described embodiments are to be considered in all respects as illustrative and not restrictive. In particular, the scope of the invention is indicated by the appended claims rather than by the description and figures herein. All changes that come within the meaning and range of equivalency of the claims are to be embraced within their scope.

[0049] The elements and features recited in the appended claims may be combined in different ways to produce new claims that likewise fall within the scope of the present invention. Thus, whereas the dependent claims appended below depend from only a single independent or dependent claim, it is to be understood that these dependent claims may, alternatively, be made to depend in the alternative from any preceding or following claim, whether independent or dependent. Such new combinations are to be understood as forming a part of the present specification.

[0050] While the present invention has been described above by reference to various embodiments, it should be understood that many changes and modifications can be madeto the described embodiments. It is therefore intended that the foregoing description be regarded as illustrative rather than limiting, and that it be understood that all equivalents and / or combinations of embodiments are intended to be included in this description.

Claims

CLAIMS1. A computer- implemented method for decoding trace data output by monitoring circuitry configured to monitor execution of a program on a computing system, the computer-implemented method comprising: receiving trace data from the computing system, the trace data comprising: a sequence of trace packets; a synchronization packet in a first predefined format at a start of the sequence of trace packets; and one or more further synchronization packets, each of the one or more further synchronization packets comprising either a synchronization packet in the first predefined format or a synchronization packet in a second predefined format, the second predefined format being different than the first predefined format; identifying the synchronization packet in the first predefined format; identifying the one or more further synchronization packets; partitioning the sequence of trace packets into subsequences based on the identified synchronization packet and the identified one or more further synchronization packets; and decoding the subsequences, wherein synchronization packets in the first predefined format are inserted into the sequence of trace packets periodically based on a predetermined parameter, and synchronization packets in the second predefined format are inserted into the sequence of trace packets in response to an event in the computing system.

2. The computer- implemented method of claim 1 , wherein the predetermined parameter comprises a number of packets between a previous synchronization packet and a subsequent synchronization packet in the first predefined format.

3. The computer- implemented method of claim 1, wherein identifying the one or more further synchronization packets comprises: determining an expected location of a subsequent synchronization packet in the first predefined format based on the predetermined parameter; and identifying the subsequent synchronization packet in: the first predefined format when the subsequent synchronization packet at the expected location is a synchronization packet in the first predefined format; or the second predefined format when the subsequent synchronization packet at the expected location is not a synchronization packet in the first predefined format.

4. The computer- implemented method of claim 3, wherein when the subsequent synchronization packet is identified in the second predefined format, identifying the subsequent synchronization packet in the second predefined format comprises evaluating the sequence of trace packets sequentially, such that the subsequent synchronization packet is identified.

5. The computer-implemented method of claim 1, wherein decoding the subsequences comprises decoding at least two of the subsequences in parallel.

6. The computer-implemented method of claim 1 , wherein decoding the subsequences comprises reconstructing program flow execution based on data in the sequence of trace packets.

7. The computer- implemented method of claim 1 , wherein the event in the computing system comprises an interrupt or an exception.

8. An apparatus for decoding trace data output by monitoring circuitry in a computing system, the monitoring circuitry being configured to monitor execution of a program on the computing system, the apparatus comprising: a decoding device configured to: receive trace data from the computing system, the trace data comprising: a sequence of trace packets; a synchronization packet in a first predefined format at a start of the sequence of trace packets; and one or more further synchronization packets, each of the one or more further synchronization packets comprising a synchronization packet in the first predefined format or a synchronization packet in a second predefined format, the second predefined format being different than the first predefined format; identify the first synchronization packet in the first predefined format; identify the one or more further synchronization packets; partition the sequence of trace packets into subsequences based on the identified first synchronization packet and the identified one or more further synchronization packets; anddecode the subsequences, wherein synchronization packets in the first predefined format are inserted into the sequence of trace packets periodically based on a predetermined parameter, and synchronization packets in the second predefined format are inserted into the sequence of trace packets in response to an event in the computing system.

9. The apparatus of claim 8, wherein the predetermined parameter comprises a number of packets between a previous synchronization packet and a subsequent synchronization packet in the first predefined format.

10. The apparatus of claim 8, wherein the decoder being configured to identify the one or more further synchronization packets comprises the decoder being configured to: determine an expected location of a subsequent synchronization packet in the first predefined format based on the predetermined parameter; and identify the subsequent synchronization packet in: the first predefined format when the subsequent synchronization packet at the expected location is a synchronization packet in the first predefined format; or the second predefined format when the subsequent synchronization packet at the expected location is not a synchronization packet in the first predefined format.

11. The apparatus of claim 10, wherein when the identified subsequent synchronization packet is in the second predefined format, the decoder being configured to identify the subsequent synchronization packet in the second predefined formatcomprises the decoder being configured to evaluate the sequence of trace packets sequentially to identify the subsequent synchronization packet.

12. The apparatus of claim 8, wherein the decoder being configured to decode the subsequences comprises the decoder being configured to decode at least two of the subsequences in parallel.

13. The apparatus of claim 8, wherein the decoder being configured to decode the subsequences comprises the decoder being configured to reconstruct a program flow execution based on data in the trace packets.

14. The apparatus of claim 8, wherein the event in the computing system comprises an interrupt or an exception.

Images