Redundant power supply for an hfac system

Abstract

A redundant power supply for a high frequency alternating current, HFAC, system, the HFAC system comprising an HFAC power distribution bus configured to provide an HFAC voltage supply to a plurality of devices positioned along the HFAC power distribution bus to receive the HFAC voltage, is disclosed herein. The redundant power supply comprises: a first inverter and a second inverter, wherein the first inverter is configured as a master which provides a phase reference signal to the second inverter and the second inverter is configured as a slave to synchronise with the phase reference signal; wherein the second inverter comprises a PWM controller configured to provide a PWM signal for controlling gate drives of the second inverter to output power from the second inverter; and wherein the phase reference signal comprises a triangle wave and the PWM controller is configured to synchronise with the phase reference signal by centre-aligned pulse width modulation, PWM.

Description

[0001]Redundant Power Supply for an HFAC system Field of Invention The present invention relates to a redundant power supply for providing high frequency alternating current (HFAC), and more particularly to a power supply comprising a first inverter and a second inverter. Background In high frequency alternating current (HFAC) power distribution systems, there can be difficulties in implementing redundancy for the purposes of power sharing. In a multi-inverter power distribution system, each inverter must continually adjust its own output voltage magnitude, output current magnitude, output phase and output frequency to equal the other inverters so that even power sharing is achieved. Failure to do so may result in one inverter powering the others, rather than all the inverters equally powering a load of the power distribution system. To achieve this function, there is a need for magnitude error control, phase error control and frequency error control. Phase error control for implementation of a multi-inverter high frequency power distribution system is typically performed using a multiplier circuit. However, in such circuits, the output control signal often has a highly non-linear response to phase error and it may be challenging to implement as part of a feedback control system. To handle heavy current loads, many systems utilise load sharing. An example is a droop current sharing method (open-loop), in which modulator gain is reduced if output current increases. This is simpler to implement, since no current share bus is needed, but may result in poor load sharing at light to medium loads. Active current sharing using a closed loop is another method of handling such loads. Such a method utilises a current share bus, which greatly improves the load sharing, even at light loads. Such methods are typically limited to DC-DC converters, with no similar implementation into the HFAC domain. For the HFAC domain, much more complex methods are often used, such as phasor current sharing control – here, the output current is decomposed into active and reactive parts to be separately controlled, with the active part being distributed evenly among inverters and the reactive part being minimised to achieve load sharing. Such methods are more difficult and costly to implement. Summary Aspects of the disclosure are set out in the independent claims and optional features are set out in the dependent claims. Aspects of the disclosure may be provided in conjunction with each other and features of one aspect may be applied to other aspects. An aspect of the disclosure provides a redundant power supply for a high frequency alternating current (HFAC) system, the HFAC system comprising an HFAC power distribution bus configured to provide an HFAC voltage supply to a plurality of devices positioned along the HFAC power distribution bus to receive the HFAC voltage, the redundant power supply comprising: a first inverter and a second inverter, wherein the first inverter is configured as a master which provides a phase reference signal to the second inverter and the second inverter is configured as a slave to synchronise with the phase reference signal; wherein the second inverter comprises a PWM controller configured to provide a PWM signal for controlling gate drives of the second inverter to output power from the second inverter; and wherein the phase reference signal comprises a triangle wave and the PWM controller is configured to synchronise with the phase reference signal by centre-aligned pulse width modulation (PWM). Additionally, the second inverter may comprise a phase control circuit, configured selectively to advance or retard the PWM signal to provide said synchronisation. Additionally, the phase control circuit may be configured to: determine a phase error based on the phase reference signal and an HFAC output voltage, wherein the HFAC output voltage comprises the voltage at an output of a transformer which couples the second inverter to the HFAC power distribution bus; and provide a phase control signal based on the phase error. This means that error control can take place to help determine the extent to which the PWM signal requires adjusting. Additionally, the second inverter may further comprise a current share control circuit configured to determine a local current adjustment based on a shared current reference and an HFAC output current, wherein the HFAC output current comprises the current at an output of a transformer which couples the second inverter to the HFAC power distribution bus. This helps to determine whether or not equal current sharing is being achieved, and if not, helps to determine what changes must be made in order to achieve it. Additionally, the shared current reference may comprise the sum and averaged current signals of all inverters present on a current share bus of the current share control circuit. Additionally, the second inverter may further comprise a magnitude control circuit configured to provide a duty cycle adjustment based on the local current adjustment and a magnitude indication, the magnitude indication based on the output voltage of the transformer which couples the second inverter to the HFAC power distribution bus. Additionally, the magnitude control circuit may be configured to: determine the duty cycle adjustment based on comparing the magnitude indication and the local current adjustment; and provide a magnitude control signal based on said comparing. This can then be used to help the PWM controller determine how to adjust the PWM signal. Additionally, the duty cycle adjustment may be provided to the PWM controller to adjust the HFAC output voltage such that the HFAC output current achieves equal output current sharing on the HFAC power distribution bus. Additionally, the first inverter may be configured to provide a frequency reference signal and the second inverter may further comprise a frequency control circuit configured selectively to increase or decrease a frequency of the PWM signal to provide frequency synchronisation with the first inverter. Additionally, the frequency control circuit may be configured to: determine a frequency error based on the frequency reference signal and the HFAC output voltage; and provide a frequency control signal based on the frequency error. This may help to keep the second inverter synchronised with the first inverter, which is necessary for current sharing. Another aspect of the disclosure provides a method of outputting power in a high frequency alternating current (HFAC) system, the method comprising: configuring a first inverter of the HFAC system as a master inverter and a second inverter of the HFAC system as a slave inverter, the second inverter comprising a PWM controller; providing, by the first inverter, a phase reference signal; establishing, by the first inverter, an HFAC output voltage of the first inverter on an HFAC power distribution bus of the HFAC system; providing, by the PWM controller of the second inverter, a PWM signal for controlling gate drives of the second inverter to output power from the second inverter wherein the PWM signal is synchronised with the phase reference signal by centre-aligned PWM; establishing, by the second inverter, an HFAC output voltage of the second inverter on the HFAC power distribution bus; and providing an HFAC voltage supply based on the HFAC output voltage of the first inverter and the HFAC output voltage of the second inverter to a plurality of devices positioned along the HFAC power distribution bus. Additionally, the synchronising may comprise selectively advancing or retarding the PWM signal by a phase control circuit of the second inverter. Additionally, the method may further comprise: determining, by the phase control circuit, a phase error based on the phase reference signal and the HFAC output voltage, wherein the HFAC output voltage comprises the voltage at an output of a transformer which couples the second inverter to the HFAC power distribution bus; and providing, by the phase control circuit, a phase control signal based on the phase error. Additionally, determining the phase error may comprise: sensing, by the second inverter, an output voltage phase of the second inverter; and comparing, by the second inverter, the output voltage phase of the second inverter with the phase reference signal. Additionally, the method may further comprise adjusting the PWM signal based on the phase error. This may help to bring the second inverter in phase with the first inverter. Additionally, the method may further comprise: establishing, by the first inverter, an HFAC output current of the first inverter on a current share bus of the HFAC system; and establishing, by the second inverter, an HFAC output current of the second inverter on the current share bus. Additionally, the method may further comprise determining, by a current share control circuit of the second inverter, a local current adjustment based on a shared current reference and the HFAC output current of the second inverter, wherein the HFAC output current of the second inverter comprises the current at an output of a transformer which couples the second inverter to the HFAC power distribution bus. This determination helps to inform the PWM controller about whether any adjustments need to be made to the PWM signal. Additionally, the shared current reference may comprise the sum and averaged current signals of all inverters present on a current share bus of the current share control circuit. In this way, it can easily be determined if any adjustment is required. Additionally, the method may further comprise: determining, by a magnitude control circuit, a duty cycle adjustment based on the local current adjustment and a magnitude indication, the magnitude indication based on the output voltage of the transformer which couples the second inverter to the HFAC power distribution bus; and providing, by the magnitude control circuit, the duty cycle adjustment. Additionally, determining the duty cycle adjustment may comprise comparing the magnitude indication and the local current adjustment. Additionally, providing the duty cycle adjustment may comprise providing the duty cycle adjustment to the PWM controller to adjust the HFAC output voltage such that the HFAC output current achieves equal output current sharing among the first inverter and the second inverter on the HFAC power distribution bus. Additionally, the method may further comprise: providing, by the first inverter, a frequency reference signal; and selectively or decreasing, by a frequency control circuit, a frequency of the PWM signal to provide frequency synchronisation with the first inverter. Additionally, selectively increasing or decreasing the frequency of the PWM signal may comprise: determining, by the frequency control circuit, a frequency error based on the frequency reference signal and the HFAC output voltage; and providing, by the frequency control circuit, a frequency control signal based on the frequency error. Additionally, establishing the HFAC output voltage of the first inverter on the HFAC power distribution bus may comprise switching on, by the first inverter, an output enable switch of the first inverter; and establishing the HFAC output voltage of the second inverter on the HFAC power distribution bus may comprise switching on, by the second inverter, an output enable switch of the second inverter. Additionally, the method may further comprise configuring the the inverter. This helps to ensure continuity of the power supply. Brief Description of Drawings Embodiments of the disclosure will now be described, by way of example only, with reference to the accompanying drawings. Figure 1 shows a functional block diagram of a redundant power supply for an HFAC system. Figure 2 shows a functional block diagram of the second inverter from Figure 1. Figure 3 shows a functional block diagram of the phase control circuit from Figure 2. Figure 4 shows a functional block diagram of the magnitude control circuit from Figure 2. Figure 5 shows a functional block diagram of the frequency control circuit from Figure 2. Figure 6A shows a series of plots of signals relating to a phase synchronisation process. Figure 6B also shows a series of plots of signals relating to a phase synchronisation process. Figure 7 shows a series of plots of signals relating to a magnitude control process. Figure 8 shows a flow chart describing a method of outputting power in an HFAC system. In the drawings like reference numerals are used to indicate like elements. Specific Description Figure 1 shows a functional block diagram 100 of a redundant power supply for an HFAC system. The redundant power supply may comprise a DC supply 101, which is connected to a first inverter 102 and a second inverter 103 in parallel. The DC supply may be any supply configured to output DC power, such as a battery, a DC-DC supply or an AC-DC supply. The first inverter 102 may be connected to a primary winding of a first transformer 104. A secondary winding of the first transformer 104 may be connected to an HFAC power distribution bus 106. The second inverter 103 may be connected to a primary winding of a second transformer 105. A secondary winding of the second transformer 105 may also be connected to the HFAC power distribution bus 106. The HFAC power distribution bus 106 may be formed by any suitable medium of transmission, depending on the application of the HFAC system. For example, the HFAC may be distributed through a motherboard, or through a power distribution printed circuit board that then connects to the motherboard. Alternatively, the medium of transmission may be high frequency rated wire such as Litz wire. The HFAC power distribution bus 106 may form part of a load circuit, which may further comprise a plurality of devices (not shown) positioned along the HFAC power distribution bus 106. The plurality of devices may be coupled to the HFAC power distribution bus 106 and may comprise, for example, lights, sensors, battery chargers, audio devices, cameras, irrigation devices or motors. The HFAC power distribution bus 106 may be configured to provide an HFAC power supply to the plurality of devices positioned along the HFAC power distribution bus 106 to receive the HFAC voltage. Figure 1 shows a first inverter 102 and a second inverter 103, but it be incorporated into the power supply. In this way, the system can be considered an N+1 redundant power supply. Figure 1 also only shows one bus 106, but it should be appreciated that multiple output buses 106 may be employed, with the output of the inverters split across the multiple buses 106. The DC supply 101 may provide input power, which may then be supplied to the first inverter 102 and the second inverter 103. The first inverter 102 may output a variable frequency wave which may be fed to a first resonant network (not shown) and to the primary winding of first transformer 104. If the second inverter 103 is connected to the HFAC power distribution bus 106, it may also output a variable frequency wave which may be fed to a second resonant network (not shown) and the primary winding of second transformer 105. The secondary windings of first transformer 104 and second transformer 105 may generate an alternating current and an alternating voltage at a high frequency on the HFAC power distribution bus 106 of the load circuit. The frequency of the HFAC circuit can be varied in the range 50kHz to 1MHz. The system can provide power of up to 1.2kW at zero to 35A and using any suitable voltage, depending on the application of the circuit. A range of voltages may be zero to 84V AC. In a preferred embodiment, the voltage may be 34V. Figure 2 shows a functional block diagram 200 of the second inverter 103 from Figure 1. The second inverter 103 may comprise a phase control circuit 201, into which a shared phase reference and an HFAC output voltage may be fed. The shared phase reference may correspond to a phase reference of the first inverter 102. The HFAC output voltage may comprise the voltage at an output of the transformer 105 which couples the second inverter 103 to the HFAC power distribution bus 106. An output of the phase control circuit 201 may be a phase control signal, which may represent the error between the phase of the output voltage and the phase of the shared phase reference. The second inverter 103 may further comprise a current share control circuit 202, into which a shared current reference and an HFAC output current may be fed. The shared current reference may comprise the sum and averaged current signals of all inverters present on a current share bus of the HFAC system. The HFAC output current may comprise the current at an output of the transformer 105 which couples the second inverter 103 to the HFAC power distribution bus 106. An output of the current share control circuit 202 may be a local current adjustment, which may be an amplified error between the HFAC output current and the shared current reference. The second inverter 103 may further comprise a magnitude control circuit 203, into which the HFAC output voltage, the local current adjustment and a magnitude reference may be fed. The magnitude reference may be a reference signal that has a fixed value and may therefore scale up or scale down the incoming signal representing the magnitude of the pulses applied when compared with this signal. An output of the magnitude control circuit 203 may be a magnitude control signal, which may represent the error between the output waveform of the second inverter 103 (i.e. a magnitude of the pulses applied by the gate drives) and the magnitude of the pulses required to enable current sharing. The second inverter 103 may further comprise a frequency control circuit 204, into which a shared frequency reference and an HFAC output voltage may be fed. The shared frequency reference may correspond to a frequency of the first inverter 102. An output of the phase control circuit 201 may be a frequency control signal, which may represent the error between the frequency of the second inverter 103 and the frequency of the first inverter 102. The second inverter 103 may further comprise a phase shift modulation circuit 205, into which the phase control signal, the magnitude control signal and the frequency control signal may be fed. More specifically, the phase shift modulation circuit 205 may comprise a pulse width modulation (PWM) controller 206, into which the phase control signal, the magnitude control signal and the frequency control signal may be fed. An output of the PWM controller 206 may be a PWM signal. The second inverter 103 may further comprise gate drives 207, into which the PWM signal may be fed. Based on the PWM signal, the gate drives may enable power to be outputted from the second inverter 103. The number of gate drives 207 may be the same as the number of gates / switches in the inverter 103. For example, the second inverter may comprise four gates / switches (e.g. gates A, B, C and D) and each gate drive 207 may be responsible for one of these gates / switches. The gates may be paired, so that one pair can never be on at the same time as the other pair. The pairs may comprise a first pair of gates A and D, and a second pair of gates B and C. The PWM signal may be synchronised with the shared phase reference by centre-aligned PWM. The phase control circuit 201 may be configured to compare the phase of the second inverter 103 with the shared phase reference, which, as described above, corresponds to the phase of the first inverter 102. In doing so, the phase control circuit 201 may be configured to determine a phase error based on these inputs. The phase control circuit 201 may also be configured to generate a phase control signal representative of the phase error based on this comparison, which may be fed into the PWM controller 206 in order to adjust the phase of the second inverter 103, so that it may be synchronised with the first inverter 102. In this way, the phase control circuit may be configured selectively to advance or retard the PWM signal to provide the necessary synchronisation. Further details about the phase control circuit 201 are described with reference to Figure 3. The current share control circuit 202 may be configured to compare the output current of the second inverter 103 with the shared current reference, which, as described above, corresponds to the sum and averaged current signals of all inverters present on a current share bus of the HFAC system. This comparison may help the system to determine whether equal current sharing is taking place, and if it is not, to help determine the error between the output current and the shared current reference. The current share control circuit 202 may also be configured to generate a local current adjustment value based on this comparison, which may be fed into the magnitude control circuit 203 in order to help determine how the output of the second inverter 103 should be adjusted to ensure equal current sharing. The magnitude control circuit 203 may be configured to detect a magnitude indication of the output waveform of the second inverter 103 and to receive the local current adjustment from the current share control circuit 202. The magnitude control circuit 203 may also be configured to compare these two inputs, and then compare the output of this comparison with a magnitude reference signal. The magnitude control circuit 203 may also be configured to generate a magnitude control signal based on these comparisons, which may represent a required adjustment to the duty cycle of the second inverter 103 in order to rectify the local current adjustment. In this way, the magnitude control circuit may be configured to determine a duty cycle adjustment based on comparing the magnitude indication and the local current adjustment and then adjust the magnitude control signal based on said comparing. This duty cycle adjustment is represented by the magnitude control signal, which may be fed into the PWM controller 206 such that the duty cycle of the second inverter 103 may be adjusted. In doing so, this may adjust the power supplied by the second inverter 103, which correspondingly adjusts the magnitude of the pulses applied to the gate drives. This may help to ensure equal current sharing. The frequency control circuit 204 may be configured to compare the frequency of the second inverter 103 with a frequency reference signal that represents the frequency of the first inverter 102. In doing so, the frequency control circuit 204 may be configured to determine a frequency error based on these inputs. The frequency control circuit 204 may also be configured to generate a frequency control signal representative of the frequency error based on this comparison, which may be fed into the PWM controller 206 of the phase shift modulation circuit 205 in order to adjust the frequency of the second inverter 103, so that it may be synchronised with the first inverter 102. In this way, the frequency control circuit 204 may be configured selectively to increase or decrease the frequency of the PWM signal to provide the necessary synchronisation. Further details about the frequency control circuit 204 are described with reference to Figure 5. The phase shift modulation circuit 205 may be configured to receive the phase control signal from the phase control circuit 201, the magnitude control signal from the magnitude control circuit 203 and the frequency control signal from the frequency control circuit 204, and then perform the necessary phase shift modulation on the PWM signal. More specifically, the PWM controller 206 of the phase shift modulation circuit 205 may be configured to receive the phase control signal, the magnitude control signal and the frequency control signal and, based on these inputs, generate a PWM signal and provide this signal to the gate drives 207. This PWM signal may be adjusted based on any combination of the phase control signal, the magnitude control signal and the frequency control signal, such that the duty cycle and / or phase and / or frequency of the second inverter 103 may be adjusted as appropriate. In use, the first inverter 102 may function as a master inverter and the second inverter 103 may function as a slave inverter. The first inverter 102 may establish its own phase reference as the shared phase reference and may then switch on its output enable switch so that its HFAC voltage is present on the HFAC power distribution bus 106. The first inverter 102 may also establish its own output current on the current shared bus as a shared current reference. The second inverter 103 may sense its own output voltage phase by way of a phase sensor in the phase control circuit 201. This may then be compared with the shared phase reference, which, as described, may comprise the phase reference of the first inverter 102. The error between the two phases may be passed on to a phase controller of the phase control circuit 201, which may then generate a phase control signal based on this error. Further details about the operation of the phase control circuit 201 are described with reference to Figure 3. The phase control signal may be fed into the PWM controller 206. The phase control signal may be compared with a triangular wave of the PWM controller 206 and its crossing points may be used to generate a delay pulse corresponding to a required delay time to be applied to the gate drives 207. For example, if the phase error is lagging, the delay pulse will reflect the time that the gate drive signals need to be shifted forward by in order to correct the phase error. If the phase error is leading, the delay pulse will reflect the time that the gate drive signals need to be shifted backwards by in order to correct the phase error. The triangular wave may be implemented by analogue or software means. The PWM signal sent by the PWM controller 206 may then be selectively advanced or retarded based on this comparison in order to control the output of the gate drives 207 so that the phase of the second inverter 103 matches the phase of the first inverter 102, which corresponds to the shared phase reference. At this point, the phases of the first inverter 102 and the second inverter 103 have been synchronised. The second inverter 103 may then receive instructions from the first inverter 102 to participate in output current sharing. The second inverter 103 may switch on its output connect switch so that its output voltage is present on the HFAC power distribution bus 106. The second inverter 103 may sense its own output current by way of a current sensor in the current share control circuit 202. This output current may then be compared with the shared current reference, which, as described, may comprise the sum and averaged current sense signals of all inverters present on the bus. A current controller within the current share control circuit 202 may then generate the local current adjustment signal based on the difference between the sensed output current of the second inverter 103 and the shared current reference. The second inverter 103 may then sense a magnitude of the pulses which are presently being applied to its switches by way of a magnitude sensor in the magnitude control circuit 203. This magnitude may then be compared with the local current adjustment, which is also fed into the magnitude control circuit 203. An output of this comparison may be compared with a magnitude reference signal, which may be fixed. This may scale up or scale down the initial output. The final output of the magnitude control circuit 203 is a magnitude control signal. Further details about the operation of the magnitude control circuit 203 are described with reference to Figure 4. The magnitude control signal may then be fed into the PWM controller 206. The magnitude control signal may be compared with a triangular wave of the PWM controller 206 and its crossing points may be used to determine how to adjust the duty cycle of the second inverter 103. In this case, the duty cycle may represent the time for which two corresponding gates of a gate pair (e.g. gates A and D) of the secondary inverter 103 are both on. The duty cycle may be increased or decreased by varying the magnitude of the pulses applied to the gates. For example, if current is being drawn from the second inverter 103, the amount of overlap of the gates (i.e. the duty cycle) may need to be increased so as to increase the power transferred. The PWM controller 206 may then adjust the PWM signal based on this comparison in order to control the output of the gate drives 207 so that the duty cycle is adjusted to the required level. The second inverter 103 may sense its own output frequency by way of a frequency sensor in the frequency control circuit 204. This may then be compared with the frequency of the first inverter 102. The error between the two frequencies may be passed on to a frequency controller of the frequency control circuit 204, which may then generate a frequency control signal based on this error. Further details about the operation of the frequency control circuit 204 are described with reference to Figure 5. The frequency control signal may be fed into the PWM controller 206. The frequency of the triangular waveform of the PWM controller 206 may then be adjusted based on the frequency control signal, thus adjusting the frequency of the PWM signal that is to be applied to the gate drives 207. As a result the frequency of the gate drive signals will be adjusted, such that the second inverter 103 may operate at the same frequency as the first inverter 103. This may also have the effect of cancelling out any phase error between the first inverter 102 and the second inverter 103. In the event of failure of the first inverter 102, the second inverter 103 may be configured as the master inverter. Although only a first inverter 102 and a second inverter 103 are described, as discussed it should be understood that any number of inverters may be present in the system. Processes for determining which inverter should be configured as the master inverter are described below. For simplicity, again only two inverters will be described. If all inverters are off by default, both inverters may be switched on together. A “Power On” signal may be sent out by both inverters to each other via a communication line or bus. The inverter that receives this signal first may be designated as the slave inverter with a unique ID number, while the other inverter may be designated as the master inverter with another unique ID number. If additional slave inverters are inserted, the unique ID numbers of the inverters in the system are shared and monitored by each slave inverter. The slave inverters may assign a hierarchical order in order to determine which inverter should take over as the next master inverter in the event of failure of the master inverter. Alternatively, if one of the inverters is already on, it will have already asserted itself as the master inverter by default. Any additional inverters that are inserted will switch on and then receive a communication informing them that a master inverter has already been assigned. These inverters will assign themselves as slave inverters with their own unique ID numbers and will remain in standby mode until requested to participate in output current mode sharing. the unique ID numbers of the inverters in the system are shared and monitored by each slave inverter. The slave inverters may assign a hierarchical order in order to determine which inverter should take over as the next master inverter in the event of failure of the master inverter. With regard to the phase shift modulation process, it should be noted that in another embodiment, the centre-aligned PWM may be applied with a frequency increment or reduction in order to cancel out any phase error. Figure 3 shows a functional block diagram 300 of a phase control circuit, such as phase control circuit 201 from Figure 2. Phase control circuit 201 may comprise a phase sensor 301, into which an HFAC output voltage may be fed. The HFAC output voltage may comprise the voltage at an output of the transformer 105 which couples the second inverter 103 to the HFAC power distribution bus 106. Specifically, this input may be a sine wave output voltage waveform feedback signal. An output of the phase sensor 301 may be a phase sensor waveform. The phase sensor waveform may be a unipolar square pulse waveform where the low and high portions are in sync with the negative going and positive going portions of the input waveform. The phase sensor 301 may comprise a zero crossing detector comparator circuit. Phase control circuit 201 may further comprise a shared phase reference circuit 302, into which the shared phase reference may be fed. As described, the shared phase reference may be the phase reference of the first inverter 102. Specifically, the output voltage of the first inverter 102 may be fed into the shared phase reference circuit. This output voltage may comprise the voltage at an output of the transformer 104 which couples the first inverter 102 to the HFAC power distribution bus 106. More specifically, this input may be a sine wave, square, sawtooth or triangle carrier reference waveform. An output of the shared phase reference circuit 302 may be a shared phase reference waveform. The shared phase reference waveform may be a unipolar square pulse waveform where the low and high portions are in sync with the negative going and positive going portions of the input waveform. The shared phase reference circuit 302 may comprise a zero crossing detector comparator circuit. Phase control circuit 201 may further comprise a phase error detector circuit 303, into which the outputs of the phase sensor circuit 301 and the shared phase reference circuit 302 may be fed. An output of the phase error detector circuit 303 may be a pulsed waveform that represents the difference between the phases of the output voltages of the two inverters. Phase control circuit 201 may further comprise a phase controller 304, into which the pulsed waveform may be fed. An output of the phase controller 304 may be the phase control signal, which has been described with reference to Figure 2. The phase sensor 301 may be configured to sense the phase of the output voltage of the second transformer 103 and to generate a signal representing this phase that can be used by the rest of the phase control circuit 201. The shared phase reference circuit 302 may be configured to determine the shared phase reference and to generate a signal representing this reference phase that can be used by the rest of the phase control circuit 201. The phase error detector circuit 303 may be configured to determine the error between the phase of the second inverter 103 and the shared phase reference. The phase controller 304 may be configured to generate a phase control signal based on this error that may be used by the PWM controller 206 in order to adjust the phase of the second inverter 103 if necessary. In use, the output voltage of the second inverter 103 may be fed into the phase sensor 301. This output voltage may firstly be scaled down by means of a transformer winding and / or a voltage divider to a voltage range which is suitable for the phase sensor 301. A zero crossing detector comparison may take place, with the output being a phase sensor waveform. The output voltage of the first inverter 102 may be fed into the shared phase reference circuit 302. A zero crossing detector comparison may take place, with the output being phase reference waveform. The phase sensor waveform and the shared phase reference waveform may then both be fed into the phase error detector circuit 303, such that any error between the two waveforms can be detected. The phase error detector circuit 303 may then generate two independent unipolar pulse waveforms that are synchronised to one another. The on-time duration of each pulse depends on the amount of error detected. A novel full bridge amplifier circuit is biased for maximum switching speed and minimal waveform distortion which extracts the relevant lead / lag and phase error information from the two unipolar pulse waveforms and outputs a single square bipolar pulsed waveform. This waveform may have a positive polarity if the input feedback signal phase lags the reference signal phase, or may have a negative polarity if the input feedback signal phase leads the reference signal phase. The duration of the pulse may be linearly related to the amount of phase difference. Any remaining non- linearity can be compensated where required by additional hardware or software means. Alternatively, the output waveform polarity described above can be inverted by swapping the nodes of the amplifier circuit to suit the requirements of an op amp based negative feedback phase controller. Finally, the bipolar pulse output waveform is fed into the phase controller 304, which may output a linearised and differentially amplified bipolar phase control signal. The differential amplified output is buffered by a current gain amplifier stage and then low pass filtered to remove high frequency AC voltage ripple. The resulting phase control signal will then be fed to the PWM controller in order to impose an appropriate amount of time lead or lag on the inverter gate drive logic signals so that the phase error is reduced to a minimum, as described with reference to Figure 2. Figure 4 shows a functional block diagram 400 of a magnitude control circuit, such as magnitude control circuit 203 from Figure 2. Magnitude control circuit 203 may comprise a magnitude sensor 401, into which an HFAC output voltage may be fed. The HFAC output voltage may comprise the voltage at an output of the transformer 105 which couples the second inverter 103 to the HFAC power distribution bus 106. Specifically, this input may be a sine wave output voltage waveform feedback signal. An output of the magnitude sensor 401 may be a magnitude sensor waveform. Magnitude control circuit 203 may further comprise a magnitude error detector circuit 402, into which the magnitude sensor waveform and the local current adjustment from the current control circuit 202 may be fed. An output of the magnitude error detector circuit 402 may be a waveform that represents the difference between the magnitude of the output voltage of the second inverter 103 and the magnitude required to compensate for the local current adjustment. Magnitude control circuit 203 may further comprise a magnitude reference circuit 403. The magnitude reference circuit 403 may generate a magnitude reference waveform, which may be a reference signal that has a fixed value. The magnitude reference waveform may also be referred to as a magnitude reference signal. Magnitude control circuit 203 may further comprise a magnitude reference comparator 404, into which the magnitude error waveform and the magnitude reference waveform may be fed. An output of the magnitude reference comparator 404 may be a modified magnitude error waveform, which may be a scaled-up or scaled-down version of the magnitude error waveform. Magnitude control circuit 203 may further comprise a magnitude controller 405, into which the modified magnitude error waveform may be fed. An output of the magnitude controller 405 may be the magnitude control signal, which has been described with reference to Figure 2. The magnitude sensor 401 may be configured to sense the magnitude of the output voltage waveform of the second transformer 103 and to generate a signal representing this magnitude that can be used by the rest of the magnitude control circuit 203. The magnitude error detector circuit 402 may be configured to compare the local current adjustment with the magnitude sensor waveform and determine an error between the magnitude of the output waveform of the second inverter 103 and the magnitude required to compensate for the local current adjustment. The magnitude reference circuit 403 may be configured to provide a magnitude reference waveform that can be used by the rest of the magnitude control circuit 203. The magnitude reference comparator 404 may be configured to compare the magnitude error waveform with the magnitude reference waveform and modify (by scaling up or scaling down) the magnitude error waveform accordingly. The magnitude controller 405 may be configured to generate a magnitude control signal based on the error that may be used by the PWM controller 206 in order to adjust the duty cycle of the second inverter 103 if necessary. In use, the output voltage of the second inverter 103 may be fed into the magnitude sensor 401. This output voltage may firstly be scaled down by means of a transformer winding and / or a voltage divider to a voltage range which is suitable for the magnitude sensor 401. The magnitude sensor 401 may, after sensing the magnitude, rectify the signal and apply a low pass filter. The resulting magnitude sensor waveform and the local current adjustment may then both be fed into the magnitude error detector circuit 402, such that any error between the magnitude of the output waveform and the magnitude required to compensate for the local current adjustment can be detected. The magnitude error detector circuit 402 may then output a magnitude error waveform based on this error. This waveform may then be compared with the magnitude reference waveform provided by the magnitude reference circuit 403. This comparison may take place at the magnitude reference comparator 404, which modifies the magnitude error waveform by scaling it up or down based on the magnitude reference waveform, with which the magnitude error waveform may have a linear relationship. The result is the modified magnitude error waveform, which is fed into the magnitude controller 405. The magnitude controller 405 may output a linearised and differentially amplified bipolar magnitude control signal. The differential amplified output may then be buffered by a current gain amplifier stage and then low pass filtered to remove high frequency AC voltage ripple. The resulting magnitude control signal will then be fed to the PWM controller 206 in order to impose an appropriate amount of time lead or lag on one of the gates of each gate pair, so that the duty cycle is adjusted by the necessary amount to compensate for the local current adjustment and ensure equal current sharing, as described with reference to Figure 2. Figure 5 shows a functional block diagram 500 of a frequency control circuit, such as frequency control circuit 204 from Figure 2. Frequency control circuit 204 may comprise a frequency sensor 501, into which an HFAC output voltage may be fed. The HFAC output voltage may comprise the voltage at an output of the transformer 105 which couples the second inverter 103 to the HFAC power distribution bus 106. Specifically, this input may be a sine wave output voltage waveform feedback signal. An output of the phase sensor 501 may be a frequency sensor waveform. The frequency sensor waveform may be a unipolar square pulse waveform where the low and high portions are in sync with the negative going and positive going portions of the input waveform. The frequency sensor 501 may comprise a zero crossing detector comparator circuit. Frequency control circuit 204 may further comprise a shared frequency reference circuit 502, into which a shared frequency reference may be fed. The shared frequency reference may represent the frequency of the first inverter 102. Specifically, the output voltage of the first inverter 102 may be fed into the shared frequency reference circuit. This output voltage may comprise the voltage at an output of the transformer 104 which couples the first inverter 102 to the HFAC power distribution bus 106. More specifically, this input may be a sine wave, square, sawtooth or triangle carrier reference waveform. An output of the shared frequency reference circuit 502 may be a shared frequency reference waveform. The shared frequency reference waveform may be a unipolar square pulse waveform where the low and high portions are in sync with the negative going and positive going portions of the input waveform. The shared frequency reference circuit 502 may comprise a zero crossing detector comparator circuit. Frequency control circuit 204 may further comprise a frequency error detector circuit 503, into which the outputs of the frequency sensor circuit 501 and the shared frequency reference circuit 502 may be fed. An output of the frequency error detector circuit 503 may be a pulsed waveform that represents the difference between the frequencies of the output voltages of the two inverters. Frequency control circuit 204 may further comprise a frequency controller 504, into which the pulsed waveform may be fed. An output of the frequency controller 504 may be the frequency control signal, which has been described with reference to Figure 2. The frequency sensor 501 may be configured to sense the frequency of the output voltage of the second transformer 103 and to generate a signal representing this frequency that can be used by the rest of the frequency control circuit 204. The shared frequency reference circuit 502 may be configured to determine the shared frequency reference and to generate a signal representing this reference frequency that can be used by the rest of the frequency control circuit 204. The frequency error detector circuit 503 may be configured to determine the error between the frequency of the second inverter 103 and the shared frequency reference. The frequency controller 504 may be configured to generate a frequency control signal based on this error that may be used by the PWM controller 206 in order to adjust the phase of the second inverter 103 if necessary. In use, the output voltage of the second inverter 103 may be fed into the frequency sensor 501. This output voltage may firstly be scaled down by means of a transformer winding and / or a voltage divider to a voltage range which is suitable for the frequency sensor 501. A zero crossing detector comparison may take place, with the output being a frequency sensor waveform. The output voltage of the first inverter 102 may be fed into the shared frequency reference circuit 502. A zero crossing detector comparison may take place, with the output being a shared frequency reference waveform. The frequency sensor waveform and the shared frequency reference waveform may then both be fed into the frequency error detector circuit 503, such that any error between the two waveforms can be detected. The frequency error detector circuit 503 may then generate two independent unipolar pulse waveforms that are synchronised to one another. The on-time duration of each pulse depends on the amount of error detected. A novel full bridge amplifier circuit is biased for maximum switching speed and minimal waveform distortion which extracts the relevant frequency error information from the two unipolar pulse waveforms and outputs a single square bipolar pulsed waveform. This waveform may have a positive or negative polarity depending on how the frequency of the second inverter 103 differs from the frequency of the first inverter 102. The duration of the pulse may be linearly related to the amount of frequency difference. Any remaining non- linearity can be compensated where required by additional hardware or software means. Alternatively, the output waveform polarity described above can be inverted by swapping the nodes of the amplifier circuit to suit the requirements of an op amp based negative feedback frequency controller. Finally, the bipolar pulse output waveform is fed into the frequency controller 504, which may output a linearised differentially amplified bipolar frequency control signal. The differential amplified output is buffered by a current gain amplifier stage and then low pass filtered to remove high frequency AC voltage ripple. The resulting frequency control signal will then be fed to the PWM controller such that the frequency of the PWM signal, and therefore the frequency of the second inverter 103, can be adjusted accordingly. Figure 6A shows a series of plots 600 of signals relating to the phase synchronisation process described with reference to Figure 2. Specifically, Figure 6A shows a signal 601 corresponding to the magnitude control signal, as described with reference to Figure 2. For simplicity, the magnitude control signal 601 is shown here as being a constant signal. Figure 6A also shows a signal 602 corresponding to the phase control signal. As described, this signal is used to determine how much the gate drive signals need to be adjusted by in order to synchronise the phase of the second inverter 103 with the shared phase reference. The plots are split into three regions. Region 620 represents the second inverter 103 having a positive phase error with respect to the shared phase reference, region 630 represents the second inverter 103 having no phase error with respect to the shared phase reference, and region 640 represents the second inverter 103 having a negative phase error with respect to the shared phase reference. Signals 601 and 602 may be combined to produce signal 603, which represents the sum of the phase control signal and the magnitude control signal. Signal 603 may then be compared to a triangular waveform as part of the PWM process, which is represented by signal 604. Signal 605 represents the PWM signal. More specifically, the logic low state of signal 605 represents the duty cycle of the second inverter 103. Signal 605 is high when only one of the two gates that make up a pair of gates is on. For example, signal 605 may be high when gate A is on, but gate D is off, or vice versa. When signal 605 is high, power is not transferred from the second inverter 103 through these gates, since both gates of the gate pair must be on for this to take place. Signal 605 goes low when the second gate of the pair of gates also turns on, or when the gate that was already on turns off. This means that when signal 605 is low, the two gates that make up the respective pair of gates are either both on, meaning that power can be transferred, or both off, meaning that no power is transferred through these gates. In the case of Figure 6, only one gate (gate D) of a particular gate pair (gates A and D) is shown, but it should be understood that the same principles apply to gate A, and indeed to the other gate pair (gates B and C). Starting at region 620, in which the phase error is positive, whenever signal 603 crosses the falling edge of signal 604, a delay pulse is generated. The delay pulse can be seen in signal 606, which may be considered a delay pulse signal. When the pulse is generated, the delay pulse signal 606 switches from low to high and then remains high until signal 601, which represents the magnitude control signal, crosses the falling edge of signal 604, at which point signal 606 returns to low. More specifically, the delay pulse signal 606 switches between its low and high states whenever either of the signals 601 and 603 cross the falling edge of signal 604. Since the phase error is positive, signal 603 will cross the falling edge of signal 604 before signal 601 does, meaning that the delay pulse starts when signal 603 crosses the falling edge and ends when signal 601 crosses the falling edge. The width of this resulting delay pulse represents the time by which the phase of the second inverter 103 needs to be shifted in order to achieve phase synchronisation. More specifically, the delay pulse width represents the time by which the PWM signal 605 needs to be phase shifted in order to synchronise the phase of the second inverter 103 with the phase of the first inverter 102. Accordingly, the PWM signal 605 may be shifted backwards by the amount indicated by the delay pulse signal 606. Signal 607 represents the signal that is being applied to gate drive D of the second inverter 103 prior to the phase shift modulation. By shifting the PWM signal 605 as described above, signal 607 will be shifted by the same amount, as will the corresponding signal for gate drive A. More specifically, the delay pulse signal 606 may be applied to the relative gate drive and an XOR operation may be performed on signals 606 and 607. The output of this operation is signal 608, which represents the phase shifted gate drive signal. As can be seen, the net result of this operation is that the output of the gate drive has been shifted by an amount equal to the width of the delay pulse. As mentioned above, the same steps may be performed with respect to gate drive A (as well as to the other gate drive pair of gate drives B and C), at which point the phase of the second inverter 103 may be synchronised with the first inverter 102. Moving now to region 630, where the phase error is zero, it can be seen that no delay pulses are generated. This is because signals 601 and 603 both cross the triangular waveform 604 at the same points, so the delay pulse signal 606 goes from low to high and back to low at the exact same time. No shifting of signal 607 is therefore required, meaning that signal 608 is the same as signal 607. Moving now to region 640, in which the phase error is negative, whenever signal 601 crosses the falling edge of signal 604, a delay pulse is generated, as shown by delay pulse signal 606. When the pulse is generated, the delay pulse signal 606 switches from low to high and then remains high until signal 603, crosses the falling edge of signal 604, at which point signal 606 returns to low. More specifically, the delay pulse signal 606 switches between its low and high states whenever either of the signals 601 and 603 cross the falling edge of signal 604. Since the phase error is negative, signal 601 will cross the falling edge of signal 604 before signal 603 does, meaning that the delay pulse starts when signal 601 crosses the falling edge and ends when signal 603 crosses the falling edge. This is the opposite way round to when the phase error is positive. The width of this resulting delay pulse represents the time by which the phase of the second inverter 103 needs to be shifted in order to achieve phase synchronisation. More specifically, the delay pulse width represents the time by which the PWM signal 605 needs to be phase shifted in order to synchronise the phase of the second inverter 103 with the phase of the first inverter 102. Accordingly, the PWM signal 605 may be shifted forwards by the amount indicated by the delay pulse signal 606. By shifting the PWM signal 605 as described above, signal 607 will be shifted by the same amount, as will the corresponding signal for gate drive A. In this way, phase shift modulation may occur without altering the duty cycle of the second inverter 103. Each gate drive signal is shifted by the same amount, so the amount of overlap time between each gate in a gate pair remains the same. It should be appreciated that the use of delay pulse signal 606 is an optional step and that the phase control process can be conducted without signal 606. For example, the amount by which signal 607 needs to be shifted in order to produce signal 608 can be determined simply by utilising the crossing points of signal 604 as described above, but without representing this in a signal form and conducting an XOR operation. In such a method the time between the crossing points of signals 601 and 602 with signal 604 is determined to be the time by which signal 607 needs to be shifted and the PWM signal is therefore shifted to reflect this. Figure 6B shows a series of plots 650 of signals relating to the phase synchronisation process described with reference to Figure 2. Figure 6B is substantially similar to Figure 6A, as it shows signals 601, 602, 603, 604, 605, 607 and 608 from Figure 6A. Figure 6B does not show the delay pulse signal 606 – as mentioned with reference to Figure 6A, the use of signal 606 is optional. Figure 6B comprises signals 609 and 610, which are not present in Figure 6A. Signals 609 and 610 both show the duty cycle of the second inverter 103, which, as discussed, corresponds to the time during which both gates in a gate pair are on. Here, signals 609 and 610 show the duty cycle for gates A and D, although it should be understood that the same principles apply to the other gate pair of gates B and C. When signals 609 and 610 are high, both of gates A and D are on, and power can be transferred from the second inverter 103 via these gates. More specifically, signal 609 shows the duty cycle prior to any phase shift modulation, and signal 610 shows the duty cycle after phase shift modulation. In this way, signal 609 corresponds to signal 607 and signal 610 corresponds to signal 608. The process by which signal 607 (representing gate D) is phase shifted to provide signal 608 has already been described with respect to Figure 6A. It has also been described that the same process is applied to gate A, such that the duty cycle of this gate pair remains unchanged. This can be seen by signals 609 and 610. The width of the “high” section of signal 609 is the same as the width of the “high” section of signal 610, meaning that the duty cycle is unchanged. Instead, signal 609 is simply shifted by the same amount as signal 607. The phase of the second inverter 103 is therefore changed without affecting the duty cycle. Figure 7 shows a series of plots 700 of signals relating to the magnitude control process described with reference to Figure 2. Specifically, Figure 7 shows a signal 701 corresponding to the magnitude control signal, as described with reference to Figure 2. As described, this signal is used to determine how much the magnitude of the pulses applied to the second inverter 103 need to be adjusted by in order to achieve the desired effect. Figure 7 also shows a signal 702 corresponding to the phase control signal. For simplicity, the phase control signal 702 is shown here as being a constant signal. Signals 701 and 702 may be combined to produce signal 703, which represents the sum of the phase control signal and the magnitude control signal. Signal 703 may then be compared to a triangular waveform as part of the PWM process, which is represented by signal 704. Signal 705 represents the PWM signal. More specifically, the logic low state of signal 705 represents the duty cycle of the second inverter 103. Signal 705 is high when only one of the two gates that make up a pair of gates is on. For example, signal 705 may be high when gate A is on, but gate D is off, or vice versa. When signal 705 is high, power is not transferred from the second inverter 103 through these gates, since both gates of the gate pair must be on for this to take place. Signal 705 goes low when the second gate of the pair of gates also turns on, or when the gate that was already on turns off. This means that when signal 705 is low, the two gates that make up the respective pair of gates are either both on, meaning that power can be transferred, or both off, meaning that no power is transferred through these gates. In the case of Figure 7, the two gates used are the first pair (i.e. gates A and D), although it should be understood that the same principles apply to the second pair of gates B and C, but at different times to the first pair, since the two pairs can never be on at the same time. Signal 706 represents the signal that is applied to one of the gate drives of the second inverter 103 – in this case, gate D. Signal 707 represents the signal that is applied to a corresponding gate drive of the second inverter 103 – specifically, the other gate in the gate pair (in this case, gate A). Starting at a point in the cycle where both gates A and D are off (i.e. signals 706 and 707 are both low), whenever signal 703 crosses the rising edge of signal 704, signal 705 will switch to its high state. This may cause signal 707 to switch to its high state (i.e. this may cause gate A to turn on). When signal 703 crosses the next falling edge of signal 704, signal 705 will switch to its low state. This may cause signal 706 to switch to its high state (i.e. this may cause gate D to turn on). At this point, both gates A and D are on, meaning that power can be transferred from the second inverter 103 via these gates. When signal 703 crosses the next rising edge of signal 704, signal 705 will switch back to its high state again, which may cause signal 707 to switch to its low state (i.e. this may cause gate A to turn off). Power can no longer be transferred from the second inverter 103 via these gates, since only gate D is on. When signal 703 crosses the next falling edge of signal 704, signal 705 will switch back to its low state again, which may cause signal 706 to switch to its low state (i.e. this may cause gate D to turn off). This represents one complete cycle. Since signal 704 has a constant frequency, and the changes in state of signals 705, 706 and 707 are between signal 703 and 704, signals 705, 706 and 707 each have a constant frequency as well. No change is made to the frequencies of signals 706 and 707 in this process – rather, the result is that one or both of the signals are phase shifted in order to alter the amount of time in which both gate drives are on. This phase shift modulation therefore enables magnitude control without necessarily altering the overall phase of the second inverter 103. This is shown by signal 708, which represents the resulting output pulse of power caused by signals 706 and 707 both being in their high states (i.e. both gate drives being on). Depending on the overlap time of signals 706 and 707, the width of the pulses of signal 708 may vary, as may the magnitude of the resulting pulses of power. The wider the pulse width, the greater the amount of power transferred. As discussed, the overlap time may also be referred to as the duty cycle. If the system requires a different amount of power to be transferred, the magnitude control signal 701 will change accordingly. This results in different crossing points of signal 704, which causes the gate drives to switch between high and low at different times, thus resulting in a different amount of overlap and, subsequently, a different amount of power transfer. For example, if current is being drawn from the HFAC system, there may be a need to increase the duty cycle in order to transfer a greater amount of power, thus helping to keep the voltage of the second inverter 103 steady. The magnitude control signal may therefore vary if the output current changes, resulting in different crossing points with signal 704. This will result in different amounts of overlap between signals 706 and 707, which will adjust the duty cycle and the resulting power transfer accordingly. A frequency control method, such as the one described with reference to Figure 5, will now be described with reference to Figures 6 and 7. In particular, the triangular waveform of the PWM controller 205 (signal 604 from Figures 6A-B and signal 704 from Figure 7) will be described. This triangular waveform is generated from a voltage or current controlled oscillator (VCO) circuit block, whose frequency is proportional to the amplitude of the frequency control signal at its input. As described earlier, the frequency control signal is a linear DC output signal that comes from a frequency controller 504. If there is a frequency error between the first inverter 102 and the second inverter 103, the frequency control signal will reflect this, thus adjusting the frequency of the triangular waveform. This change in the triangular waveform frequency adjusts the slope of its rising and falling ramps, thus changing the intersection points of triangular waveform with the magnitude control signal and the phase control signal. As a result, the PWM frequency will change, thus changing the frequencies of the gate drives and the overall frequency of the second inverter 102. At the same time, the frequency control signal can also be used to change the value of the resonant tank network of the inverter so that the inverter resonant frequency matches closely with the PWM frequency for even better load current sharing, compared with just changing only the PWM frequency. Figure 8 is a flow chart describing a method 800 of outputting power in an HFAC system, such as the HFAC system 100 from Figure 1. The method may be performed by components of the HFAC system 100. Starting at step 801, the method 800 may comprise configuring a first inverter of the HFAC system as a master inverter and a second inverter of the HFAC system as a slave inverter. The first inverter may be the first inverter 102 from Figure 1 and the second inverter may be the second inverter 103 from Figure 1. As has been described with reference to Figure 2, the second inverter may comprise a PWM controller. Moving now to step 802, the method 800 may further comprise providing, by the first inverter, a phase reference signal. As has been described with reference to earlier Figures, the phase reference signal may correspond to the output voltage phase of the first inverter. Moving now to step 803, the method 800 may further comprise establishing, by the first inverter, an HFAC output voltage of the first inverter on an HFAC power distribution bus of the HFAC system. This may be achieved by switching on an output enable switch of the first inverter. Moving now to step 804, the method 800 may further comprise providing, by a PWM controller of the second inverter, a PWM signal for controlling gate drives of the second inverter to output power from the second inverter. The PWM signal may be synchronised with the shared phase reference by centre-aligned PWM. The PWM controller may be the PWM controller 206 from Figure 2. As has been described with reference to earlier Figures, the PWM signal may be based on the phase control signal and the magnitude control signal received by the PWM controller. This signal may instruct the gate drives to adjust the phase of the second inverter so that it is synchronised with the first inverter. Moving now to step 805, the method 800 may further comprise establishing, by the second inverter, an HFAC output voltage of the second inverter on the HFAC power distribution bus. This may be achieved by switching on an output enable switch of the second inverter. Moving finally to step 806, the method 800 may further comprise providing an HFAC voltage supply based on the HFAC output voltage of the first inverter and the HFAC output voltage of the second inverter to a plurality of devices positioned along the HFAC power distribution bus. In this way, current sharing between the two inverters may be achieved. The method may further comprise determining, by a phase control circuit of the second inverter, a phase error based on the phase reference signal and the HFAC output voltage, wherein the HFAC output voltage comprises the voltage at an output of a transformer which couples the second inverter to the HFAC power distribution bus. As has been described with reference to Figures 2 and 3, this phase error may represent the difference between the phases of the two inverters and may be used to generate the phase control signal. The method may further comprise providing, by the phase control circuit, a phase control signal based on the phase error. As has been described with reference to Figure 3, determining the phase error may comprise sensing, by the second inverter, an output voltage phase of the second inverter. Determining the phase error may also comprise comparing, by the second inverter, the output voltage phase of the second inverter with the phase reference signal. The method may further comprise adjusting the PWM signal based on the phase error. In this way, the adjusted PWM signal may instruct the gate drives to adjust the phase of the second inverter in order to reduce the phase error. The method may further comprise establishing, by the first inverter, an HFAC output current of the first inverter on a current share bus of the HFAC system and may also comprise establishing, by the second inverter, an HFAC output current of the second inverter on the current share bus. The method may further comprise determining, by a current share control circuit of the second inverter, a local current adjustment based on a shared current reference and the HFAC output current of the second inverter, wherein the HFAC output current of the second inverter comprises the current at an output of a transformer which couples the second inverter to the HFAC power distribution bus. As has been described with reference to earlier Figures, the shared current reference may comprise the sum and averaged current signals of all inverters present on a current share bus of the current share control circuit. In the scenario where the first and second inverters are the only two inverters present, the shared current reference comprises the sum and averaged current signals of both of these inverters. The method may further comprise determining, by a magnitude control circuit of the second inverter, a duty cycle adjustment based on the local current adjustment and a magnitude indication. The magnitude indication may be based on the output voltage of the transformer which couples the second inverter to the HFAC power distribution bus 106. The method may also comprise providing, by the magnitude control circuit, the duty cycle adjustment in the form of a magnitude control signal. As described with reference to earlier Figures, the duty cycle adjustment may be provided in the form of the magnitude control signal. Determining the duty cycle adjustment may comprise comparing the magnitude indication and the local current adjustment, and may further comprise comparing the output of this comparison with a magnitude reference signal. Providing the duty cycle adjustment may comprise providing the duty cycle adjustment to the PWM controller to adjust the HFAC output voltage such that the HFAC output current achieves equal output current sharing among the first inverter and the second inverter on the HFAC power distribution bus. The method may further comprise providing, by the first inverter, a frequency reference signal and selectively increasing or decreasing, by a frequency control circuit, a frequency of the PWM signal to provide frequency synchronisation with the first inverter. Selectively increasing or decreasing the frequency of the PWM signal may comprise determining, by the frequency control circuit, a frequency error based on the frequency reference signal and the HFAC output voltage and providing, by the frequency control circuit, a frequency control signal based on the frequency error. As has been described with reference to Figures 2 and 5, this frequency error may represent the difference between the frequencies of the two inverters and may be used to generate the frequency control signal. As described with reference to earlier Figures, establishing the HFAC output voltage of the first inverter on the HFAC power distribution bus may comprise switching on, by the first inverter, an output enable switch of the first inverter. Similarly, establishing the HFAC output voltage of the second inverter on the HFAC power distribution bus may comprise switching on, by the second inverter, an output enable switch of the second inverter. The method may further comprise configuring the second inverter as the master inverter in the event of failure of the first inverter. If the system comprises more than two inverters, the method may comprise configuring any one of the slave inverters as the master inverter in the event of failure of the first inverter. Any feature of any one of the examples disclosed herein may be combined with any selected features of any of the other examples described herein. For example, features of methods may be implemented in suitably configured hardware, and the configuration of the specific hardware described herein may be employed in methods implemented using other hardware. It will be appreciated from the discussion above that the embodiments shown in the Figures are merely exemplary, and include features which may be generalised, removed or replaced as described herein and as set out in the claims. With reference to the drawings in general, it will be appreciated that schematic functional block diagrams are used to indicate functionality of systems and apparatus described herein. It will be appreciated however that the functionality need not be divided in this way, and should not be taken to imply any particular structure of hardware other than that described and claimed below. The function of one or more of the elements shown in the drawings may be further subdivided, and / or distributed throughout apparatus of the disclosure. In some embodiments the function of one or more elements shown in the drawings may be integrated into a single functional unit. In some examples the functionality of the controller may be provided by a general purpose processor, which may be configured to perform a method according to any one of those described herein. In some examples the controller may comprise digital logic, such as field programmable gate arrays, FPGA, application specific integrated circuits, ASIC, a digital signal processor, DSP, or by any other appropriate hardware. In some examples, one or more memory elements can store data and / or program instructions used to implement the operations described herein. Embodiments of the disclosure provide tangible, non-transitory storage media comprising program instructions operable to program a processor to perform any one or more of the methods described and / or claimed herein and / or to provide data processing apparatus as described and / or claimed herein. The controller may comprise an analogue control circuit which provides at least a part of this control functionality. An embodiment provides an analogue control circuit configured to perform any one or more of the methods described herein. The above embodiments are to be understood as illustrative examples. Further embodiments are envisaged. It is to be understood that any feature described in relation to any one embodiment may be used alone, or in combination with other features described, and may also be used in combination with one or more features of any other of the embodiments, or any combination of any other of the embodiments. Furthermore, equivalents and modifications not described above may also be employed without departing from the scope of the invention, which is defined in the accompanyingclaims.

Claims

Claims 1. A redundant power supply for a high frequency alternating current, HFAC, system, the HFAC system comprising an HFAC power distribution bus configured to provide an HFAC voltage supply to a plurality of devices positioned along the HFAC power distribution bus to receive the HFAC voltage, the redundant power supply comprising: a first inverter and a second inverter, wherein the first inverter is configured as a master which provides a phase reference signal to the second inverter and the second inverter is configured as a slave to synchronise with the phase reference signal; wherein the second inverter comprises a PWM controller configured to provide a PWM signal for controlling gate drives of the second inverter to output power from the second inverter; and wherein the phase reference signal comprises a triangle wave and the PWM controller is configured to synchronise with the phase reference signal by centre-aligned pulse width modulation, PWM.

2. The apparatus of claim 1, wherein the second inverter comprises a phase control circuit, configured selectively to advance or retard the PWM signal to provide said synchronisation.

3. The apparatus of claim 2, wherein the phase control circuit is configured to: determine a phase error based on the phase reference signal and an HFAC output voltage, wherein the HFAC output voltage comprises the voltage at an output of a transformer which couples the second inverter to the HFAC power distribution bus; and provide a phase control signal based on the phase error.

4. The apparatus of any preceding claim, wherein the second inverter further comprises a current share control circuit configured to determine a local current adjustment based on ashared current reference and an HFAC output current, wherein the HFAC output current comprises the current at an output of a transformer which couples the second inverter to the HFAC power distribution bus.

5. The apparatus of claim 4, wherein the shared current reference comprises the sum and averaged current signals of all inverters present on a current share bus of the current share control circuit.

6. The apparatus of claims 4 or 5, wherein the second inverter further comprises a magnitude control circuit configured to provide a duty cycle adjustment based on the local current adjustment and a magnitude indication, the magnitude indication based on the output voltage of the transformer which couples the second inverter to the HFAC power distribution bus.

7. The apparatus of claim 6, wherein the magnitude control circuit is configured to: determine the duty cycle adjustment based on comparing the magnitude indication and the local current adjustment; and provide a magnitude control signal based on said comparing.

8. The apparatus of claims 6 or 7 wherein the magnitude control signal is provided to the PWM controller to adjust the HFAC output voltage such that the HFAC output current achieves equal output current sharing on the HFAC power distribution bus.

9. The apparatus of any of claims 6 to 8, wherein the first inverter is configured to provide a frequency reference signal and the second inverter further comprises a frequency control circuit configured selectively to increase or decrease a frequency of the PWM signal to provide frequency synchronisation with the first inverter.

10. The apparatus of claim 9, wherein the frequency control circuit is configured to: determine a frequency error based on the frequency reference signal and the HFAC output voltage; and provide a frequency control signal based on the frequency error.

11. A method of outputting power in a high frequency alternating current, HFAC, system, the method comprising: configuring a first inverter of the HFAC system as a master inverter and a second inverter of the HFAC system as a slave inverter, the second inverter comprising a PWM controller; providing, by the first inverter, a phase reference signal; establishing, by the first inverter, an HFAC output voltage of the first inverter on an HFAC power distribution bus of the HFAC system; providing, by the PWM controller of the second inverter, a PWM signal for controlling gate drives of the second inverter to output power from the second inverter wherein the PWM signal is synchronised with the phase reference signal by centre-aligned PWM; establishing, by the second inverter, an HFAC output voltage of the second inverter on the HFAC power distribution bus; and providing an HFAC voltage supply based on the HFAC output voltage of the first inverter and the HFAC output voltage of the second inverter to a plurality of devices positioned along the HFAC power distribution bus.

12. The method of claim 11, wherein the synchronising comprises selectively advancing or retarding the PWM signal by a phase control circuit of the second inverter.

13. The method of claim 12, further comprising: determining, by the phase control circuit, a phase error based on the phase reference signal and the HFAC output voltage, whereinthe HFAC output voltage comprises the voltage at an output of a transformer which couples the second inverter to the HFAC power distribution bus; and providing, by the phase control circuit, a phase control signal based on the phase error.

14. The method of claim 13, wherein determining the phase error comprises: sensing, by the second inverter, an output voltage phase of the second inverter; and comparing, by the second inverter, the output voltage phase of the second inverter with the phase reference signal.

15. The method of claim 14, further comprising adjusting the PWM signal based on the phase error.

16. The method of any of claims 11 to 15, further comprising: establishing, by the first inverter, an HFAC output current of the first inverter on a current share bus of the HFAC system; and establishing, by the second inverter, an HFAC output current of the second inverter on the current share bus.

17. The method of claim 16, further comprising determining, by a current share control circuit of the second inverter, a local current adjustment based on a shared current reference and the HFAC output current of the second inverter, wherein the HFAC output current of the second inverter comprises the current at an output of a transformer which couples the second inverter to the HFAC power distribution bus.

18. The method of claim 17, wherein the shared current reference comprises the sum and averaged current signals of all inverters present on a current share bus of the current share control circuit.

19. The method of claims 17 or 18, further comprising: determining, by a magnitude control circuit, a duty cycle adjustment based on the local current adjustment and a magnitude indication, the magnitude indication based on the output voltage of the transformer which couples the second inverter to the HFAC power distribution bus; and providing, by the magnitude control circuit, the duty cycle adjustment in the form of a magnitude control signal.

20. The method of claim 19, wherein determining the duty cycle adjustment comprises: comparing the magnitude indication and the local current adjustment.

21. The method of claims 19 or 20 wherein providing the duty cycle adjustment comprises providing the duty cycle adjustment to the PWM controller to adjust the HFAC output voltage such that the HFAC output current achieves equal output current sharing among the first inverter and the second inverter on the HFAC power distribution bus.

22. The method of any of claims 19 to 21, further comprising: providing, by the first inverter, a frequency reference signal; and selectively increasing or decreasing, by a frequency control circuit, a frequency of the PWM signal to provide frequency synchronisation with the first inverter.

23. The method of claim 22, wherein selectively increasing or decreasing the frequency of the PWM signal comprises: determining, by the frequency control circuit, a frequency error based on the frequency reference signal and the HFAC output voltage; andproviding, by the frequency control circuit, a frequency control signal based on the frequency error.

24. The method of any of claims 11 to 23, wherein: establishing the HFAC output voltage of the first inverter on the HFAC power distribution bus comprises switching on, by the first inverter, an output enable switch of the first inverter; and establishing the HFAC output voltage of the second inverter on the HFAC power distribution bus comprises switching on, by the second inverter, an output enable switch of the second inverter.

25. The method of any of claims 11 to 24, further comprising configuring the second inverter as the master inverter in the eventof failure of the first inverter.

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