Method for training machine learning models for stochastic substrates

Abstract

The present invention relates to a method for training signal processing pipeline for deployment to a programmable fabric of a target device. The method comprises obtaining a model and characterization data of the components of the target device, obtaining programmable parameter values of the signal processing pipeline. Next, a plurality of target devices is simulated. The simulated target devices are based on the characterization data, such that the simulated target devices represent digital twins and / or the stochastic variability of the plurality of target devices. Optimization methods are used to compute updates of the programmable parameter values of the programmable parameters for each of the simulated target devices independently, after which the programmable parameter value updates are reduced to a single update of the programmable parameter values of the signal processing pipeline.

Description

Method for training machine learning models for stochastic substratesTECHNICAL FIELD

[0001] The present invention relates to the optimization of parameters of programmable fabrics, in particular artificial neural networks and spiking neural networks, implemented (at least in part) as analog circuits on hardware devices, taking into account the stochastic variability of the hardware devices.BACKGROUND

[0002] Analog mixed-signal systems, fuzzy logic devices, approximate compute devices or in-material accelerators (optical or arising from deposited material properties) deliver results with lower latency and energy dissipation than comparable deterministic, digital solutions. However, these solutions have historically been more susceptible to device-level mismatch compared to conventional digital systems.

[0003] A traditionally utilized mechanism for training a neural network for deployment to an analog mixed-signal acceleration platform involved hardware-in-the-loop training (HITL). See for example Neuromorphic Hardware In The Loop: Training a Deep Spiking Network on the BrainScaleS Wafer-Scale System by Schmitt et al., 2017, arXiv: 1703.01909.

[0004] Within the HITL scheme, a gradient-based optimization mechanism would be used with the forward pass (feeding input data through the neural network to generate neuron activations and network-level predictions) executed on device and the error backward propagation (adjusting neural network parameters based on computed errors) is executed through a surrogate computational graph maintained on a host machine. A HITL flow requires that the observables of the neural network be injected into the surrogate computational graph, simulating the forward pass.

[0005] This training flow, while efficient in extracting performance from a target device, does not generalize to a family of target device instantiations, thus requiring additional per-device optimization or re-mapping.SUMMARY OF INVENTION

[0006] In order to solve the aforementioned problems, the subj ect-matter of the present claims is proposed.

[0007] The proposed method avoids the use of a target device in the loop by utilizing high- fidelity digital reconstructions thereof. Therefore, a Simulator-in-the-loop (SITL) methodology is employed, wherein the inner loop (forward pass through the computational graph) occurs in the high-fidelity simulator and the outer loop (backward pass through the computational graph, parameter updates) is handled by the automatic differentiation framework. As an example of an automatic differentiation framework, Pytorch can be used.

[0008] The method described here enables the training of a single set of parameters that can be deployed without retraining to a large number of chips, that accelerate the operation of the neural network,.

[0009] The method starts by training a principal neural network in a map-reduce fashion. During the map phase, the principal neural network is mapped onto many independent simulated chips, each one with different network parameters from each other, and a forward computational graph execution is performed. This phase includes an error gradient computation. During the reduce phase, the computed gradients are applied to the principal network. The cycle of map-reduce phases continues until convergence is achieved. The resultant network, defined as the combination of topology, neuron and synapse parameters, can be represented in a binary or textual representation and deployed to many instances of the target hardware.

[0010] According to a first aspect of the disclosure a method for training a signal processing pipeline comprising a neural network, for deployment to a programmable fabric of a target device, is disclosed. The method may comprise one or more of the following steps.

[0011] In a first step, obtaining a model of a plurality of components of the target device, wherein the model describes information of the plurality of components and how the components interact. In a second step, obtaining programmable parameter values for a plurality of programmable parameters of the signal processing pipeline, wherein the programmable parameter values are compatible with the signal processing pipeline and the target device. In a third step, obtaining characterization data of the plurality of components of the target device, wherein the characterization data comprises measured component information of at least a portion of the components of a plurality of instances of the target device and / or stochastic variability information of at least a portion of the components of the plurality of instances of the target device. In a fourth step, simulating the plurality of instances of the target device using the model, wherein the model of each target device instance is configured with the programmable parameter values and the characterization data for the target device instance. Ina fifth step, using one or more optimization methods to compute updates of the programmable parameter values of the programmable parameters for each of the simulated target device instances independently. In a sixth step, reducing the programmable parameter value updates for each of the simulated target device instances to a single update of the programmable parameter values of the signal processing pipeline. In an eight step, updating the programmable parameter values of the signal processing pipeline with the single update of the programmable parameter values of the signal processing pipeline.

[0012] In an embodiment of the first aspect, the method may further comprise: checking whether a target device performance threshold is reached or convergence is reached using the signal processing pipeline with the updated programmable parameter values; and repeating the above steps if the target device performance threshold or convergence is not reached.

[0013] In an embodiment of the first aspect, the method may further comprise deploying the signal processing pipeline with the updated programmable parameter values to the programmable fabric of the target device if the target device performance threshold or convergence is reached.

[0014] In an embodiment of the first aspect, the model of each target device instance may be configured with characterization data for the target device instance in such a way that the simulated target device instances represent digital twins of the number of target device instances and / or represent the stochastic variability of the plurality of target device instances.

[0015] In an embodiment of the first aspect, the step of obtaining programmable parameter values may comprise: initializing the programmable parameters of the signal processing pipeline; optimizing the programmable parameters by performing a high-level simulation until an initial acceptance threshold or convergence is achieved.

[0016] In an embodiment of the first aspect, the step of obtaining programmable parameter values further comprises: quantizing the programmable parameters to be compliant with an available parameter resolution when the signal processing pipeline is deployed to the programmable fabric of the target device; and preferably performing a further optimization of the set of values of the quantized programmable parameters by performing a high-level simulation until a second initial acceptance threshold or convergence is achieved, to recover any performance loss from the quantization step.

[0017] In an embodiment of the first aspect, the step of obtaining characterization data comprises operating and observing the behavior of at least one of the plurality of target devices.

[0018] In an embodiment of the first aspect, the stochastic variability of the plurality of components of the target device may comprise stochastic variability between the plurality of target hardware devices and / or stochastic variability within each of the target hardware devices over time; and the stochastic variability may be caused by device-level mismatch, either through fabrication inaccuracies or analog circuit behavior under process, voltage, and temperature variations.

[0019] In an embodiment of the first aspect, at least one of the simulated target device instances which the simulation implements may be a twin of a non-simulated target device instance by replicating in simulation the behavior of individual components of the nonsimulated target device instance; and / or at least one of the simulated target device instances which the simulation implements may be a twin of a potential, but fictitious target device instance by abstracting the behavior of individual components into one or more distributions from which the behavior of simulated components of the simulated target device instance are drawn.

[0020] In an embodiment of the first aspect, the step of using one or more optimization methods to compute updates of the programmable parameter values of the programmable parameters comprises using gradient-based optimization methods or derivative-free optimization methods.

[0021] In an embodiment of the first aspect, the step of using one or more optimization methods (107) to compute updates of the programmable parameter values of the programmable parameters may comprise a forward pass and an error-computing backward pass through the simulated target devices, in particular the simulated programmable fabric; and the forward pass may be executed on a high-fidelity System-on-Chip simulator and the error-computing backward pass is handled by a computational framework implementing automatic differentiation.

[0022] In an embodiment of the first aspect, the step of reducing the programmable parameter value updates for each of the simulated target devices may comprise averaging each of the programmable parameter value updates per programmable parameter value over all the simulated target devices or choosing the update of the programmable parameter values from the possible updates that minimizes the variability of the simulated target devices to a level where it falls within two or three standard deviations from an acceptable value.

[0023] In an embodiment of the first aspect, the programmable fabric may comprise a spiking neural network or an artificial neural network; and / or the target devices may comprise analogmixed-signal systems, fuzzy logic devices, approximate compute devices or in-material accelerators.

[0024] In an embodiment of the first aspect, the programmable fabric may comprise a spiking neural network and the target devices comprise analog-mixed signal systems, more preferably the target devices may comprise analog mixed-signal systems with an on-chip spiking neural network acceleration fabric.

[0025] In an embodiment of the first aspect, the programmable parameters may comprise at least one of: spiking neuron model parameters such as membrane potential threshold, membrane time constant, resting potential, refractory period, adaptive factors such as threshold adaptation time constants; synaptic weight parameters such as synaptic weights, synaptic time constants, adaptive factors such as short-term synaptic weight scaling; network topology parameters such as number of neurons, connectivity pattern, network architecture; learning rule parameters such as spike-timing-dependent plasticity (STDP) parameters, optimizer hyperparameter learning rate; and input encoding parameters such as spike encoder mapping between data and spike rate, and spike encoder thresholds.

[0026] In an embodiment of the first aspect, the programmable parameters may comprise the weights of the synaptic elements of the spiking neural network, and the programmable parameter values may comprise the weight values of the weights; and the step of using optimization methods (107) to compute updates of the programmable parameter values of the programmable parameters may comprise obtaining an error per weight for all the weights of each of the simulated target device instances.

[0027] According to a second aspect of the disclosure, a device is disclosed comprising a programmable fabric, wherein the programmable fabric is trained and subsequently deployed to the device according to first aspect of the disclosure.

[0028] According to a third aspect of the disclosure, a computer system is disclosed for training a signal processing pipeline, comprising a neural network, for deployment to a programmable fabric of a target device. The computer system may comprise a memory, a processor and an output.

[0029] The memory may comprise: a model of a plurality of components of the target device, describing information of the plurality of components and how these interact; programmable parameter values for the programmable parameters of the signal processing pipeline, wherein the programmable parameter values are compatible with the target device and the signal processing pipeline; characterization data (200) of the plurality of components of the targetdevice, wherein the characterization data comprises measured component information of at least a portion of the components of a plurality of instances of the target device and / or stochastic variability information of at least a portion of the components of the plurality of instances of the target device.

[0030] The processor may perform the method according to the first aspect of the disclosure, wherein the steps of obtaining the model, the programmable parameter values and the characterization data may be performed by respectively obtaining the model, the programable parameter values and the characterization data from the memory.

[0031] In an embodiment of the third aspect, when the processor performs the step of deploying the signal processing pipeline with the updated programmable parameter values to the programmable fabric of the target device, the step of deploying may be performed by saving the updated programmable parameter values to the memory or a permanent storage device and using the output to initialize the programmable fabric on the target device using the updated programmable parameter values.BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Embodiments will now be described, by way of example only, with reference to the accompanying drawings in which corresponding reference symbols indicate corresponding parts, and in which:

[0033] FIG. 1 shows a neural network development lifecycle targeting deployment on many physical instantiations of a device.DESCRIPTION OF EMBODIMENTS

[0034] Hereinafter, certain embodiments will be described in further detail. It should be appreciated, however, that these embodiments should not be construed as limiting the scope of protection for the present disclosure.

[0035] This invention relies on an optimizer responsible for tuning model parameters to reduce the error compared to a pre-defined objective function. A possible instantiation implements supervised and gradient-based learning relying on frameworks enabling auto differentiation, such as PyTorch (see https: / / pytorch.org / ) or TensorFlow (see https: / / www.tensorflow.org / ). In the absence of a gradient based optimization scheme, a gradient-free scheme can be used instead.

[0036] Furthermore, the generic optimization platform is combined with a high-fidelity system simulation environment that captures the salient features of the System-on-Chip (SoC). There is no limitation here on the level of heterogeneity or complexity of the SoC; increased complexity would likely incur additional costs in terms of duration of training.

[0037] The hardware utilized for this invention can for example be Innatera’ s Spiking Neural Processors, which are analog mixed-signal devices with an on-chip spiking neural network acceleration fabric, although this choice of system is not a limiting use case.

[0038] The chips onto which a principal network is ultimately deployed is assumed to have been calibrated, although this is not a strict requirement. The calibration process involves the modification of on-chip control parameters to bring the operation of individual components within a similar operating range to each other or within a prescribed operational range. This process also has the effect of bringing the neural network’s behavior within a nominal, guaranteed range.

[0039] FIG. 1 describes the process 100 of training a neural network or equivalent parameterized machine learning or artificial intelligence model and deploying it on an acceleration device. In particular, it shows a neural network development lifecycle targeting deployment on many physical instantiations of a device.

[0040] For ease of reading, the components before (e.g. preprocessing or encoding) and after (postprocessing or decoding) the network, including the network itself, are referred to by the short hand “principal network” or “network”, used interchangeably.

[0041] The process 100 comprises a high-level simulation 100A, a system simulation 100B and hardware deployment 100C.

[0042] In a first step 101, a topology for the model is selected and instantiated. An arbitrary topology could be selected here, for example: a shallow feedforward network, a recurrent network, a deep network with residual connections or even a convolutional neural network. Note that this list of examples is non-exhaustive and meant only for exemplification.

[0043] After the topology for the model is selected and instantiated, the parameters of the model are initialized in step 102. For example, the weights are initialized with a standard Xavier initializer or with more exotic and SNN-oriented initialization techniques, while other neurosynaptic parameters can be initialized manually.

[0044] After the parameters of the model are initialized, the parameters are subsequently optimized in step 103 until convergence or an acceptance threshold is achieved (i.e., the test A which checks whether the model’s performance passes the acceptability threshold returns no(N) and the process moves back to step 103). In this learning or optimization process, the network’s operation can be simulated with a lower precision simulator that is faster to execute but provides a higher-level abstraction of the target deployment hardware. This first phase of optimization can thus act as an initialization phase for the next step in network optimization.

[0045] Once the model performance passes an acceptability threshold (i.e., the test A which checks whether the model’s performance passes the acceptability threshold returns yes (Y)), the parameters involved in its operation are quantized in step 104 to be compliant with the available on-chip parameter resolution and range. For example, a 6-bit quantization of the weights can be selected, with additional 6- or 7-bit quantization for other neuro- synaptic parameters such as neuron input current gains or refractory period, or synapse peak amplitude or decay.

[0046] The quantized network or model can be optionally further optimized to recover any performance loss from the quantization step.

[0047] The resultant network of some or all of the steps 101-104 (steps 101-104 making up the high-level simulation 100A) is considered to be the (potentially pre-trained through steps 102-104) principal network to be optimized with the view to deploy to many devices.

[0048] Instead of performing steps 101-104, the method may comprise simply obtaining a set of programmable parameter values for the programmable parameters of the signal processing pipeline e.g. by loading them from a description on disk, and obtaining characterization data 200 of the plurality of components of the target device.

[0049] The model of the plurality of components of the target device describes information of the plurality of components and how these interact. The programmable parameter values are compatible with the target device and the signal processing pipeline.

[0050] That the programmable values are compatible with the target device and the signal processing pipeline may mean that the values of these parameters meet certain criteria to function correctly within the given hardware (target device) and software (signal processing pipeline) environment. For example, the parameter values should be within the limits of the target device’s resources, such as memory size, processing power, and available computational units. Furthermore, the parameter values should for example be in a format or datatype that the hardware can process. As a further example, the parameters should allow the pipeline to meet the timing requirements of the target device. This includes processing time per operation and overall latency constraints. Furthermore, the parameter values should work correctly with the algorithms used in the signal processing pipeline. This means for example they should help theneural network and other components perform their intended functions without causing errors or suboptimal performance. As a further example, the parameters should adhere to the configuration standards and protocols expected by the pipeline components. This includes conforming to expected ranges, scales, and initialization conditions. Furthermore, for example, the parameters should be suited to the programmable fabric of the target device. This could mean they should align with the way the programmable fabric is configured and used for signal processing tasks.

[0051] The characterization data comprises determined component information of the plurality of components of a number of target devices and / or stochastic variability information of the plurality of components of the number of target devices;

[0052] In step 105, the principal network is prepared by performing any additional checks or operations required to simulate the network within the system simulation platform. For example, the signal processing pipeline may be represented using a different format or representation to be used by the system simulator, or timing and bandwidth requirements could be verified here because the upstream simulator could not have sufficient data or accuracy to perform.

[0053] Next, in step 106, a number of devices N are simulated. These devices represent stochastic variability of the hardware onto which the principal network needs to be deployed. These can also be digital twins of a real target devices, obtained through measurement. Or these can be digital twins of a fictive target devices. The principal network is fine-tuned by mapping and its operation simulated onto the N simulated devices. One could use the same mapping onto all devices or a refined mapping per device. A single mapping solution could entail the creation of a single configuration file for many devices that implements a fixed partition, placement and routing for the network. A refined mapping solution could entail different placements, partitions or even routing that could result in a configuration file per device. A refined mapping could be created by applying additional optimization algorithms within the mapper to minimize the error between desired component behavior and available range of physical components.

[0054] In order to simulate the N devices, characterization data 200 is used. The characterization data 200 is produced through appropriately driving and subsequently observing the behavior of the device, for example a component or circuit, under test. One can iteratively set each possible value for the control currents on the device and record the effect on the parameter one observes. The relationship between the control current and parameterbehavior as well as parameter mismatch across a chip and over time may be called characterization data. For the generation of the characterization data an iterative configure then estimate process is used wherein for example a control signal is swept from its minimum to its maximum range and the impact on the parameter it implements is estimated. This process yields information regarding the implemented parameter ranges and mismatch on a particular physical device. The resulting characterization data 200 (also called device information) can be utilized in two exemplary ways.

[0055] In a first way, the characterization data 200 is used ad litteram. The behavior of individual components is replicated in simulation, therefore each of the N devices which the simulation implements is a twin of a real, physical chip. In a second way, the characterization data is used in a statistical manner. The behavior of individual components is abstracted into parameter distributions from which the simulated components are drawn, therefore each of the N devices which the simulation implements is a twin of a potential, but fictitious, chip.

[0056] The interpretation of the characterization data 200 allows for flexibility in the solution’s applicability and performance. In one approach, the characterization data 200 can be utilized to create highly optimized neural networks for a relatively small number of known devices. Alternatively, the characterization data 200 can be used to deploy a target network to a large number of devices, therefore creating a generalist network.

[0057] The characterization data 200 or device information can comprise statistical information about how individual devices operate statistically. This may allow one to simulate the number of devices N using the statistical information. For example, the statistical information indicates that a particular parameter of the device when fabricated follows a particular statistical distribution. The devices can then be simulated following the statistical distribution.

[0058] For example, an accelerator (accelerators are hardware devices designed to perform specialized computations more efficiently than general-purpose processors) can implement a particular spiking neural network in hardware. For this reason, the accelerator comprises synaptic elements and neurons, for example implemented as (analog) circuitry. Because of fabrication and operating restrictions, certain parameters of such circuitry will follow a statistical distribution (over multiple devices or within a device, or over time) when fabricated.

[0059] With respect to the synaptic elements for example, the damping- or gain factor can be non-linear, the damping- or gain factor thus having a statistical distribution. The (spiking) neurons for example use an activation function, which takes as input spikes, integrates the inputover time within a internal state parameter, checks the internal state against a threshold function, and then fires when the threshold is reached or exceeded. However, because of the implementation as analog circuitry, the threshold function is not a static function but can vary e.g., by 10% of the actual threshold function value. Hence, also the threshold function can follow a statistical distribution.

[0060] One can thus extract real statistical information from a number of devices and use this as characterization data 200. The characterization data 200 can then be used to generate artificial devices, of which a particular number N are then simulated.

[0061] The stochastic variability of targeted hardware devices was for example described in applications PCT / EP2019 / 081662 and PCT / EP2021 / 077323.

[0062] Optimization methods, such as for example gradient-based optimization methods or derivative-free optimization methods, are used in step 107 to compute parameter updates of the principal network for each of the N simulated devices independently. Gradient-based optimization methods may update parameters so that the derivative or gradient of the provided objective loss function is reduced. Meanwhile, gradient-free methods, such as evolutionary algorithms, define a non-differentiable fitness function that is successively increased through random mutations. Either technique could be applied for the presented method to modify the parameters of the signal processing pipeline to optimise for a particular goal, e.g. minimum loss when deploying the principal network to the N simulated devices. In the gradient-based case the steps that are followed involve the forward pass (data inject at the input stage of the network is propagated through the network through activations, the loss calculation (the output predictions are compared to a true label using a loss function e.g. negative log-likelihood or categorial cross entropy which quantifies the difference between the predictions and ground truth), the backward pass (the gradients of the loss with respect to each parameter in the network is computed), and the parameter update phase (parameters are adjusted by a scaled amount of the gradient computed for them in the previous step).

[0063] A cost function, also known as a loss function, plays a crucial role in quantifying the disparity between the predicted output of the network and the actual target output. The cost function can thus be used in the one or more optimization methods to determine the programmable parameter updates. The objective of training a neural network is to minimize this cost function, thereby improving the network's ability to make accurate predictions.

[0064] For spiking neural networks specifically, the choice of cost function may differ from traditional neural networks. SNNs operate in discrete time steps, and the timing of spikescarries important information. Therefore, the cost function should take into account the temporal dynamics of spike timing when comparing predictions with target outputs. In SNNs, synaptic connections between neurons can be modified based on the timing of spikes, following principles like STDP. A suitable cost function for SNNs might incorporate these synaptic plasticity rules to guide learning and adjust the network's connectivity over time. SNNs often use event-based encoding, where information is represented by the timing and rate of spikes. The cost function should be designed to appropriately evaluate the fidelity of this encoding scheme and encourage the network to produce spike patterns that accurately represent the input data. Depending on the task, the cost function for SNNs may be tailored for classification tasks (e.g., spike-based classification of input patterns) or regression tasks (e.g., predicting continuous variables based on spike patterns). The choice of cost function will depend on the specific requirements of the task at hand. Since SNNs are often considered as models inspired by biological neurons, energy efficiency is a crucial consideration. The cost function may be designed to encourage sparse spike activity or minimize energy consumption while achieving the desired task performance. Common choices for cost functions in SNNs include variants of spike-based error metrics, such as spike train distance metrics, spike time prediction errors, or metrics based on the similarity of spike patterns between the network's output and target spike trains. Next, these parameter updates are applied to a single principal network by reducing the parameter updates to the single principal network in step 108.

[0065] For example, in step 107 one obtains a gradient, e.g. an error per weight for all the weights of each of the N devices. In step 108, the errors per weight of the principal network of step 105 can then be updated by for example averaging of the errors for a particular weight over all the N devices and using the average error to update the corresponding particular weight of the principal network of step 105.

[0066] For example, in step 107 one obtains a gradient with which one can update a value of a particular programmable value of a simulated programmable fabric on each of the N simulated devices. The errors of this value can then be reduced to a single error (e.g., by averaging the errors obtained from all the devices for this particular value), and the resulting single error can then be used to update the value of the principal network one started with in step 105. One can also e.g. work towards 2<J or 3<J acceptability, by minimizing the variability of the devices to a level where it falls within two or three standard deviations (<J) from an acceptable value.

[0067] This single principal network which has been updated in step 108 can then be re-used as the principal network to be optimized in steps 105-108 (steps 105-108 making up the system simulation 100B) until a system performance threshold is passed or convergence is reached (test B returns yes (Y), instead of no (N)).

[0068] Hence, the method can be described as training a principal neural network in a map- reduce fashion. During the map phase, the principal neural network is mapped onto many independent simulated chips, each one with different network parameters from each other, and a forward computational graph execution is performed. This phase includes an error gradient computation. During the reduce phase, the computed gradients are applied to the principal network. The steps of mapping and reducing can be repeated, and this cycle of map-reduce phases continues until convergence is achieved. The resultant network, defined as the combination of topology, neuron and synapse parameters, can be represented in a binary or textual representation and deployed to many instances of the target hardware.

[0069] For this main optimization phase, the forward pass through the network can be executed on a high-fidelity System-on-Chip (SoC) simulator, while the error-computing backward pass is handled by the computational framework implementing automatic differentiation described previously. The forward pass for the neural network in practice involves creating data structures that represent the neural network (for example, neuron and synapse parameters, as well as their hidden internal states) and computing the neuron and synapse state updates in a timesteped fashion. Additionally, for the SoC simulator to be considered cycle-accurate (highest-fidelity) or semi-cycle-accurate (high fidelity) it may incorporate information regarding number of clock cycles required per operation of each digital components on the device, or time required per analog component on the device. Clocked or synchronous digital systems can be characterized by the existence of one or many on-chip periodic events that progress the state of the device. The multiple clocks may or may not be synchronized with each other. Each time step the state of the network is updated according to the inputs (spikes) provided to the network and the activations produced by the neurons in previous time steps. The number of time steps, and therefore iterations over the network, are provided to the simulation platform. For example, a 2 layer feedforward network would involve the simulation of one or more of the following steps: the memory of the simulated device contains the data sample i of mini-batch j (the entire dataset is comprised of m mini-batches of predefined size with the exception of the last batch which may be of a different size), the transfer of data from memory to encoder blocks, the transfer of spikes from the encoder to theinput stage of the programmable fabric accelerating SNN operations, the spike shaping, broadcasting and integration within neurons, the communication of the spikes generated by the neurons in the first hidden layer to the input stages of other section of the programmable fabric responsible for modelling the input, synapse scaling and integration stages of the output layer of the network, communicating the spikes produced by the output layer of the network to the decoder blocks which for example counts the asynchronous spiking activity per output neuron to produce a classification decision by selecting the class corresponding to the neuron with the highest number of produced spikes. Different observables from the previously mentioned computational chain, such as spikes produced by all the neurons in the network, may be stored to be replayed onto the computational graph produced during the backward pass. The backward pass requires the construction of an equivalent computational graph as used by the forward pass. For this, for example PyTorch can be utilized; PyTorch holds the computational graph in memory, onto which observables from the system simulator are injected. This means that states and outputs of computational elements in the system simulator, such as spikes, internal potentials and currents of neurons and synapses, are tracked over time. Their impact on the computation, the so-called credit assignment problem, can be estimated.

[0070] After a system performance threshold is passed or convergence is reached, a complete description of the principal network can be deployed to any number of target hardware devices in step 109, making up the hardware deployment 100C.

[0071] The invention enables the deployment of a single neural network or parameterized model to multiple accelerators through the strategic modelling of device stochasticity, race conditions (presence or lack of synchronization or barriers) or noise sources (e.g. PVT).

[0072] A race condition is a situation in which the behavior of a system depends on the timing or sequence of events. It can occur when multiple processes or threads attempt to access shared resources simultaneously, leading to unpredictable outcomes. In an analogous fashion, different parts of the neural network accelerator fabric may finish their computation at different rates, therefore potentially resulting in a different spike sequence, which could be interpreted incorrectly on some devices. Examples include synchronization (coordination) between processes or threads, or barriers (such as locks or semaphores) which are in place to control access to shared resources. Noise sources refer to sources of interference or disturbances in the hardware devices. PVT stands for Process, Voltage, and Temperature variations, which are factors that can affect the performance and behavior of electronic circuits in the hardware devices.

[0073] The process enables a map-once strategy on edge devices. Namely, a single mapping output is produced that implements a neural network on accelerators incorporating stochastic components.

[0074] Furthermore, the process maximizes the yield of chip fabrication. Namely, individual networks are enabled to include sufficient redundancy to work around non-functional or out- of-spec components.

[0075] The invention can be applied to analog mixed-signal systems, fuzzy logic devices, approximate compute devices or in-material accelerators, and in particular to devices that implement one or more signal processing pipelines in a programmable fabric comprising an artificial neural networks (ANNs) or spiking neural networks (SNNs). A programmable fabric may be a computational structure that performs a series of operations subject to a provided set of configurations. The provided set of configurations are applied onto the programmable fabric to control for example the weights and connectivity between two user-provided layers of units (neurons). A signal processing pipeline is a sequence of processing stages or steps applied to input signals to achieve desired outcomes or extract relevant information. It's a systematic approach and can be applied in various fields, including audio processing, image processing, telecommunications, and sensor data analysis. If feature processing in the signal processing pipeline is performed using a neural network, it means that instead of employing traditional signal processing techniques for feature extraction and transformation, a neural network architecture is utilized to automatically learn and extract relevant features directly from the input signals.

[0076] If the programmable fabric is or comprises a spiking neural network, parameters that can be optimized in the manner described above include: (1) spiking neuron model parameters such as membrane potential threshold, membrane time constant, resting potential, refractory period, adaptive factors such as threshold adaptation time constants; (2) synaptic weight parameters such as synaptic weights, synaptic time constants, adaptive factors such as shortterm synaptic weight scaling; (3) network topology parameters such as number of neurons, connectivity pattern, network architecture; (4) learning rule parameters such as spike-timing- dependent plasticity (STDP) parameters, rate-based learning parameters optimizer hyperparameters and learning rate; and (5) input parameters such as input spike encoder mapping between data and spike rate, and spike encoder thresholds. Note that hyperparameters are configuration settings used to control the learning process, which are not learned from the data but set before the training starts.

[0077] If the programmable fabric is or comprises an artificial neural network, parameters that can be optimized in the manner described above include: (1) neuron activation function parameters such as activation function type (e.g., sigmoid, ReLU, tanh), parameters specific to the chosen activation function (e.g., slope of the sigmoid function); (2) synaptic weight parameters such as initial synaptic weights, synaptic weight scaling factor, learning rate; (3) network topology parameters such as number of layers, number of neurons in each layer, connectivity pattern (e.g., fully connected, convolutional); (4) learning rule parameters such as learning algorithm (e.g., stochastic gradient descent, reinforcement learning, evolutionary algorithms), regularization parameters (e.g., L1 / L2 regularization, dropout rate); and (5) input parameters such as input scaling and normalization, mini-batch size, learning rate schedules.

[0078] Note that features of any of the embodiments disclosed herein may be combined in an appropriate manner.

Claims

CLAIMS1. A method (100) for training a signal processing pipeline comprising a neural network, for deployment to a programmable fabric of a target device, the method comprising: obtaining a model of a plurality of components of the target device, wherein the model describes information of the plurality of components and how the components interact; obtaining programmable parameter values for a plurality of programmable parameters of the signal processing pipeline, wherein the programmable parameter values are compatible with the signal processing pipeline and the target device; obtaining characterization data (200) of the plurality of components of the target device, wherein the characterization data comprises measured component information of at least a portion of the components of a plurality of instances of the target device and / or stochastic variability information of at least a portion of the components of the plurality of instances of the target device; simulating (106) the plurality of instances of the target device using the model, wherein the model of each target device instance is configured with the programmable parameter values and the characterization data for the target device instance; using one or more optimization methods (107) to compute updates of the programmable parameter values of the programmable parameters for each of the simulated target device instances independently; reducing (108) the programmable parameter value updates for each of the simulated target device instances to a single update of the programmable parameter values of the signal processing pipeline; and updating the programmable parameter values of the signal processing pipeline with the single update of the programmable parameter values of the signal processing pipeline.

2. The method of claim 1, the method further comprising: checking (B) whether a target device performance threshold is reached or convergence is reached using the signal processing pipeline with the updated programmable parameter values; and repeating the above steps (105, 106, 107, 108) if the target device performance threshold or convergence is not reached.

3. The method of claim 1 or 2, the method further comprising:deploying (109) the signal processing pipeline with the updated programmable parameter values to the programmable fabric of the target device if the target device performance threshold or convergence is reached.

4. The method of any one of the preceding claims, wherein the model of each target device instance is configured with characterization data for the target device instance in such a way that the simulated target device instances represent digital twins of the number of target device instances and / or represent the stochastic variability of the plurality of target device instances.

5. The method of any one of the preceding claims, wherein the step of obtaining programmable parameter values comprises: initializing (102) the programmable parameters of the signal processing pipeline; optimizing (103) the programmable parameters by performing a high-level simulation until an initial acceptance threshold or convergence is achieved.6 The method of any one of the preceding claims, wherein the step of obtaining programmable parameter values further comprises: quantizing (104) the programmable parameters to be compliant with an available parameter resolution when the signal processing pipeline is deployed to the programmable fabric of the target device; and preferably performing a further optimization of the set of values of the quantized programmable parameters by performing a high-level simulation until a second initial acceptance threshold or convergence is achieved, to recover any performance loss from the quantization step.

7. The method of any one of the preceding claims, wherein the step of obtaining characterization data (200) comprises operating and observing the behavior of at least one of the plurality of target devices.

8. The method of any one of the preceding claims, wherein the stochastic variability of the plurality of components of the target device comprises stochastic variability between the plurality of target hardware devices and / or stochastic variability within each of the target hardware devices over time; andwherein the stochastic variability is caused by device-level mismatch, either through fabrication inaccuracies or analog circuit behavior under process, voltage, and temperature variations.

9. The method of any one of the preceding claims, wherein at least one of the simulated target device instances which the simulation implements is a twin of a non-simulated target device instance by replicating in simulation the behavior of individual components of the nonsimulated target device instance; and / or wherein at least one of the simulated target device instances which the simulation implements is a twin of a potential, but fictitious target device instance by abstracting the behavior of individual components into one or more distributions from which the behavior of simulated components of the simulated target device instance are drawn.

10. The method of any one of the preceding claims, wherein the step of using one or more optimization methods (107) to compute updates of the programmable parameter values of the programmable parameters comprises using gradient-based optimization methods or derivative- free optimization methods.

11. The method of any one of the preceding claims, wherein the step of using one or more optimization methods (107) to compute updates of the programmable parameter values of the programmable parameters comprises a forward pass and an error-computing backward pass through the simulated target devices, in particular the simulated programmable fabric; and wherein the forward pass is executed on a high-fidelity System-on-Chip simulator and the error-computing backward pass is handled by a computational framework implementing automatic differentiation.

12. The method of any one of the preceding claims, wherein the step of reducing (108) the programmable parameter value updates for each of the simulated target devices comprises averaging each of the programmable parameter value updates per programmable parameter value over all the simulated target devices or choosing the update of the programmable parameter values from the possible updates that minimizes the variability of the simulated target devices to a level where it falls within two or three standard deviations from an acceptable value.

13. The method of any one of the preceding claims, wherein the programmable fabric comprises a spiking neural network or an artificial neural network; and / or wherein the target devices comprise analog mixed-signal systems, fuzzy logic devices, approximate compute devices or in-material accelerators.

14. The method of claim 13, wherein the programmable fabric comprises a spiking neural network and the target devices comprise analog-mixed signal systems, more preferably wherein the target devices comprise analog mixed-signal systems with an on-chip spiking neural network acceleration fabric.

15. The method of claim 14, wherein the programmable parameters comprise at least one of: spiking neuron model parameters such as membrane potential threshold, membrane time constant, resting potential, refractory period, adaptive factors such as threshold adaptation time constants; synaptic weight parameters such as synaptic weights, synaptic time constants, adaptive factors such as short-term synaptic weight scaling; network topology parameters such as number of neurons, connectivity pattern, network architecture; learning rule parameters such as spike-timing-dependent plasticity (STDP) parameters, optimizer hyperparameter learning rate; and input encoding parameters such as spike encoder mapping between data and spike rate, and spike encoder thresholds.

16. The method of claim 15, wherein the programmable parameters comprise the weights of the synaptic elements of the spiking neural network, and wherein the programmable parameter values comprise the weight values of the weights; and wherein the step of using optimization methods (107) to compute updates of the programmable parameter values of the programmable parameters comprises obtaining an error per weight for all the weights of each of the simulated target device instances.

17. A device comprising a programmable fabric, wherein the programmable fabric is trained and subsequently deployed to the device according to the method of any one of the preceding claims.

18. A computer system for training a signal processing pipeline, comprising a neural network, for deployment to a programmable fabric of a target device, the computer system comprising a memory, a processor and an output; wherein the memory comprises: a model of a plurality of components of the target device, describing information of the plurality of components and how these interact; programmable parameter values for the programmable parameters of the signal processing pipeline, wherein the programmable parameter values are compatible with the target device and the signal processing pipeline; characterization data (200) of the plurality of components of the target device, wherein the characterization data comprises measured component information of at least a portion of the components of a plurality of instances of the target device and / or stochastic variability information of at least a portion of the components of the plurality of instances of the target device; wherein the processor performs the method of any one of the claims 1-16, wherein the steps of obtaining (105) the model, the programmable parameter values and the characterization data (200) are performed by respectively obtaining the model, the programable parameter values and the characterization data from the memory.

19. The computer system of claim 18, wherein when the processor performs the step of deploying (109) the signal processing pipeline with the updated programmable parameter values to the programmable fabric of the target device, the step of deploying is performed by saving the updated programmable parameter values to the memory or a permanent storage device and using the output to initialize the programmable fabric on each target device using the updated programmable parameter values.

Images