Gate all around semiconductor structure and its method of preparation

Abstract

The invention relates to a semiconductor structure (SC) comprising a support (1a) and a dielectric layer (1b) directly disposed on the support (1a). At least one pFET structure is directly residing on the dielectric layer (1b), each pFET structure comprising a first stack of channel nanosheets made of compressively strained silicon germanium and a pFET gate structure encapsulating each channel nanosheet of the first stack. At least one nFET structure is directly residing on the dielectric layer, each nFET structure comprising a second stack of channel nanosheets made of silicon and a nFET gate structure encapsulating each channel nanosheet of the second stack.

Description

GATE ALL AROUND SEMICONDUCTOR STRUCTURE AND ITS METHOD OF PREPARATIONFIELD OF THE INVENTION

[0001] The present invention relates to a gate-all-around semiconductor structure and to a method of preparing such a structure.BACKGROUND OF THE INVENTION

[0002] Gate-all-around semiconductor structures provide many improvements over planar and non-planar (eg FinFET) transistors. In particular, the improved gate control over the channel provides greater immunity to the short channel effect and lower leakage currents.

[0003] Figures 1A-1K represent the main steps of preparation of a Gate-All-Around semiconductor structure according to the state of the art. For simplicity of the representation, a single structure is shown on the figures but, usually, an array of such structures are collectively prepared during the execution of those steps.

[0004] As represented on, a pseudomorphic superlattice SL made of silicon layers SL1 and compressively strained silicon germanium layers SL2 is initially grown on a silicon substrate 1, for instance a p-type bulk (100) silicon substrate. The silicon-germanium layers SL2 may comprise about 30% of germanium and present a thickness of about 8 nm to 20 nm. The silicon layers SL1 may present a thickness of about 4 nm to 10 nm.

[0005] Then, the superlattice SL is protected with stacked of low temperature oxide and nitride before using conventional photolithography and etching techniques to define a fin 2 in the pseudomorphic superlattice SL. Etching may for instance be formed by reactive ion etching. The intermediate structure after the etching step is represented on.

[0006] In a following step of forming the shallow trench isolations, silicon dioxide is deposited on the intermediate structure, and a chemical mechanical planarization (CMP) step carried out to make the surface flat. A low temperature shallow trench isolation annealing before the application of the CMP is possible. Then the silicon dioxide is etched back to reveal the fin 2, and preserve the shallow trench isolation features 3 on each side of the fin. This is represented on.

[0007] In a following step, a dummy gate 4 is formed over the fin 2, by deposition of a stack made of a relatively thin oxide protection film and a relatively thick layer of amorphous or polycrystalline silicon. As represented on, The dummy gate 4 is defined in the stack by photolithography and etching. Then silicon nitride spacers 5 are formed by deposition and etching on each side of the dummy gate 4.

[0008] In the following step, dual source / drain 6 is formed by epitaxy on each side of the fin, against the spacer 5.

[0009] Then, a first interlayer dielectric layer 7 is formed over the intermediate structure of the, which is planarized by CMP to expose the top of the dummy gate 4, as represented on, which can then be removed, for instance by wet etching. In the resulting intermediate structure, represented on, the pseudomorphic superlattice SL is partially exposed by the removal of the dummy gate 4. Then the suspended channel nanosheets 8 of the semiconductor structure, extending between the source / drain regions 6, are defined by selectively removing the silicon-germanium layers SL2. A gate structure 9, made of a multilayer high k material (i.e a material presenting a dielectric value greater than silicon dioxide) and metal is then deposited, for instance by atomic layer deposition, to completely encapsulate each channel nanosheet 8, a form a gate-all-around structure, as shown on.

[0010] After a CMP planarization step to remove excess metal deposition () further inter dielectric layer(s) 7 may be formed on the intermediate structure (). Gate, source and drain vias (not shown) may be formed into the interdielectric layers 7 to respectively contact the corresponding electrodes.

[0011] As this is reported in the document of Sun, X. et al. ”A Novel Si Nanosheet Channel Release Process for the Fabrication of Gate-All-Around Transistors and Its Mechanism Investigation” Nanomaterials 2023, 13, 504, the main conduction surface orientation in the channel nanosheets is usually (100), and therefore there exists an unbalanced mobility between holes and electrons into these channels. To achieve current matching between a pFET structure and an nFET structure of a device, compressive stress may be introduced in the channel nanosheets of the pFET structure to enhance the hole mobility.

[0012] In document US2021 / 0151601 a strained material is formed along a sidewall surface of the gate. The strained material is configured to create strain in the channel nanosheets.

[0013] In the document US2023031490 a substrate is prepared comprising a superficial relaxed silicon germanium region and a superficial silicon region. A pFET structure is made from strained silicon germanium material formed over the superficial silicon region. An nFET structure is formed from strained silicon material formed over the superficial relaxed silicon germanium region. The superficial relaxed silicon germanium region and the superficial silicon region remain in the final structure, and the nFET et pFET structures are not relying directly on a dielectric layer.

[0014] In the document US2023147499A1, channel nanosheets of silicon germanium (SiGe) or germanium tin (GeSn) are formed and subsequently annealed to drive the germanium or tin inwards along a portion of the channel nanosheets thus increasing the germanium or tin concentration and providing strain to the channels. The channel nanosheets composing the nFET and pFET structures are necessarily staggered and not coplanar. In this case also, the nFET et pFET structures are not relying directly on a dielectric layer.OBJECT OF THE INVENTION

[0015] An object of the invention is to provide a semiconductor structure that compensate at least in part the unbalanced current matching between a pFET and an nFET gate-all-around structure.

[0016] Another object of the invention is to provide a method of preparing such a semiconductor structure.SUMMARY OF THE INVENTION

[0017] To this effect, the invention relates to a semiconductor structure comprising:a support;a dielectric layer directly disposed on the support;at least one pFET structure directly residing on the dielectric layer, each pFET structure comprising:a first stack of channel nanosheets made of compressively strained silicon germanium;a pFET gate structure encapsulating each channel nanosheet of the first stack; andat least one nFET structure directly residing on the dielectric layer, each nFET structure comprising:a second stack of channel nanosheets made of silicon;a nFET gate structure encapsulating each channel nanosheet of the second stack.

[0018] According to further non limitative features of the invention, either taken alone or in any technically feasible combination:the channel nanosheets of the first stack of channel nanosheets are coplanar with the channel nanosheets of the second stack of channel nanosheets;silicon of the channel nanosheets of the second stack is under tensile strain;the semiconductor structure further comprises :source and drain pFET regions formed on the support and respectively associated with the channel nanosheets of the first stack and ;source and drain nFET regions formed on the support and respectively associated with the channel nanosheets of the second stack;the semiconductor structure further comprises a boundary trench separating the pFET structures and the nFET structures;the channel nanosheets of the first stack and of the second stack present a thickness comprised between 4 nm and 20 nm.

[0019] According to another aspect, the invention relates to a method of preparing a semiconductor structure, the method comprising:providing a substrate comprising a support, a dielectric layer directly disposed on the support, and a top silicon film directly disposed on the dielectric layer ;transforming, in a pFET region of the substrate, a portion of the top silicon film into a compressively strained silicon germanium film, a remaining part of the top silicon film forming a nFET region of the substrate ;selectively growing, on the pFET region, a first pseudomorphic superlattice made of silicon layers and compressively strained silicon germanium layers ;defining at least one pFET structure directly residing on the dielectric layer by :selectively removing the silicon layers of the first pseudomorphic superlattice to define a first stack of channel nanosheets made of the compressively strained silicon germanium layers;forming by deposition a pFET gate structure encapsulating each channel nanosheet of the first stack.selectively growing on the nFET region a second pseudomorphic superlattice made of silicon layers and silicon germanium layers ;defining at least one nFET structure directly residing on the dielectric layer by :selectively removing the silicon germanium layers of the second pseudomorphic superlattice to define a second stack of channel nanosheets made of the silicon layers;

[0020] forming by deposition a nFET gate structure encapsulating each channel nanosheet of the second stack;

[0021] According to further non limitative features of this aspect of the invention, either taken alone or in any technically feasible combination:the top silicon film of the substrate is under tensile strain;the method further comprises, before the step of transforming a portion of the top silicon film, a step of relaxing, at least in part, the tensile strain of the top silicon film in the pFET region;relaxing the tensile strain comprises amorphizing, in the pFET region, a portion of the top silicon film by ion implantation and thermally treating the substrate to recrystallize the amorphous portion;transforming a portion of the top silicon film comprises:selectively forming a germanium rich layer on the top silicon film of the pFET region; andoxidizing at least a portion of the germanium rich layer to diffuse germanium species into the top silicon film in the pFET region thereby forming the compressively strained silicon germanium layer;wherein the germanium rich layer is a silicon geranium layer presenting a germanium concentration comprised between 10% and 20%, and presenting a thickness comprised between 5 and 10 nm;the silicon layers of the first pseudomorphic superlattice each presents a thickness comprised between 4 nm and 20 nm, and the silicon germanium layers of the first pseudomorphic superlattice each presents a thickness comprised between 4 nm and 20 nm;the silicon germanium layers of the second pseudomorphic superlattice each presents a thickness comprised between 4 nm and 20 nm, and the silicon layers of the second pseudomorphic superlattice each presents a thickness comprised between 4 nm and 20 nm.

[0022] Many other features and advantages of the present invention will become apparent from reading the following detailed description, when considered in conjunction with the accompanying drawings, in which:

[0023]

[0024] Figures 1A to 1K represent a method of preparing a semiconductor gate-all-around structure according to the state of the art ;

[0025]

[0026] Figures 2A to 2Q represent a method of preparing a semiconductor gate-all-around structure according to the invention;

[0027]

[0028] Figures 3A,3B,2C and 3D illustrate a particular application of a method according to the invention to manufacture forksheet FET structures.

[0029] DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS OF THE INVENTION

[0030] The illustrations presented herein are not meant to be actual views of any particular semiconductor structure, device, system, or method, but are merely idealized representations that are used to describe embodiments of the disclosure.

[0031] Methods that may be used to fabricate semiconductor structure are described below with reference to the figures 2A to 2Q

[0032] In a first step of a method according to the invention, represented on, a substrate 1 is provided. The substrate 1 comprises a support 1a, a dielectric layer 1b directly disposed on the support 1a, and a top silicon film 1c directly disposed on the dielectric layer 1b. The substrate 1 may be in the form of a circular wafer with a diameter of 100, 150, 200, 300 or even 450mm.

[0033] The support 1a is typically several hundred micrometers thick, sufficient to be self-supporting and to receive the other layers forming the substrate 1. For reasons of availability and cost, the support 1a is preferably made of monocrystalline silicon. It may comprise a superficial charge trapping layer, such as a superficial polysilicon layer, disposed under the dielectric layer 1b, and in contact with this layer 1b.

[0034] The dielectric layer 1b may present a thickness comprised between 10 nm and 1 micron. A thin dielectric layer 1b, below 20nm, may be privileged in some embodiments to allow a better thermal diffusion to the underlying support. Also, if the dielectric layer 1b is meant to also replace the shallow trench isolation, as this will be presented in greater details below, a greater thickness, for instance of 90 nm or above, may be chosen. The dielectric layer 1b may be formed of any dielectric material but preferably, it consists of a silicon dioxide layer.

[0035] The top silicon film 1c is made of monocrystalline silicon. It may present a thickness comprised between 4 et 20 nm. In some embodiments, the top silicon film 1c is unstrained. In other embodiments, the top silicon film 1c is presenting tensile strain, with the strain being typically comprised between 0,5 GPa to 2 GPa. Methods for preparing such a strained top silicon layer are well known, and for instance described in US6953736B2.

[0036] A second step of a method according to the invention comprises patterning the top silicon film 1c to define two distinct regions of the substrate 1 that extend over the surface of this film. A fist region, named “pFET region”, is configured to receive at least one pFET structure and a second region, named “nFET region” is configured to receive at least one nFET structure. As this is well known to the skilled person, a pFET structure is a semiconductor device, such as a transistor, comprising a low p doped channel disposed between heavy p doped drain and source regions. Current carriers are holes in a pFET structure. Similarly, a nFET structure is a semiconductor device, such as a transistor, comprising a low n doped channel disposed between heavy n doped drain and source regions. Current carriers are electrons in a nFET structure.

[0037] The pFET and of the nFET regions do not need to be continuous regions. Each of those regions may be formed of unconnected subregions arranged over the surface of the top silicon film 1c to pave it.

[0038] The pFET regions of the substrate 1 are defined by transforming a portion of the top silicon film 1c into a compressively strained silicon germanium film 1c’. The remaining part of the top silicon film 1c forming a nFET region of the substrate 1. The transformation may be performed according to the steps illustrated onto 2F.

[0039] On, the top silicon film 1c of the substrate 1 is entirely covered with a protection layer 1d. The protection layer may comprise a single layer or a plurality of layers of protection material. Typically, the protection layer 1d may comprise a relatively thin pad silicon oxide film in contact with the top silicon film 1c, covered with a relatively thick silicon nitride film. The pad silicon oxide film may present a thickness comprised between 2 and 5 nm and the silicon nitride film may present a thickness comprised between 20 nm and 100 nm.

[0040] In a subsequent step, represented on, the protection layer 1d is opened by conventional photolithography techniques, using a photo-resist mask layer 1e disposed on the protection layer 1d, and etching techniques to selectively expose the top silicon film 1c. This opening (that may be discontinuous and formed of unconnected subregions, as mentioned above) is corresponding to the pFET region of the substrate. The non-exposed part of the top silicon film 1c is forming the nFET region of the substrate 1.

[0041] If the top silicon film 1c is under tensile strain, an embodiment may comprise, during the formation of the opening, selectively releasing the tensile strain of the top silicon film 1c in the pFET region of the substrate, as this is represented on. This can be performed by preserving the pad silicon oxide film on the pFET region while etching selectively the silicon nitride of the protection layer 1d film during the opening formation. The nFET region is protected by the photo-resist mask layer 1e, such that this region remains unaffected by the strain releasing operations. Atomic species such as argon, germanium or silicon may then be selectively implanted into the bottom part of the top silicon film 1c (i.e. the part of the film in contact with the dielectric layer 1b) of the pFET region, through the pad silicon oxide silicon film. This implantation may amorphize the bottom part of the top silicon film 1c in the pFET region and release the tensile strain. A low temperature anneal applied to the substrate 1 may then be applied to recrystallize the amorphous part of the top silicon film 1c after removing photo-resist mask layer 1e. Then, the pad silicon oxide film over the pFET region is removed to obtain the structure represented on.

[0042] Whether or not this strain releasing steps have been carried out, the substrate 1 present a top silicon film 1c made of monocrystalline silicon, the portion of the top silicon film 1c corresponding to the pFET region being unstrained and exposed while the portion of the top silicon film 1c corresponding to the nFET region is disposed under the protection layer 1d. This portion may be under tensile strain if the substrate 1 originally provided was comprising such a strained top silicon layer 1c.

[0043] Then, as this is represented inand 2F, a germanium rich layer 1f, such as a silicon germanium film 1f, is epitaxially and selectively formed on the exposed pFET region of the top silicon film 1c. The epitaxial silicon germanium film 1f may typically comprise between 10% to 20% of germanium content and may present a thickness comprised between 4 nm and 20 nm. The substrate 1 is then exposed to an oxygen rich atmosphere and the epitaxial silicon germanium film 1f oxidized. During this oxidation step, the oxygen species from the oxygen rich atmosphere binds with the silicon of the silicon germanium film to form a superficial silicon oxide layer 1g. The germanium species are not oxidized and are injected into the underlying top silicon film 1c, as this phenomenon is explained in US9219150B1, to constitute a compressively strained silicon germanium film 1c’.

[0044] After this oxidation step, the portion of the top silicon film 1c in the pFET region is transformed into a compressively strained silicon germanium film 1c’. The portion of the top silicon film 1c in the nFET region is kept unaffected by this step and its crystalline silicon nature is preserved. After removal of the superficial silicon oxide layer 1g the structure represented onis obtained. This structure forms a platform for providing at least one pFET structure on the pFET region of the substrate (i.e. on the compressively strained silicon germanium layer 1c’), the pFET structure benefiting from exposed the strained germanium layer 1c’. Also, at least one nFET structure is formed on the nFET region of the substrate (i.e. on the strained or unstrained top silicon film 1c).

[0045] More precisely, in a next step represented on, a first pseudomorphic superlattice SL’ made of silicon layers SL1’ and compressively strained silicon germanium layers SL2’ is grown on the exposed the compressively strained silicon germanium film 1c’. The compressively strained silicon-germanium layers SL2’ of the first pseudomorphic superlattice SL’ may be comprise about 30% of germanium and present a thickness comprised between 4 nm to 20 nm, while the silicon layers SL1’ of this superlattice SL’ may present a thickness comprised between 4 nm and 20 nm. The layers of the first pseudomorphic superlattice SL’ may be grown undoped or slightly p doped.

[0046] Then a further protection layer 1d’ is disposed over the substrate 1, as represented on. This further protection layer 1d’ may also comprise a thin CVD or ALD silicon oxide pad layer covered by a silicon nitride layer. The protection layers 1d,1d’ may then be selectively removed, by photolithography and wet or dry etch to expose the top silicon film 1c in the nFET region of the substrate 1. Advantageously, the protection layers 1d,1d’ are not entirely removed over the nFET region, and a residual part 1d’’ is preserved to encapsulate the side of the first pseudomorphic superlattice SL’, as this can be seen on. Then a second pseudomorphic superlattice SL made of silicon layers SL1 and silicon germanium layers SL2 is grown on the exposed top silicon layer 1c of the nFET region (). The silicon-germanium layers SL2 of the second pseudomorphic superlattice SL may be comprise about 30% of germanium and present a thickness comprised between 4 nm to 20 nm, while the silicon layers SL1 of the second pseudomorphic superlattice SL may present a thickness comprised between 4 nm and 20 nm. The layers of the second pseudomorphic superlattice SL may be grown undoped or slightly n doped.

[0047] The further protection layer 1d’ and the remaining part of the protection layer 1d’’ are then removed, as shown in. On the resulting substrate 1, at least one pFET structure may be directly defined in the pFET region and at least one nFET structure may be directly defined in the nFET region, by using the main steps of preparation of a Gate-All-Around semiconductor structure illustrated on the figures 1A-1K. The pFET structure and the nFET structure are directly residing on the dielectric layer 1b.

[0048] In more details, the first and second pseudomorphic superlattice SL,SL’ may be patterned and etched to define at least one nFET fin 2 and one pFET fin 2’ in each of the first and second pseudomorphic superlattice SL,SL’. The etched opening may extend down to the dielectric layer 1b (and in such a case, the dielectric layer is preferably presenting a thickness equal or greater to 90 nm, as mentioned previously). If shallow trench isolations are desirable, the opening may be defined to penetrate into the support 1a, through the dielectric layer 1b, and may then be filled with recess silicon oxide. The substrate may be polished to remove any excess of recess silicon oxide.

[0049] Advantageously, at least one of the openings is formed at the boundary between the pFET and the nFET regions, to electrically isolate the two regions from each other. This opening is filled with oxide to form a boundary trench 10 that will be preserved during the rest of the process steps to maintain this electrical isolation, by protecting it with a protection layer ().

[0050] In the next step, the pFET and nFET regions are treated to form the dummy gate 4, defining the silicon nitride spacers on each side of the dummy gate, epitaxial deposition of the dual source / drain on each side of the fins 2,2’ (for instance in-situ doped epitaxial formation of the source and drain), and the deposition of the interlayer dielectric 7 ().

[0051] As shown on, a protective layer 1d is then selectively formed over the nFET region, and the pFET fin 2’ is partially exposed by the selective removal of the dummy gate 4. The suspended channel nanosheets of the pFET semiconductor structure, extending between the source / drain regions are defined by selectively removing the silicon layers SL1’, for instance by wet etch. The etching reveals a first stack of channel nanosheets 8’ made of compressively strained silicon germanium SL2’. A pFET gate structure 9’, made of a multilayer high k material (such as hafnium oxide) and p workfunction metal is then deposited, for instance by atomic layer deposition, to completely encapsulate each channel nanosheet 8’, a form a gate-all-around pFET structure).

[0052] The same process is repeated on nFET region, while the pFET region is protected by a selectively formed protection layer. The suspended channel nanosheets 8 of the nFET semiconductor structure, extending between the source / drain regions are defined by selectively removing the silicon-germanium layers SL2 of the nFET fin, for instance by wet etch. The etching reveals a first stack of channel nanosheets 8 made of silicon SL1. The channel nanosheet 8 may be strained if the original top silicon layer 1c was initially strained. A nFET gate structure 9, made of a multilayer high k material (such as hafnium oxide) and n work function metal is then deposited, for instance by atomic layer deposition, to completely encapsulate each channel nanosheet 8, a form a gate-all-around nFET structure.

[0053] After the removal of the protection layer 1d, and as shown on, a method according to the invention results in a semiconductor structure SC comprising a support 1a and a dielectric layer 1b directly disposed on the support 1a. At least one pFET structure is directly residing on the dielectric layer 1b. Each pFET structure comprises a first stack of channel nanosheets 8’ made of compressively strained silicon germanium and a pFET gate structure 9’ encapsulating each channel nanosheet 8 of the first stack. The semiconductor structure SC also comprises, at least one nFET structure directly residing on the dielectric layer 1b. Each nFET structure comprises a second stack of channel nanosheets 8 made of silicon and a nFET gate structure 9 encapsulating each channel nanosheet 8 of the second stack. The pFET structures and the nFET structures are separated by a boundary trench 10.

[0054] By “directly residing on the dielectric layer” it is meant that a channel nanosheet of the pFET and nFET structures, the first in each stack, is in contact with the dielectric layer 1b. Consequently, the channel nanosheets 8,8’ of the pFET and nFET structures according to the invention are coplanar.

[0055] Although not visible on the figures, the semiconductor structure SC also comprises source and drain pFET regions (n doped) formed on the support and respectively associated with the channel nanosheets of the first stack, and source and drain nFET regions (p doped) formed on the support and respectively associated with the channel nanosheets of the second stack.

[0056] A method according to the invention may be employed for forming so called forksheet FET structures. A forksheet FET structure comprises both a nFET and pFET structures, with a thin dielectric wall separating the two structures.

[0057] As shown on, the method according to the invention is applied to a substrate 1 to define a plurality of pFET and nFET subregions that are adjacent to each other’s and paving the front face of the substrate. The steps illustrated on the figures 2A to 2L may be applied accordingly to the substrate 1.

[0058] The pFET and nFET sub regions are separated from each other by boundary grooves 1t. A portion of the top silicon layer 1c is forming the bottom of the boundary grooves. According to one embodiment, this portion may be removed by etching and the trench filled with a dielectric, such as silicon nitride to form a plurality of boundary trenches, completely electrically isolating the pFET and nFET subregions ().

[0059] The method may then be applied to the resulting structure, to define two pFET fins 2’ in a pFET subregion and two nFET fins 2 in a nFET subregion, as shown on. After the finalization of the pFET and nFET structures, a plurality of forksheet semiconductor structure FS1-FS5 may be defined by grouping together adjacent pFET and nFET structures, as shown on.

[0060] Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.

[0061] In particular, the channel nanosheets thicknesses may be selected depending on the final application of the structure. Digital application typically requires or benefit from thinner channels, and channel nanosheets thicknesses may then be selected to be comprised between 4 nm and 10 nm. Analog application may require or benefit from thicker channels, and the channel nanosheets thicknesses may then be selected for this application to be comprised between 10 nm and 20 nm.

[0062] A plurality of semiconductor structures according to the present invention may be stacked together, in a 3D structure, or fabricated separately and connected in a system using in a 2.5D or 3D integration or packaging approach.

Claims

A semiconductor structure (SC) comprising:a support (1a);a dielectric layer (1b) directly disposed on the support (1a);at least one pFET structure directly residing on the dielectric layer (1b), each pFET structure comprising:a first stack of channel nanosheets made of compressively strained silicon germanium;a pFET gate structure encapsulating each channel nanosheet of the first stack; andat least one nFET structure directly residing on the dielectric layer, each nFET structure comprising:a second stack of channel nanosheets made of silicon;a nFET gate structure encapsulating each channel nanosheet of the second stack.The semiconductor structure according to claim 1, wherein the channel nanosheets of the first stack of channel nanosheets are coplanar with the channel nanosheets of the second stack of channel nanosheets.The semiconductor structure according to claim 1 or 2 wherein the silicon of the channel nanosheets of the second stack is under tensile strain.The semiconductor structure according to any preceding claims further comprising :source and drain pFET regions formed on the support and respectively associated with the channel nanosheets of the first stack and ;source and drain nFET regions formed on the support and respectively associated with the channel nanosheets of the second stack.The semiconductor structure according to any preceding claims further comprising a boundary trench (10) separating the pFET structures and the nFET structures.The semiconductor structure according to any preceding claims wherein the channel nanosheets of the first stack and of the second stack present a thickness comprised between 4 nm and 20 nm.A method of preparing a semiconductor structure (SC), the method comprising:providing a substrate (1) comprising a support (1a), a dielectric layer (1b) directly disposed on the support (1a), and a top silicon film (1c) directly disposed on the dielectric layer (1b);transforming, in a pFET region of the substrate (1), a portion of the top silicon film (1c) into a compressively strained silicon germanium film (1c’), the remaining part of the top silicon film (1c) forming a nFET region of the substrate (1);selectively growing, on the pFET region, a first pseudomorphic superlattice (SL’) made of silicon layers (SL1’) and compressively strained silicon germanium layers (SL2’);defining at least one pFET structure directly residing on the dielectric layer (1b) by :selectively removing the silicon layers of the first pseudomorphic superlattice (SL’) to define a first stack of channel nanosheets (8’) made of the compressively strained silicon germanium layers;forming by deposition a pFET gate structure (9’) encapsulating each channel nanosheet of the first stack.selectively growing on the nFET region a second pseudomorphic superlattice (SL) made of silicon layers (SL1) and silicon germanium layers (SL2);defining at least one nFET structure directly residing on the dielectric layer (1b) by :selectively removing the silicon germanium layers (SL2) of the second pseudomorphic superlattice (SL) to define a second stack of channel nanosheets (8) made of the silicon layers (SL1);forming by deposition a nFET gate structure (9) encapsulating each channel nanosheet (8) of the second stack.The method of claim 7 wherein the top silicon film (1c) of the substrate (1) is under tensile strain.The method of claim 8 further comprising, before the step of transforming a portion of the top silicon film (1c), a step of relaxing, at least in part, the tensile strain of the top silicon film (1c) in the pFET region.The method of claim 9 wherein relaxing the tensile strain comprises amorphizing, in the pFET region, a portion of the top silicon film (1b) by ion implantation and thermally treating the substrate (1) to recrystallize the amorphous portion.The method of claim 7 to 10 wherein transforming a portion of the top silicon film (1c) comprises:selectively forming a germanium rich layer (1f) on the top silicon film (1c) of the pFET region; andoxidizing at least a portion of the germanium rich layer (1f) to diffuse germanium species into the top silicon film (1) in the pFET region thereby forming the compressively strained silicon germanium layer.The method of claim 11 wherein the germanium rich layer (1f) is a silicon geranium layer presenting a germanium concentration comprised between 10% and 20%, and presenting a thickness comprised between 5 and 10 nm.The method according to any of claims 7 to 12 wherein the silicon layers (SL1’) of the first pseudomorphic superlattice (SL’) each presents a thickness comprised between 4 nm and 20 nm, and the silicon germanium layers (SL2’) of the first pseudomorphic superlattice (SL) each presents a thickness comprised between 4 nm and 20 nm.The method according to any of claims 7 to 13 wherein the silicon germanium layers (SL2) of the second pseudomorphic superlattice (SL) each presents a thickness comprised between 4 nm and 20 nm, and the silicon layers (SL1) of the second pseudomorphic superlattice (SL) each presents a thickness comprised between 4 nm and 20 nm.

Images