Semiconductor device and method of forming the same

Abstract

The present disclosure relates to semiconductor devices and methods of forming the same. One method includes forming a gate dielectric cap over a gate structure; forming source / drain contacts over a semiconductor substrate, and the gate dielectric cap laterally between the source / drain contacts; depositing an etch resist layer over the gate dielectric cap; depositing a contact etch stop layer over the etch resist layer, and depositing an interlayer dielectric (ILD) layer over the contact etch stop layer; performing a first etch process to form a via opening that extends through the ILD layer and terminates before reaching the etch resist layer; performing a second etch process to deepen the via opening so that one of the source / drain contacts is exposed, wherein the second etch process etches the etch resist layer at a slower etch rate than the contact etch stop layer; and depositing a metal material to fill the deepened via opening.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices and methods of forming the same. Background Technology

[0002] Technological advancements in IC materials and design have resulted in several generations of ICs, each featuring smaller and more complex circuitry than the previous generation. Throughout IC evolution, functional density (the number of interconnect devices per chip area) has typically increased, while geometry (the smallest component (or line) that can be produced using manufacturing processes) has decreased. This miniaturization process generally provides benefits through increased production efficiency and reduced associated costs. Summary of the Invention

[0003] According to one embodiment of this disclosure, a method of forming a semiconductor device is provided, comprising: forming a gate structure on a semiconductor substrate; forming a gate dielectric cap on the gate structure; forming source / drain contacts on the semiconductor substrate, wherein the gate dielectric cap is located between the source / drain contacts; depositing an etch resist layer on the gate dielectric cap; depositing a contact etch stop layer on the etch resist layer and depositing an interlayer dielectric (ILD) layer on the contact etch stop layer; performing a first etching process to form a via opening extending through the ILD layer and terminating before reaching the etch resist layer; performing a second etching process to deepen the via opening such that one of the source / drain contacts is exposed, wherein the second etching process etches the etch resist layer at a slower etch rate than etching the contact etch stop layer; and depositing a metal material to fill the deepened via opening.

[0004] According to another embodiment of this disclosure, a method of forming a semiconductor device is provided, comprising: forming a gate structure between gate spacers and on a semiconductor substrate; etching back the gate structure to below the top of the gate spacers; forming a gate dielectric cap on the etched-back gate structure; forming source / drain contacts adjacent to sidewalls of the gate dielectric cap; depositing an etch resist layer on the gate dielectric cap and the source / drain contacts; sequentially depositing an etch stop layer and an interlayer dielectric (ILD) layer on the etch resist layer; performing a first etch process to form a via opening extending through the ILD layer; after the first etch process is completed, performing a second etch process to extend the via opening downward to the source / drain contacts, wherein, after the second etch process etches through the etch resist layer, the sidewall profile of the via opening becomes more vertical than before etching the etch resist layer; and after performing the second etch process, forming a via structure in the via opening.

[0005] According to another embodiment of this disclosure, a semiconductor device is provided, comprising: a source / drain epitaxial structure located on a substrate; source / drain contacts located on the source / drain epitaxial structure; a gate structure laterally located between the source / drain contacts; a gate dielectric cap located on the gate structure with its bottom surface lower than the top surface of the source / drain contacts; an oxide-based etch resist layer located on the gate dielectric cap; a nitride-based etch stop layer located on the oxide-based etch resist layer; an interlayer dielectric (ILD) layer located on the nitride-based etch stop layer; and a via structure extending through the ILD layer, the nitride-based etch stop layer, and the oxide-based etch resist layer to be electrically connected to one of the source / drain contacts. Attached Figure Description

[0006] The various aspects of this disclosure are best understood through the following detailed description, taken in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figures 1-19B Perspective views and cross-sectional views of intermediate stages in the formation of an integrated circuit structure according to some embodiments of the present disclosure are shown.

[0008] Figures 20-25 Exemplary cross-sectional views of various stages for manufacturing an integrated circuit structure according to some other embodiments of the present disclosure are shown.

[0009] Figures 26-45B Perspective views and cross-sectional views of intermediate stages in the formation of an integrated circuit structure according to some embodiments of the present disclosure are shown.

[0010] Figures 46-51 Exemplary cross-sectional views of various stages for manufacturing an integrated circuit structure according to some other embodiments of the present disclosure are shown. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, for ease of description, this document uses spatially related terms (e.g., “below,” “under,” “down,” “above,” “up,” etc.) to describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted accordingly. As used herein, “approximately,” “about,” “close to,” or “substantially” should generally mean within twenty percent, or ten percent, or five percent of a given value or range. The numerical quantities given herein are approximate, meaning that the terms “approximately,” “about,” “close to,” or “substantially” can be inferred unless explicitly stated otherwise.

[0013] This disclosure generally relates to integrated circuit structures and methods of forming them, and more specifically, to the fabrication of transistors (e.g., FinFETs, Gate All-Around (GAA) transistors), and source / drain vias above the source / drain contacts of transistors. It should also be noted that embodiments are presented in the form of multi-gate transistors. Multi-gate transistors include those whose gate structures are formed on at least two sides of a channel region. These multi-gate devices can include p-type metal-oxide-semiconductor devices or n-type metal-oxide-semiconductor devices. Specific examples are presented and referred to as FinFETs due to their fin-like structures. FinFETs have gate structures formed on three sides of a channel region (e.g., around the upper portion of the channel region in a semiconductor fin). Embodiments of a class of multi-gate transistors referred to herein as GAA devices are also presented. GAA devices include any device in which a gate structure or a portion thereof is formed on all four sides of a channel region (e.g., around a portion of the channel region). Devices presented herein also include embodiments in which the channel region is arranged in one or more nanosheet channels, one or more nanowire channels, and / or other suitable channel configurations.

[0014] After the front-end-of-line (FEOL) process for manufacturing transistors is completed, source / drain contacts are formed over the source / drain regions of the transistor. Then, source / drain vias are formed over the source / drain contacts to electrically connect them to subsequently formed interconnect metal lines. Forming source / drain vias typically involves depositing an interlayer dielectric (ILD) layer over the source / drain contacts, forming via openings extending through the ILD layer using anisotropic etching, and then depositing one or more metal layers in the via openings to serve as source / drain vias. To prevent excessive over-etching of the source / drain contacts during the anisotropic etching process, an additional etch stop layer (also known as an intermediate contact etch stop layer (MCESL)) is formed over the source / drain contacts before forming the ILD layer. MCESL has different etch selectivity than ILD layers, so MCESL can slow down the etching process that forms via openings, thereby preventing excessive over-etching of source / drain contacts.

[0015] After etching the via opening through the ILD layer, another etching process (sometimes called liner removal (LRM) etching, since the MCESL can be used as a liner for the top surface of the source / drain contacts) is performed to pass through the MCESL. The etch duration of the LRM etching is set to allow a controlled amount of over-etching so that the MCESL passes through at every target location across the wafer. However, LRM etching can create serrated recesses in the gate dielectric cap next to the source / drain contacts. This is because both the gate dielectric cap and the MCESL are made of nitride-based materials (e.g., silicon nitride) without significant etch selectivity. Serrated recesses in the gate dielectric cap can increase the risk of leakage current (e.g., leakage current from the source / drain via to the gate structure and / or gate contacts). Therefore, in various embodiments, this disclosure provides an additional oxide-based layer on the gate dielectric cap. This oxide layer has a different material composition than the nitride-based gate dielectric cap and / or MCESL, and therefore has a different etch selectivity. Therefore, this oxide-based layer allows for a slower LRM etching process as the via openings reach the oxide-based layer. Slowing down the LRM etching prevents serrated patterns in the via openings, which in turn reduces the risk of leakage current. Furthermore, slowing down the LRM etching allows for the formation of via openings with a more vertical profile, which in turn increases the contact area and thus reduces the contact resistance between the source / drain vias and the underlying source / drain contacts.

[0016] Figures 1 to 19BPerspective views and cross-sectional views of intermediate stages in the formation of an integrated circuit structure 100 according to some embodiments of the present disclosure are shown. According to some exemplary embodiments, the formed transistors may include p-type transistors (e.g., p-type FinFETs) and n-type transistors (e.g., n-type FinFETs). In the various views and illustrative embodiments, the same reference numerals are used to designate the same elements. It should be understood that... Figure 1-19B Additional operations are provided before, during, and after the illustrated process, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of these operations / processes may be interchangeable.

[0017] Figure 1 A perspective view of the initial structure is shown. This initial structure includes a substrate 12. The substrate 12 may be a semiconductor substrate (also referred to as a wafer in some embodiments), which may be a silicon substrate, a silicon-germanium substrate, or a substrate formed of other semiconductor materials. According to some embodiments of this disclosure, the substrate 12 includes a bulk silicon substrate and an epitaxial silicon-germanium (SiGe) layer or germanium layer (without silicon) on the bulk silicon substrate. The substrate 12 may be doped with p-type or n-type impurities. Isolation regions 14, such as shallow trench isolation (STI) regions, may be formed to extend into the substrate 12. The portion of the substrate 12 located between adjacent STI regions 14 is referred to as a semiconductor strip 102.

[0018] STI region 14 may include a liner oxide (not shown). The liner oxide may be formed from a thermal oxide formed by thermal oxidation of a surface layer of substrate 12. The liner oxide may also be a deposited silicon oxide layer formed using methods such as atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), and chemical vapor deposition (CVD). STI region 14 may also include a dielectric material situated on the liner oxide, and this dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, etc.

[0019] refer to Figure 2 The STI region 14 is recessed such that the top portion of the semiconductor strip 102 protrudes above the top surface of the adjacent STI region 14 to form a protruding fin 104. This etching can be performed using a dry etching process, wherein NH3 and NF3 are used as etching gases. A plasma may be generated during this etching process. Argon may also be included. According to an alternative embodiment of this disclosure, the recess of the STI region 14 is performed using a wet etching process. For example, the etching chemicals may include diluted HF.

[0020] In the exemplary embodiments described above, the fins can be patterned using any suitable method. For example, the fins can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns, for example, with a pitch smaller than that achievable using a single direct photolithography process. For example, in some embodiments, a sacrificial layer is formed on a substrate, and the sacrificial layer is patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fins.

[0021] The material of the protruding fin 104 can also be replaced with a material different from that of the substrate 12. For example, if the protruding fin 104 is used in an n-type transistor, it can be formed of Si, SiP, SiC, SiPC, or a III-V compound semiconductor (e.g., InP, GaAs, AlAs, InAs, InAlAs, InGaAs). On the other hand, if the protruding fin 104 is used in a p-type transistor, it can be formed of Si, SiGe, SiGeB, Ge, or a III-V compound semiconductor (e.g., InSb, GaSb, InGaSb).

[0022] refer to Figure 3A and Figure 3B A dummy gate structure 106 is formed on the top surface and sidewalls of the protruding fin 104. Figure 3B It shows the contents Figure 3A A cross-sectional view obtained from the vertical plane of line BB in the diagram. The formation of the dummy gate structure 106 includes sequentially depositing a gate dielectric layer and a dummy gate electrode layer across fin 104, followed by patterning the gate dielectric layer and the dummy gate electrode layer. As a result of this patterning, the dummy gate structure 106 includes a gate dielectric layer 108 and a dummy gate electrode 110 located above the gate dielectric layer 108. The gate dielectric layer 108 can be any acceptable dielectric layer (e.g., silicon oxide, silicon nitride, etc., or combinations thereof) and can be formed using any acceptable process (e.g., thermal oxidation, spin coating, CVD, etc.). The dummy gate electrode 110 can be any acceptable electrode layer, including, for example, polysilicon, metal, etc., or combinations thereof. The gate electrode layer can be deposited using any acceptable deposition process, such as CVD, plasma-enhanced CVD (PECVD), etc. Each dummy gate structure 106 spans one or more protruding fins 104. The dummy gate structure 106 may have a length direction perpendicular to the length direction of the corresponding protruding fin 104.

[0023] A mask pattern can be formed on the dummy gate electrode layer to assist in patterning. In some embodiments, the hard mask pattern includes a bottom mask 112 on top of the blanket polysilicon layer and a top mask 114 on top of the bottom mask 112. The hard mask pattern is made of one or more layers of SiO2, SiCN, SiON, Al2O3, SiN, or other suitable materials. In some embodiments, the bottom mask 112 comprises silicon nitride, and the top mask 114 comprises silicon oxide. By using the mask pattern as an etching mask, the dummy electrode layer is patterned into the dummy gate electrode 110, and the blanket gate dielectric layer is patterned into the gate dielectric layer 108.

[0024] Next, as Figure 4 As shown, a gate spacer 116 is formed on the sidewall of the dummy gate structure 106. In some embodiments of the gate spacer formation step, a spacer material layer is deposited on the substrate 12. The spacer material layer may be a conformal layer that is subsequently etched back to form the gate spacer 116. In some embodiments, the spacer material layer comprises multiple layers, such as a first spacer layer 118 and a second spacer layer 120 formed on the first spacer layer 118. The first spacer layer 118 and the second spacer layer 120 are each made of a suitable material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof. By way of example and not limitation, the first spacer layer 118 and the second spacer layer 120 may be formed by sequentially depositing two different dielectric materials on the dummy gate structure 106 using a process such as a CVD process, a subatmospheric pressure CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable processes. An anisotropic etching process is then performed on the deposited spacer layers 118 and 120 to expose portions of fin 104 not covered by dummy gate structure 106 (e.g., in the source / drain regions of fin 104). The portion of spacer layers 118 and 120 directly above the dummy gate structure 106 can be completely removed by this anisotropic etching process. The portions of spacer layers 118 and 120 on the sidewalls of the dummy gate structure 106 can be retained to form a gate sidewall spacer, which is referred to as gate spacer 116 for simplicity. In some embodiments, the first spacer layer 118 is formed of silicon oxide, which has a lower dielectric constant than silicon nitride, and the second spacer layer 120 is formed of silicon nitride, which has higher etch resistance than silicon oxide for subsequent etching processes (e.g., etching the source / drain recesses in fin 104). In some embodiments, gate spacer 116 can be used to offset subsequently formed doped regions (e.g., source / drain regions). The gate spacer 116 can be further used to design or modify the source / drain region profile.

[0025] After the gate spacer 116 is formed, a source / drain epitaxial structure 122 is formed on the source / drain region of the fin 104 that is not covered by the dummy gate structure 106 and the gate spacer 116. Figure 5 The resulting structure is shown. In some embodiments, the formation of the source / drain epitaxial structure 122 includes recessing the source / drain regions of the fin 104 and then epitaxially growing semiconductor material in the recessed source / drain regions of the fin 104.

[0026] A suitable selective etching process can be used to recess the source / drain regions of the fin 104. This suitable selective etching process etches the semiconductor fin 104 but hardly etches the gate spacer 116 and the top mask 114 of the dummy gate structure 106. For example, recessing the semiconductor fin 104 can be performed by dry chemical etching using a plasma source and an etchant gas. The plasma source can be inductively coupled plasma (ICR) etching, transformer coupled plasma (TCP) etching, electron cyclotron resonance (ECR) etching, reactive ion etching (RIE), etc., and the etchant gas can be fluorine, chlorine, bromine, or combinations thereof, which etches the semiconductor fin 104 at a faster etch rate than etching the gate spacer 116 and the top mask 114 of the dummy gate structure 106. In some other embodiments, recessing the semiconductor fin 104 can be performed by wet chemical etching (e.g., ammonium peroxide mixture (APM), NH4OH, tetramethylammonium hydroxide (TMAH), combinations thereof), which etches the semiconductor fin 104 at a faster etch rate than etching the top mask 114 of the gate spacer 116 and the dummy gate structure 106. In some other embodiments, recessing the semiconductor fin 104 can be performed by a combination of dry chemical etching and wet chemical etching.

[0027] Once a recess is formed in the source / drain region of fin 104, a source / drain epitaxial structure 122 is formed in the source / drain recess in fin 104 using one or more epitaxial processes that provide one or more epitaxial materials on semiconductor fin 104. During the epitaxial growth process, gate spacer 116 confines the one or more epitaxial materials in the source / drain region of fin 104. In some embodiments, the lattice constant of epitaxial structure 122 is different from the lattice constant of semiconductor fin 104, such that strain or stress can be applied to the channel region in fin 104 and between epitaxial structures 122 through epitaxial structures 122 to improve carrier mobility and enhance device performance of semiconductor devices. Epitaxial processes include CVD deposition techniques (e.g., PECVD, vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and / or other suitable processes. Epitaxial processes can use gaseous and / or liquid precursors that interact with the components of semiconductor fin 104.

[0028] In some embodiments, the source / drain epitaxial structure 122 may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable materials. The source / drain epitaxial structure 122 may be in-situ doped during the epitaxial process by introducing dopants, including: p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and / or other suitable dopants, including combinations of the foregoing. If the source / drain epitaxial structure 122 is not in-situ doped, an implantation process (i.e., a junction implantation process) is performed to dope the source / drain epitaxial structure 122. In some exemplary embodiments, the source / drain epitaxial structure 122 in an n-type transistor includes SiP, while the source / drain epitaxial structure 122 in a p-type transistor includes GeSnB and / or SiGeSnB. In embodiments with different device types, a mask (e.g., photoresist) can be formed over the n-type device region while exposing the p-type device region, and a p-type epitaxial structure can be formed on the exposed fin 104 in the p-type device region. The mask can then be removed. Subsequently, a mask (e.g., photoresist) can be formed over the p-type device region while exposing the n-type device region, and an n-type epitaxial structure can be formed on the exposed fin 104 in the n-type device region. The mask can then be removed.

[0029] Once the source / drain epitaxial structure 122 is formed, an annealing process can be performed to activate the p-type or n-type dopant in the source / drain epitaxial structure 122. This annealing process can be, for example, rapid thermal annealing (RTA), laser annealing, millisecond thermal annealing (MSA), etc.

[0030] Next, in Figure 6In this process, an interlayer dielectric (ILD) layer 126 is formed on substrate 12. In some embodiments, a contact etch stop layer (CESL) may be formed prior to the formation of the ILD layer 126. In some examples, the CESL comprises a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and / or other suitable materials having a different etch selectivity than the ILD layer 126. The CESL may be formed by a plasma-enhanced chemical vapor deposition (PECVD) process and / or other suitable deposition or oxidation processes. In some embodiments, the ILD layer 126 comprises materials such as oxides forming tetraethyl orthosilicate (TEOS), undoped silicate glass, or doped silicon oxide (e.g., borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), etc.), and / or other suitable dielectric materials having a different etch selectivity than the CESL. The ILD layer 126 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after the ILD layer 126 is formed, the wafer may undergo a high thermal budget process to anneal the ILD layer 126.

[0031] In some examples, after the formation of the ILD layer 126, a planarization process can be performed to remove excess material from the ILD layer 126. For example, the planarization process includes a chemical mechanical planarization (CMP) process, which removes portions of the ILD layer 126 (and the CESL layer, if present) above the dummy gate structure 106. In some embodiments, the CMP process also removes hard mask layers 112, 114 (e.g., Figure 5 (as shown) and exposes the dummy gate electrode 110.

[0032] Next, as Figure 7 As shown, the remaining dummy gate structure 106 is removed, thereby forming a gate trench GT1 between the respective gate spacers 116. The dummy gate structure 106 is removed using a selective etching process (e.g., selective dry etching, selective wet etching, or a combination thereof), which etches the material in the dummy gate structure 106 at a faster etch rate than etching other materials (e.g., gate spacers 116 and / or ILD layer 126).

[0033] After that, as Figure 8As shown, alternative gate structures 130 are formed in the gate trench GT1. Gate structures 130 can be the final gate of a FinFET. Each final gate structure can be a high-k / metal gate stack, however other compositions are possible. In some embodiments, each gate structure 130 forms a gate associated with three sides of the channel region provided by the fin 104. In other words, each gate structure 130 surrounds the fin 104 on three sides. In various embodiments, the high-k / metal gate structure 130 includes a gate dielectric layer 132 lining the gate trench GT1, a work function metal layer 134 formed over the gate dielectric layer 132, and a fill metal 136 formed over the work function metal layer 134 and filling the remainder of the gate trench GT1. The gate dielectric layer 132 includes an interface layer (e.g., a silicon oxide layer) and a high-k gate dielectric layer located above the interface layer. As used and described herein, the high-k gate dielectric includes a dielectric material having a high dielectric constant (e.g., greater than the dielectric constant of thermally heated silicon oxide (about 3.9)). The work function metal layer 134 and / or fill metal 136 used in the high-k / metal gate structure 130 may include metal, metal alloy, or metal silicide. The formation of the high-k / metal gate structure 130 may include a variety of deposition processes for forming various gate materials, one or more inner liner layers, and one or more CMP processes for removing excess gate material.

[0034] In some embodiments, the interface layer of the gate dielectric layer 132 may include a dielectric material such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-k dielectric layer of the gate dielectric layer 132 may include hafnium oxide (HfO2). Alternatively, the gate dielectric layer 132 may include other high-k dielectrics, such as hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), strontium titanium oxide (SrTiO3, STO), barium titanium oxide (BaTiO3, BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al2O3), silicon nitride (Si3N4), oxynitride (SiON), and combinations thereof.

[0035] The work function metal layer 134 may include a work function metal for providing a suitable work function for the high-k / metal gate structure 130. For an n-type FinFET, the work function metal layer 134 may include one or more n-type work function metals (N-metals). The n-type work function metals may, exemplarily, include, but are not limited to, the following: titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminides, and / or other suitable materials. On the other hand, for a p-type FinFET, the work function metal layer 134 may include one or more p-type work function metals (P-metals). p-type work function metals may include, but are not limited to, the following: titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and / or other suitable materials.

[0036] In some embodiments, the filler metal 136 may include, but is not limited to, the following: tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other suitable materials.

[0037] Then refer to Figure 9 An etch-back process is performed to etch back the gate structure 130 and the gate spacer 116, thereby forming a recess R1 on the etched-back gate structure 130 and the etched-back gate spacer 116. In some embodiments, since the material replacing the gate structure 130 has a different etch selectivity than the gate spacer 116, a first selective etch-back process can be initially performed to etch back the gate structure 130 to lower the replacement gate structure 130 below the top of the gate spacer 116. Then, a second selective etch-back process can be performed to lower the gate spacer 116. As a result, the top surface of the replacement gate structure 130 can be at a different level than the top surface of the gate spacer 116. For example, in... Figure 9 In the illustrated embodiment, the top surface of the replacement gate structure 130 is lower than the top surface of the gate spacer 116. However, in some other embodiments, the top surface of the replacement gate structure 130 may be flush with or higher than the top surface of the gate spacer 116.

[0038] Subsequently, a metal cap 138 is formed on top of the replacement gate structure 130 using a suitable process such as CVD or ALD. In some embodiments, the metal cap 138 is formed on the replacement gate structure 130 in a bottom-up manner. For example, the metal cap 138 is selectively grown on metal surfaces (e.g., work function metal layer 134 and filler metal 136), so that the gate spacer 116 is substantially ungrown with the metal cap 138. By way of example and not limitation, the metal cap 138 may be a substantially fluorine-free tungsten (FFW) film with less than 5 atomic percent fluorine impurities and more than 3 atomic percent chlorine impurities. One or more fluorine-based tungsten precursors (e.g., but not limited to, tungsten pentachloride (WCl5), tungsten hexachloride (WCl6)) may be used to form the FFW film or films including FFW by ALD or CVD. In some embodiments, portions of the metal cap 138 may extend over the gate dielectric layer 132, such that the metal cap 138 may also cover the exposed surface of the gate dielectric layer 132. Since the metal cap 138 is formed in a bottom-up manner, its formation can be simplified, for example, by reducing the repeated etching process used to remove unwanted metallic material generated due to conformal growth.

[0039] In some embodiments where a bottom-up approach is used to form the metal cap 138, the growth of the metal cap 138 on the metal surface (i.e., the metal in the gate structure 130) has a different nucleation delay compared to the dielectric surface (i.e., the dielectric in the gate spacer 116). The nucleation delay on the metal surface is shorter than that on the dielectric surface. Therefore, the difference in nucleation delay allows for selective growth on the metal surface. This disclosure utilizes such selectivity in various embodiments to allow metal growth from the gate structure 130 while suppressing metal growth from the gate spacer 116. As a result, the deposition rate of the metal cap 138 on the gate structure 130 is faster than that on the gate spacer 116. In some embodiments, the top surface of the resulting metal cap 138 is lower than the top surface of the etched-back gate spacer 116. However, in some embodiments, the top surface of the metal cap 138 may be flush with or higher than the top surface of the etched-back gate spacer 116.

[0040] Next, as Figure 10As shown, a dielectric capping layer 140 is deposited on substrate 12 until the recess R1 is overfilled. The dielectric capping layer 140 includes SiN, SiC, SiCN, SiON, SiCON, combinations thereof, etc., and is formed by a suitable deposition technique, such as CVD, plasma-enhanced CVD (PECVD), ALD, remote plasma ALD (RPALD), plasma-enhanced ALD (PEALD), or combinations thereof. Then, a CMP process is performed to remove the capping layer located outside the recess R1, thereby leaving the portion of the dielectric capping layer 140 located in the recess R1 to serve as the gate dielectric capping layer 142. Figure 11 The resulting structure is shown.

[0041] refer to Figure 12 A source / drain contact 144 is formed, extending through the ILD layer 126 (and CESL, if present). By way of example and not limitation, the formation of the source / drain contact 144 includes: performing one or more etching processes to form contact openings extending through the ILD layer 126 to expose the source / drain epitaxial structure 122, depositing one or more metal materials to overfill the contact openings, and then performing a CMP process to remove excess metal material located outside the contact openings. In some embodiments, the one or more etching processes are selective etching, which etches the ILD layer 126 at a faster etch rate than etching the gate dielectric cap 142 and the gate spacer 116. As a result, this selective etching is performed using the gate dielectric cap 142 and the gate spacer 116 as an etch mask, such that the contact openings, and therefore the source / drain contact 144, are formed to be self-aligned with the source / drain epitaxial structure 122 without the use of additional photolithography processes. In this case, the gate dielectric cap 142 that allows the source / drain contacts 144 to be formed in a self-aligned manner can be referred to as the self-aligned contact (SAC) cap 142.

[0042] exist Figure 13 In this process, an etch resist layer 145 is formed over the gate dielectric cap 142 and the source / drain contacts 144. The etch resist layer 145 can be formed using an ALD process, a PECVD process, and / or other suitable deposition processes. In some embodiments, the etch resist layer 145 is made of a material different from the material of the gate dielectric cap 142 and the subsequently formed MCESL. For example, the gate dielectric cap 142 and the subsequently formed MCESL are made of the same material (e.g., silicon nitride), with no etch selectivity between them, and the etch resist layer 145 is made of an oxide-based material or other suitable dielectric material different from silicon nitride. Oxide-based materials include, but are not limited to, silicon oxide (SiO2). xThe resist layer 145 may be a TEOS (tetraethoxysilane; tetraethyl orthosilicate; tetraethoxysilicate; tetraethoxysilicide) oxide, silicon-rich silicon oxide, or another suitable oxide-based dielectric material. Silicon-rich silicon oxide is silicon oxide comprising, for example, more than 50% silicon. Due to the material differences, the resist layer 145 has a different etch selectivity than the subsequently formed MCESL and gate dielectric cap 142. As a result, the resist layer 145 can have a slower etch rate in the subsequent LRM etch process than both the gate dielectric cap 142 and the MCESL, which allows for a slower LRM etch process, as will be discussed in more detail below.

[0043] In some embodiments, the etch resist layer 145 has a thickness T1. In some embodiments, for the 3nm technology node, the thickness T1 ranges from about 1 angstrom to about 50 angstroms. In some other embodiments, the ratio of thickness T1 to the maximum thickness T2 of the gate dielectric cap 142 ranges from about 3:100 to about 60:100. If the thickness is too small than T1 / T2, the etch resist layer 145 may be too thin to slow down the subsequent LRM etching process. If the thickness is too large than T1 / T2, the etch resist layer 145 may be too thick to be penetrated within the expected etching duration. For other technology nodes, such as the 20nm, 16nm, 10nm, 7nm, and / or 5nm nodes, the thickness T1 of the etch resist layer 145 can range from about 1nm to about 20nm.

[0044] exist Figure 14 Once an etch resist layer 145 has been formed over the gate dielectric cap 142, an intermediate contact etch stop layer (MCESL) 146 is formed over the etch resist layer 145. The MCESL 146 can be formed using a PECVD process and / or other suitable deposition processes. In some embodiments, the MCESL 146 is a silicon nitride layer and / or has a junction with the subsequently formed ILD layer (such as...). Figure 15 Other suitable materials with different etch selectivity (as shown). In some embodiments, both the gate dielectric cap 142 and MCESL 146 are silicon nitride, so the etch resist layer 145 (e.g., an oxide-based layer) has a different etch selectivity than both the gate dielectric cap 142 and MCESL 146. In some embodiments, the thickness T3 of MCESL 146 is greater than the thickness T1 of the etch resist layer 145. For example, the thickness T3 of MCESL 146 is in the range of about 3 nm to about 20 nm.

[0045] refer to Figure 15Another ILD layer 148 is formed on top of the MCESL 146. In some embodiments, the ILD layer 148 comprises materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide (e.g., borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG)), and / or other suitable dielectric materials (e.g., silicon nitride) having a different etch selectivity than the MCESL 146. In some embodiments, the ILD layer 148 is made of silicon oxide (SiO2). x The ILD layer 148 can be deposited using a PECVD process or other suitable deposition techniques. In some embodiments, the thickness T4 of the ILD layer 148 is greater than the thickness T3 of the MCESL 146 and the thickness T1 of the etch-resistant layer 145. In some other embodiments, the thickness T4 of the ILD layer 148 is greater than the total thickness of the MCESL 146 and the etch-resistant layer 145. For example, the thickness T4 of the ILD layer 148 is in the range of about 3 nm to about 100 nm.

[0046] refer to Figure 16 The ILD layer 148 is patterned using a first etching process (also known as a via etching process) ET1 to form via openings O21 extending through the ILD layer 148. In some embodiments, the via etching process ET1 is an anisotropic etching process, such as plasma etching. Taking plasma etching as an example, [the process involves] patterning the ILD layer 148 to form via openings O21 extending through the ILD layer 148. Figure 15 The semiconductor substrate 12 of the illustrated structure is loaded into a plasma tool and exposed to a plasma environment generated by RF or microwave power in a gaseous mixture of a fluorine-containing gas (e.g., C4F8, C5F8, C4F6, CHF3, or similar substances), an inert gas (e.g., argon or helium), and optionally a weak oxidant (e.g., O2 or CO, or similar substances) for a duration sufficient to etch through the ILD layer 148 and even recess the exposed portion of the MCESL 146 at the bottom of the via opening O21. The plasma generated in a gaseous mixture including C4F6, CF4, CHF3, O2, and argon can be used to etch through the ILD layer 148 and recess the exposed portion of the MCESL 146 at the bottom of the via opening O21. The pressure of the plasma etching environment is between about 10 mTorr and about 100 mTorr, and the plasma is generated by RF power between about 50 watts and 1000 watts.

[0047] In some embodiments, the aforementioned etchant and etching conditions for the via etching process ET1 are selected in such a way that MCESL 146 (e.g., SiN) exhibits better performance than ILD layer 148 (e.g., SiO2). xA slower etch rate. This allows MCESL 146 to act as a detectable etch endpoint, which in turn prevents excessive over-etching and thus prevents punch-through or penetration through MCESL 146. In other words, the via etching process ET1 is adapted to etch silicon oxide at a faster etch rate than etching silicon nitride. It has been observed that the etch rate of silicon nitride increases when the etch plasma is generated from a hydrogen (H2) gaseous mixture. Therefore, according to some embodiments of this disclosure, the via etching process ET1 is performed using a hydrogen-free gaseous mixture. In other words, the plasma in the via etching process ET1 is generated in a hydrogen-free (H2) gaseous mixture. This keeps the silicon nitride etch rate low in the via etching process ET1, which in turn allows the silicon oxide (i.e., the ILD material) to be etched at a faster etch rate than etching silicon nitride (i.e., MCESL and gate dielectric cap material).

[0048] In some embodiments, a photolithography process is performed prior to the via etching process ET1 to define a desired top-view pattern of the via opening O21. For example, this photolithography process may include spin-coating a photoresist layer (such as...) over the ILD layer 148. Figure 15 As shown), a post-exposure baking process is performed, and a photoresist layer is developed to form a patterned mask with a top-view pattern of via openings O21. In some embodiments, patterning the photoresist to form the patterned mask can be performed using electron beam lithography or extreme ultraviolet (EUV) lithography.

[0049] Figure 17 A cross-sectional view of the initial stage of a second etching process (also known as an LRM etching process) ET2 according to some embodiments of the present disclosure is shown, as well as Figure 18 A cross-sectional view of the final stage of the LRM etching process ET2 according to some embodiments of the present disclosure is shown. The etching duration of the LRM etching process ET2 is controlled to penetrate (or through) the MCESL 146 and the resist layer 145, thereby deepening or extending the via O21 down to the source / drain contact 144. As a result of the LRM etching process ET2, the source / drain contact 144 is exposed at the bottom of the deepened via opening O21.

[0050] In some embodiments, the LRM etching process ET2 is an anisotropic etching process using different etchants and / or etching conditions than the via etching process ET1, such as plasma etching (e.g., inductively coupled plasma (ICP), capacitively coupled plasma (CCP), etc.). The etchant and / or etching conditions of the LRM etching process ET2 are selected such that the resist layer 145 (e.g., an oxide-based material) exhibits a slower etching rate than the MCESL 146 and the gate dielectric cap 142 (e.g., silicon nitride). In other words, in the LRM etching process ET2, the resist layer 145 has higher etch resistance than the MCESL 146 and the gate dielectric cap 142. In this way, the resist layer 145 can slow down the LRM etching process ET2, which in turn slows down the vertical etching rate and thus slows down the depth increase in the via opening O21 when it reaches the resist layer 145. This reduced depth increase thus prevents the formation of a serrated pattern in the deepened via opening O21, which in turn reduces the risk of leakage current (e.g., leakage current from the source / drain via to the gate structure). Furthermore, since the etch resist layer 145 slows down the vertical etch rate of the lower portion of the via opening O21 but not its lateral etch rate when the via opening O21 reaches the etch resist layer 145, the LRM etching process ET2 can laterally extend the lower portion of the via opening O21 during etching the etch resist layer 145. This allows for an increase in the bottom width of the via opening O21, and the sidewall profile of the via opening O21 can become more vertical or steeper than before penetrating the etch resist layer 145, such as... Figures 17-18 As shown. For example, before the resist layer 145 is etched, the via opening O21 has sidewalls extending at an angle θ1, as... Figure 17 As shown. However, after the etch-resistant layer 145 is etched, as... Figure 18 As shown, the via opening O21 has a sidewall extending at an angle θ2, which is greater than the previous angle θ1. Furthermore, before the resist layer 145 is etched, the via opening O21 has a bottom width WB1 at its bottom, as shown... Figure 17 As shown. After the resist layer 145 is etched, as Figure 18 As shown, the bottom width WB2 of the via opening O21 is greater than the previous bottom width WB1.

[0051] Taking plasma etching as an example of the LRM etching process ET2, it will have Figure 16 The semiconductor substrate 12 with the structure shown is loaded into a plasma tool and exposed to fluorine-containing gases (e.g., CHF3, CF4, C2F2, C4F6, C6) by RF or microwave power. x H y F zThe plasma environment is generated in a gaseous mixture of one or more of the following: (x, y, z = 0-9) or similar substances, hydrogen-containing gases (e.g., H2), nitrogen-containing gases (e.g., N2), oxygen-containing gases (e.g., O2), and inert gases (e.g., argon or helium) for a controlled transition time sufficient to etch through MCESL 146 and the underlying resist layer 145 at each target location across the entire wafer. The pressure of the plasma etching environment is between approximately 10 mTorr and approximately 100 mTorr, and the plasma is generated by an RF power between approximately 50 watts and 1000 watts.

[0052] The plasma generated by the hydrogen-containing gas mixture can etch nitride-based materials (e.g., silicon nitride) at a faster etch rate than etching oxide-based materials (e.g., silicon oxide). Therefore, the LRM etching process ET2 using the hydrogen-containing gas mixture etches the oxide-based resist layer 145 at a slower etch rate than etching the nitride-based MCESL 146. In this way, the resist layer 145 can slow down the LRM etching process ET2 as the via opening O21 extends downwards into the resist layer 145. In some embodiments, the LRM etching ET2 uses a gas mixture of CHF3 and H2 gases, wherein the flow rate ratio of CHF3 to H2 gases is from about 1:1 to about 1:100. In some embodiments, the LRM etching ET2 uses a gas mixture of CF4 and H2 gases, wherein the flow rate ratio of CF4 to H2 gases is from about 1:1 to about 1:100. Excessive H2 gas flow rate may result in an excessively fast etch rate when etching the gate dielectric cap 142, which, in turn, may lead to non-negligible serrated recesses in the via opening O21. Insufficient H2 gas flow rate may result in insufficient etch selectivity between the etch resist layer 145 and the MCESL 146. In some embodiments, the ratio of the etch rate of the etch resist layer 145 to the etch rate of the MCESL 146 and / or the gate dielectric cap 142 is in the range of about 5 to about 10.

[0053] In some embodiments where the thickness of the resist layer 145 is no greater than about 5 nm, the LRM etching process ET2 is a single-step etching using a highly selective hydrogen-containing etchant, which etches the nitride-based material at a faster etch rate than the etch of oxide-based materials. In some embodiments where the thickness of the resist layer 145 is greater than about 5 nm, the LRM etching process ET2 is a two-step etching, which first performs a highly selective etching followed by a low-selective etching. The highly selective etching etches the MCESL 146 at a faster etch rate than the etch resist layer 145 and is performed with a controlled over-etch time sufficient to etch through the MCESL 146 and shape the via opening O21 to have a more vertical sidewall profile. The low-selective etching etches both the resist layer 145 and the MCESL 146 at a comparable etch rate, thereby allowing through-etch of the resist layer 145 in a shortened duration. In some embodiments where the LRM etching process ET2 is a two-step etching, the highly selective etching through the nitride-based MCESL 146 uses etchants such as a mixture of CHF3 and H2 gases with a CHF3 / H2 flow rate ratio from about 1:1 to about 1:100, or a mixture of CF4 and H2 gases with a CF4 / H2 flow rate ratio from about 1:1 to about 1:100. The low-selectivity etching through the oxide-based resist layer 145 uses etchants such as CF4 / CH3F / CH2F2 / CHF3 / H2 and N2 or O2 / Ar gases to achieve low-selectivity etching.

[0054] In the initial stage of the LRM etching process ET2, such as Figure 17 As shown, the plasma etchant etches MCESL 146 at a first vertical etch rate A1. In the next stage of the LRM etching process ET2, once the via opening O21 penetrates MCESL 146, the resist layer 145 is exposed, and then the plasma etchant etches the resist layer 145 at a second vertical etch rate A2, which is slower than the first vertical etch rate A1, as shown. Figure 18 As shown. As a result, the increase in depth within the via opening O21 can be slowed down by the etch resist layer 145, thereby preventing the tiger-tooth-shaped recess from extending from the bottom of the via opening O21 into the gate dielectric cap 142. Furthermore, the LRM etching process ET2 can laterally expand the lower portion of the via opening O21 during etching the etch resist layer 145, resulting in the via opening O21 having an increased bottom width and a more vertical sidewall profile, as shown. Figure 18 As shown. More specifically, the sidewall profile of the via opening O21 after etching through the resist layer 145 (as shown). Figure 18(As shown) is steeper or more vertical than before etching the resist layer 145. Due to the increased bottom width of the via opening O21, the contact area between the source / drain contact 144 and the source / drain via subsequently formed in the via opening O21 can be increased, thus reducing the contact resistance.

[0055] exist Figure 18 In some embodiments shown, the via opening O21 may expose local areas of the target source / drain contact 144 and local areas of the gate dielectric cap 142 adjacent to the target source / drain contact 144. This misalignment between the via opening O21 and the target source / drain contact 144 may be unintentionally formed due to errors in the via etching process ET1 and / or the LRM etching process ET2 (e.g., misalignment occurring during a photolithography process used to define the pattern of the via opening O21 in a patterned photoresist coated on the ILD layer 148). However, even in such misalignment, the gate dielectric cap 142 adjacent to the target source / drain contact 144 will not be unintentionally over-etched to form a serrated recess because the increase in depth in the via opening O21 is slowed during penetration through the resist layer 145, as previously discussed. Assuming that the via opening O21 has no tiger-tooth-shaped recess or has a negligible tiger-tooth-shaped recess, the risk of leakage current (e.g., leakage current between the gate structure 130 and the source / drain via subsequently formed in the via opening O21) can be reduced.

[0056] exist Figure 18 In some embodiments shown, the sidewall of the via opening O21 extends linearly through the entire thickness of the ILD layer 148, the entire thickness of the MCESL 146, and the entire thickness of the etch-resistant layer 145, without any change in slope. Figure 18 In some embodiments shown, the via opening O21 may still have a tapered sidewall profile due to the anisotropic etching nature of the LRM etching process ET2, but this tapered profile is more vertical compared to not using the resist layer 145 to slow down the LRM etching process ET2. In some other embodiments, the etching conditions of the LRM etching process ET2 and / or the preceding via etching process ET1 can be fine-tuned to allow the via opening O21 to have a vertical sidewall profile.

[0057] refer to Figure 19AA source / drain via 150 is then formed in the via opening O21 to physically connect and electrically connect to the target source / drain contact 144. By way of example and not limitation, the source / drain via 150 is formed by depositing one or more metallic materials to overfill the via opening O21, followed by a CMP process to remove excess (one or more) metallic materials outside the via opening O21. As a result of the CMP process, the source / drain via 150 has a top surface substantially coplanar with the ILD layer 148. The source / drain via 150 may include metallic materials such as copper, aluminum, tungsten, or combinations thereof, and may be formed using PVD, CVD, or ALD. In some embodiments, the source / drain via 150 may also include one or more barrier / adhesion layers (not shown) to protect the ILD layer 148, MCESL 146, and / or etch resist layer 145 from metal diffusion (e.g., copper diffusion). The one or more barrier / adhesion layers may include titanium, titanium nitride, tantalum, or tantalum nitride, and may be formed using PVD, CVD, or ALD, etc.

[0058] The source / drain via 150 inherits the geometry of the via opening O21, which has a vertical sidewall profile and lacks a serrated profile. Therefore, the source / drain via 150 also has a vertical sidewall profile and lacks a serrated profile. More specifically, the sidewalls of the source / drain via 150 extend linearly through the entire thickness of the ILD layer 148, the entire thickness of the MCESL 146, and the entire thickness of the etch resist layer 145, without any change in slope.

[0059] exist Figure 19A In some embodiments shown, due to unintentional misalignment during the photolithography and etching processes that form the source / drain via 150, the source / drain via 150 may contact local areas of the source / drain contact 144 and local areas of the adjacent gate dielectric cap 142. However, in Figure 19B In some other embodiments shown, the entire bottom surface of the source / drain via 150 may contact the underlying source / drain contact 144 and be spaced apart from the adjacent gate dielectric cap 142.

[0060] Figures 20-25 Exemplary cross-sectional views of various stages for manufacturing an integrated circuit structure 100a according to some other embodiments of the present disclosure are shown. It should be understood that... Figures 20-25 Additional operations are provided before, during, and after the process shown, and for additional embodiments of the method, some of the operations described below may be replaced or eliminated. The order of these operations / processes may be interchangeable. In the following embodiments, [the following may be used in conjunction with]... Figures 1-19BThe same or similar configurations, materials, processes and / or operations described herein may be omitted, and detailed descriptions may be omitted.

[0061] In formation Figure 15 Following the structure shown, the ILD layer 148 is patterned to form a gate contact opening O31, which extends downward through the ILD layer 148, MCESL 146, etch resist layer 145 and gate dielectric cap 142 to reach the gate metal cap 138. Figure 20 The resulting structure is shown. The ILD layer 148 can be patterned using appropriate photolithography and etching techniques.

[0062] Next, as Figure 21 As shown, a patterned mask layer MA1 is formed on substrate 12 to fill the gate contact opening O31. The patterned mask layer MA1 has an opening O32 located directly above the target source / drain contact 144. In some embodiments, the patterned mask layer MA1 may be a photoresist mask formed by a suitable photolithography process. For example, the photolithography process may include, for example, a photoresist mask formed by a suitable photolithography process. Figure 20 A photoresist layer is spin-coated onto the structure shown, followed by a post-exposure baking process and development of the photoresist layer to form a patterned mask layer MA1. In some embodiments, patterning the photoresist to form a patterned mask element can be performed using electron beam lithography or extreme ultraviolet (EUV) lithography.

[0063] refer to Figure 22 With the patterned mask layer MA1 completed, via etching process ET3 is performed to form via openings O33 extending through ILD layer 148. The etching duration of via etching process ET3 is controlled to stop before penetrating MCESL 146. Process details of via etching process ET3 have been discussed previously regarding via etching process ET1, and therefore will not be repeated here for the sake of brevity.

[0064] Figure 23 A cross-sectional view of the initial stage of the LRM etching process ET4 according to some embodiments of the present disclosure is shown, and Figure 24 A cross-sectional view of the final stage of the LRM etching process ET4 according to some embodiments of the present disclosure is shown. The etching duration of the LRM etching process ET4 is controlled to penetrate the MCESL 146 and the resist layer 145, thereby deepening or expanding the via opening O33 down to the target source / drain contact 144. As a result of the LRM etching process ET4, the source / drain contact 144 is exposed at the bottom of the deepened via opening O33. Process details of the LRM etching process ET4 have been discussed previously with respect to the LRM etching process ET2, and therefore will not be repeated here for the sake of brevity.

[0065] The etchant and / or etching conditions of the LRM etching process ET4 are selected in such a way that the resist layer 145 (e.g., an oxide-based material) exhibits a slower etching rate than the MCESL 146 and the gate dielectric cap 142 (e.g., silicon nitride). In this manner, the resist layer 145 slows down the LRM etching process ET4, which in turn slows down the vertical etching rate and thus slows down the depth increase in the via opening O33 as it reaches the resist layer 145. This slowed depth increase therefore prevents the formation of a serrated pattern in the deepened via opening O33 (e.g., in the portion of the gate dielectric cap 142 exposed by the via opening O33), which in turn reduces the risk of leakage current. Furthermore, since the etch resist layer 145 slows down the vertical etching rate of the lower part of the via opening O33 but not its lateral etching rate when the via opening O33 reaches the etch resist layer 145, the LRM etching process ET4 can laterally expand the lower part of the via opening O33 during etching the etch resist layer 145. This allows the bottom width of the via opening O33 to increase, and the sidewall profile of the via opening O33 can become more vertical or steeper than before penetrating the etch resist layer 145. Figures 23-24 As shown.

[0066] After the LRM etching process ET4 is completed, the patterned mask layer MA1 is removed from the gate contact opening O31 by ashing and / or wet stripping, and then the mating contact 152 is formed to fill both the deepened via opening O33 and the gate contact opening O31. Figure 25 The resulting structure is shown. The gate structure 130 is electrically coupled to the source / drain epitaxial structure 122 via the source / drain contact 144, the mating contact 152, and the metal cap 138. The material and manufacturing process details of the mating contact 152 are similar to those of the source / drain via 150, and therefore will not be repeated here for the sake of brevity.

[0067] Figures 26 to 45B Perspective views and cross-sectional views of intermediate stages in the formation of an integrated circuit structure 200 according to some embodiments of the present disclosure are shown. According to some exemplary embodiments, the formed transistors may include p-type transistors (e.g., p-type GAA FETs) and n-type transistors (e.g., n-type FAA FETs). In the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. It should be understood that... Figures 26 to 45B Additional operations are provided before, during, and after the process shown, and some of the operations described below may be replaced or eliminated in additional embodiments of the method. The order of these operations / processes may be interchangeable.

[0068] Figure 26 , Figure 27 , Figure 29A , Figure 30A , Figure 31A and Figure 32A These are perspective views of some embodiments of an integrated circuit structure 200 during an intermediate stage of manufacturing. Figure 29B , Figure 30B , Figure 31B , Figure 32B , Figure 33-35 , Figure 36A and Figure 37-45B It is along the first tangent (e.g., Figure 29A The first tangent (XX) is a cross-sectional view of some embodiments of an integrated circuit structure 200 during an intermediate stage of manufacturing, the first tangent being along the length of the channel and perpendicular to the top surface of the substrate. Figure 36B It is along the second tangent (e.g., Figure 29A The second tangent (YY) is a cross-sectional view of some embodiments of the integrated circuit structure 200 during the intermediate stage of manufacturing, in the gate region and perpendicular to the length direction of the channel.

[0069] refer to Figure 26 An epitaxial stack 220 is formed on substrate 210. In some embodiments, substrate 210 may include silicon (Si). Alternatively, substrate 210 may include germanium (Ge), silicon germanium (SiGe), III-V materials (e.g., GaAs, GaP, GaAsP, AlInAs, AlGaAs, GaInAs, InAs, GaInP, InP, InSb, and / or GaInAsP; or combinations thereof), or other suitable semiconductor materials. In some embodiments, substrate 210 may include a semiconductor-on-insulator (SOI) structure, such as a buried dielectric layer. Alternatively, substrate 210 may include a buried dielectric layer such as a buried oxide (BOX) layer, which is formed, for example, by a technique called oxygen implantation separation (SIMOX), wafer bonding, SEG, or other suitable methods.

[0070] The epitaxial stack 220 includes epitaxial layers 222 having a first composition, with epitaxial layers 224 having a second composition interposed in these epitaxial layers 222. The first and second compositions may be different. In some embodiments, the epitaxial layer 222 is SiGe, and the epitaxial layer 224 is silicon (Si). However, other embodiments are possible, including those providing first and second compositions with different oxidation rates and / or etch selectivity. In some embodiments, the epitaxial layer 222 comprises SiGe, and in the case where the epitaxial layer 224 comprises Si, the Si oxidation rate of the epitaxial layer 224 is less than the SiGe oxidation rate of the epitaxial layer 222.

[0071] Epitaxial layer 224, or portions thereof, can form one or more nanosheet channels of a multi-gate transistor. The term nanosheet is used herein to refer to any portion of material having a nanometer or even micrometer-scale size and an elongated shape, regardless of the cross-sectional shape of that portion. Thus, the term refers to both elongated material portions with circular and substantially circular cross-sections, and beam-shaped or strip-shaped material portions including, for example, cylindrical or substantially rectangular cross-sections. The use of epitaxial layer 224 to define one or more channels of a device is further discussed below.

[0072] Note that the three epitaxial layers 222 and 224 are as follows: Figure 26 The alternating arrangement shown is for illustrative purposes only and is not intended to limit the scope beyond that specifically described in the claims. It will be understood that any number of epitaxial layers may be formed in the epitaxial stack 220; the number of layers depends on the desired number of channel regions of the transistor. In some embodiments, the number of epitaxial layers 224 is between 2 and 10.

[0073] As described in more detail below, epitaxial layer 224 can be used as one or more channel regions of a subsequently formed multi-gate device, and its thickness is selected based on device performance considerations. Epitaxial layer 222 in the channel region(s) can eventually be removed and used to define the vertical distance between adjacent channel regions(s) of the subsequently formed multi-gate device, and its thickness is selected based on device performance considerations. Therefore, epitaxial layer 222 can also be referred to as a sacrificial layer, and epitaxial layer 224 can also be referred to as a channel layer.

[0074] For example, the epitaxial growth of the layers of epitaxial stack 220 can be performed using molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes. In some embodiments, the epitaxially grown layer (e.g., epitaxial layer 224) comprises the same material as the substrate 210. In some embodiments, the epitaxially grown layers 222 and 224 comprise materials different from the substrate 210. As described above, in at least some examples, epitaxial layer 222 comprises an epitaxially grown silicon-germanium (SiGe) layer, and epitaxial layer 224 comprises an epitaxially grown silicon (Si) layer. Alternatively, in some embodiments, either epitaxial layer 222 or 224 may comprise other materials, such as germanium, compound semiconductors (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (e.g., SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP), or combinations thereof. As discussed, the materials of epitaxial layers 222 and 224 can be selected based on providing different oxidation and / or etch selectivity characteristics. In some embodiments, epitaxial layers 222 and 224 are substantially doped (i.e., having about 0 cm⁻¹). -3 To approximately 1×10 18 cm -3 (the concentration of non-intrinsic dopants), where, for example, no intentional doping is performed during the epitaxial growth process.

[0075] refer to Figure 27 A plurality of semiconductor fins 230 extending from the substrate 210 are formed. In various embodiments, each fin 230 includes a substrate portion 212 formed from the substrate 210 and portions of each epitaxial layer of the epitaxial stack including epitaxial layers 222 and 224. The fins 230 can be fabricated using suitable processes including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns, for example, with spacing smaller than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on the substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the fins 230 can then be patterned using the remaining spacers or mandrels by etching the initial epitaxial stack 220. This etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes.

[0076] exist Figure 26 and Figure 27In the illustrated embodiment, a hard mask (HM) layer 910 is formed on the epitaxial stack 220 prior to patterning the fin 230. In some embodiments, the HM layer includes an oxide layer 912 (e.g., a pad oxide layer that may include SiO2) and a nitride layer 914 (e.g., a pad nitride layer that may include Si3N4) formed on the oxide layer. The oxide layer 912 may act as an adhesion layer between the epitaxial stack 220 and the nitride layer 914, and may also act as an etch stop layer for etching the nitride layer 914. In some examples, the HM oxide layer 912 includes thermally grown oxides, oxides deposited by chemical vapor deposition (CVD), and / or oxides deposited by atomic layer deposition (ALD). In some embodiments, the HM nitride layer 914 is deposited on the HM oxide layer 912 by CVD and / or other suitable techniques.

[0077] The fins 230 can then be fabricated using appropriate processes including photolithography and etching. The photolithography process may include: forming a photoresist layer (not shown) over the HM layer 910, exposing the photoresist to a pattern, performing a post-exposure baking process, and developing the photoresist to form a patterned mask comprising the photoresist. In some embodiments, patterning the photoresist to form a patterned mask element can be performed using an electron beam lithography process or an extreme ultraviolet (EUV) lithography process utilizing light in the EUV region (having a wavelength of, for example, about 1-200 nm). The patterned mask can then be used to protect certain areas of the substrate 210 and the layers formed thereon, while the etching process forms trenches 202 in the unprotected areas, which penetrate the HM layer 910, through the epitaxial stack 220, and into the substrate 210, thereby leaving a plurality of extended fins 230. The trenches 202 can be etched using dry etching (e.g., reactive ion etching), wet etching, and / or combinations thereof. Many other embodiments of the method of forming fins on a substrate can also be used, including, for example, defining a fin region (e.g., by means of a mask or isolation region) and epitaxially growing an epitaxial stack 220 in the form of fin 230.

[0078] Next, as Figure 28 As shown, an STI region 240 is formed between the insertion fins 230. The material and process details of the STI region 240 are similar to those of the previously discussed STI region 14, and therefore will not be repeated for the sake of brevity.

[0079] refer to Figure 29A and Figure 29BA dummy gate structure 250 is formed on the substrate 210 and is at least partially disposed on the fin 230. The portion of the fin 230 located below the dummy gate structure 250 may be referred to as a channel region. The dummy gate structure 250 may also define a source / drain (S / D) region of the fin 230, for example, a region of the fin 230 adjacent to the channel region and located on the opposite side of the channel region.

[0080] The dummy gate formation step first forms a dummy gate dielectric layer 252 over the fin 230. Subsequently, a dummy gate electrode layer 254 and a hard mask are formed over the dummy gate dielectric layer 252. The hard mask may include multiple layers 256 and 258 (e.g., oxide layer 256 and nitride layer 258). The hard mask is then patterned, and subsequently, the dummy gate electrode layer 254 is patterned using the patterned hard mask as an etch mask. In some embodiments, after patterning the dummy gate electrode layer 254, the dummy gate dielectric layer 252 is removed from the S / D region of the fin 230. The etching process may include wet etching, dry etching, and / or combinations thereof. The etching process is selected to selectively etch the dummy gate dielectric layer 252 while substantially not etching the fin 230, the dummy gate electrode layer 254, the oxide mask layer 256, and the nitride mask layer 258. The materials of the dummy gate dielectric layer and the dummy gate electrode layer are similar to those of the previously discussed dummy gate dielectric layer 108 and dummy gate electrode layer 110, so they will not be repeated for the sake of brevity.

[0081] After the dummy gate structure 250 is formed, gate spacers 260 are formed on the sidewalls of the dummy gate structure 250. For example, a spacer material layer is deposited on the substrate 210. The spacer material layer may be a conformal layer, which is subsequently etched back to form gate sidewall spacers. In the illustrated embodiment, the spacer material layer 260 is conformally disposed on the top and sidewalls of the dummy gate structure 250. The spacer material layer 260 may include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon oxycarbide, SiOCN film, and / or combinations thereof. In some embodiments, the spacer material layer 260 includes multiple layers, such as a first spacer layer 262 and a second spacer layer 264 formed on the first spacer layer 262 (in Figure 29B(As shown in the diagram). For example, spacer material layer 260 can be formed by depositing a dielectric material on gate structure 250 using a suitable deposition process. An anisotropic etching process is then performed on the deposited spacer material layer 260 to expose portions of fin 230 not covered by dummy gate structure 250 (e.g., in the source / drain regions of fin 230). The portion of the spacer material layer directly above the dummy gate structure 250 can be completely removed by this anisotropic etching process. The portions of the spacer material layer on the sidewalls of the dummy gate structure 250 can be retained, forming gate sidewall spacers, which are referred to as gate spacers 260 for simplicity. It should be noted that although gate spacers 260 are... Figure 29B The cross-sectional view shows a multi-layered structure, but for simplicity, they are... Figure 29A It is shown as a single-layer structure in the perspective view.

[0082] Next, as Figure 30A and Figure 30B As shown, a recess R6 is formed in the semiconductor fin 230 and between the corresponding dummy gate structures 250 by etching the lateral extension of the semiconductor fin 230 beyond the exposed portion of the gate spacer 260 (e.g., in the source / drain region of the fin 230) using, for example, an anisotropic etching process. This anisotropic etching process uses the dummy gate structures 250 and the gate spacer 260 as etching masks. After this anisotropic etching, the end faces of the sacrificial layer 222 and the channel layer 224 can be aligned with the corresponding outermost walls of the gate spacer 260 due to the anisotropic etching. In some embodiments, this anisotropic etching can be performed by dry chemical etching utilizing a plasma source and reactive gases. The plasma source can be an inductively coupled plasma (ICR) source, a transformer coupled plasma (TCP) source, an electron cyclotron resonance (ECR) source, etc., and the reactant gas can be, for example, a fluorine-based gas (e.g., SF6, CH2F2, CH3F, CHF3, etc.), a chloride-based gas (e.g., Cl2), hydrogen bromide gas (HBr), oxygen (O2), etc., or a combination of the foregoing.

[0083] Next, in Figure 31A and Figure 31BIn this process, the sacrificial layer 222 is recessed laterally or horizontally using a suitable etching technique to form lateral recesses R7, each of which is vertically located between the respective channel layers 224. This step can be performed using a selective etching process. By way of example and not limitation, the sacrificial layer 222 is SiGe and the channel layer 224 is silicon, thereby allowing selective etching of the sacrificial layer 222. In some embodiments, selective wet etching includes APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture), which etches SiGe at a faster etch rate than etching Si. In some embodiments, selective etching includes SiGe oxidation followed by SiGeO. x Removal. For example, oxidation can be provided by O3 cleaning, then SiGeO x Removed by an etchant such as NH4OH, which selectively etches SiGeO at a faster etch rate than Si. x Furthermore, because the oxidation rate of Si is much lower than that of SiGe (sometimes as low as 1 / 30th), the channel layer 224 is not significantly etched by the process of laterally recessed sacrificial layer 222. As a result, the channel layer 224 extends laterally beyond the opposite end face of sacrificial layer 222.

[0084] exist Figure 32A and Figure 32B In the middle, an internal spacer material layer 270 is formed to fill the spacer material layer 270 referenced above. Figure 31A and Figure 31B The recess R7 left by the lateral etching of the sacrificial layer 222 is discussed. The internal spacer material layer 270 can be a low-k dielectric material, such as SiO2, SiN, SiCN, or SiOCN, and can be formed by a suitable deposition method such as ALD. After the deposition of the internal spacer material layer 270, an anisotropic etching process can be performed to trim the deposited internal spacer material 270 so that only a portion of the deposited internal spacer material 270 filling the recess R7 left by the lateral etching of the sacrificial layer 222 is retained. After the trimming process, for simplicity, the remaining portion of the deposited internal spacer material is referred to as the internal spacer 270. The internal spacer 270 is used to isolate the metal gate from the source / drain regions formed in subsequent processes. Figure 32A and Figure 32B In the example, the sidewall of the inner spacer 270 is aligned with the sidewall of the channel layer 224.

[0085] exist Figure 33In this process, a source / drain epitaxial structure 280 is formed on the source / drain region S / D of the semiconductor fin 230. The source / drain epitaxial structure 280 can be formed by performing an epitaxial growth process that provides epitaxial material on the fin 230. During this epitaxial growth process, a dummy gate structure 250, a gate sidewall spacer 260, and an internal spacer 270 confine the source / drain epitaxial structure 280 to the source / drain region S / D. The material and process details of the source / drain epitaxial structure 280 of the GAA FET are similar to those of the previously discussed FinFET source / drain epitaxial structure 122, and therefore will not be repeated for the sake of brevity.

[0086] exist Figure 34 In this configuration, an interlayer dielectric (ILD) layer 310 is formed on the substrate 210. In some embodiments, a contact etch stop layer (CESL) is also formed prior to the formation of the ILD layer 310. The material and process details of the ILD layer 310 are similar to those of the ILD layer 126, and therefore will not be repeated for the sake of brevity. In some examples, a planarization process may be performed after the deposition of the ILD layer 310 to remove excess material from the ILD layer 310. For example, the planarization process includes a chemical mechanical planarization (CMP) process, which removes the portion of the ILD layer 310 (and the CESL layer, if present) above the dummy gate structure 250 and planarizes the top surface of the integrated circuit structure 200. In some embodiments, the CMP process also removes hard mask layers 256, 258 (e.g., Figure 33 (as shown) and exposes the dummy gate electrode layer 254.

[0087] Subsequently, the dummy gate structure 250 (e.g.) is first removed. Figure 34 (as shown), and then remove the sacrificial layer 222. Figure 35The resulting structure is illustrated. In some embodiments, the dummy gate structure 250 is removed using a selective etching process (e.g., selective dry etching, selective wet etching, or a combination thereof) that etches the material in the dummy gate structure 250 at a faster etch rate than etching other materials (e.g., gate sidewall spacers 260 and / or ILD layer 310), thereby forming a gate trench GT2 between the respective gate sidewall spacers 260, and exposing the sacrificial layer 222 in the gate trench GT2. Subsequently, the sacrificial layer 222 in the gate trench GT2 is removed using another selective etching process that etches the sacrificial layer 222 at a faster etch rate than etching the channel layer 224, thereby forming an opening O6 between adjacent channel layers 224. In this way, the channel layer 224 becomes a nanosheet suspended above the substrate 210 and located between the source / drain epitaxial structures 280. This step is also referred to as a channel release process. In this intermediate processing step, the openings O6 between the nanosheets 224 can be filled with ambient conditions (e.g., air, nitrogen, etc.). In some embodiments, the nanosheets 224 can be interchangeably referred to as nanowires, nanoplates, and nanorings, depending on their geometry. For example, in some other embodiments, the channel layer 224 can be trimmed into a substantially circular shape (i.e., cylindrical) due to a selective etching process used to completely remove the sacrificial layer 222. In this case, the resulting channel layer 224 can be referred to as nanowires.

[0088] In some embodiments, the sacrificial layer 222 is removed using a selective wet etching process. In some embodiments, the sacrificial layer 222 is SiGe and the channel layer 224 is silicon, thereby allowing selective removal of the sacrificial layer 222. In some embodiments, the selective wet etching includes APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture). In some embodiments, the selective removal includes SiGe oxidation followed by SiGeO. x Removal. For example, oxidation can be provided by O3 cleaning, then SiGeO x Removed by an etchant such as NH4OH, which selectively etches SiGeO at a faster etch rate than Si. x Furthermore, because the oxidation rate of Si is much lower than that of SiGe (sometimes as low as 1 / 30th), the channel layer 224 may not be significantly etched by the channel release process. It can be noted that the channel release step and the preceding lateral recess sacrificial layer step (such as...) Figure 31A and Figure 31BBoth steps (as shown) use a selective etching process to etch SiGe at a faster etch rate than etching Si, so in some embodiments, the two steps can use the same etchant chemicals. In this case, the etch time / duration of the channel release step is longer than the etch time / duration of the previous lateral recess sacrificial layer step in order to completely remove the sacrificial SiGe layer.

[0089] exist Figure 36A and Figure 36B In this configuration, replacement gate structures 320 are respectively formed in the gate trench GT2 to surround each nanosheet 224 suspended in the gate trench GT2. The gate structure 320 can be the final gate of a GAA FET. The final gate structure can be a high-k / metal gate stack, but other compositions are also possible. In some embodiments, each gate structure 320 forms a gate associated with a multi-channel provided by a plurality of nanosheets 224. For example, the high-k / metal gate structure 320 is formed in an opening O6 provided by releasing the nanosheets 224 (e.g., ...). Figure 35 (As shown). In various embodiments, the high-k / metal gate structure 320 includes: a gate dielectric layer 322 formed around a nanosheet 224, a work function metal layer 324 formed around the gate dielectric layer 322, and a fill metal 326 formed around the work function metal layer 324 and filling the remaining portion of the gate trench GT2. The gate dielectric layer 322 includes an interface layer (e.g., a silicon oxide layer) and a high-k gate dielectric layer located above the interface layer. As used and described herein, the high-k gate dielectric includes a dielectric material having a high dielectric constant (e.g., greater than the dielectric constant (~3.9) of thermally heated silicon oxide). The work function metal layer 324 and / or the fill metal layer 326 used within the high-k / metal gate structure 320 may include a metal, a metal alloy, or a metal silicide. The formation of the high-k / metal gate structure 320 may include the deposition of various gate materials, one or more liner layers, and one or more CMP processes for removing excess gate material. As shown in the figure taken along the longitudinal axis of the high-k / metal gate structure 320 Figure 36B As shown in the cross-sectional view, the high-k / metal gate structure 320 surrounds each nanosheet 224 and is therefore referred to as the gate of the GAA FET. The material and process details of the gate structure 320 of the GAA FET are similar to those of the gate structure 130 of the FinFET, and therefore will not be repeated for the sake of brevity.

[0090] exist Figure 37In this process, an etch-back process is performed to replace the gate structure 320 and the gate spacer 260, thereby forming a recess on the etch-back gate structure 320 and the etch-back gate spacer 260. In some embodiments, because the material replacing the gate structure 320 has a different etch selectivity than the gate spacer 260, the top surface of the replacing gate structure 320 can be at a different level than the top surface of the gate spacer 260. For example, in... Figure 37 In the illustrated embodiment, the top surface of the replacement gate structure 320 is lower than the top surface of the gate spacer 260. However, in some other embodiments, the top surface of the replacement gate structure 320 may be flush with or higher than the top surface of the gate spacer 260.

[0091] Then, a metal cap 330 is formed on top of the replacement gate structure 320 using a suitable process such as CVD or ALD. By way of example and not limitation, the metal cap 330 may be a substantially fluorine-free tungsten (FFW) film with less than 5 atomic percent fluorine impurities and more than 3 atomic percent chlorine impurities. Process details regarding the formation of the FFW have been previously discussed with respect to the metal cap 138, and will therefore be repeated for the sake of brevity.

[0092] exist Figure 38 In this configuration, a gate dielectric cap 340 is formed over the metal cap 330 and the gate spacer 260. Because the top surface of the metal cap 330 is lower than the top surface of the gate spacer 260, each dielectric cap 340 has a stepped bottom surface, with the lower step contacting the top surface of the metal cap 330 and the upper step contacting the top surface of the gate spacer 260. The material and process details of the dielectric cap 340 are similar to those of the previously discussed dielectric cap 142, and therefore will not be repeated for the sake of brevity.

[0093] exist Figure 39In this process, source / drain contacts 350 extending through the ILD layer 310 are formed. By way of example and not limitation, the formation of the source / drain contacts 350 includes: performing one or more etching processes to form contact openings extending through the ILD layer 310 to expose the source / drain epitaxial structure 280, depositing one or more metal materials to overfill the contact openings, and then performing a CMP process to remove excess metal material located outside the contact openings. In some embodiments, the one or more etching processes are selective etching, which etches the ILD layer 310 at a faster etch rate than etching the dielectric cap 340 and the gate spacer 260. As a result, this selective etching is performed using the dielectric cap 340 and the gate spacer 260 as etch masks, such that the contact openings, and therefore the source / drain contacts 350, are formed to be self-aligned with the source / drain epitaxial structure 280 without the use of additional photolithography processes. In this case, the dielectric cap 340 that allows the formation of the self-aligned contacts 350 may be referred to as the SAC cap 340.

[0094] exist Figure 40 In this process, an etch resist layer 352 is formed over the gate dielectric cap 340 and the source / drain contacts 350 using an ALD process, a PECVD process, and / or other suitable deposition processes. In some embodiments, the etch resist layer 352 is made of a different material than the material of the gate dielectric cap 340 and the subsequently formed MCESL. For example, when the gate dielectric cap 340 and the subsequently formed MCESL are made of one or more nitride-based materials (e.g., silicon nitride), the etch resist layer 352 is made of an oxide-based material, such as silicon oxide, TEOS oxide, silicon-rich silicon oxide, or other suitable oxide-based dielectric materials. Due to the difference in materials, the etch resist layer 352 has a different etch selectivity than the subsequently formed MCESL and the gate dielectric cap 340. As a result, the etch resist layer 352 can have a slower etch rate in the subsequent LRM etch process than both the gate dielectric cap 340 and the MCESL, which allows for a slower LRM etch process, as will be discussed in more detail below.

[0095] In some embodiments, the resist layer 352 has a thickness T5. In some embodiments, for the 3nm technology node, the thickness T5 ranges from about 1 angstrom to about 50 angstroms. In some other embodiments, the ratio of thickness T5 to the maximum thickness T6 of the gate dielectric cap 340 ranges from about 3:100 to about 60:100. If the thickness is too small than T5 / T6, the resist layer 352 may be too thin to slow down the subsequent LRM etching process. If the thickness is too large than T5 / T6, the resist layer 352 may be too thick to be penetrated within the expected duration. For other technology nodes, such as the 20nm, 16nm, 10nm, 7nm, and / or 5nm nodes, the thickness T5 of the resist layer 352 can range from about 1nm to about 20nm.

[0096] exist Figure 41 In this process, after an etch resist layer 352 has been formed on the gate dielectric cap 340, an MCESL 360 is subsequently deposited on the etch resist layer 352. Then, another ILD layer 370 is deposited on the MCESL 360. In some embodiments, both the gate dielectric cap 340 and the MCESL 360 are nitride-based materials (e.g., silicon nitride), and both the etch resist layer 352 and the ILD layer 370 are oxide-based materials (e.g., silicon oxide), thus the ILD layer 370 and the etch resist layer 352 have different etch selectivity than both the gate dielectric cap 340 and the MCESL 360. In some embodiments, the thickness T7 of the MCESL 360 is greater than the thickness T5 of the etch resist layer 352. For example, the thickness T7 of the MCESL 360 is in the range of about 3 nm to about 20 nm. In some embodiments, the thickness T8 of the ILD layer 370 is greater than the thickness T7 of the MCESL 360 and the thickness T5 of the etch resist layer 352. In some other embodiments, the thickness T8 of the ILD layer 370 is greater than the combined thickness of the MCESL 360 and the etch-resistant layer 352. For example, the thickness T8 of the ILD layer 370 is in the range of about 3 nm to about 100 nm.

[0097] exist Figure 42 In this process, the ILD layer 370 is patterned using a via etching process ET5 to form via openings O41 extending through the ILD layer 370. In some embodiments, the via etching process ET5 is an anisotropic etching process, such as plasma etching. The process details of the via etching process ET5 are similar to those of the previously discussed via etching process ET1, and therefore will not be repeated for the sake of brevity.

[0098] According to some embodiments of this disclosure Figure 43 A cross-sectional view of the initial stage of the LRM etching process ET6 is shown, and Figure 44The final stage of the LRM etching process ET6 is shown. The etching duration of LRM etching process ET6 is controlled to penetrate the MCESL 360 and the resist layer 352, thereby deepening or expanding the via opening O41 down to the target source / drain contact 350. As a result of LRM etching process ET6, the target source / drain contact 350 is exposed at the bottom of the deepened via opening O41. Process details of LRM etching process ET6 have been discussed previously regarding LRM etching process ET2, and therefore will not be repeated for brevity.

[0099] Due to the etch selectivity between the resist layer 352 and the MCESL 360, the resist layer 352 can slow down the LRM etching process ET6 when the MCESL 360 is penetrated. This, in turn, slows down the vertical etch rate and the depth increase in via opening O41 when it reaches the resist layer 352. This slowed depth increase can therefore prevent the formation of a serrated pattern in the via opening O41, thereby reducing the risk of leakage current. Furthermore, since the resist layer 352 slows down the vertical etch rate but not the lateral etch rate when the via opening O41 reaches the resist layer 352, the LRM etching process ET6 can laterally expand the lower part of the via opening O41 during etching the resist layer 352. This allows the bottom width of the via opening O41 to increase, and the sidewall profile of the via opening O41 can become more vertical or steeper than before penetrating the resist layer 352. Figures 43-44 As shown.

[0100] exist Figure 44 In some embodiments shown, the via opening O41 may expose local areas of the target source / drain contact 350 and local areas of the gate dielectric cap 340 adjacent to the target source / drain contact 350. This misalignment between the via opening O41 and the target source / drain contact 350 may be unintentionally formed due to errors in the via etching process ET5 and / or the LRM etching process ET6 (e.g., misalignment occurring during a photolithography process used to define the pattern of the via opening O41 in a patterned photoresist coated on the ILD layer 370). However, even in such misalignment, the gate dielectric cap 340 adjacent to the target source / drain contact 350 will not be unintentionally over-etched to form a serrated recess because the increase in depth in the via opening O41 is slowed down as it penetrates the resist layer 352, as previously discussed. Assuming that the via opening O41 has no tiger-tooth-shaped recess or has a negligible tiger-tooth-shaped recess, the risk of leakage current (e.g., leakage current between the gate structure 320 and the source / drain via subsequently formed in the via opening O41) can be reduced.

[0101] Next, in Figure 45A In the process, a source / drain via 380 is then formed in the via opening O41 to physically connect and electrically connect to the target source / drain contact 350. The material and process details of the source / drain via 380 are similar to those of the previously discussed source / drain via 150, and therefore will not be repeated for the sake of brevity.

[0102] The source / drain via 380 inherits the geometry of the via opening O41, which has a vertical sidewall profile and lacks a serrated profile. Therefore, the source / drain via 380 also has a vertical sidewall profile and lacks a serrated profile. More specifically, the sidewalls of the source / drain via 380 extend linearly through the entire thickness of the ILD layer 370, the entire thickness of the MCESL 360, and the entire thickness of the etch resist layer 352, without any change in slope.

[0103] exist Figure 45A In some embodiments shown, due to unintentional misalignment during the photolithography and etching processes of the source / drain via 380, the source / drain via 380 may contact local areas of the source / drain contact 350 and adjacent local areas of the gate dielectric cap 340. However, in Figure 45B In some other embodiments shown, the entire bottom surface of the source / drain via 380 can contact the underlying source / drain contact 350.

[0104] Figures 46-51 Exemplary cross-sectional views of various stages for manufacturing an integrated circuit structure 200a according to some other embodiments of the present disclosure are shown. It should be understood that... Figures 46-51 Additional operations are provided before, during, and after the process shown, and for additional embodiments of the method, some of the operations described below may be replaced or eliminated. The order of these operations / processes may be interchangeable. In the following embodiments, [the following may be used in conjunction with]... Figures 26-45B The same or similar configurations, materials, processes and / or operations described herein may be omitted, and detailed descriptions may be omitted.

[0105] In the formation of such Figure 41 Following the structure shown, the ILD layer 370 is patterned to form a gate contact opening O51, which extends downward through the ILD layer 370, MCESL 360 and dielectric cap 340 to reach the metal cap 330. Figure 46 The resulting structure is shown. The ILD layer 370 can be patterned using appropriate photolithography and etching techniques.

[0106] Next, as Figure 47As shown, a patterned mask layer MA2 is formed on substrate 210 to fill gate contact opening O51. The patterned mask layer MA2 has an opening O52 located directly above the target source / drain contact 350. In some embodiments, the patterned mask layer MA2 may be a photoresist mask formed by a suitable photolithography process. For example, the photolithography process may include... Figure 46 A photoresist layer is spin-coated onto the structure shown, followed by a post-exposure baking process and development of the photoresist layer to form a patterned mask layer MA2.

[0107] exist Figure 48 In this process, via etching process ET7 is performed using a patterned mask layer MA2 as an etching mask to form via openings O53 extending through ILD layer 370. The etching duration of via etching process ET7 is controlled to stop before penetrating MCESL 360. Process details of via etching process ET7 have been discussed previously regarding via etching process ET1, and therefore will not be repeated here for the sake of brevity.

[0108] Figure 49 A cross-sectional view of the initial stage of the LRM etching process ET8 according to some embodiments of the present disclosure is shown, and Figure 50 A cross-sectional view of the final stage of the LRM etching process ET8 according to some embodiments of the present disclosure is shown. The etching duration of the LRM etching process ET8 is controlled to penetrate the MCESL 360 and the resist layer 352, thereby deepening or expanding the via opening O53 down to the target source / drain contact 350. As a result of the LRM etching process ET8, the source / drain contact 350 is exposed at the bottom of the deepened via opening O53. Process details of the LRM etching process ET8 have been discussed previously with respect to the LRM etching process ET2, and therefore will not be repeated here for the sake of brevity.

[0109] The etchant and / or etching conditions of the LRM etching process ET8 are selected in such a way that the resist layer 352 (e.g., an oxide-based material) exhibits a slower etching rate than the MCESL 360 and the gate dielectric cap 340 (e.g., a nitride-based material). In this way, the resist layer 352 slows down the LRM etching process ET8, which in turn slows down the vertical etching rate and thus slows down the depth increase in the via opening O53 as it reaches the resist layer 352. This slowed depth increase therefore prevents the formation of a serrated pattern in the deepened via opening O53 (particularly in the gate dielectric cap 340 located on the opposite side of the target source / drain contact 350), which in turn reduces the risk of leakage current. Furthermore, since the etch resist layer 352 slows down the vertical etch rate of the lower part of the via opening O53 but not its lateral etch rate when the via opening O53 reaches the etch resist layer 352, the LRM etching process ET8 can laterally expand the lower part of the via opening O53 during the etching of the etch resist layer 352. This allows the bottom width of the via opening O53 to increase, and the sidewall profile of the via opening O53 can become more vertical or steeper than before penetrating the etch resist layer 352. Figures 49-50 As shown.

[0110] After completing the LRM etching process ET8, the patterned mask layer MA2 is removed from the gate contact opening O51 by ashing and / or wet stripping, and then the mating contact 390 is formed to fill both the deepened via opening O53 and the gate contact opening O51. Figure 51 The resulting structure is shown. Gate structure 320 is electrically coupled to source / drain epitaxial structure 280 via source / drain contact 350, mating contact 390, and gate metal cap 330. The material and manufacturing process details of mating contact 390 are similar to those of source / drain via 150, and therefore will not be repeated here for the sake of brevity.

[0111] Based on the above discussion, it is clear that this disclosure provides advantages. However, it should be understood that other embodiments may provide additional advantages, and not all advantages are necessarily disclosed herein, nor is any particular advantage necessary for all embodiments. One advantage is that the increase in depth within the source / drain via opening can be slowed down during the LRM etching process, which in turn prevents the formation of serrated recesses or forms negligible serrated recesses in the gate dielectric cap located next to the target source / drain contacts. Another advantage is that leakage current from the source / drain via to, for example, the gate structure can be reduced due to the prevention of serrated profiles in the source / drain via. Another advantage is that the source / drain via opening can have a more vertical sidewall profile. Another advantage is that the bottom surface area of ​​a source / drain via with a vertical sidewall profile can be increased compared to a tapered source / drain via, thus reducing the contact resistance between the source / drain via and the source / drain contacts.

[0112] In some embodiments, a method includes: forming a gate structure on a semiconductor substrate; forming a gate dielectric cap on the gate structure; forming source / drain contacts on the semiconductor substrate, with the gate dielectric cap laterally positioned between the source / drain contacts; depositing an etch resist layer on the gate dielectric cap; depositing a contact etch stop layer on the etch resist layer and depositing an interlayer dielectric (ILD) layer on the contact etch stop layer; performing a first etching process to form a via opening extending through the ILD layer and terminating before reaching the etch resist layer; performing a second etching process to deepen the via opening such that one of the source / drain contacts is exposed, wherein the second etching process etches the etch resist layer at a slower etch rate than etching the contact etch stop layer; and depositing a metal material to fill the deepened via opening. In some embodiments, the gate dielectric cap and the contact etch stop layer are nitride-based. In some embodiments, the gate dielectric cap is formed of the same material as the contact etch stop layer. In some embodiments, the etch resist layer is oxide-based. In some embodiments, the thickness of the etch resist layer is less than the thickness of the contact etch stop layer. In some embodiments, the thickness of the etch-resistant layer is less than the maximum thickness of the gate dielectric cap.

[0113] In some embodiments, the thickness of the etch-resistant layer ranges from about 1 angstrom to about 50 angstroms. In some embodiments, the etch-resistant layer is deposited using atomic layer deposition (ALD) or plasma-enhanced chemical vapor deposition (PECVD). In some embodiments, the first etching process is a plasma etching process using plasma generated from a hydrogen-free gaseous mixture. In some embodiments, the second etching process is a plasma etching process using plasma generated from a hydrogen-containing gaseous mixture. In some embodiments, the hydrogen-containing gaseous mixture is a mixture of a fluorine-containing gas and hydrogen. In some embodiments, the fluorine-containing gas is CHF3 gas, CF4 gas, or C. x H y F z The gas, or a combination thereof, wherein x, y, and z are greater than zero. In some embodiments, the gate dielectric cap remains substantially intact after the second etching process is completed.

[0114] In some embodiments, a method includes: forming a gate structure between gate spacers and on a semiconductor substrate; etching back the gate structure below the tops of the gate spacers; forming a gate dielectric cap on the etched-back gate structure; forming source / drain contacts adjacent to the sidewalls of the gate dielectric cap; depositing an etch resist layer on the gate dielectric cap and the source / drain contacts; sequentially depositing an etch stop layer and an interlayer dielectric (ILD) layer on the etch resist layer; performing a first etch process to form a via opening extending through the ILD layer; after the first etch process is completed, performing a second etch process to extend the via opening downward to the source / drain contacts, wherein after the second etch process etches through the etch resist layer, the sidewall profile of the via opening becomes more vertical than before etching the etch resist layer; and after performing the second etch process, forming a via structure in the via opening. In some embodiments, the first etch process does not etch the etch resist layer. In some embodiments, the etch resist layer and the ILD layer are oxide-based, and the etch stop layer and the gate dielectric cap are nitride-based. In some embodiments, the second etching process uses a gas mixture containing hydrogen, while the first etching process does not contain hydrogen.

[0115] In some embodiments, a device includes: source / drain epitaxial structures on a substrate; source / drain contacts on the source / drain epitaxial structures; a gate structure laterally disposed between the source / drain contacts; a gate dielectric cap on the gate structure with its bottom surface lower than the top surface of the source / drain contacts; an oxide-based etch resist layer on the gate dielectric cap; a nitride-based etch stop layer on the oxide-based etch resist layer; an interlayer dielectric (ILD) layer on the nitride-based etch stop layer; and a via structure extending through the ILD layer, the nitride-based etch stop layer, and the oxide-based etch resist layer to be electrically connected to one of the source / drain contacts. In some embodiments, the oxide-based etch resist layer is thinner than the nitride-based etch stop layer. In some embodiments, the oxide-based etch resist layer is thinner than the gate dielectric cap.

[0116] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0117] Example 1 is a method of forming a semiconductor device, comprising: forming a gate structure on a semiconductor substrate; forming a gate dielectric cap on the gate structure; forming source / drain contacts on the semiconductor substrate, wherein the gate dielectric cap is located between the source / drain contacts; depositing an etch resist layer on the gate dielectric cap; depositing a contact etch stop layer on the etch resist layer and depositing an interlayer dielectric (ILD) layer on the contact etch stop layer; performing a first etching process to form a via opening extending through the ILD layer and terminating before reaching the etch resist layer; performing a second etching process to deepen the via opening such that one of the source / drain contacts is exposed, wherein the second etching process etches the etch resist layer at a slower etch rate than etching the contact etch stop layer; and depositing a metal material to fill the deepened via opening.

[0118] Example 2 is the method described in Example 1, wherein the gate dielectric cap and the contact etch stop layer are nitride-based.

[0119] Example 3 is the method described in Example 1, wherein the gate dielectric cap is formed of the same material as the contact etch stop layer.

[0120] Example 4 is the method described in Example 1, wherein the etch-resistant layer is oxide-based.

[0121] Example 5 is the method described in Example 1, wherein the thickness of the anti-etching layer is less than the thickness of the contact etch stop layer.

[0122] Example 6 is the method described in Example 1, wherein the thickness of the etch-resistant layer is less than the maximum thickness of the gate dielectric cap.

[0123] Example 7 is the method described in Example 1, wherein the thickness of the etch-resistant layer is in the range of about 1 angstrom to about 50 angstroms.

[0124] Example 8 is the method described in Example 1, wherein the etch-resistant layer is deposited using atomic layer deposition (ALD) or plasma-enhanced chemical vapor deposition (PECVD).

[0125] Example 9 is the method described in Example 1, wherein the first etching process is a plasma etching process using plasma generated from a hydrogen-free gaseous mixture.

[0126] Example 10 is the method described in Example 1, wherein the second etching process is a plasma etching process using plasma generated from a hydrogen-containing gaseous mixture.

[0127] Example 11 is the method described in Example 10, wherein the hydrogen-containing gaseous mixture is a mixture of fluorine-containing gas and hydrogen.

[0128] Example 12 is the method described in Example 11, wherein the fluorine-containing gas is CHF3 gas, CF4 gas, or C. x H y F z A gas, or a combination thereof, wherein x, y, and z are greater than zero.

[0129] Example 13 is the method described in Example 1, wherein the gate dielectric cap remains substantially intact after the second etching process is completed.

[0130] Example 14 is a method of forming a semiconductor device, comprising: forming a gate structure between gate spacers and on a semiconductor substrate; etching back the gate structure below the top of the gate spacers; forming a gate dielectric cap on the etched-back gate structure; forming source / drain contacts adjacent to the sidewalls of the gate dielectric cap; depositing an etch resist layer on the gate dielectric cap and the source / drain contacts; sequentially depositing an etch stop layer and an interlayer dielectric (ILD) layer on the etch resist layer; performing a first etch process to form a via opening extending through the ILD layer; after the first etch process is completed, performing a second etch process to extend the via opening downward to the source / drain contacts, wherein after the second etch process etches through the etch resist layer, the sidewall profile of the via opening becomes more vertical than before etching the etch resist layer; and after performing the second etch process, forming a via structure in the via opening.

[0131] Example 15 is the method described in Example 14, wherein the first etching process does not etch the etch-resistant layer.

[0132] Example 16 is the method described in Example 14, wherein the etch-resistant layer and the ILD layer are oxide-based, and the etch-stop layer and the gate dielectric cap are nitride-based.

[0133] Example 17 is the method described in Example 14, wherein the second etching process uses a gas mixture containing hydrogen, and the first etching process does not contain the hydrogen.

[0134] Example 18 is a semiconductor device comprising: source / drain epitaxial structures on a substrate; source / drain contacts on the source / drain epitaxial structures; a gate structure laterally disposed between the source / drain contacts; a gate dielectric cap on the gate structure with its bottom surface lower than the top surface of the source / drain contacts; an oxide-based etch resist layer on the gate dielectric cap; a nitride-based etch stop layer on the oxide-based etch resist layer; an interlayer dielectric (ILD) layer on the nitride-based etch stop layer; and a via structure extending through the ILD layer, the nitride-based etch stop layer, and the oxide-based etch resist layer to be electrically connected to one of the source / drain contacts.

[0135] Example 19 is the device described in Example 18, wherein the oxide-based etch-resistant layer is thinner than the nitride-based etch-stop layer.

[0136] Example 20 is the device described in Example 18, wherein the oxide-based etch-resistant layer is thinner than the gate dielectric cap.

Claims

1. A method for forming a semiconductor device, comprising: A gate structure is formed on a semiconductor substrate; A gate dielectric cap is formed on the gate structure; Source / drain contacts are formed on the semiconductor substrate, and the gate dielectric cap is located between the source / drain contacts; An etch-resistant layer is deposited on the gate dielectric cap; A contact etch stop layer is deposited on the etch-resistant layer, and an interlayer dielectric (ILD) layer is deposited on the contact etch stop layer. A first etching process is performed to form a via opening that extends through the ILD layer and terminates before reaching the etch-resistant layer; A second etching process is performed to deepen the via opening, exposing one of the source / drain contacts. The second etching process etches the etch resist layer at a slower etch rate than the etch stop layer, and laterally expands the lower portion of the via opening while etching the etch resist layer. Deposit metallic material to fill the deepened via opening.

2. The method according to claim 1, wherein, The gate dielectric cap and the contact etch stop layer are nitride-based.

3. The method according to claim 1, wherein, The gate dielectric cap is formed of the same material as the contact etch stop layer.

4. The method according to claim 1, wherein, The etch-resistant layer is oxide-based.

5. The method according to claim 1, wherein, The thickness of the anti-etching layer is less than the thickness of the contact etch stop layer.

6. The method according to claim 1, wherein, The thickness of the etch-resistant layer is less than the maximum thickness of the gate dielectric cap.

7. The method according to claim 1, wherein, The thickness of the etch-resistant layer is in the range of 1 angstrom to 50 angstroms.

8. The method according to claim 1, wherein, The etch-resistant layer is deposited using atomic layer deposition (ALD) or plasma-enhanced chemical vapor deposition (PECVD).

9. The method according to claim 1, wherein, The first etching process is a plasma etching process that uses plasma generated from a hydrogen-free gaseous mixture.

10. The method according to claim 1, wherein, The second etching process is a plasma etching process that uses plasma generated from a hydrogen-containing gaseous mixture.

11. The method according to claim 10, wherein, The hydrogen-containing gaseous mixture is a mixture of fluorine-containing gas and hydrogen.

12. The method according to claim 11, wherein, The fluorine-containing gas is CHF3 gas, CF4 gas, or C. x H y F z A gas, or a combination thereof, wherein x, y, and z are greater than zero.

13. The method according to claim 1, wherein, The gate dielectric cap remains substantially intact after the second etching process is completed.

14. A method of forming a semiconductor device, comprising: A gate structure is formed between gate spacers and on a semiconductor substrate; The gate structure is etched back below the top of the gate spacer; A gate dielectric cap is formed on the gate structure after back etching; A source / drain contact is formed, which is adjacent to the sidewall of the gate dielectric cap; An etch-resistant layer is deposited on the gate dielectric cap and the source / drain contacts; An etch stop layer and an interlayer dielectric (ILD) layer are sequentially deposited on top of the etch-resistant layer. A first etching process is performed to form a via opening that extends through the ILD layer; After the first etching process is completed, a second etching process is performed to extend the via opening downwards to the source / drain contacts, wherein, after the second etching process etches through the resist layer, the sidewall profile of the via opening becomes more vertical than before etching the resist layer, wherein the second etching process laterally expands the lower portion of the via opening while etching the resist layer; and After performing the second etching process, a via structure is formed in the via opening.

15. The method according to claim 14, wherein, The first etching process did not etch the etch-resistant layer.

16. The method of claim 14, wherein, The etch-resistant layer and the ILD layer are oxide-based, and the etch-stop layer and the gate dielectric cap are nitride-based.

17. The method of claim 14, wherein, The second etching process uses a gas mixture containing hydrogen, while the first etching process does not contain the hydrogen.

18. A semiconductor device, comprising: Source / drain epitaxial structure, located on the substrate; Source / drain contacts are respectively located on the source / drain epitaxial structure; The gate structure is laterally located between the source / drain contacts; A gate spacer separates the gate structure from the source / drain contacts; A gate dielectric cap is located above the gate structure and its bottom surface is lower than the top surface of the source / drain contact, wherein the lower portion of the gate dielectric cap is lower than the top surface of the gate spacer. An oxide-based etch-resistant layer is located on the gate dielectric cap, wherein the oxide-based etch-resistant layer is separated from the interface between the gate dielectric cap and a gate spacer by a first distance, and the oxide-based etch-resistant layer is separated from the bottommost point of the gate dielectric cap by a second distance, the second distance being greater than the first distance. A nitride-based etch stop layer is located above the oxide-based etch resist layer; An interlayer dielectric (ILD) layer is located above the nitride-based etch stop layer; and A via structure extends through the ILD layer, the nitride-based etch stop layer, and the oxide-based etch resist layer to be electrically connected to one of the source / drain contacts, wherein the bottom of the via structure contacts a portion of the gate dielectric cap and a portion of one of the source / drain contacts.

19. The device according to claim 18, wherein, The oxide-based etch-resistant layer is thinner than the nitride-based etch-stop layer.

20. The device according to claim 18, wherein, The oxide-based etch-resistant layer is thinner than the gate dielectric cap.

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