Integrated quantum random number generator

Abstract

The present invention relates to an integrated quantum random number generator, iQRNG, in particular a photonic QRNG which is monolithically scalable in a common semiconductor substrate in the same material system and constructed in a completely integrated manner, consisting of a photon source and a detector, coupled directly to the source, for individual photons in a particularly compact and attack-resistant design on a technology platform, open for diverse applications, for semiconductor structuring. The subject matter of the present invention is an integrated quantum random number generator, iQRNG, (200), comprising a photon source (120) and an individual photon detector (130), wherein the photon source (120) and the individual photon detector (130) are arranged in the vertical direction one above the other in a common substrate (110) made of a semiconductor material. The present invention also relates to an integrated electronic circuit (500) which comprises at least one iQRNG (200) according to the invention.

Description

[0001] Integrated quantum random number generator

[0002] Subject of the invention

[0003] The present invention relates to an integrated quantum random number generator (iQRNG), in particular a monolithic, scalable and fully integrated photonic QRNG constructed in a common semiconductor substrate in the same material system, consisting of a photon source and a detector for individual photons directly coupled to the source in a particularly compact and attack-proof design on a technology platform for semiconductor structuring that is open for a wide range of applications.

[0004] Technological background

[0005] Random events and the determination of probabilities play a particularly prominent role in many areas of science and technology. For example, Monte Carlo simulations and secure encryption methods rely heavily on the generation of random numbers. A general distinction is made between so-called pseudo-random numbers and true random numbers. While the former are generated using deterministic formulas by pseudo-random number generators (PRNGs), and are therefore not absolutely random, non-deterministic random number generators (TRNGs) for generating true random numbers are generally based on real, unpredictable processes such as thermal or atmospheric noise, rather than on artificially generated patterns by deterministic algorithms.However, even the results of such non-deterministic random number generators based on external parameters can, depending on the underlying random element, still tend slightly towards higher or even numbers due to weak correlations, for example, and thus enable at least a partial predictability of the random numbers generated in this way.

[0006] Quantum random number generators (QRNGs), a special subgroup of TRNGs, are based on fundamental quantum processes for random number generation and are therefore, at least theoretically, not dependent on other external factors and effects that influence statistics. Quantum random number generators thus represent the currently best available source of true random numbers. Current digital QNRGs can deliver entropy rates (i.e., a sequence of bit values ​​with maximum randomness or entropy) of up to several hundred Mbps. The generated random numbers are required in both classical encryption methods and a variety of quantum computing and quantum cryptography methods to ensure secure key exchange (Secure / Quantum Key Distribution, SKD / QKD).Therefore, non-manipulable and fast QRNGs are essential for generating secure keys in cryptography.

[0007] Due to their particularly easy implementation, many QRNGs are realized as photonic QRNGs using the random properties of photons. A simple concept for generating random numbers is the behavior of a photon, which is either reflected or transmitted at a semitransparent beam splitter independently of other photons. Another approach is to utilize the random arrival times of photons at a single-photon detector. This distribution effect, based on intrinsic, fundamentally non-deterministically computable photon statistics of the photons of a corresponding photon source, can also be used to generate truly random numbers with high entropy. The arrival times of photons at a single-photon detector generally exhibit an exponential distribution.

[0008] Typically, a single-photon detector (SPD) initially generates a detector pulse from a single incident photon. This pulse is then converted into a timestamped digital representation of the detection event in a time-to-digital converter (TDC) and can be further processed accordingly. The photon or entropy source in QRNGs is usually laser diodes (LDs) or simple light-emitting diodes (LEDs) that are highly attenuated to the single-photon level. Their emitted photons can then be recorded as SPDs with temporal resolution by one or more particularly sensitive single-photon avalanche diodes (SPADs).Such photon sources, which simultaneously provide only a single photon or a few photons, are also referred to as single-photon sources (SPS) in this application. However, they do not necessarily have to be true single-photon emitters, for example, based on a single isolated two-level system. SPADs are a type of photodetector similar to photodiodes (PDs) and avalanche photodiodes (APDs), but with significantly increased sensitivity. SPADs can be read and evaluated digitally – even within a common integrated circuit.If such an integrated detector circuit is excited by single photons, only one electron-hole pair is generated per exciting photon in the sensor-active region (absorption region). The excited electrons are drawn to the cathode by electric fields, and the excited holes are drawn to the anode. In a SPAD, the charge carriers drift through a so-called avalanche region, within which a charge avalanche is generated by enhanced impact ionization. These are thus highly sensitive photon-receiving elements that, upon activation, store a high amount of charge (approximately 10 5 - 10 6 electrons) with high temporal resolution.

[0009] A SPAD is typically operated in Geiger mode above its breakdown voltage, whereby a single photon is detected via the generated charge avalanche and subsequently registered as a single event. To reduce the dead time during registration, active or passive suppression or quenching of further charge carrier amplification can occur immediately after the onset of the avalanche formation. In addition to the SPAD, the integrated circuit can also include a so-called single-photon counter (SPC). In this case, instead of directly outputting a single detector pulse, an immediate statistical evaluation of the temporal distribution of the individual detected single-photon events is generally performed.

[0010] In the context of this application, the term quantum random number generator (QRNG) is primarily to be understood as an abstract definition in the sense of an arrangement for providing numerically measurable quantized random events. A quantum random number generator always comprises a so-called entropy source, i.e., an element that actually provides these random events (e.g., a PLC alone or in combination with an SPD). However, the term quantum random number generator is not limited to the entropy source, but can also encompass, for example, the environment and structural arrangement of the entropy source in a device or substrate. In general, however, this term also includes corresponding control and evaluation circuits or entire circuit layouts or logic components for actually outputting random events as directly processable random numbers.The random numbers can result directly from the statistics of the entropy source or, for example, through a conversion as random values ​​derived from it by additional measures. To better distinguish the abstract definition from a real circuit, the latter will be referred to below as a quantum random number generator for the sake of simplicity. This is not intended to represent a restriction with regard to the two terms mentioned, but merely to emphasize different aspects. In this respect, the terms quantum random number generator and quantum random number generator can also represent one and the same device, in which case both devices include at least one entropy source. In a circuit block diagram (ieAt circuit level), a quantum random number generator according to the invention is therefore also referred to as an entropy source, while the circuit represented by the block diagram for outputting directly processable random numbers is referred to as a quantum random number generator for better differentiation.

[0011] In particular, the substrate of a quantum random number generator does not need to include any additional components to form a quantum random number generator. Instead, the substrate can, for example, be a single semiconductor crystal containing only one or more entropy sources. In this case, the additional components of a quantum random number generator can also be provided externally, for example, on another substrate.

[0012] Statistical analysis performed in parallel with random number generation can, for example, be used to further secure the random number generation process against potential attacks. Particularly in the case of non-integrated photonic QRNGs constructed from individual components, the required transmission paths within the system offer a wide range of attack possibilities. Therefore, to increase security, such systems are implemented as compactly and isolated from their external environment as possible. In addition to avoiding potential attack scenarios, a further advantage of such compact QRNGs is that natural influences from outside the system that may impair random number generation can also be largely minimized. Accordingly, compact QRNGs based on photon noise have typically been provided as hybrid integrated systems.

[0013] EP 3 529 694 B1 also discloses an integrated quantum random number generator (iQRNG) with a PLC and one or more SPDs, in which the PLC and the SPD(s) are fully integrated using CMOS technology in a single semiconductor substrate such that they are arranged directly next to one another (see FIG. 1 with the associated figure description). The PLC is provided by an appropriately doped pn junction so that it generates a photon current to be detected when the photon source is suitably biased in the forward or reverse direction. The SPDs are said to be, in particular, SPADs, which are preferably produced by common manufacturing processes with the PLCs and have the same chemical structure.

[0014] The joint integration ensures that the photon flux generated by the SPS can flow directly to an adjacent SPAD through optical crosstalk within one and the same semiconductor material. Unlike other hybrid-integrated QRNGs known from the state of the art, it does not first have to overcome or tunnel through a possibly empty coupling gap that physically separates the two components. The integrated "side-by-side" configuration makes the QRNG presented in the publication more compact and structurally less complex than hybrid QRNGs of the same functional type. Furthermore, thanks to the integration of all components, the random number generator is significantly more robust and immune to external environmental influences as well as attempts at manipulation by external attackers.

[0015] However, it is still possible, at significantly increased expense, to interfere with, influence, and / or monitor the random number generation process during the QRNG's operation. Since the iQRNG disclosed in the publication essentially has a planar structure, individual photons could certainly be tapped or additionally introduced from above or below the plane of the substrate.

[0016] The horizontal juxtaposition of the structures is also not ideal in terms of efficiency and required space consumption. Efficiency is particularly limited by the required lateral distance between the SPS and the SPAD and the associated high absorption of the photons in the semiconductor material. Furthermore, without special precautions, the photons emitted by the SPS are largely scattered into the material surrounding the SPS, meaning that only a portion of the generated photons can be detected by an associated SPAD. While multiple SPADs can be arranged around a single SPS, increasing efficiency and thus the digital entropy rate through joint evaluation of the connected SPADs, this significantly increases the space consumption of such an iQRNG.On the other hand, even with a single emitter-detector pair, it must be ensured that undetectable photons cannot propagate uncontrollably within the substrate and cause interference elsewhere in the substrate. The associated lateral blocking regions therefore also increase the effective area consumption of the iQRNG.

[0017] An iQRNG, also realized in CMOS technology (HV-CMOS), with a corresponding arrangement of a photon source and a single-photon detector next to each other is also known from Khanmohammadi et al. (Khanmohammadi, Abbas, et al. “A monolithic silicon quantum random number generator based on measurement of photon detection time.” IEEE Photonics Journal 7.5 (2015): 1-13). An n-well located in a circular near-surface region between a central n ++The Si-LED, which acts as a photon source and is made up of a p++ region as the cathode and several p++ regions arranged in a ring around it as the anode, is enclosed in a circular ring by a SPAD as a single-photon detector (see FIG. 2 with the associated figure description). The photons emitted by the SPS are thus detected on all sides in the plane, which increases efficiency while requiring less space compared to the iQRNG known from EP 3 52 694 B1. The SPS is thus integrated directly into the SPAD. However, individual photons can also be emitted into the substrate or extracted from its surface. Likewise, the injection of corresponding photons by an attacker to influence the statistics is also possible in this way.

[0018] Therefore, to further increase security and reduce space requirements, there is a need for further miniaturization of integrated QRNGs compared to the state of the art. The iQRNG should be largely protected against external attacks while exhibiting the highest possible efficiency and the lowest possible substrate losses. To avoid being limited by manufacturing technology constraints in the design of SoCs (System on Chip, SoC), the underlying manufacturing process should be as technology-open as possible and be based on the most widely applicable technology platform for semiconductor structuring.

[0019] DE 10 2022 125 568 A1 relates to a data processing device comprising an integrated circuit containing a data processor and a non-volatile memory that stores at least one security code. A first memory outside the integrated circuit stores data, wherein the data is cryptographically protected in a first format. A second memory outside the integrated circuit serves to store data. The device is configured to transmit data from the first memory via the integrated circuit to the second memory so that the data processor can access it from the second memory. The integrated circuit is arranged to validate the data read from the first memory during transmission using a security code stored in the non-volatile memory.Once the data is validated, cryptographic protection in a second format is applied to the validated data using a security code stored in the non-volatile memory. The protected data is stored in the second memory in the second format. The disclosure is directed to a computer comprising at least one quantum-process-based microintegrable true random number generator as a random number generator with a high random bit output rate, particularly for encryption. Corresponding devices can also be found in DE 10 2022 125 569 A1, DE 10 2022 125 570 A1, DE 10 2022 125 571 A1, DE 10 2022 125 572 A1, DE 10 2022 125 573 A1 and the unpublished application with the application number DE 10 2022 125 574.3.

[0020] Description of the invention

[0021] The object of the invention is achieved by the subject matter of the independent patent claims. Preferred developments are the subject matter of the dependent claims.

[0022] A first aspect of the present disclosure relates to an integrated quantum random number generator, iQRNG, comprising a photon source and a single-photon detector, wherein the photon source and the single-photon detector are arranged vertically one above the other in a common substrate made of a semiconductor material. "Vertical stacking" means that the photon source and the single-photon detector are arranged stacked at different depths relative to a surface of the substrate (a side-by-side arrangement would then occur, for example, in a horizontal direction). "Vertical stacking" preferably means that the propagation direction of the photons transmitted between the photon source and the single-photon detector has at least one component in said vertical direction.The photon source and the single-photon detector may therefore also have a mutual lateral offset or a tilt of the active regions with respect to the surface of the substrate, as long as photons emitted by the photon source can be detected by the single-photon detector with at least one propagation component in said vertical direction. It is particularly preferred if the propagation of the photons essentially (i.e., in a ray-optical approximation without diffraction effects) has only one component in said vertical direction (i.e., no horizontal component). An iQRNG according to the invention may also comprise multiple photon sources coupled to a single single-photon detector (e.g., to increase the photon rate or reliability) or multiple single-photon detectors coupled to a single photon source (e.g., for monitoring purposes).It is also possible to combine several photon sources and single-photon detectors into a single iQRNG.

[0023] In contrast to the prior art, there is no juxtaposition of the individual optoelectronic components. Rather, according to the invention, a compact arrangement of a photon source and a single-photon detector is arranged one above the other in a common substrate made of a semiconductor material. This therefore represents a particularly compact monolithic 3D integration with minimal space requirements for the iQRNG, wherein the structures can preferably be formed in one piece. In particular, an arrangement is preferred in which the single-photon detector is arranged lower than the photon source in the semiconductor material (i.e., photon source on top, single-photon detector on the bottom) for improved shielding against external influences. In an alternative embodiment, however, the single-photon detector can also be arranged higher than the photon source in the semiconductor material (i.e.,Photon source below, single-photon detector above). For example, in addition to an inversion of the basic structural design during processing from the surface of the substrate, an inverse arrangement of the elements can also be achieved by appropriate structuring from the back of the substrate. In particular, structuring can be performed on both sides, from both the front and back of the substrate.

[0024] The photon source is preferably a single-photon source (SPS), configured to simultaneously emit only a single photon or a few photons. Such photon sources that simultaneously emit only a single photon or a few photons are also referred to as single-photon sources in this application. However, they do not necessarily have to be true single-photon emitters, for example, based on a single isolated two-level system; rather, conventional light sources can also be configured as SPSs by attenuating the emission or the supplied current accordingly.

[0025] In the context of the present disclosure, a substrate is understood to mean the entire semiconductor chip as a body in which, for example, a specific element structure is structured into the semiconductor material using CMOS or other technologies, for example by forming differently doped wells or regions. However, the structure can also be formed additively by applying further layers and structures or by a sequence of etching and application steps for such further layers and structures. A corresponding substrate can therefore comprise, in addition to a so-called carrier or base substrate (e.g., an unstructured monocrystalline semiconductor substrate as the basis for the epitaxial growth of further semiconductor layers), a plurality of such epitaxially grown layers as well as other coatings.In this application, the substrate is therefore understood as a material carrier for the semiconductor structures of an iQRNG according to the invention and not as a simple carrier or base substrate for applying these structures. In this respect, the integral formation of an iQRNG according to the invention, one above the other in a common substrate made of a semiconductor material, represents a distinction, particularly compared to hybrid-integrated combinations (e.g., by flip-chip assembly) consisting of at least one photon source and at least one single-photon detector, for example, on a common submount as a carrier structure.

[0026] The photon source is preferably a light-emitting avalanche Zener diode (Zener-avLED) operated at an operating point below or close to the breakdown voltage. The Zener-avLED preferably has a breakdown voltage of <10 V, more preferably a breakdown voltage of <8 V, and even more preferably a breakdown voltage of <7 V. The advantages of using a Zener-avLED as a single-photon source are explained in more detail below. This new type of single-photon source allows for a high single-photon rate at a relatively low operating voltage, even below and in the range of the Zener breakdown voltage, and, with the desired design, exhibits a preferentially directed emission of the generated photons into the interior of the substrate and thus toward the single-photon detector. This makes Zener-avLEDs particularly suitable for use as a single-photon source in an iQRNG.The single-photon detector is preferably a single-photon avalanche diode (SPAD). These are detectors that, due to their particularly high sensitivity with high amplification and low (dark) noise, are in principle capable of detecting and proving single photons.

[0027] A main idea of ​​the present invention is therefore to provide a particularly compact and safe integrated QRNG by arranging a Zener avLED and a SPAD one above the other in a common semiconductor substrate.

[0028] One approach to improving the state-of-the-art iQRNG is to select a correspondingly broad technology platform. For SoC designs with the broadest possible range of potential applications, integrated circuits based on bipolar CMOS-DMOS (BCD) technology on silicon offer great potential. Highly efficient SPADs have already been successfully demonstrated and implemented using BCD technology. BCD technology allows for particularly effective and optimized integration of these SPADs with a wide range of other functional groups, such as digital and analog circuit components, particularly energy-efficient digital memory and switching elements, general power and driver electronics, and detector and sensor components.

[0029] The silicon-based PLCs known in the state of the art can, in principle, also be implemented in BCD technologies. However, due to the undirected emission of photons and their typically near-surface implementation, such Si LEDs are not optimal for the realization of particularly efficient and attack-protected iQRNGs. The near-surface implementation also usually results in degradation in the case of a Si LED used in avalanche operation. However, since silicon, as an indirect semiconductor, is poorly suited for photon generation, and these can generally only be generated through further processes via additional interaction with the crystal lattice, the selection of possible alternative silicon-based photon sources is severely limited.

[0030] In investigating Zener diodes provided in different layers by corresponding pn junctions in a BCD technology, which are optimized for a permanent operating point even in the breakdown region, with a near-surface Zener diode operating as an emitter and an underlying simple pn diode without bias (zero bias) operating as a detector, the inventors were able to demonstrate that, contrary to the general expectation of the skilled person, in this configuration, strong electroluminescence with an efficiency of at least 0.03% can be observed in the Zener diode in avalanche operation at the breakdown voltage. Such Zener diodes are not typically intended for operation as optoelectronic components (LEDs) in the prior art.

[0031] In particular, the generated photons are preferentially emitted toward the lower pn diode, which can thus detect almost all emitted photons, which can also be demonstrated via a photocurrent in the inventive structure (see FIGS. 4 to 7 with the associated figure description). It was thus shown that the investigated Zener diode exhibits a low but nevertheless significant efficiency in the range of the breakdown Zener voltage (approximately one detected photon per 3000 electrons of the Zener diode current) and therefore appears to be ideally suited as single-photon sources for the realization of QRNGs in silicon-based BCD technology. Above all, the preferential radiation toward the detector offers significant advantages over the isotropic radiation of conventional photon sources used in iQRNGs.The silicide commonly used in CMOS technology to reduce contact resistance between the metal contacts and the semiconductor silicide is both light-tight and mirror-smooth, allowing photons originally emitted upwards to be reflected back into the substrate by the silicide mirror. Zener diodes designed accordingly and operated as SPS in avalanche mode are therefore referred to below as light-emitting avalanche Zener diodes (Avalanche Light Emitting Zener diodes, Zener-avLEDs), in contrast to the Si-LEDs known from the prior art.

[0032] The Zener avLEDs provided in the BCD technology used emit photons with wavelengths from the visible spectral range and have a relatively low Zener operating voltage of usually less than 8 V. Since the radiation from a Zener avLED is also typically directed such that the photons are emitted preferentially in a vertical direction, i.e. away from the surface into the substrate, a much stronger isolation of the SPS and the generated photons from the environment of the semiconductor material can be achieved when used in an iQRNG, and tapping or injecting photons at the detector surface is made significantly more difficult. With a suitable design of the SPAD belonging to an iQRNG, the efficiency of random number generation can also be significantly increased and uncontrolled photon propagation in the semiconductor material can be largely prevented.

[0033] The second essential component for constructing a compact QRNG is therefore the selection of a suitably adapted SPAD design. Typically, these are also implemented near the surface in BCD technologies by appropriately forming p- or n-wells. Such near-surface SPADs are quite comparable to the prior art SPADs implemented in CMOS technology. In principle, the iQRNG known from EP 3 529 694 B1 with the Zener avLEDs described above could therefore also be implemented in BCD technologies. However, as already described above, the Zener avLEDs advantageously emit the photons preferably in the direction into the substrate. A juxtaposition of a Zener avLED as an SPS and a near-surface SPAD, as known from the prior art, could in principle be implemented, but not necessarily effectively.When using Zener avLEDs, it is advisable to place the corresponding SPAD below the Zener avLED.

[0034] In addition to the implementation of conventional n-SPADs and p-SPADs, BCD technology also enables the implementation of completely new SPAD concepts, including the use of deep n- or p-doped layers in a BCD substrate.

[0035] Using a method also recently developed by the inventors for generating deep pn junctions in a BCD process to provide a corresponding BCD substrate with deep pn junctions, a particularly efficient deep-lying single-photon avalanche diode ("deepSPAD") was realized. This deepSPAD can be easily arranged directly below a Zener avLED configured to generate single photons. The combination of a Zener avLED with a deep-lying SPAD thus provides the essential components of a QRNG fully vertically integrated using BCD technology, in contrast to a horizontal integration of a QNRG based on CMOS technology according to the state of the art.

[0036] By vertically arranging a Zener avLED as the emitter and a deepSPAD implemented using extremely deep pn junctions as the receiver, a miniaturized quantum random number generator based on a monolithic silicon die with highly efficient optical coupling, high attack resistance, and low operating voltage can be realized using BCD technologies. The BCD-based iQRNG design presented here thus represents an optimal solution to the inventive problem. In particular, the vertical 3D integration further increases the compactness of an iQRNG and reduces the area consumption compared to conventional lateral 2D designs while simultaneously increasing efficiency.

[0037] Preferably, an iQRNG according to the invention is therefore formed in a BCD substrate using BCD technology.

[0038] Preferably, the BCD substrate comprises a carrier substrate; and an epitaxial layer grown on the carrier substrate, wherein a deep pn junction located in the epitaxial layer is created between the carrier substrate and the epitaxial layer by diffusion of dopants introduced into a surface of the carrier substrate below the epitaxial layer.

[0039] The carrier substrate can preferably be a p-type substrate. However, n-type substrates or intrinsic substrates can also be used. The substrate material can in particular be silicon. However, the processes are in principle also adaptable for other semiconductor materials. A typical dopant for forming a p-type region is boron. Phosphorus (P), arsenic (As), or antimony (Sb) can be used to form an n-type region. In silicon, for example, boron as a dopant diffuses significantly further than the heavy donors (P, As, or Sb). It can also be seen that the n-type regions created are largely dominant due to the higher doses used, i.e. an n-type region already doped with phosphorus can retain its existing conductivity type even after additional boron has been added.To provide the deep pn junctions, additional mask, lithography and epitaxy steps in the usual BCD process can sometimes be omitted.

[0040] Preferably, the first and second dopant have different diffusion properties in the carrier substrate and / or in the epitaxial layer. Preferably, the second dopant has greater mobility in the carrier substrate and / or in the epitaxial layer than the first dopant. Preferably, the introduction of the first dopant and / or the second dopant takes place maskless or via a mask process. For maskless introduction, a direct ion beam writing process, for example, can be used. In a mask process, the introduction takes place with the aid of a previously provided mask, wherein the introduction takes place, for example, via a chemical or physical deposition process or likewise by means of an ion beam writing process.Preferably, immediately after the introduction of the second dopant, the first region or the second region completely overlies the other region in a plan view of the surface of the carrier substrate. Preferably, the first region is a deep n-type layer (NBL layer) and the second region is a deep p-type layer (PBL layer).

[0041] Preferably, the single-photon detector forms an avalanche region in a region around the deep pn junction and comprises an absorption region for converting photons into electron-hole pairs, wherein the absorption region is directly adjacent to the deep pn junction.

[0042] It is preferred that the deep pn junction is formed at least partially between a deep n-layer as the cathode and a deep p-layer directly adjacent to the deep n-layer. It is also preferred that the absorption region directly adjoins the deep p-layer and is essentially formed as a p-region. Essentially means that the absorption region can also be partially formed as an intrinsic region. It is further preferred that a + -area formed anode is directly adjacent to the absorption area.

[0043] Preferably, a second deep pn junction formed below the deep pn junction of the single-photon detector located in the epitaxial layer (e.g., in the carrier substrate) is used as an additional photodetector for monitoring for external attacks. The aforementioned method for generating deep pn junctions in a BCD process results in a second pn junction located below the first pn junction in some embodiments (see FIG. 3 with the associated figure description). Due to its largely identical electronic properties, this second pn junction can also be configured as a photodetector or single-photon avalanche diode. Since this additional photodetector is thus arranged below the actual QRNG arrangement, buried deep in the semiconductor material, it can provide a protective function against photons injected from the back of the substrate.These can be detected in close proximity to the QRNG over a wide angular range. This allows external attacks to be detected with a high degree of probability.

[0044] Furthermore, the additional photodetector can be configured to enable monitoring of the photon count rate via additional evaluation electronics. Under otherwise constant operating conditions, the photon source and the associated single-photon detector should exhibit a roughly constant photon count rate, apart from random statistical fluctuations in the detected photon events. However, since not all photons emitted by the photon source may be detected by the associated single-photon detector, and external natural influences (e.g., cosmic rays) and artificial radiation (e.g., radio sources) can also cause isolated detection events at the additional photodetector, the second photodetector will, with a certain probability, also exhibit a roughly constant background count rate.Deviations from this long-term statistical average can therefore indicate a possible error within the iQRNG or external interference, such as from an attacker. A detected change in the background count rate at the second photodetector can indicate both active interventions by an attacker (e.g., irradiation of additional photons to change or influence the photon statistics) and passive attacks, such as the targeted thinning of a shield to increase the transmission of individual photons to the outside (which may, however, also cause additional irradiation of ambient light from this direction).

[0045] Since background count rates are also statistical variables, an analysis based on machine learning methods is recommended for evaluating possible deviations from expected normal values. Artificial intelligence methods can be used for the evaluation. In particular, the use of at least one appropriately trained artificial neural network (ANN) is preferred for detecting an attack and / or identifying possible error sources and events. A variety of different types of ANNs can be found in the literature; the expert can select suitable methods based on the specific requirements.

[0046] In some embodiments, the at least one ANN may comprise a stochastic neural network (SNN), which can provide variable outputs for the same photon count rates. This allows for the investigation of network errors based on the available data or insufficient training of the network. For example, it can also identify deviations that are not represented by the deviation space of a training data set (out-of-distribution).

[0047] Another possible application of the deep second pn junction as an additional photodetector can be the provision of independent random numbers based on another independent photon source located below the deep second pn junction or on or near the back of the substrate. For this purpose, the deep second pn junction is preferably also configured as a single-photon detector or SPAD, analogous to the deep first pn junction located above it.Since the absorption of photons in the region of the first single-photon detector can also be subject to a probability distribution and, depending on the specific realization of the arrangement of the individual elements, individual photons from the actual photon source of the iQRNG according to the invention can also reach the region of the deep-lying second pn junction, it is also possible that these can also be used as a basis for providing quantum random numbers, for example as an additional independent iQRNG.

[0048] Regardless of the use of a deep second pn junction as an additional photodetector, an iQRNG according to the invention (or a corresponding quantum random generator) can also comprise a further photodetector that is independent of the described deep pn junctions. Preferably, the further photodetector is also integrated into the iQRNG according to the invention, but it can also be connected to the iQRNG according to the invention in a hybrid manner. Particularly preferably, the further photodetector is also a single-photon detector, e.g., a SPAD. Analogous to the use of the deep second pn junction described above, the additional photodetector can also be used to monitor the functionality and safety of an iQRNG according to the invention.

[0049] Preferably, the deep-lying first pn junction and the deep-lying second pn junction are connected to one another via a common internal terminal, for example a common anode or cathode. Typically, pn junctions configured for operation as single-photon detectors are connected directly via the substrate on one side of the pn junction. However, due to the shielding or isolation of the structures and circuits from the substrate, which is common practice, particularly in BCD technologies, corresponding terminals for contacting are often placed on the substrate surface. However, with a design of a pn junction double structure according to the invention, a common terminal region (anode or cathode) is immediately created, which enables joint control via a single contact, e.g. on the substrate surface.Preferably, the top and / or bottom surface of the substrate in the region of the iQRNG is mirrored on one surface or comprises a light-blocking layer. Mirroring the surfaces of a substrate (e.g., by means of metallization or the application of dichroic layers) as well as the application of a light-blocking layer are known in the prior art and have already been discussed above. These approaches can also be used in an iQRNG according to the invention to shield against external photons ("shadowing") and to increase efficiency by reflecting back the photons generated by the associated photon source. Alternatively or additionally, appropriate encapsulation can also be provided in the region of the iQRNG or this region can be surrounded by a metal box.

[0050] Preferably, the surface of the substrate is covered with a silicide layer in the area of ​​the iQRNG and with a metallization layer above it. Preferably, the metallization is closed in the area of ​​the iQRNG. The metallization can act as a mirror coating for the interior and / or as a wavelength-independent shading for external photons. The same applies to a formed silicide layer.

[0051] Preferably, photons provided by the photon or single-photon source are prevented from escaping at the surface of the substrate and / or the back of the substrate by a combination of at least one element each consisting of metal covers, sidewall contacts, and vias. These elements can achieve a largely complete shielding or encapsulation of the iQRNG, which not only provides external shielding but also ensures high immunity to external interference.

[0052] With regard to possible attack scenarios, however, other external access routes are conceivable in addition to purely optical interference or the reading of emitted photons. A further aspect of the present invention therefore consists in further hardening an iQRNG according to the invention, which already offers significantly increased security compared to the prior art due to its specific arrangement of the included photon source and the associated single-photon detector, against unauthorized access and external interference, for example, by observers or attackers. Possible optical shielding has already been discussed above; further attacks could be based, for example, on the targeted evaluation or influencing of chemical or electronic properties of the iQRNG according to the invention.

[0053] As mentioned at the beginning, quantum random number generators utilize the principles of quantum mechanics to generate truly random numbers that can be used in cryptography and other security-critical applications. These random numbers are crucial because they form the basis for secure encryption keys and other cryptographic processes. Despite their theoretical security, however, QRNGs can be vulnerable to various types of side-channel attacks that can compromise the integrity and confidentiality of the generated random numbers.

[0054] One possible attack vector is electromagnetic radiation. QRNGs can emit electromagnetic signals that can be intercepted and analyzed by an attacker. These signals could reveal information about the internal states of the QRNG, which could allow an attacker to reconstruct or predict the generated random numbers. To prevent such attacks, QRNGs should be well-shielded and protected against electromagnetic radiation.

[0055] Another attack vector is power consumption. The power consumption of a QRNG can vary depending on the random numbers generated. An attacker could measure these fluctuations and use them to draw conclusions about the generated random numbers. This could be achieved by using highly sensitive power meters capable of detecting even the smallest changes in power consumption. To prevent such attacks, QRNGs should be designed so that their power consumption remains constant regardless of the random numbers generated.

[0056] Temperature dependence can also play a role. The performance of QRNGs can be temperature-dependent, meaning that changes in the ambient temperature could affect random number generation. An attacker could manipulate the device's temperature to influence or predict the random numbers. To prevent such attacks, QRNGs can be operated in temperature-controlled environments and have mechanisms that keep their performance stable regardless of temperature fluctuations.

[0057] With optical QRNGs such as the iQRNG according to the invention, an attacker could also attempt to influence the light source or monitor the detectors to manipulate the generated random numbers. This could be done by introducing additional light or by blocking light. To prevent such attacks, optical QRNGs should be well shielded and protected against external influences.

[0058] There are also so-called timing attacks. By measuring the time a QRNG takes to generate random numbers, an attacker could identify patterns and predict the random numbers. This could be achieved by using high-precision timing devices capable of detecting even the smallest differences in generation time. To prevent such attacks, QRNGs should be designed so that their generation time remains constant regardless of the random numbers generated.

[0059] Chemical attacks on semiconductor-integrated QRNGs are a less researched but potentially serious risk. These attacks could, for example, aim to alter the physical properties of the semiconductor components in order to influence or disrupt random number generation.

[0060] One possible approach for chemical attacks is to alter the semiconductor materials through chemical reactions. This could be achieved through exposure to corrosive substances that compromise the integrity of the semiconductor structures. Such attacks could impair the performance of QRNGs by reducing the efficiency of the light sources or detectors or by altering the electrical properties of the circuits.

[0061] Another potential chemical attack could involve the targeted doping of semiconductor materials. By introducing foreign atoms into the semiconductor layer, an attacker could alter the electronic properties of the material and thus influence random number generation. This could lead to predictability of the generated random numbers, which would significantly compromise the security of the QRNGs.

[0062] Although chemical attacks on QRNGs are currently theoretical and not yet widespread in practice, these potential threats should be considered and measures should be taken to ensure the chemical stability and integrity of QRNGs. This can be achieved, for example, through the use of protective coatings, the selection of chemically resistant materials, and the implementation of monitoring mechanisms to detect chemical changes.

[0063] These potential attack scenarios demonstrate that even state-of-the-art QRNGs are not fully protected against side-channel attacks. It is therefore important to implement additional security measures to ensure the integrity and confidentiality of the generated random numbers. These include, among other things, physically shielding the devices, implementing mechanisms to stabilize power consumption and generation time, and operating in controlled environments.

[0064] In an iQRNG according to the invention, the aforementioned shielding can be achieved directly via the implemented structural system itself or the buried arrangement of the entropy source inside a substrate. Shielding against both electromagnetic and optical radiation can be achieved, for example, by a common and continuous metallization of the surface of the substrate above the entire build volume of the iQRNG (or the associated entropy source). Metallization can also be applied at the corresponding location on the underside of the substrate to shield the lower build volume. In addition to their shielding function, these individual metallizations can also simultaneously enable electrical contacting of individual areas of the iQRNG. Preferably, several metallization levels can be arranged one above the other to increase the layer thickness (e.g., 12-15 layers).

[0065] Metallic multilayers generally provide better shielding than a single metal layer. This is because multiple layers of different or identical metals can be combined to maximize the shielding effect. One reason for this is that each metal layer can reflect and absorb electromagnetic waves. Combining multiple layers increases the likelihood that the waves will be reflected and absorbed multiple times, improving overall shielding. Different metals have different shielding properties. More effective shielding can be achieved by combining metals with complementary properties. For example, a layer of a highly conductive metal such as copper could be combined with a layer of a ferromagnetic material such as nickel.Multiple layers can also help dampen the penetration effects that might occur with a single layer. This is especially important for high-frequency electromagnetic waves, which tend to penetrate thin metal layers. Multilayer shields also provide an additional layer of safety. If one layer becomes damaged or corroded, the other layers can continue to provide effective shielding. Instead of one or more metal layers, a layer of polysilicon can be applied to the surface of the substrate in the iQRNG area to shield against electromagnetic radiation (including photons). Polysilicon is widely used in the semiconductor industry, particularly in the manufacture of transistors and solar cells.Although it does not have the same shielding properties as metals and is also generally more optically transparent to photons at the same thickness, it is a more cost-effective process that is much easier to implement.

[0066] Furthermore, a circuit or IC comprising the iQRNG according to the invention (or a region or part thereof) can be covered, in addition to the above-mentioned layers for shielding or as a single element, preferably with a layer of silicon nitride (SiN). Such a layer can keep a certain previously set hydrogen content (H2) in an IC as constant as possible, since SiN layers have only low permeability for this. A constant hydrogen content is important in the manufacture and operation of ICs for several reasons. First, hydrogen helps to avoid defects in semiconductor materials such as silicon. These defects can impair the electrical properties of the semiconductor components and lead to malfunctions. A constant hydrogen content minimizes such defects and ensures the reliability of the ICs.In addition, hydrogen is often used to passivate the surfaces of semiconductor materials. This means that hydrogen binds to the surface atoms, thus reducing the number of free electrons that could cause unwanted chemical reactions. A constant hydrogen concentration ensures that passivation remains effective. Hydrogen can also help reduce the oxidation of metal compounds in ICs. Oxidation can reduce the conductivity of metal compounds and thus impair IC performance. A constant hydrogen content helps control oxidation and maintain the conductivity of the metal compounds. Finally, fluctuations in the hydrogen content contribute to changes in the electrical properties of semiconductor materials. This can impair the performance and reliability of the ICs and also open up a vector for chemical attack.A constant hydrogen content helps to keep the electrical properties stable and ensure consistent performance.

[0067] The lateral region around the iQRNG or the enclosed entropy source can be created by appropriate deep doping of the substrate or by designing it as a conductive region. Such an arrangement can be used, analogous to metallization of the substrate surfaces, simultaneously for deep contacting of regions located within the substrate, such as for contacting buried layers. However, to avoid additional electromagnetic radiation from these structures, they are preferably not used to transmit modulated signals. In the exemplary embodiments of iQRNGs according to the invention shown in the figures, this shielding region can be seen as isolated outer deep structures extending vertically from the surface into the substrate.In a preferred embodiment of an iQRNG according to the invention, the "detector surface" of the single-photon detector is designed as a circular structure, so that the lateral shielding then preferably forms a closed circular-ring-shaped cylindrical structure (however, the shielding can have any shape, preferably one with a closed side). Such an arrangement of lateral shielding against electromagnetic radiation is also referred to as a so-called seal ring (iQRNG seal ring).

[0068] The insulating well regions typically formed in BCD technologies, especially around the photon source and the single-photon detector, can also be used for shielding. These are usually used to electrically isolate different regions within a substrate, allowing, for example, different reference potentials (GND) to be provided in these regions. However, such local isolation also acts as a current-blocking barrier for signal transmission and, with appropriate design of the individual well regions, can also effectively suppress electromagnetic coupling between the isolated regions.

[0069] As a further shielding element, a conventional encapsulation of an iQRNG according to the invention (or of an IC comprising one or more iQRNGs according to the invention) can be carried out using a conventional potting material such as plastic. The plastic can, in particular, be a thermoset. Silicon oxide (e.g., SiO2) can be added to the thermoset to adjust the thermal expansion coefficient of the interconnected materials.

[0070] Preferably, several iQRNGs according to the invention or a multi-channel QRNG system comprising a plurality of iQRNGs according to the invention are implemented on the same substrate. Together with compact shielding of the individual iQRNGs, very high integration densities can be achieved with a large number of densely packed, decoupled iQRNGs and thus overall high effective random number rates. In prior art iQRNGs, the integration density is primarily limited by the structural juxtaposition of the individual components.

[0071] Preferably, a QRNG according to the invention comprises an electronic circuit for generating and outputting a digital random number sequence based on the statistical evaluation of the temporal sequence of signals from the single-photon detector.

[0072] A further aspect of the present invention relates to an integrated electronic circuit (IC) comprising at least one iQRNG according to the invention. In particular, these ICs can be used for applications based on security-relevant chip-based systems (SoCs).

[0073] Preferably, an iQRNG according to the invention is placed in a pad frame (also referred to as a pad edge) of the integrated electronic circuit. In non-pad-determined integrated electronic circuits, the pad frame typically contains a large number of free areas, which, however, typically cannot be used for digital circuits or larger analog circuit blocks. However, since an iQRNG according to the invention is correspondingly small in size due to its extremely compact design and the subsequent circuitry usually only comprises a small number of gates, this type of QRNG can nevertheless be integrated into a conventional pad frame. Due to the extremely compact design of the iQRNG according to the invention, it can also be implemented in existing designs for integrated electronic circuits in a space-saving manner and without major effort.This results in a significant reduction in space requirements compared to conventional approaches for integrating QRNGs. The advantages of an iQRNG according to the invention can be fully exploited.

[0074] The advantages of an iQRNG according to the invention compared to the known implementations in the prior art are based primarily on the further miniaturization of the entire random number generator structure and the resulting high degree of integration or miniaturization of the generated structures. Due to the complete isolation of the PLC and the associated SPAD from the environment, the security of the random number generation can be significantly increased. The directed vertical radiation from the Zener avLED used as the PLC also contributes to increasing the security as well as to a significant increase in the efficiency of the random number generation. The cointegration of a suitable photon source and a single-photon detector on the same vertical layout cross-section of a common substrate, especially when using a commonly used cost-effective planar technology (i.e.This type of integration (i.e., processing only from one substrate side and without using other complex approaches, such as hybrid integration, e.g. via a chiplet approach) has not been possible in the state of the art so far.

[0075] A second deep pn junction, formed below the pn junction of the SPAD using a novel BCD technology, can be used as an additional photodetector to monitor for attacks, particularly from the back of the substrate. The efficiency of optical coupling into the associated SPADs, as well as isolation and security, can be further increased through the use of internal metal and silicide mirrors. Compared to the state of the art, the Zener avLED used as a photon source requires only a relatively low operating voltage of < 8 V. Furthermore, since the absorption length of the emitted visible light in silicon is short (i.e., the associated absorption coefficient is high), very good optical isolation between adjacent elements can be achieved.This enables arrangement in an array with high cell density and a resulting correspondingly high generation or entropy rate.

[0076] Further aspects of the present invention are disclosed in the dependent claims or in the following description of the drawings.

[0077] Short description of the characters

[0078] The invention is explained below in exemplary embodiments with reference to the accompanying drawings. They show:

[0079] Figure 1 is a schematic representation of a first embodiment of an iQRNG according to the prior art in plan view;

[0080] Figure 2 is a schematic representation of a second embodiment of an iQRNG according to the prior art in a side view;

[0081] Figure 3 shows a schematic representation of a BCD substrate produced using a method for providing deep pn junctions in a BCD process and a TCAD representation of the resulting dopant distribution; Figure 4 shows a schematic representation of an exemplary first embodiment of an iQRNG according to the invention;

[0082] Figure 5 is a schematic representation of an exemplary second embodiment of an iQRNG according to the invention;

[0083] Figure 6 is a schematic representation of an exemplary third embodiment of an iQRNG according to the invention;

[0084] Figure 7 graphical representation of the dependence of a) SPAD current and b) the ratio between SPAD current and Zener current as a function of the Zener blocking voltage at different SPAD blocking voltages (less than, equal to, greater than the breakdown voltage) within an iQRNG according to the invention;

[0085] Figure 8 is a schematic representation of an exemplary electronic circuit of a quantum random number generator for generating and outputting a digital random number sequence;

[0086] Figure 9 is a schematic representation of an exemplary layout of an integrated electronic circuit with an iQRNG according to the invention in the pad frame in plan view;

[0087] Figure 10 shows an exemplary schematic block diagram for a quantum random generator with integrated power supply, data bus driver and control logic;

[0088] Figure 11 is an exemplary schematic block diagram of a data processing device in combination with a controlled system;

[0089] Figure 12 is an exemplary schematic block diagram of a circuit for deactivating a test interface of the device according to Figure 11;

[0090] Figure 13 shows an exemplary flow chart illustrating the verification of digital signatures;

[0091] Figure 14 is an exemplary flowchart illustrating the use of HASH functions in storing and retrieving data from a DRAM of the device of Figure 11;

[0092] Figure 15 is a flowchart of an exemplary method for entropy extraction; Figure 16 is an exemplary oscillogram of the voltage signal of the entropy source from Figure 9;

[0093] Figure 17 shows an exemplary schematic sequence of a server-client communication using a quantum random generator;

[0094] Figure 18 shows an exemplary schematic flow of the functions KeyExchangeServer() and KeyExchangeClient();

[0095] Figure 19 shows an exemplary schematic flow of the setPrimes() function;

[0096] Figure 20 shows an exemplary schematic flow of the setE() function;

[0097] Figure 21 shows an exemplary schematic flow of the findD() function;

[0098] Figure 22 shows an exemplary schematic sequence of a secure transmission of quantum-based random numbers;

[0099] Figure 23 schematically shows an exemplary method for generating a quantum random number;

[0100] Figure 24 shows an embodiment of a time-to-pseudo-random number converter; and

[0101] Figure 25 is an exemplary diagram illustrating the detection of pulses on the voltage signal of the entropy source shown in Figure 9.

[0102] Detailed description of the characters

[0103] Detailed embodiments will now be described, which are illustrated by way of example in the accompanying drawings. The effects and features of these embodiments will be described with reference to the accompanying drawings. Throughout the drawings, like reference numerals designate like elements, and redundant descriptions are omitted. The present disclosure may be embodied in various forms and should not be construed as limited only to the embodiments shown herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects and features of the present disclosure to those skilled in the art.

[0104] Therefore, methods, elements, and techniques that are not necessary for a person skilled in the art to fully understand the aspects and features of the present disclosure may not be described. In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity.

[0105] As used herein, the term "and / or" includes all combinations of one or more of the listed elements. Furthermore, the use of "may" in describing embodiments of the present disclosure refers to "one or more embodiments of the present disclosure." In the following description of embodiments, the singular terms may also include the plural, unless the context clearly indicates otherwise.

[0106] Although the terms "first" and "second" are used to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the present disclosure. Terms such as "at least one of," when preceded by a list of elements, modify the entire list, not just the individual elements of the list.

[0107] Terms such as "substantially," "approximately," and similar terms are used as approximations rather than degrees, and are intended to account for inherent variations in measured or calculated values ​​that will be recognized by those skilled in the art. When the term "substantially" is used in connection with a characteristic that can be expressed by a numerical value, the term "substantially" means a range of at least + / - 5% of the value centered on the value.

[0108] Figure 1 shows a schematic representation of a first embodiment of an iQRNG according to the prior art in plan view. The representation is based on a corresponding figure in EP 3 529 694 B1 and shows the surface O of an associated substrate 110 into which the QRNG is integrated. A circular photon source 120 with a pn junction configured to provide photons is supplied with current via a corresponding contact and is thereby excited to emit individual photons 128. To detect the emitted photons 128, an associated single-photon detector 130 in the form of a SPAD is arranged next to the photon source 120. However, as with conventional hybrid approaches for photonic QNRGs, the photon source 120 and the single-photon detector 130 continue to be structurally and functionally separate elements that are simply arranged next to one another for integration in a common substrate.

[0109] A current pulse generated by the single-photon detector 130 upon absorption of a photon 128 can then first be registered and evaluated in an associated electronic sampling means 152, in particular to generate a bit sequence based on the number of photons detected in the single-photon detector 130. Furthermore, an electronic post-processing means 154 is provided, which is to be configured to process the binary sequences of the electronic sampling means 152 in such a way that a so-called "whitening" operation is performed. This whitening operation is to comprise a plurality of compression operations intended to improve the statistical properties of the generated binary sequences. The post-processing step is intended to increase the entropy level of the QRNG.However, it must be ensured that the compression operations used do not lead to a fundamental predictability of the generated random numbers by introducing deterministic dependencies in the application.

[0110] To increase the efficiency of random number generation, i.e., the effective entropy rate, the photonic part of the QRNG on the surface O of the substrate 110 is protected by a light-blocking layer 150 ("light inhibitor filter"), which serves to shade it from external light. The light-blocking layer 150 can be provided, in particular, by a metallization layer that can be applied directly during the production process, for example, using CMOS technology, as the last metallization level. This is intended to shield the photon detector 130 from external light and make it sensitive only to those photons that pass through the substrate 110 due to crosstalk from the photon source 120.In addition, the metallization layer is also intended to improve the optical coupling of the photons 128 emitted by the photon source 120 by reflecting them inwards and thus preventing them from exiting the surface O of the substrate 110.

[0111] A disadvantage of such a side-by-side arrangement of the optical components is the distance between the components, which reduces the coupling strength due to the low illumination angle and the potential photon absorption in the various materials. Furthermore, despite the partially applied light-blocking layer 150, there is still the potential for optical access and thus an attack from the surface O of the substrate 110 or even from the back of the substrate. This can be used, for example, to specifically inject or extract additional photons, ultimately influencing and compromising the counting statistics and thus the entropy of the generated random numbers.Furthermore, the illustration also shows that the individual photons 128 are emitted isotropically distributed in all spatial directions, so that only a fraction of the photons 128 can be detected by the photon detector 130 and thus statistically evaluated. This significantly reduces the efficiency of random number generation and, on the other hand, results in a large number of photons 128 being emitted unused into the substrate 110, where they may also be extracted elsewhere by observers or attackers or cause interference.

[0112] Figure 2 shows a schematic representation of a second embodiment of an iQRNG according to the prior art in a side view. The representation is based on a corresponding figure from Khanmohammadi et al. (A. Khanmohammadi, R. Enne, M. Hofbauer and H. Zimmermann, “A Monolithic Silicon Quantum Random Number Generator Based on Measurement of Photon Detection Time,” in IEEE Photonics Journal, vol. 7, no. 5, pp. 1-13, Oct. 2015, Art no. 7500113). In this example, too, the basic structure of a side-by-side arrangement of a photon source 120 (Si LED), which is configured to emit individual photons 128, and a single-photon detector 130 (SPAD) is clearly visible. In contrast to the embodiment shown in FIG. 1, the photon source 120 is provided as a circular central element, which is essentially completely surrounded by a correspondingly adapted circular ring-shaped single-photon detector 130.The common radial symmetry axis R lies at the center of the iQRNG thus formed. The photon source 120 is realized by an n-well formed in a deep n-well (“deep n-well”), which is connected to the surface O of the substrate 110 (“p-substrate”) via an n-well introduced centrally around the radial symmetry axis R. ++ -area as cathode 122 and a p ++ -region is supplied with current as anode 124. Outside the deep n-well, the single photon detector 130 is also connected to the surface O via an introduced n ++ -region as cathode 132 and a p arranged further away from the radial symmetry axis R ++-region is contacted as anode 134. A p-well ("p well") is located below the cathode 132. Below the anode 134, however, a p-well ("p well") is formed in a deep p-well ("deep p well"). The photon source 120 is provided as an element within the structure of the photon detector 130, so that, in contrast to FIG. 1, they form a structural and functional unit.

[0113] In this example of an iQRNG according to the prior art, the photons 128 are emitted into the substrate 110 essentially from all sides, so that the disadvantages already described for the embodiment according to FIG. 1 with regard to security against observers or attackers and reduced efficiency also apply. However, due to the specific design as a circular ring-shaped arrangement and the structural connection of the single-photon detector 130 to the photon source 120, the integration density can be further increased compared to FIG. 1. In addition to a smaller area requirement for forming the iQRNG, this also includes increased security against attacks and increased efficiency in random number generation or the entropy rate as advantages.This is particularly due to the fact that reducing all distances reduces the loss of photons 128 due to material absorption and unfavorable emission directions. Furthermore, this reduces the area available for potential attacks. Apart from this, however, it is still possible, in principle, for attackers to extract or inject individual photons 128, particularly at the surface O as well as at other locations on the substrate 110, in order to influence the counting statistics. Such a juxtaposition of the two optical components of a QRNG therefore has several disadvantages that have so far prevented particularly secure, compact, and reliable random number generation for SoC applications.

[0114] Figure 3 shows a schematic representation of a BCD substrate 110 provided with a method for providing deep pn junctions 50 and 52 in a BCD process and a TCAD representation of the resulting dopant distribution. An embodiment of a method for producing deep pn junctions 50 and 52 in a BCD process comprises providing a carrier substrate 10; introducing a first dopant to form a first region 22 (e.g., NBL) of the first conductivity type (negative for NBL) into a surface S of the carrier substrate 10; introducing a second dopant to form a second region 32 (e.g.,PBL) of the second conductivity type (positive for PBL) into the surface S of the carrier substrate 10, wherein the first region 22 (NBL) and the second region 32 (PBL) at least partially overlap; growing an epitaxial layer 40 on the surface S of the carrier substrate 10, wherein the first region 22 (NBL) and the second region 32 (PBL) spread by diffusion of the first dopant and the second dopant in the epitaxial layer 40 and thereby form a pn junction 50 lying in the epitaxial layer.

[0115] In the illustration, the first region 22 is a deep NBL layer and the second region 32 is a deep PBL layer. However, the sequence can be interchanged, so that the first region 22 can also be a deep PBL layer and the second region 32 can be a deep NBL layer. By appropriately adjusting the diffusion lengths of the individual dopants, the layer sequence of the pn junctions 50 and 52 can also be reversed. For example, in FIG. 3, the NBL and PBL layers at the pn junction 50 and 52 could also be interchanged.

[0116] The described method differs from conventional methods for providing BCD substrates 110 according to the prior art, in particular in that the first region 22 (NBL) and the second region 32 (PBL) at least partially overlap. In particular, immediately after the introduction of the second dopant, in a plan view of the surface S of the carrier substrate 10, the first region 22 or the second region 32 can completely overlap the other region (32, 22). Therefore, in the embodiment shown, immediately after the introduction of the second dopant to form the second region 32 (PBL), the second region 32 (PBL) lies completely in the first region 22 (NBL) in a plan view of the surface S of the carrier substrate 10.In order to form a pn junction 50 located in the epitaxial layer, the first and second dopant preferably have different diffusion properties in the carrier substrate 10 and / or in the epitaxial layer 40. In particular, the second dopant in the second region 32 (PBL), as shown, can have a higher diffusion mobility (and thus diffusion length) in the carrier substrate 10 and in the epitaxial layer 40 than the first dopant in the first region 22 (NBL).

[0117] To enhance diffusion, the carrier substrate 10 can be heated after the introduction of the first dopant and / or the second dopant. Furthermore, after the growth of the epitaxial layer 40, the carrier substrate 10 can be heated to enhance dopant diffusion. In the method presented, the first dopant and / or the second dopant can be introduced either maskless or using a mask process. In the BCD wafer shown, a complete overlay of the first region 22 (NBL) with a single second region 32 (PBL) can be assumed. Conventionally, however, the first and second regions 22 and 32 are formed spatially separate from one another. In particular, their distance is generally chosen to be at least large enough that even after the individual dopants have diffused out, no overlapping regions are created.

[0118] The TCAD (Technology Computer-Aided Design, TCAD) representation shown below the schematic diagram shows the dopant distribution within the contacted BCD substrate 110 for simulating a corresponding integrated diode structure. Due to the double structure shown in this embodiment, with an upper pn junction 50 in the epitaxial layer 40 and a lower pn junction 52 in the carrier substrate 10, the side view shown shows an effective constriction of the n-type region NBL enclosed in the area of ​​the pn junctions 50 and 52 by the two p-type regions PBL surrounding this n-type region NBL. Both pn junctions 50 and 52 can be configured to provide mutually independent SPADs with a doping density and field strength distribution suitable for generating an avalanche effect.

[0119] Using appropriate BCD substrates 110 for further use in BCD technologies, particularly deep-lying SPADs ("deepSPADs") can thus be produced. In particular, sufficient installation space remains above the provided SPADs for the integration of further optoelectronic components. According to the invention, a Zener avLED formed above the deep-lying SPAD can therefore be used, in particular, to realize a particularly compact, vertically constructed iQRNG, in which individual photons 128 are emitted by the Zener avLED preferably in the direction of the upper pn junction 50 and are thus provided for detection by a SPAD formed directly below the Zener avLED at the upper pn junction 50 as a single-photon detector (see FIG. 4 with the associated figure description).

[0120] Figure 4 shows a schematic representation of an exemplary first embodiment of an iQRNG 200 according to the invention. The integrated QRNG 200 shown comprises a photon source 120 and a single-photon detector 130, wherein the photon source 120 and the single-photon detector 130 are arranged vertically one above the other in a common substrate made of a semiconductor material. Preferably, the photon source 120 is a single-photon source (SPS) configured to provide only single or a few photons 128 at a time. Preferably, the photon source 120 is a light-emitting avalanche Zener diode (Zener-avLED) operated at an operating point below or close to the breakdown voltage. Preferably, the single-photon detector 130 is a single-photon avalanche diode (SPAD).

[0121] The iQRNG 200 is preferably formed in a BCD substrate 110 using BCD technology. The BCD substrate 110 preferably comprises a carrier substrate 10 and an epitaxial layer 40 grown on the carrier substrate 10, wherein a deep pn junction 50 located in the epitaxial layer was created between the carrier substrate 10 and the epitaxial layer 40 by diffusion of dopants introduced into a surface S of the carrier substrate 10 below the epitaxial layer 40 (see FIG. 3). The single-photon detector 130 preferably forms an avalanche region in a region around the deep pn junction 50 and comprises an absorption region PW / HPW with a high-voltage p-type well HPW and a p-type well PW."p-type well") for converting photons into electron-hole pairs, with the absorption region PW / HPW directly adjacent to the regions NBL and PBL forming the deep pn junction 50. The fully developed high-voltage p-well HPW enables optimal connection of the deep pn junction 50 from the anode.

[0122] It is preferred that the deep pn junction 50 is formed at least partially between a deep n-layer NBL as cathode 132 and a deep p-layer PBL directly adjoining the deep n-layer NBL, the absorption region PW / HPW directly adjoins the deep p-layer PBL and is formed substantially as a p-region (optionally comprising an intrinsic region), and an anode 134 formed as a p+ region directly adjoins the absorption region PW / HPW.

[0123] In the illustrated embodiment, the respective anodes 124 and 134 of the photon source 120 and the single-photon detector 130 are combined. These can then be electrically contacted, for example, via a common second metallization MET2 on the surface S of the BCD substrate 110. A common and continuous second metallization MET2 can also achieve shading to shield the entire installation space below. The common anodes 124, 134 of the photon source 120 and the single-photon detector 130 are connected, on the one hand, via the p-well PW to the high-voltage p-well HPW and the deep p-layer PBL for contacting the first p-n junction 50, and, on the other hand, to the p-doped region (p-type body) PBODY for contacting the pn junction 121 of the photon source 120.The associated cathodes 122 and 132 are each individually configured, for example, and can be electrically contacted via a first associated metallization MET1 and are preferably connected to the reference potential GND. The iQRNG according to the invention can be configured as a circular structure (corresponding to a spatial rotation of the illustrated plane around an imaginary central axis in the vertical direction). However, other configurations of the illustrated structure are also possible.

[0124] For voltage supply, the cathode 132 of the single-photon detector 130 can be connected, for example, via a load resistor R2 to a preferably monitored second positive supply voltage on a second supply voltage line VENT2. Upon detection of a photon, an electric current flows through the reverse-biased pn junction 50 of the single-photon detector 130. This results, for example, in a voltage drop across the load resistor R2 in the form of a typically rapidly rising and then exponentially falling voltage signal 405 at the output of the entropy source (for further possible processing, reference is made to the exemplary electronic circuit of a quantum random generator 400 shown in FIG. 8). For example, an analog-to-digital converter (ADC) (403 in FIG. 8) can subsequently evaluate this entropy output signal.The ADC (403) may also include amplifiers and / or filters for conditioning the voltage signal (405). The load resistor R2 also limits the current through the single-photon detector 130.

[0125] The cathode 122 of the single-photon detector 130 can, for example, be connected via a first load resistor Ri to a preferably monitored first positive supply voltage on a first supply voltage line VENTI. The first load resistor Ri limits the current through the photon source 120. Upon emission of a photon, the reverse current of the reverse-biased pn junction 121 of the photon source 120 typically exhibits a spike-like increase. This reverse current increase leads to a voltage pulse across the first load resistor Ri. This voltage pulse can be evaluated. For example, the ADC (403) can be configured, using an ADC-internal correlation device, to evaluate only those pulses on the voltage signal 405 at the output of the entropy source that correlate with a voltage pulse at the first load resistor Ri, for example, on an optional correlation signal 430.Only those pulses on the voltage signal 405 are then counted as pulses of the single-photon detector 130 that correlate with the emission of a photon by the photon source 120. This increases the entropy quality of the provided quantum random numbers.

[0126] Figure 5 shows a schematic representation of an exemplary second embodiment of an iQRNG according to the invention. The embodiment shown largely corresponds to the first embodiment shown in FIG. 4. The reference numerals and their respective assignment to individual features therefore apply accordingly. Compared to FIG. 4, however, the high-voltage p-well HPW has been structurally replaced by a tapered high-voltage p-well HPW and a weakly n-doped or intrinsic epitaxial region NEPI. The high-voltage p-well HPW of the absorption region PW / HPW merely forms a narrow channel between the upper p-well PW, also shown in FIG. 2, and the deep p-layer PBL of the deep pn junction 50. The area surrounding the channel is defined by the weakly n-doped or intrinsic epitaxial region NEPI. Through the channel, the deep pn junction 50 can be formed without an additional punch through the weakly n-doped or.intrinsic epitaxial region NEPI connected from the anode.

[0127] Figure 6 shows a schematic representation of an exemplary third embodiment of an iQRNG according to the invention. The embodiment shown largely corresponds to the first embodiment shown in FIG. 5. The reference numerals and their respective assignment to individual features therefore apply accordingly. In comparison to FIG. 4, the channel-shaped high-voltage p-well HPW in the absorption region PW / HPW has been omitted, and the weakly n-doped or intrinsic epitaxial region NEPI extends over the entire lower area. In this respect, in comparison to FIG. 4, the high-voltage p-well HPW has been structurally replaced by a weakly n-doped or intrinsic epitaxial region NEPI. The deep pn junction 50 is thus only formed after an additional punch through the weakly n-doped or intrinsic epitaxial region NEPI.intrinsic epitaxial region NEPI is connected from the anode, which results in a decoupling of possibly several cells arranged next to each other in parallel.

[0128] Figure 7 shows a graphical representation of the dependence of a) the SPAD current and b) the ratio between SPAD current and Zener current as a function of the Zener reverse voltage at various SPAD reverse voltages (less than, equal to, or greater than the breakdown voltage) within an iQRNG according to the invention. The dependence shown under a) clearly shows that the SPAD current increases exponentially with the Zener reverse voltage in the range from 5.6 V to 6.6 V. This applies to all operating modes of the SPAD, i.e. below its own breakdown voltage (< VBD, linear range), close to the breakdown voltage (~ VBD, avalanche range), as well as above the breakdown voltage (> VBD), and thus also in Geiger operation.

[0129] The lower curve shown under b) (< VBD) shows that the measured current ratio between the SPAD current and the Zener current for various Zener reverse voltages in the range 5.8 to 6.6 V is approximately 1:4000. In the breakdown voltage range (~ VBD) of the SPAD, the ratio increases to values ​​of around 1:10. This is due to the so-called multiplication factor of the SPAD, which leaves the linear range in the breakdown voltage range. The upper curve shows the corresponding ratio for the SPAD operated above the corresponding breakdown voltage (> VBD) (approximately 1:1). This means that when the SPAD is operated above the corresponding breakdown voltage (> VBD), the generated photocurrent and the Zener current of the Zener avLED are approximately equal, and a clear measurement signal can be measured by coupling photons to the SPAD.

[0130] Figure 8 shows a schematic representation of an exemplary electronic circuit of a quantum random number generator 400 for generating and outputting a digital random number sequence. The entropy source 401 shown can be, in particular, a photon source 120 and a single-photon detector 130 of an iQRNG 200 according to the invention, wherein the iQRNG 200 (or its entropy source) is connected to the supply voltage via a first supply voltage line VENTI and a second supply voltage line V ENT2, which is connected to a voltage converter 408, is supplied with different supply voltages, for example, compared to a reference potential on a reference potential line GND. It should be noted that a general quantum random generator 400 (and in particular the one shown here as an example) can, in some embodiments, directly correspond to an inventive iQRNG 200, as shown as a semiconductor structure, for example, in FIGS. 4 to 6, with the addition of further circuit components. In particular, a photon source 120 and a single-photon detector 130 of an inventive iQRNG 200 can together be regarded as an entropy source 401 of the shown quantum random generator 400, i.e., even in an inventive iQRNG 200, the combination of a photon source 120 and a single-photon detector 130 can be referred to as an entropy source.A voltage signal 405 generated by the entropy source 401 is first digitized in an analog-to-digital converter (ADC) 403, which is supplied via a reference voltage line VREF, and then passed as a digital output signal 407 to a pulse extension circuit 406. The supply voltage line VENT and the reference voltage line VREF are monitored by a voltage monitor 413, with both the voltage converter 408 and the voltage monitor 413 being supplied with voltage via a positive supply voltage line VDD relative to the reference potential on the reference potential line GND. The voltage converter 408 is connected to the voltage monitor 413 via a voltage converter line 421.

[0131] Pulse extension circuit 406 can, in particular, be a monostable multivibrator (MF). The monostable multivibrator can be used to extend a pulse on the line of the digital output signal 407 of the ADC 403 depending on a certain predetermined system clock, for example, to a time length of at least one clock period of the system clock.

[0132] A synchronized voltage signal 415, i.e., for example, a pulse with a specific minimum length, is then output by the pulse extension circuit 406 and passed to a time-to-pseudo-random-number converter (TPRC) 404.3. This converter can be composed of one or more stages. For example, the TPRC 404.3 can comprise an analog instrument, a time-to-analog converter (TAC), and / or an analog-to-pseudo-random-number converter (APRC), which together can also provide a TPRC 404.3. The pseudorandom number generator of the TPRC 404.3 can comprise a feedback shift register which, depending on the design, shifts its values ​​one place to the left or right with each clock pulse of the system clock and feeds the feedback value of a given feedback polynomial into the released bit.The feedback polynomial can preferably be a simple primitive feedback polynomial. The TPRC 404.3 can be directly connected to an internal data bus 419. The output signal 410 of the TPRC 404.3 can also be fed to an entropy extraction unit 404.4.

[0133] Starting with a starting value of the pseudorandom number generator (a so-called seed value), exactly one pseudorandom number of the pseudorandom number generator can be bijectively assigned to each clock pulse of the system clock starting from a falling edge of the synchronized voltage signal 415, ie the time position of the relevant clock pulse of the system clock after the falling edge of the synchronized voltage signal 415 can then be deduced from the value of the pseudorandom number.

[0134] Instead of a conventional digital counter as in the prior art, a pseudorandom number generator can thus be used. The advantage is that even if an attacker successfully introduces a disturbance into the synchronized voltage signal 415, the randomness of the quantum random bit at the output 411 of the entropy extraction 404.4 is only marginally disturbed, since the attacker would have to know the corresponding feedback polynomial. This can preferably be randomly selected from a multitude of possibilities. The same applies to the seed value of the pseudorandom number generator, which an attacker would then also have to determine. A further advantage of a pseudorandom number generator instead of a simple digital counter is the smaller space requirement of the feedback logic using a simple primitive feedback polynomial compared to a binary counter.If the linear feedback shift register of the pseudorandom number generator is long enough, each clock pulse between two pulses of the voltage signal 405 generated by the entropy source 401 is typically assigned a unique pseudorandom number.

[0135] Entropy extraction 404.4 can be used to determine an error (i.e., an undesired state) in the output signal 410 of TPRC 404.3. For this purpose, entropy extraction 404.4 can, in particular, comprise two linear feedback shift registers that can be compared with one another via a comparator. Conventional binary counters can therefore be dispensed with here as well. Depending on the register depth, feedback can also be provided via simple primitive polynomials as feedback polynomials. The length of the linear feedback shift registers can be freely adjustable. Long shift registers generally have a lower data rate and improved random statistics. Shorter shift registers, on the other hand, allow a higher data rate but exhibit a poorer random distribution.The use of shift registers here has the advantage of requiring fewer gates than in the prior art, reducing the logic depth of the circuits, and thus allowing for a higher clock rate. This reduces the probability of two identical numbers occurring and increases the random bit rate.

[0136] A corresponding method for entropy extraction can provide that two values ​​of the output signal 410 of the TPRC 404.3 are first determined and stored in shift registers of the entropy extraction 404.4. If two values ​​are stored in the shift register of the entropy extraction 404.4, the entropy extraction 404.4 can compare these two values. The values ​​in the shift registers of the entropy extraction 404.4 thus comprise a first value and a second value, both of which were determined by the TPRC 404.3. The entropy extraction 404.4 can then evaluate the two values. If the first value is smaller than the second value and the difference between the first value and the second value is greater than a minimum difference e, the entropy extraction 404.4 can set the value of its output 411 to a first logical value.If the first value is greater than the second value and the difference between the first value and the second value is greater than the minimum difference e, the entropy extraction 404.4 can set its output 411 to a second logical value that is different from the first logical value. If the difference between the first value and the second value is smaller than the minimum difference e, the entropy extraction 404.4 can discard the first value and the second value.

[0137] In such a case, entropy extraction 404.4 preferably causes a so-called watchdog 404.5 to increment an error counter by a first error counter increment. The first error counter increment may be negative. Conversely, entropy extraction 404.4 may decrement the error counter of watchdog 404.5 by a second error counter increment if the difference between the first value and the second value is greater than the minimum difference e. The second error counter increment may be equal to the first error counter increment.

[0138] Watchdog 404.5 is also connected to internal data bus 419. Additionally, watchdog 404.5 can be connected to voltage monitor 413 via one or more, preferably digital, input / output signal lines 414. Watchdog 404.5 preferably monitors the voltage values ​​determined by voltage monitor 413. It has proven useful for voltage monitor 413 to determine and monitor not only the voltages in quantum random generator 400, but also other voltages within the respective application circuit. Voltage monitor 413 can be, for example, an ADC.

[0139] The actual task of watchdog 404.5, however, is to monitor the quantum random number RN at output 411 of entropy extraction 404.4. Watchdog 404.5 can preferably detect at least three defined error cases. Watchdog 404.5 can forward valid quantum random bits at output 411, generating a seed value S 412, to an optional additional linear feedback shift register as a backup pseudorandom number generator (PRNG) 404.6. Preferably, watchdog 404.5 prevents the use of the valid quantum random bits by a finite state machine 404.8. If an error occurs, watchdog 404.5 can set certain error bits for further evaluation.

[0140] If, for example, the watchdog 404.5 has detected an error in the quantum random generator 400, it can preferably put the quantum random generator 400 into an emergency state. To do so, the watchdog 404.5 preferably sets a selection signal 416 of a signal multiplexer 404.7 downstream of the random number generation, so that the signal multiplexer 404.7, instead of the random numbers RN at the output 411 of the entropy extraction 404.4, applies the pseudorandom number PRN of the optional PRNG 404.6 in the form of a stream of pseudorandom bits via a pseudorandom signal line 417 to the input of the finite state machine 404.8 as a replacement for the at least potentially faulty random number RN of the output 411 of the entropy extraction 404.4.

[0141] The optional additional linear feedback shift register of the PRNG 404.6 can be configured to generate pseudorandom numbers PRN. The seed value S 412 preferably comprises the last valid quantum random bits of the output 411 of the entropy extraction 404.4. The watchdog 404.5 then preferably applies these last valid quantum random bits at the output 411 to the input of the optional PRNG 404.6. The seed value S can thus be used as a random, secure starting value for a generator polynomial of the feedback of the optional additional linear feedback shift register of the PRNG 404.6 for generating the pseudorandom number PRN and signaling it via the pseudorandom signal line 417. The generator polynomial and the degree of the generator polynomial are preferably freely selectable. The optional backup pseudo-random number generator can enable the provision of secure random numbers, at least temporarily, in the event of an error.

[0142] The finite-state machine 404.8 is responsible for receiving the random number RN or the pseudorandom number PRN at the output of the signal multiplexer 404.7 and writing corresponding quantum random data words 418 via a pseudorandom signal line 417 into a volatile memory (RAM) or a FIFO (First In - First Out) memory 404.9. If the write operation is successful, the finite-state machine 404.8 can set a finish flag 404.10 via the internal data bus 419. A processor can then access the volatile memory (RAM) or a FIFO (First In - First Out) memory 404.9, for example, and read the random number, for example, for encryption.

[0143] The quantum random generator 400 may further comprise a temperature sensor or other sensors with which the watchdog 404.5 or another device part of the quantum random generator 400, possibly by means of the ADO 403 or another analog-to-digital converter and / or other device parts such as sensor amplifiers and / or filters, monitors physical parameters of the environment of the quantum random generator 400, such as the temperature, and initiates countermeasures if a value of such a physical parameter lies outside a predetermined value range. Such countermeasures may include signaling to other devices, for example via the internal data bus 419 or an emergency operation, e.g., using the PRGNG 404.6 and the multiplexer 404.7, and / or changing internal operating parameters, such as the voltage levels of the internal supply voltages, e.g.,by means of the voltage converter 408 and / or the switching off of the random number generation, etc. This closes side channels for influencing the quantum random generator 400.

[0144] Figure 9 shows a schematic representation of an exemplary layout of an integrated electronic circuit 500 with an iQRNG 200 according to the invention in the pad frame 503, viewed from above. The integrated electronic circuit 500, for example, a microcontroller, has an inner region 505 in which the essential subcircuits of the integrated electronic circuit 500 are located. Typically, the inner region 505 is surrounded by a wiring region 504, in which, above all, supply voltage lines, data bus lines, and other lines can be routed.

[0145] The wiring area 504 and the inner area 505 of the integrated electronic circuit 500 are typically surrounded by the pad frame 503 (also referred to as pad edge), which includes the connection pads 502 (connection areas) for the electrical bonds or other electrical connections.

[0146] Preferably, an iQRNG 200 according to the invention or a corresponding quantum random generator 400, as shown, for example, in Figure 8, can be placed entirely or at least substantially in the pad frame 503, since the gaps between the individual connection pads 502 are often not filled with electronic circuit components. However, these gaps must still be processed during the manufacture of the integrated electronic circuit 500 and therefore cause unnecessary manufacturing costs. Placing an iQRNG 200 according to the invention or a corresponding quantum random generator 400 entirely or at least substantially in the pad frame 503 therefore significantly reduces the additional costs for their provision.

[0147] In particular, at least the photon source 120 and the single-photon detector 130 (entropy source 401) can preferably be placed in the pad frame 503 between two connection pads 502. Furthermore, an ADC 403, a voltage converter 408 for supplying power to the entropy source 403, a pulse extension circuit 406, and / or analog components of a quantum random generator 400 according to the invention (e.g., an amplifier) ​​can also be placed in the pad frame 503 between two connection pads 502.

[0148] Figure 10 shows an exemplary schematic block diagram for a quantum random generator 600 with integrated power supply 608, data bus driver 603, and control logic 605. Power supply 608 and a voltage regulator (VREG) 609 are supplied with electrical energy from a common power supply line (GND, V1V8). Power supply 608 can generate the necessary voltages for operating entropy source 601 of quantum random generator 600. The supplied voltages can be monitored via a voltage monitor 607.

[0149] The entropy source 601 shown can, in particular, be a photon source 120 and a single-photon detector 130 of an iQRNG 200 according to the invention. However, as explained above in the introduction, the iQRNG 200 according to the invention can, in principle, also comprise further components or even the entire quantum random generator 600 shown by incorporating further components. The data bus driver 603 can, in particular, be a serial data bus according to the known PC standard. However, other types of bus systems can also be used, and the bus driver 603 is not limited to the PC standard. The use of a standard interface enables easy access by an external device, for example a microprocessor, to the generated random numbers. The entropy source 601 generally provides a random signal with random pulses. An evaluation electronics unit, abbreviated to number generator 602 (i.e.The random number generator (i.e., an electronic circuit for generating and outputting a digital random number sequence based on the statistical evaluation of the temporal sequence of signals from the single-photon detector) can be configured to generate machine-readable random numbers in bit format depending on the temporal spacing of the random pulses.

[0150] A watchdog 604 (also referred to as a health check) can be configured to monitor the correct generation of the random bits and / or random numbers. The voltage regulator 609 can supply electrical power to a control logic 605 for the operation of the circuit. The control logic 605 can be configured to control and monitor all parts of the quantum random generator 600 shown. For testing, the control logic can receive a test signal via a test line. If the quantitative values ​​of the statistical properties of the generated random bits and / or random numbers deviate outside the permissible value ranges, the watchdog 604 can signal the control logic 605 that an error may be present.

[0151] Preferably, a microcontroller can query information about the status of the watchdog 604 via the data bus. It can be provided that the quantum random generator 600 can additionally send an interrupt signal to said microcontroller at its interrupt port via a further connection (not shown). Using this interrupt signal, the quantum random generator 600 can signal to the microcontroller that the microcontroller should read the status registers of the control logic 605 via a serial data line SDA, possibly taking into account a clock signal provided on a serial clock line, at the data interface. A corresponding clock signal (e.g., 100 MHz) can be provided via a local oscillator (OSC) 610.In the illustration shown, the oscillator 610 is, by way of example, only connected to the control logic 605 and the data bus driver 603, but one or more clock signals of the oscillator 610 can also be provided to other components of the quantum random generator 600 shown.

[0152] Figure 11 shows an exemplary schematic block diagram of a data processing device in combination with a controlled system. In the following, it is assumed that the data processing device is a computer in the form of a monolithic, microintegrated circuit 702, for example, a microcontroller, for controlling a controlled system 726. First, the configuration of an exemplary microcontroller as an example of a monolithic, microintegrated circuit 702 with a quantum random number generator 728, for example, comprising an iQRNG according to the invention, and an exemplary content of various memories, as it could be used after production, is described. The computer in the form of the monolithic, microintegrated circuit 702, for example, the microcontroller, is connected to a controlled system 726 via a connection 703.The controlled system could, for example, be a backup tape drive. With a tape drive, it is important that the integrity of the backed-up data is maintained. It is therefore also important that the integrity of the data and programs used by the computer in the form of the monolithic microintegrated circuit 702, for example, the microcontroller, is maintained.

[0153] The computer shown in the example of FIG. 11 comprises, for example, the monolithic integrated circuit 702 of an exemplary microcontroller, which includes, for example, a control device 704, a non-volatile memory 706, and a random access memory 708, also referred to below as RAM (Random Access Memory). The non-volatile memory 706 can comprise any suitable type, e.g., a flash memory and other types. In this example, it is a read-only memory, e.g., an EEPROM. The microcontroller here is only an exemplary embodiment of a one-piece and monolithic integrated circuit 702 with a monolithically integrated quantum random number generator 728. Other microelectronic integrated circuits 702 are expressly encompassed by the technical teaching of the document presented here.When this document refers to an “integrated circuit 702 of a microcontroller” or an “integrated circuit 702 of the microcontroller,” the person skilled in the art will automatically include other microelectronic integrated circuits and devices. These microelectronic integrated circuits and devices, within the meaning of the submitted document, expressly also include MEMS (Micro-Electro-Mechanical System), MOEMS (also: MOMS) (Micro-Optical-Electro-Mechanical System), optical MEMS, optical microsystems, BioMEMS (stands for the application of MEMS to, for example, cell biology or related fields), micromachines, MEFS (Micro-Electro-Fluidic System), NEMS (Nano-Electro-Mechanical System), pMEMS (Piezo-Electric Micro-Electro-Mechanical System), RF-MEMS (Radio-Frequency MEMS).

[0154] The document presented here therefore considers the term "microcontroller" to be used only as an example. Those skilled in the art will immediately understand the possible use of a quantum random number generator 728 with a time-to-pseudorandom number converter 404.3, as described above, in a monolithic co-integration with conventional microintegrated circuits when referring to an "integrated circuit 702 of the microcontroller," and expressly does not limit the technical teaching of this document to the co-integration of the proposed quantum random number generator 728 with a microcontroller shown.Such other common integrated circuits 702 may include, for example: microcontrollers, microprocessors, memories, DRAMs, SRAMs, RAMs, volatile memories, OTP memories, EEPROMs, flash memories, MRAMs, FRAMs, bus transceivers, sensor evaluation circuits, motor driver circuits, control circuits for automotive control circuits, graphics controllers, communication circuits, evaluation circuits for biometric sensors, evaluation circuits for input devices, control circuits, chip card circuits, circuits for mobile phones or smartphones, circuits for servers, circuits for PCs, circuits for laptops, circuits for access orAccess control systems, circuits for the coded recording of operating parameters, electronic security circuits, radio system circuits, communication circuits, encryption and / or decryption system circuits, individualization and identification circuits and / or identification systems, gaming device circuits, simulation system circuits, computer system circuits, noise and / or signal source circuits, modulation system circuits and / or devices, and circuits with a device for generating and / or using spreading codes. This list is not exhaustive and should therefore be considered incomplete.

[0155] Random access memory 708 may be any suitable memory, e.g., SRAM, but in this case, it is DRAM. Non-volatile memory 706 and random access memory 708 are located outside of controller 704 in the example shown in FIG. 11. An additional non-volatile memory 730 may optionally be provided within the microintegrated circuit outside of controller 704 and connected thereto via an internal interface 7301.

[0156] The microintegrated circuit 702 with the exemplary control device 704 is preferably a monolithic integrated circuit, which comprises, for example, the following: one or more processors 710-1, 710-2; a tightly coupled memory 714, which may be, for example, an SRAM; a non-volatile boot ROM 716 containing preferably non-modifiable code; a hashing engine 718, which may be present, for example; one or more one-time programmable memories (OTP) 720 and 722; a JTAG test interface 712; an interface 732; internal interfaces 763, 781 and 7301 coupled to the memories 706, 708 and 730; a quantum random number generator 728; and a hard-wired test disabling circuit 724. The OTP memories 720 and 722 may be separate memories or portions of a memory within the example integrated circuit 702.In this example, these are sections of a single memory. The test disabling circuit 724 is preferably located between the test port 712, which in this example is a JTAG port, and the processor(s) 710. The preferably present disabling circuit 724 responds to the data in the OTP memory section 722. The optional hashing engine 718 uses data (one or more keys) in the OTP memory section 720. The OTP memory section 720 preferably stores critical security parameters (CSPs) including a secret key and at least one public key. Additional keys may be stored in the OTP memory section 720. In one embodiment of the proposal of this example application of a quantum random number generator 728, the secret key is preferably unique for each instance of the exemplary microintegrated circuit 702 proposed herein.

[0157] The processor(s) 710 preferably execute(s) instructions only from the tightly coupled memory (TOM) 714 and from the DRAM 708 in the example presented here, as shown in FIG. 11. The boundary of the controller 704 is a cryptographic virtual boundary, and the data and program execution within this boundary are considered secure in this first proposal for applying a proposed quantum random number generator 728, as explained further below. The EEPROM 706 and the DRAM 708 (and the memory 730, if present) are located outside the cryptographic boundary, and without security measures, the contents of these memories would not be secure within the meaning of the document presented here. The interfaces 763, 7301, 732, and 781 are located at the physical and cryptographic boundary of the controller 704 within the microintegrated circuit 702.The document presented here thus discloses a microintegrated circuit 702 having internal interfaces 763, 7301, 732, and 781 at a cryptographic boundary between a control device 704 and other parts (708, 730, 706) of the integrated microelectronic circuit 702 that are classified as non-secure or less secure. The essential purpose of these internal interfaces 763, 7301, 732, and 781 is thus to securely shield an internal control device 704 within the microintegrated microelectronic circuit 702.

[0158] The contents of DRAM 708 and EEPROM 706 are preferably cryptographically protected by authentication codes. In this example, the authentication codes used in DRAM 708 are preferably of a different type than the authentication codes used in EEPROM 706. In this example, the contents of EEPROM 706 are protected from undetected malicious modification at least through the use of digital signatures. The format of the data in EEPROM 706 is also preferably different from that in DRAM 708.

[0159] For example, the EEPROM 706 preferably stores the firmware arranged in one or more data records 761, each with a digital signature 762. The digital signatures used in this example of the proposal use public and private keys. Therefore, the details of the digital signatures will not be described further, as they are known to those skilled in the art. When a processor (710-1, 710-2) reads a data record from the EEPROM 706, the processor 710 checks its digital signature. If the digital signature is valid, the data record is processed by the processor(s) 710 using computer-implemented methods of the firmware. The processor(s) 710 thus preferably only executes validly signed firmware. For signing, the processors 710 preferably use keys and authentication codes that depend on quantum random numbers from one or more quantum random number generators 728.

[0160] For example, as shown in FIG. 11, the boot ROM 716 may contain code that the processor 710 uses to read a load program S2 from the EEPROM 706 to read additional records from the EEPROM 706. Logic in the processor 710 loads a program counter (not shown) in the processor 710 with the starting address 715 of the boot ROM 716. The processor 710 then executes the code in the boot ROM 715. This boot ROM 715 code may read a computer-implemented load program from the EEPROM 706. The boot code in the boot ROM 715 is considered secure because it is within the cryptographic boundary of the controller 704. The boot program is protected by a digital signature, which the processor 710 verifies when executing the boot ROM code S4 in the boot ROM 715 using the public key stored in the first OTP memory 720. Subsequent data records are read using the boot program S6.The loading program in EEPROM 706 and the subsequent data records are each provided with a digital signature and have one or more public keys embedded. When executing the loading code of the loading program in EEPROM 706, the processor 710 checks the signature of the newly read data record from EEPROM 706 in step S8 using a public key embedded in a previously loaded data record or a data record stored in OTP memory 720.

[0161] A record read from EEPROM 706 may contain too much firmware code / data for the small, tightly coupled memory TCM 714 of controller 704 within microelectronic circuit 702 to store. TCM 714 preferably stores firmware code / data that is immediately required by processor(s) 710. The remainder of the firmware record is transferred to DRAM 708. Because DRAM 708 lies outside the cryptographic boundary of controller 704, the code / data stored there is cryptographically protected by authentication codes generated by processor 710, preferably using quantum random numbers from quantum random number generator 728.

[0162] Figure 12 shows an exemplary schematic block diagram of a circuit for disabling a test interface of the device of Figure 11. Figure 13 shows an exemplary flowchart illustrating the verification of digital signatures. Figure 14 shows an exemplary flowchart illustrating the use of HASH functions in storing and retrieving data from a DRAM of the device of Figure 11.

[0163] As shown in FIG. 13, the processor 710 reads the data as a record from the EEPROM 706 and writes it as words to the DRAM 708 or reads these words out again from this DRAM 708. In this example, when the processor 710 reads a record from the EEPROM in step S20, the processor 710 validates it as described in FIG. 14 and the associated description. The processor 710 stores at least a portion of the data of the record in the TCM 714 in step S21. The processor 710 processes the remaining data of the record, for example, as follows and stores it in the DRAM 708. The processor(s) 710 cooperate(s) with the optional hash engine 718 to calculate a hash value for each word of the remaining data, for example, in step S22 and to store the hash value in the DRAM 708 at a location associated with the stored word in step S24. The word size is chosen according to the system limitations.It can be as small as one byte. In practice, it can be 32 bits. When processor 710 reads a word from DRAM 708 in step S26, processor 710 and hash engine 718 preferably recalculate the hash value and, in step S30, compare the recalculated hash value with the corresponding hash value stored in DRAM 708.

[0164] If the hash values ​​have a predetermined relationship, which is checked in step S34, e.g., they are equal, the processor 710 processes the read data in a step S38. If the hash values ​​do not have the predetermined relationship, the processor 710 interrupts processing in step S36 and / or the processor 710 generates an error message and / or the processor 710 ignores the data / code.

[0165] Storing words in DRAM 708 with corresponding authentication codes, preferably based on quantum random numbers from quantum random number generator 728, facilitates random access to the words by processor(s) 710.

[0166] The hash function can be any suitable hash function. One example is the well-known HMAC function. In this example, the HASH function uses the secret key stored in the OTP memory 720. It could also use a different key stored in the OTP memory. Preferably, the secret key is based on a quantum random number from the quantum random number generator 728. An example of the hash value is HMAC (address | | data 1 1 secret key), where the character string "| |" here stands for the concatenation. Taking into account the number of bytes that the DRAM 708 can store, the HASH value preferably comprises at least enough bits to avoid or at least reduce duplication of HASH values ​​in the DRAM 708. The number of bits of the HASH value is preferably at least 96 bits and can also be significantly larger.The industry standard is 160 bits, which reduces the probability of duplication of hash values ​​to a sufficiently low level.

[0167] By providing the cryptographic boundary of the control device 704 and protecting the data stored in DRAM 708 and EEPROM 706, the integrated circuit 702, particularly that of the microcontroller, is protected from unauthorized access to the programs and data used by the computer's processor(s) 710 during normal operation. This is particularly important in the automotive sector to prevent counterfeiting and unauthorized replacement parts, which typically require knowledge of the firmware of the illegally copied replacement parts. However, the JTAG test interface 712 could allow access to the processor(s) 710 in a test mode using known EMULATE and TRACE routines and still permit illegal program modifications.The JTAG test port 712 is required for testing at least during the manufacturing process of the integrated circuit 702, for example, that of a microcontroller, and can be used for fault diagnosis after manufacturing. Such analysis capability of an integrated automotive circuit 702, for example, an automotive microcontroller, is an essential prerequisite for meeting the quality requirements of T16491. To prevent unauthorized and, in particular, illegal use of the JTAG interface 712, the OTP memory 722 can, for example, include at least one security bit that, together with the blocking circuit 724, blocks the JTAG interface 712.

[0168] In one example, the OTP memory 722 contains only one bit. The OTP memory 722 allows a bit to change only once from one state, e.g., "0," to the opposite state, "1." For example, during manufacture of the integrated circuit 702, e.g., the microcontroller, the bit is "0," enabling testing. In a final testing step, the manufacturer of the exemplary integrated circuit 702, e.g., the microcontroller, sets the bit to "1" before releasing the integrated circuit 702, e.g., the microcontroller, for delivery and use. The JTAG connector 712 typically has a serial input and a serial output (see FIG. 12).The deactivation circuit, which is part of the circuit of the control device 704 within the integrated circuit 702, for example, the microcontroller, preferably comprises a gate 7241, which is located, for example, between the serial output of the JTAG interface 710 and the processor(s) 710, and a gate 7242, which is located between the serial input of the JTAG interface 710 and the processor(s) 710. The security bit "1" in the OTP memory 722 deactivates the gates 7241 and 7242. Since the security bit cannot be changed, the test port is then secured against use after the manufacture and delivery of the integrated circuit 702, for example, the microcontroller.

[0169] In another example, the OTP memory 722 has a two-bit security code, initially "00." This allows for verification during manufacturing, after which the code is set to "01," meaning one of the two bits is set to "1." This "01" code disables gates 7241 and 7242. If an error occurs, the integrated circuit 702, for example, of the microcontroller, is returned to its manufacturer, who sets the other bit to "1," resulting in the code "11," which allows verification via pin 712. Such verification is preferably destructive, as it does not allow resetting to the original value.Access to the OTP memory 722 to change the security code can be achieved using a suitable access code, preferably generated by a quantum random number generator 728, which is provided with a digital signature that can be verified by a quantum random number-based key stored in the OTP memory 720. The key can be, for example, the standard public key stored in the memory 720. This allows the security code to be changed to "11," which enables verification via the JTAG interface 712. The original integrated circuit 702, for example, the microcontroller, is preferably retained and preferably destroyed by the manufacturer, and the user receives a new integrated circuit 702, for example, a microcontroller.

[0170] In another example, the security code may consist of three or more bits that change when the signed access code is used. During manufacture, the code is "000" and when released to a user, it is "001." If an error occurs, the manufacturer changes the code to "011" to enable testing. After testing, the code is changed to "111," which secures the JTAG interface 712 against use and allows the integrated circuit 702, for example, of the microcontroller, to be returned to the user. Only a signed access code, provided with a digital signature verified by a key in the OTP memory 720, can be used to change the code stored in the OTP memory 722.

[0171] Security codes of two or more bits provide an audit trail for testing (or any unauthorized testing attempts) after manufacturing.

[0172] Additional interface and additional EEPROM

[0173] As shown in FIG. 11, the control device 704 of the integrated circuit 702, for example, the microcontroller, can optionally have at least one further interface 732 in addition to the connections 703 and 712. This further interface 732 can, for example, be an Ethernet connection or a Fibre Channel connection or an automotive data bus connection for data buses such as CAN, LIN, DSI3, or PSI5. A Fibre Channel connection within the meaning of the document presented here is a data connection that uses an optical fiber or other waveguide for electromagnetic radiation.

[0174] The integrated circuit 702, for example, the microcontroller, may additionally have another non-volatile memory 730 outside the control device 704 of the integrated circuit 702, for example, a microcontroller, which stores data cryptographically protected by a security parameter stored in the OTP memory 720. The other non-volatile memory 730 is coupled to the control device 704 via the internal interface 7301 of the integrated circuit 702, for example, the microcontroller.

[0175] The additional non-volatile memory 730 can be an EEPROM, for example. The additional memory 730 can store additional critical security parameters outside of the control device 704. The additional parameters are preferably encrypted and provided with digital signatures to make them secure. The additional parameters are preferably encrypted with the secret key that is valid only for the control device 704 and is stored in the OTP memory 720. The secret key is preferably based on a quantum random number from a quantum random number generator 728. The digital signatures of the additional parameters are created using the unique secret key stored in the OTP memory 720. This secret key is used to decrypt the additional security parameters and to verify the digital signatures read from the additional memory 730.

[0176] The additional non-volatile memory 730 may contain other encrypted and / or digitally signed data.

[0177] The additional security parameters outside the control device 704 of the integrated circuit 702, for example the microcontroller, can be used to secure the data and codes transmitted via the interface(s) 732.

[0178] Manufacturing of the integrated circuit 702, for example the microcontroller

[0179] During manufacture of the integrated circuit 702, e.g., the microcontroller, the boot code is preferably hard-coded in the boot ROM 716; the loader and other codes / data are stored in the EEPROM 706 with digital signatures based on the public and private keys, preferably generated using quantum random numbers from a quantum random number generator 728; and preferably, at least one public key is generated using a quantum random number from a quantum random number generator 728 and stored in the OTP memory 720.

[0180] The secret key is preferably only stored in the OTP 720 once the security code, which is preferably based on a quantum random number from a quantum random number generator 728, has been set in the OTP 22 and the test port of the exemplary JTAG interface 712 has been disabled. The control device 704 of the integrated circuit 702, for example, the microcontroller, contains the necessary quantum random number generator QRNG 728 in the example presented here. The firmware stored in the tightly coupled memory 714 or in the DRAM 708 reads one or more quantum random numbers of, for example, 256 bits from the quantum random number generator 728 and stores them in the OTP 720 as a secret key, without this data leaving the control device 704, preferably within the integrated circuit 702, for example, the microcontroller.This preferably occurs only after the deactivation of the test connection 712, in order to prevent access to the secret key even for persons who have access to the manufacturing process. Preferably, the logic gates of the integrated circuit 702, for example, the microcontroller, or at least those of the control device 704 of the integrated circuit 702, for example, the microcontroller, are designed such that the current peaks occurring during changes in logical states within the circuits of the logic gates do not allow any conclusions to be drawn about the processes and / or the data and / or the quantum random numbers and / or the circuit states of the device. This avoids so-called side channels. For this purpose, the proposed device can comprise current sources, complementary switching, complementary dummy circuits, energy reserves (e.g., capacitors), etc.

[0181] The hash function of the hashing engine 718 may be any suitable hash function and is not limited to the HMAC example described above.

[0182] The on-chip quantum random generator 728 could be omitted from the integrated circuit 702, such as the microcontroller, and instead an off-chip quantum random generator could be used to generate the secret key during the manufacturing process. However, an on-chip quantum random generator 728 is significantly more secure.

[0183] The firmware stored in EEPROM 706 is preferably cryptographically protected, in this example by digital signatures. During manufacturing, the firmware is first compiled. It can then be digitally signed with a secret private key of a private-public key system. Preferably, the secret private key of the private-public key system is based on a quantum random number from a quantum random number generator 728. The public key is preferably stored in OTP memory 720 so that the signature can be verified. The signed firmware is stored in EEPROM 706. The digital signatures can be created by transmitting the compiled firmware to a secure signature generator during the manufacturing process. The secure signature generator can be the integrated circuit 702, for example of the microcontroller, specifically the control device 704 in cooperation with the quantum random number generator 728 itself.The signed firmware can be downloaded to EEPROM 706 via a communications connection, e.g., the Internet, if the signing is performed externally. However, processor 710 can remove the firmware signature before saving it to EEPROM 706 and replace it with its own quantum random number-based signature based on a quantum random number from its quantum random number generator 728, which then makes it impossible for anyone to read the firmware without exception.

[0184] Instead of an EEPROM, the non-volatile memory 706 can be any other suitable memory, for example, a FLASH memory. The additional non-volatile memory 730 can be, for example, a serial EEPROM memory. The one-time programmable memory OTP 722, which contains the security code, can be replaced with another reprogrammable, non-volatile memory, and the security code can be changed using signed firmware. However, a memory 722 that can only be programmed once is more secure because its programming is irreversible.

[0185] The DRAM 708 can be further protected by making access to the DRAM 708 physically very difficult and detectable in the event of an attempt. For example, the connections between the DRAM 708 and the control device 704 can be buried in layers of the metallization stack of the integrated circuit 702, for example, the microcontroller, or otherwise protected against physical sensing (e.g., by e-beam). Preferably, the device parts of the control device 704 also include such sensing protection. In particular, it is advantageous if the quantum random generator 728 has such sensing protection, for example, in the form of a metal layer at a predefined potential.

[0186] Figure 15 shows a flowchart 7500 of an exemplary method for entropy extraction, which, for example, is carried out by entropy extraction 404.4. The method provides for, in a first step 7501, two values ​​of the output 410 of the time-to-pseudo-random number converter 404.3 to be determined and stored in a shift register of entropy extraction 404.4. If two values ​​are stored in the shift register of entropy extraction 404.4, entropy extraction 404.4 compares these two values ​​in a second step 7502. The two values ​​in the shift register of entropy extraction 404.4 thus comprise a first value and a second value, both of which the time-to-pseudo-random number converter 404.3 has determined using two different pseudo-random number determinations depending on the respective time period between two signal pulses of an output signal from a comparator. In a third step 503, the entropy extraction 404 evaluates.4 the two values. If the first value is smaller than the second value and the difference between value 1 and value 2 is greater than a minimum difference E, then the entropy extraction 404.4 sets the value of its output 411 to a first logical value. If the value 1 is greater than the value 2 and the difference between the value 1 and the value 2 is greater than the minimum difference E, then the entropy extraction 404.4 sets its output 411 to a second logical value that is different from the first logical value. If the difference between the value 1 and the value 2 is smaller than the minimum difference E, then the entropy extraction discards the value 1 and the value 2. In such a case, the entropy extraction preferably causes the watchdog 404.5 to increment an error counter by a first error counter increment. The first error counter increment can be negative. Conversely, the entropy extraction 404.4 can increment the error counter of the watchdog 404.5 by a second error counter increment if the difference between the value 1 and the value 2 is greater than the minimum difference E. The second error counter increment can be equal to the first error counter increment. Typically, the signs of the first error counter increment and the second error counter increment are the same.

[0187] The processor can preferably set the error counter increments and the starting value of the error counter, as well as an error counter threshold. If the error counter count crosses the error counter threshold, the watchdog 404.5 signals the presence of a critical error condition, preferably by means of an interrupt signal 420 or other signaling to the processor. The processor then typically starts a self-test program to test the various parts of the quantum random generator 728. For this purpose, the processor can preferably, for example, place the ADC 403 into a state in which the processor can write test values ​​to an output register of the ADC 403, which the subsequent signal chain then processes like real samples. Since the test values ​​are known in advance, the processor can observe and evaluate the correct response of the rest of the system, for example, the incrementing of the error counter in the watchdog 404.5.Preferably, the processor can therefore monitor as many memory nodes as possible of the evaluation circuit 404 or the control device 704 and read their logical state.

[0188] Figure 16 shows an example oscillogram of the voltage signal 404 of the entropy source 401 from FIG. 9. As can easily be seen, first spikes 7601 occur with a first height and second spikes 7602 with a second height. The scatter of the first height of the first spikes 7601 and the scatter of the second height of the second spikes 7602 are each so small that a clear separation of these events 7601, 7602 is possible using an example cutting level 7603 by selecting a constant. The cutting level 7603 corresponds to the value that the processor sets using the constant, which is preferably stored as a processor register.

[0189] Figure 17 shows an exemplary schematic sequence of server-client communication using a quantum random number generator, for example comprising an iQRNG according to the invention. In this case, a first device, such as one according to FIG. 11, as a server, is to communicate in an encrypted manner via a data bus with a second device, such as one also according to FIG. 11, as a client. In a first example, both the first device and the second device are to each comprise a quantum random number generator 728, which the respective first processor 710-1 of the computer (here of the exemplary microintegrated circuit 702) uses for encryption. The quantum random number generator 728 preferably comprises, in whole or in part, a construction corresponding to one of FIG. 8. Very particularly preferably, the quantum random number generators 728 of the first device and the second device each comprise an iQRNG according to the invention.This increases the data rate of the generated quantum random bits and enables the first processor 710-1 of the computer (here the exemplary microintegrated circuit 702) of the respective device to generate and exchange the keys very quickly.

[0190] The respective first processors 710-1 of the respective computers (here, the exemplary microintegrated circuit 702) of the respective devices encrypt their mutual communication, preferably using an RSA encryption method. The exemplary RSA encryption method is known in particular from R.L. Rivest, A. Shamir, and L. Adleman, "A Method for Obtaining Digital Signatures and Public-Key Cryptosystems," Communications of the ACM, February 1978, Vol. 21, No. 2, pages 120 to 126. The prime numbers that the respective first processor 710-1 of the respective computer (here, the exemplary microintegrated circuit 702) of the respective device preferably uses to generate the public and private keys are preferably generated by the quantum random number generator 728.The communication of the computer (here the exemplary micro-integrated circuit 702) of the server with the respective first processor 710-1 of the respective computer (here the exemplary micro-integrated circuit 702) of the client preferably comprises, firstly, the process “Server Process”, which is started on the respective first processor 710-1 of the respective computer (here the exemplary micro-integrated circuit 702) of the server, i.e. the first device, and secondly, the process “Client Process”, which is started on the respective first processor 710-1 of the respective computer (here the exemplary micro-integrated circuit 702) of the client, i.e. the second device.

[0191] The respective first processor 710-1 of the respective computer (here, the exemplary micro-integrated circuit 702) of the client typically communicates with the respective first processor 710-1 of the respective computer (here, the exemplary micro-integrated circuit 702) of the server via so-called sockets. These are communication points provided by the respective operating system of the respective computer (here, the exemplary micro-integrated circuit 702). The functions required to establish communication preferably originate, for example, from the standard C library socket.h.

[0192] The communication according to FIG. 12 is explained below using an example: Initially, the first processor 710-1 of the server's computer (here, the exemplary microintegrated circuit 702) generates a socket descriptor in step 3000. A socket descriptor, as defined in the document presented here, is an integer-like file handle, which is generated, for example, by the Standard C Library function socket() of the socket.h library. The first processor 710-1 of the server's computer (here, the exemplary microintegrated circuit 702) can use this socket descriptor in subsequent function calls that use sockets.

[0193] In step 3010, the first processor 710-1 of the server's computer (here, the exemplary micro-integrated circuit 702) preferably binds the socket descriptor to a port and an IP address. Binding, as defined in this document, means that the first processor 710-1 of the server's computer (here, the exemplary micro-integrated circuit 702) uses the standard C function bind() from the standard C library socket.h to logically link the port and IP address to the socket descriptor generated in step 3000. A port, as defined in this document, is a part of the network address that enables the assignment of data packets between server and client programs. An IP address, as defined in this document, is a network address that uniquely identifies a participant in a network.

[0194] In the next step 3020, the first processor 710-1 of the server's computer (here, the exemplary micro-integrated circuit 702) enters a passive wait state 3020 and waits for connection requests from a first processor 710-1 of the server's computer (here, the exemplary micro-integrated circuit 702) of a client. For the purposes of the document presented here, the first processor 710-1 of the server's computer (here, the exemplary micro-integrated circuit 702) preferably calls the standard C function listen() of the socket.h library for this purpose. This function indicates that the first processor 710-1 of the server's computer (here, the exemplary micro-integrated circuit 702) is ready to accept connection requests from clients.The first processor 10-1 of the computer (here, the exemplary micro-integrated circuit 702) creates a queue for all incoming connection requests from the first processor 710-1 of the computer (here, the exemplary micro-integrated circuit 702) of the client in one of the memories of the computer (here, the exemplary micro-integrated circuit 702) or the first processor 710-1 of the computer (here, the exemplary micro-integrated circuit 702) or another device part of the computer (here, the exemplary micro-integrated circuit 702).If the first processor 710-1 of the computer (here the exemplary micro-integrated circuit 702) of the server detects a connection request from a first processor 710-1 of the computer (here the exemplary micro-integrated circuit 702) of a client, the first processor 710-1 of the computer (here the exemplary micro-integrated circuit 702) of the server accepts this connection request from the first processor 710-1 of the computer (here the exemplary micro-integrated circuit 702) of the client.

[0195] The first processor 710-1 of the computer (here of the exemplary micro-integrated circuit 702) of the server then establishes a connection to the first processor 710-1 of the computer (here of the exemplary micro-integrated circuit 702) of the client in a following step 3030. The first processor 710-1 of the computer (here of the exemplary micro-integrated circuit 702) of the server detects a connection request from the first processor 710-1 of the computer (here of the exemplary micro-integrated circuit 702) of the client by the first processor 710-1 of the computer (here of the exemplary micro-integrated circuit 702) of the server exiting the listen() function. The first processor 710-1 of the computer (here the exemplary microintegrated circuit 702) of the server accepts the connection request preferably by calling the standard C function accept() of the socket.h standard C library.The first processor 710-1 of the server's computer (here, the exemplary micro-integrated circuit 702) preferably extracts the first connection request from the queue of open connection requests for the server and then uses it to establish the connection to the first processor 710-1 of the client's computer (here, the exemplary micro-integrated circuit 702). If successful, the accept() function returns a socket descriptor of the client to the first processor 710-1 of the computer (here, the exemplary micro-integrated circuit 702). A socket descriptor, as defined in this document, is an integer similar to the file handle of the standard C library socket.h. This then creates a connection between the first processor 710-1 of the computer (here the exemplary micro-integrated circuit 702) of the server and the first processor 710-1 of the computer (here the exemplary micro-integrated circuit 702) of the client.

[0196] If such a connection exists, the first processor 710-1 of the server's computer (here, the exemplary micro-integrated circuit 702) preferably starts a keyExchangeServer() function in a subsequent step 3040. The first processor 710-1 of the server's computer (here, the exemplary micro-integrated circuit 702) then executes this keyExchange() function in this step 3040 to send its public key to the first processor 710-1 of the client's computer (here, the exemplary micro-integrated circuit 702). However, this keyExchangeServer() function is not a standard C function. In this function, the first processor 710-1 of the server's computer (here, the exemplary micro-integrated circuit 702) generates 728 quantum random numbers using a quantum random number generator. The quantum random number preferably has a bit width n.Here, n is a positive integer, including zero. These random numbers from the quantum random number generator 728 of the computer (here, the exemplary microintegrated circuit 702) of the server serve, in the example presented in this document, as indices for a look-up table of the first 2n prime numbers. This look-up table is preferably located in one of the memories of the computer (here, the exemplary microintegrated circuit 702) or in a memory of subdevices of the computer (here, the exemplary microintegrated circuit 702) of the server. The first processor 710-1 of the computer (here the exemplary microintegrated circuit 702) of the server then reads the prime number corresponding to this index of the quantum random number of the quantum random number generator 728 of the computer (here the exemplary microintegrated circuit 702) from the memory of the computer (here the exemplary microintegrated circuit 702) of the server.Using these prime numbers, the first processor 710-1 of the computer (here the exemplary micro-integrated circuit 702) server generates both a public and a private key according to the aforementioned RSA encryption method.

[0197] The first processor 710-1 of the computer (here of the exemplary micro-integrated circuit 702) then transmits a public key to the first processor 710-1 of the computer (here of the exemplary micro-integrated circuit 702) of the client, for example via a data interface of the computer (here of the exemplary micro-integrated circuit 702) of the server, and a data bus and a data interface of the computer (here of the exemplary micro-integrated circuit 702) of the client.

[0198] The first processor 710-1 of the server's computer (here, the exemplary microintegrated circuit 702) then waits for a message from the first processor 710-1 of the client's computer (here, the exemplary microintegrated circuit 702) via the client's computer's data interface (here, the exemplary microintegrated circuit 702) and the data bus and the data interface of the first processor 710-1 of the server's computer (here, the exemplary microintegrated circuit 702). Preferably, this message from the first processor 710-1 of the client's computer (here, the exemplary microintegrated circuit 702) includes a public key of the first processor 710-1 of the client's computer (here, the exemplary microintegrated circuit 702).Thus, first processor 710-1 of the client's computer (here, the exemplary microintegrated circuit 702) typically transmits the private key of the client's first processor 710-1 of the client's computer (here, the exemplary microintegrated circuit 702) to the server's first processor 710-1 of the server's computer (here, the exemplary microintegrated circuit 702) via the client's computer's data interface (here, the exemplary microintegrated circuit 702) and the server's computer's data bus and data interface (here, the exemplary microintegrated circuit 702).If the first processor 710-1 of the computer (here the exemplary micro-integrated circuit 702) of the server has received the public key of the first processor 710-1 of the computer (here the exemplary micro-integrated circuit 702) of the client, the first processor 710-1 of the computer (here the exemplary micro-integrated circuit 702) of the server stores this public key in a memory of the computer (here the exemplary micro-integrated circuit 702) of the server.

[0199] The first processor 710-1 of the server's computer (here, the exemplary micro-integrated circuit 702) then sends, for example, its public key via its data bus interface and the data bus and the data bus interface of the client's computer (here, the exemplary micro-integrated circuit 702) to the client's first processor 710-1 of the client's computer (here, the exemplary micro-integrated circuit 702).

[0200] Thus, the server is typically prepared for the exchange of encrypted data between the first processor 710-1 of the computer (here the exemplary micro-integrated circuit 702) of the client and the first processor 710-1 of the computer (here the exemplary micro-integrated circuit 702) of the server.

[0201] After the keys have been exchanged, the first processor 710-1 of the server's computer (here, the exemplary microintegrated circuit 702) preferably executes the recv() function 3050 and waits for an encrypted message from the first processor 710-1 of the client's computer (here, the exemplary microintegrated circuit 702). If the first processor 710-1 of the server's computer (here, the exemplary microintegrated circuit 702) receives a message, the first processor 710-1 of the server's computer (here, the exemplary microintegrated circuit 702) preferably first stores this encrypted message in a temporary buffer of the server's computer (here, the exemplary microintegrated circuit 702). For the purposes of this document, the recv() function is preferably a standard C function of the standard C library socket. h.The recv() function typically reads incoming data from a socket descriptor, in this case, the socket descriptor of the first processor 710-1 of the client's computer (here, the exemplary microintegrated circuit 702) from step 3030 of the method. The recv() function, which the first processor 710-1 of the server's computer (here, the exemplary microintegrated circuit 702) typically executes, typically stores the received data in the temporary cache of the server's computer (here, the exemplary microintegrated circuit 2).

[0202] If the first processor 710-1 of the server's computer (here, the exemplary microintegrated circuit 702) has received an encrypted message in this way, the first processor 710-1 of the server's computer (here, the exemplary microintegrated circuit 702) preferably executes the Decrypt() function 3060 in a further step 3060. This Decrypt() function is not a standard C function. In this step 3060, the DecryptQ function, as defined in the document presented here, decrypts the message of the server's private key from step 3040 according to the RSA method using the server's private key temporarily stored in the memory of the computer (here, the exemplary microintegrated circuit 702).As a result, the first processor 710-1 of the server's computer (here, the exemplary microintegrated circuit 702) decrypts the received encrypted message from the client using the private key from step 3040, which is temporarily stored in the memory of the server's computer (here, the exemplary microintegrated circuit 702), according to the RSA method. The first processor 710-1 of the server's computer (here, the exemplary microintegrated circuit 702) preferably stores the then decrypted message in a temporary buffer of the server's computer (here, the exemplary microintegrated circuit 702).

[0203] If the first processor 710-1 of the server's computer (here, the exemplary micro-integrated circuit 702) does not receive a message from the first processor 710-1 of the client's computer (here, the exemplary micro-integrated circuit 702) within a predetermined period of time, the first processor 710-1 of the server's computer (here, the exemplary micro-integrated circuit 702) jumps to the step now described. The first processor 710-1 of the server's computer (here, the exemplary micro-integrated circuit 702) checks whether a message should be sent to the first processor 710-1 of the client's computer (here, the exemplary micro-integrated circuit 702). Typically, such a message is stored in a memory of the server's computer (here, the exemplary micro-integrated circuit 702) for transmission in such a case.If necessary, the first processor 710-1 of the server's computer (here, the exemplary microintegrated circuit 702) can also retrieve or receive such a message from another memory or system before sending it. Preferably, the first processor 710-1 of the server's computer (here, the exemplary microintegrated circuit 702) then temporarily stores such a message in a buffer of the server's computer (here, the exemplary microintegrated circuit 702). If such a message to be sent is pending in a memory or buffer of the server's computer (here, the exemplary microintegrated circuit 702), the first processor 710-1 of the server's computer (here, the exemplary microintegrated circuit 702) preferably executes the Encrypt() function in a further step 3070.In this step 3070, the first processor 710-1 of the server's computer (here, the exemplary microintegrated circuit 702) encrypts its own message using the client's public key from 3040 according to the RSA algorithm. This Encrypt() function is not a standard C function. The server stores its now encrypted message in a temporary buffer of the server's computer (here, the exemplary microintegrated circuit 702).

[0204] The first processor 710-1 of the server's computer (here, the exemplary micro-integrated circuit 702) now executes the send() function in a step 3080. In step 3080, the first processor 710-1 of the server's computer (here, the exemplary micro-integrated circuit 702) sends its encrypted message, stored in the buffer memory of the computer (here, the exemplary micro-integrated circuit 702), to the first processor 710-1 of the client's computer (here, the exemplary micro-integrated circuit 702) via the data bus interface of the first processor 710-1 of the server's computer (here, the exemplary micro-integrated circuit 702) and via the data bus and the data interface of the first processor 710-1 of the computer (here, the exemplary micro-integrated circuit 702).For the purposes of this document, the send() function is a standard C function from the socket standard C library. The send() function sends data via a socket descriptor, in this case the client's socket descriptor from step 3030. The typical cycle ends with the end of the transfer.

[0205] Thereafter, the encrypted communication for the first processor 710-1 of the computer (here the exemplary microintegrated circuit 702) of the server starts again at step 3040.

[0206] If the communication is terminated by the first processor 710-1 of the computer (here, the exemplary micro-integrated circuit 702) of the server or the first processor 710-1 of the computer (here, the exemplary micro-integrated circuit 702) of the client, the first processor 710-1 of the computer (here, the exemplary micro-integrated circuit 702) of the server executes the close() function 3090. The close() function is a standard C function of the standard C library socket.h. By executing the close() function, the first processor 710-1 of the computer (here, the exemplary micro-integrated circuit 702) of the server closes the open connection to a socket, here, the client's socket, and thus terminates the communication.

[0207] In an analogous manner, the first processor 710-1 of the computer (here the exemplary microintegrated circuit 702) of the client executes a client process.

[0208] At the beginning of the "client process," the first processor 710-1 of the client's computer (here, the exemplary micro-integrated circuit 702) creates a socket descriptor in step 3100. A socket descriptor, as defined in this document, is again an integer similar to a file handle, which, for example, the standard C library function socket() of the socket.h library can use, which the first processor 710-1 of the client's computer (here, the exemplary micro-integrated circuit 702) can use in later function calls that utilize sockets. The first processor 710-1 of the client's computer (here, the exemplary micro-integrated circuit 702) sends a connection request to the first processor 710-1 of the server's computer (here, the exemplary micro-integrated circuit 702) using the port and IP address specified in step 3010.

[0209] To do this, the first processor 710-1 of the client's computer (here, the exemplary microintegrated circuit 702) preferably executes the standard C function connect() of the standard C library socket.h. This function establishes a connection between the server socket from step 3010 and the client socket from step 3100.

[0210] If the connection was accepted by the first processor 710-1 of the server's computer (here, the exemplary microintegrated circuit 702) according to step 3030, the first processor 710-1 of the client's computer (here, the exemplary microintegrated circuit 702) executes the KeyExchangeClient() function in a step 3120. This function is not a standard C function. By executing this function, the first processor 710-1 of the client's computer (here, the exemplary microintegrated circuit 702) generates one or more quantum random numbers using the quantum random number generator 728. This quantum random number has a bit width n. Here, n is a positive integer, including zero. These random numbers of the quantum random generator 728 of the client's computer (here the exemplary microintegrated circuit 702) preferably serve as indices for a look-up table of the first 2n prime numbers.Using these prime numbers or other prime numbers, the first processor 710-1 of the client's computer (here, the exemplary microintegrated circuit 702) generates both a public and private key according to RSA encryption. The first processor 710-1 of the client's computer (here, the exemplary microintegrated circuit 702) preferably stores its thus-generated public key and its thus-generated private key in a memory of the client's computer (here, the exemplary microintegrated circuit 702).The first processor 710-1 of the client's computer (here, the exemplary microintegrated circuit 702) then sends its public key to the first processor 710-1 of the server's computer (here, the exemplary microintegrated circuit 702) via the data interface of the client's computer (here, the exemplary microintegrated circuit 702) and via the data bus and the data interface of the server's computer (here, the exemplary microintegrated circuit 702). The first processor 710-1 of the client's computer (here, the exemplary microintegrated circuit 702) then waits for a message from the first processor 710-1 of the server's computer (here, the exemplary microintegrated circuit 702).This message from the first processor 710-1 of the computer (here the exemplary micro-integrated circuit 702) of the server typically contains the public key of the first processor 710-1 of the computer (here the exemplary micro-integrated circuit 702) of the server.

[0211] Subsequently, the first processor 710-1 of the client's computer (here, the exemplary micro-integrated circuit 702) executes the Encrypt() function 3130. By executing the Encrypt() function in step 3130, the first processor 710-1 of the client's computer (here, the exemplary micro-integrated circuit 702) encrypts its own message using the public key of the first processor 710-1 of the server's computer (here, the exemplary micro-integrated circuit 702) from step 3040 using the RSA method. This function is not a standard C function. The client stores the encrypted message in a temporary buffer.

[0212] The first processor 710-1 of the client's computer (here, the exemplary micro-integrated circuit 702) now executes the send() function in step 3140 and sends its encrypted message to the first processor 710-1 of the server's computer (here, the exemplary micro-integrated circuit 702). For the purposes of this document, the send() function is a standard C function of the standard C library socket.h. By executing the send() function, the first processor 710-1 of the client's computer (here, the exemplary micro-integrated circuit 702) sends data via a socket descriptor, in this case, the client's socket descriptor from 3100.

[0213] The first processor 710-1 of the client's computer (here, the exemplary microintegrated circuit 702) then executes the recv() function 3150. In step 3150, the first processor 710-1 of the client's computer (here, the exemplary microintegrated circuit 702) waits for an encrypted message from the first processor 710-1 of the server's computer (here, the exemplary microintegrated circuit 702). If the first processor 710-1 of the client's computer (here, the exemplary microintegrated circuit 702) receives a message, the first processor 710-1 of the client's computer (here, the exemplary microintegrated circuit 702) stores this received and typically encrypted message in a temporary buffer. For the purposes of this document, the recv() function is preferably a standard C function from the standard C library socket.h.The first processor 710-1 of the client's computer (here, the exemplary microintegrated circuit 702) reads incoming data from a socket descriptor, in this case from the socket descriptor of the first processor 710-1 of the client's computer (here, the exemplary microintegrated circuit 702) from step 3100, by executing the recv() function. The first processor 710-1 of the client's computer (here, the exemplary microintegrated circuit 702) preferably stores the read data in a temporary buffer of the client's computer (here, the exemplary microintegrated circuit 702).

[0214] If the first processor 710-1 of the client's computer (here, the exemplary micro-integrated circuit 702) has received an encrypted message in this way, the first processor 710-1 of the client's computer (here, the exemplary micro-integrated circuit 702) preferably executes the Decrypt() function in a step 3160. This DeCrypt() function is not a standard C function.The first processor 710-1 of the client's computer (here, the exemplary micro-integrated circuit 702) decrypts an encrypted message from the first processor 710-1 of the server's computer (here, the exemplary micro-integrated circuit 702) received by the first processor 710-1 of the client's computer (here, the exemplary micro-integrated circuit 702) by executing the Decrypt() function, using the private key of the first processor 710-1 of the client's computer (here, the exemplary micro-integrated circuit 702) from step 3120 using the RSA method. The first processor 710-1 of the client's computer (here the exemplary micro-integrated circuit 702) then stores the decrypted message in a temporary buffer of the client's computer (here the exemplary micro-integrated circuit 702).

[0215] Thereafter, communication between the first processor 710-1 of the computer (here the exemplary micro-integrated circuit 702) of the server and the first processor 710-1 of the computer (here the exemplary micro-integrated circuit 702) of the client starts again at step 3120.

[0216] If the communication is terminated by the first processor 710-1 of the client's computer (here, the exemplary micro-integrated circuit 702) or the first processor 710-1 of the server's computer (here, the exemplary micro-integrated circuit 702), the first processor 710-1 of the client's computer (here, the exemplary micro-integrated circuit 702) executes the close() function in step 3170. The close() function is a standard C function of the standard C library socket.h.By the first processor 710-1 of the computer (here the exemplary micro-integrated circuit 702) of the client executing the close() function, the first processor 710-1 of the computer (here the exemplary micro-integrated circuit 702) of the client closes the open connection to a socket and thus terminates the communication with the first processor 710-1 of the computer (here the exemplary micro-integrated circuit 702) of the server.

[0217] Figure 18 shows an exemplary schematic sequence of the functions KeyExchangeServer() and KeyExchangeClient(). When starting the KeyExchangeServer() function, the first processor 710-1 of the server's computer (here, the exemplary microintegrated circuit 702) first calls the setPrimes() function in step 3200. This KeyExchangeServer() function is not a standard C function. The first processor 710-1 of the server's computer (here, the exemplary microintegrated circuit 702) uses the KeyExchangeServer() function to generate two different prime numbers p and q, the product n=p*q, and the Euler phi function phi = (p-1)(q-1) in step 3200.

[0218] The first processor 710-1 of the server's computer (here, the exemplary micro-integrated circuit 702) then calls the setE() function in step 3210. This setE() function in step 3210 is not a standard C function. When calling the setE() function in step 3210, the first processor 710-1 of the server's computer (here, the exemplary micro-integrated circuit 702) generates a number e that is coprime to phi, where the number phi is the number from step 3200. Coprime in the sense of this document means that there is no natural number other than one that simultaneously divides the number e and phi.

[0219] Subsequently, the first processor 710-1 of the server's computer (here, the exemplary microintegrated circuit 702) executes the findD() function in step 3220. This findD() function is not a standard C function. The first processor 710-1 of the server's computer (here, the exemplary microintegrated circuit 702) uses the findD() function to calculate the multiplicative inverse of e, such that (e*d) mod phi = 1.

[0220] The first processor 710-1 of the server's computer (here, the exemplary micro-integrated circuit 702) now calls the recv() function in step 3230. The first processor 710-1 of the server's computer (here, the exemplary micro-integrated circuit 702) now waits for an incoming message from the first processor 710-1 of the client's computer (here, the exemplary micro-integrated circuit 702), which should typically include the client's public key. For the purposes of this document, the recv() function is a standard C function of the standard C library socket.h. By calling the recv() function, the first processor 710-1 of the server's computer (here, the exemplary micro-integrated circuit 702) reads the incoming data from a socket descriptor, in this case, the client's socket descriptor.The first processor 710-1 of the computer (here the exemplary micro-integrated circuit 702) of the server preferably stores the read data in a temporary buffer of the computer (here the exemplary micro-integrated circuit 702).

[0221] Now, the first processor 710-1 of the server's computer (here, the exemplary micro-integrated circuit 702) calls the send() function in step 3240. In this step 3240, the first processor 710-1 of the server's computer (here, the exemplary micro-integrated circuit 702) sends its public key (d,n) from steps 3200 and 3220 to the first processor 710-1 of the client's computer (here, the exemplary micro-integrated circuit 702). For the purposes of this document, the send() function is a standard C function of the standard C library socket.h. The first processor 710-1 of the server's computer (here the exemplary microintegrated circuit 702) sends data via a socket descriptor, in this case the client's socket descriptor from step 3030, using the send() function.

[0222] Subsequently, the first processor 710-1 of the computer (here the exemplary microintegrated circuit 702) of the server leaves the KeyExchangeServer() function in step 3245.

[0223] When starting the KeyExchangeClient() function, the first processor 710-1 of the client's computer (here, the exemplary micro-integrated circuit 702) first calls the setPrimes() function in step 3250. This function is not a standard C function. The first processor 710-1 of the client's computer (here, the exemplary micro-integrated circuit 702) generates the prime number p and the prime number q different from q using the KexExchangeClientQ function. The first processor 710-1 of the client's computer (here, the exemplary micro-integrated circuit 2) generates the product n=p*q using the KexExchangeClient() function. The first processor 710-1 of the computer (here the exemplary microintegrated circuit 702) of the client generates the Euler Phi function phi = (p-1)(q-1) using the function KexExchangeClient().

[0224] The first processor 710-1 of the client's computer (here, the exemplary microintegrated circuit 702) then calls the setE() function in step 3260. This function is not a standard C function. The first processor 710-1 of the client's computer (here, the exemplary microintegrated circuit 702) uses the setE() function to generate an integer e that is coprime to the number phi from step 3250. Coprime, as defined in this document, means that there is no natural number other than one that simultaneously divides the number e and phi without a remainder.

[0225] The first processor 710-1 of the client's computer (here, the exemplary microintegrated circuit 702) then calls the findD() function 3270. This function is not a standard C function. The first processor 710-1 of the client's computer (here, the exemplary microintegrated circuit 702) uses the findD() function to calculate the multiplicative inverse of the number e, such that (e*d) mod phi = 1.

[0226] The first processor 710-1 of the client's computer (here, the exemplary micro-integrated circuit 702) now calls the send() function 3280 and sends its public key (d,n) from steps 3250 and 3270 to the first processor 710-1 of the server's computer (here, the exemplary micro-integrated circuit 702). For the purposes of this document, the send() function is a standard C function of the standard C library socket. The first processor 710-1 of the client's computer (here, the exemplary micro-integrated circuit 702) uses the send() function to send data via a socket descriptor, in this case, the client's socket descriptor from step 3100.

[0227] The first processor 710-1 of the client's computer (here, the exemplary micro-integrated circuit 702) now calls the recv() function in step 3290. The first processor 710-1 of the client's computer (here, the exemplary micro-integrated circuit 702) now waits for an incoming message from the first processor 710-1 of the server's computer (here, the exemplary micro-integrated circuit 702) containing the public key of the first processor 710-1 of the server's computer (here, the exemplary micro-integrated circuit 702). For the purposes of this document, the recv() function is a standard C function of the standard C library socket.h.The first processor 710-1 of the client's computer (here, the exemplary micro-integrated circuit 702) uses the recv() function to read incoming data from the first processor 710-1 of the server's computer (here, the exemplary micro-integrated circuit 702) from a socket descriptor, in this case, from the client's socket descriptor from step 3100, and stores the data in a temporary buffer of the client's computer (here, the exemplary micro-integrated circuit 702).

[0228] Subsequently, the first processor 710-1 of the client's computer (here the exemplary microintegrated circuit 702) exits the KeyExchangeClient() function in step 3295.

[0229] Figure 19 shows an exemplary schematic flow of the setPrimes() function. The first processor 710-1 of the client's computer (here, the exemplary microintegrated circuit 702) and the first processor 710-1 of the server's computer (here, the exemplary microintegrated circuit 702) each call this function at the appropriate time. If one of these first processors 710-1 calls the function setPrimes(), the calling processor 710-1, in the case of the present document the first processor 710-1 of the computer (here the exemplary microintegrated circuit 702) of the server or the first processor 710-1 of the computer (here the exemplary microintegrated circuit 702) of the client, generates a quantum random number by means of a quantum random number generator 728 in step 3300. This quantum random number has a bit width n. Here, n is a positive integer including zero.These quantum random numbers can serve as indices for a look-up table of the first 2n prime numbers. The calling first processor 710-1 stores the prime number indexed by the quantum random number as variable p.

[0230] The calling first processor 710-1 then generates another quantum random number in step 3310 with the preferred bit width n using the quantum random generator 728. These quantum random numbers preferably serve the calling first processor 710-1 again as indices for a look-up table of the first 2n prime numbers. The calling first processor 710-1 stores the prime number, which is indexed by the random number, as a variable q in a buffer of the computer (here, the exemplary microintegrated circuit 702), of which the first processor 710-1 is preferably a part. The calling first processor 710-1 then checks in step 3320 whether the logical statement q == p holds. If this statement holds, step 3310 is repeated. Subsequently, the calling processor 710-1 calculates the product n = p * q in step 3330. After that, the calling processor 710-1 calculates the Euler phi function phi = (q-1) * (p-1) in step 3340.The calling processor 710-1 then exits the setPrimes() function in step 3350.

[0231] Figure 20 shows an exemplary schematic flow of the setE() function. When calling the setE() function in step 3400, the caller—in the case of the present document, the first processor 710-1 of the server's computer (here, the exemplary microintegrated circuit 702) or the first processor 710-1 of the client's computer (here, the exemplary microintegrated circuit 702)—generates a random number e that is coprime to the number phi. Coprime, in the sense of the present document, means that there is no natural number other than one that simultaneously divides the number e and phi. The calling processor 710-1 can generate the number e using a random number from the quantum random number generator 728, a pseudorandom number generator, or by iterating an integer number starting with 2. However, generation using the quantum random generator 728 QRNG is preferred.

[0232] The calling processor 710-1 then checks in step 3410 whether the logical statement gcd(e, phi) ! = 1 is true. If the logical statement is true, the calling processor 710-1 repeats step 3400. If the logical statement is not true, the calling processor 710-1 exits the setE() function and returns the current value of e to the calling processor 710-1. The gcd(a,b) function is not a standard C function. The calling processor 710-1 uses this gcd(a,b) function to calculate the greatest common divisor of the passed parameters a, b and returns the result to the calling processor 710-1.

[0233] Figure 21 shows an exemplary schematic flow of the findD() function. When the calling processor 710-1 calls the findD() function in step 3500, the calling processor 710-1 initializes a variable d with 0 in step 3500. In the subsequent step 3510, the calling processor 710-1 adds the number 1 to the number d. Then, in step 3520, the calling processor 710-1 checks whether the logical statement (e*d) (mod phi) == 1 is true. If the logical statement (e*d) (mod phi) == 1 is not true, the calling processor repeats the steps from step 3510.If the logical statement (e*d) (mod phi) == 1 is fulfilled, then in step 3530 the calling processor 710-1 leaves the function findDQ and the calling processor 710-1 returns the current value of d to the calling processor 710-1, in the case of the present document the first processor 710-1 of the computer (here the exemplary micro-integrated circuit 702) of the server or the first processor 710-1 of the computer (here the exemplary micro-integrated circuit 702) of the client.

[0234] Figure 22 shows an exemplary schematic sequence of a secure transmission of quantum-based random numbers between a first processor 10-1 of the computer, in particular in the form of an integrated circuit, of a server 3600, and a first processor 10-1 of the computer, in particular in the form of a further integrated circuit of a client 3610.

[0235] In the case of the present document, the server 3600 is, for example, a first processor 710-1 of a first computer (here, the exemplary microintegrated circuit 702), wherein the computer (here, the exemplary microintegrated circuit 702) of this server 3600 has a quantum random number generator 728. In the case of the present document, the client 3610 is, for example, another first processor 710-1 of a second computer, wherein this computer (here, the exemplary microintegrated circuit 702) of the client 3610 is not intended to have a quantum random number generator 728.

[0236] Initially, the first processor 710-1 of the computer (here, the exemplary microintegrated circuit 702) of the server 3600 generates quantum random numbers QZ1. The quantum random numbers QZ1 serve as the basis for the first processor 710-1 of the computer (here, the exemplary microintegrated circuit 702) of the server 3600 to generate a private and a public key of the server 3600 according to an asymmetric encryption method. The asymmetric encryption method can be, for example, the RSA method.

[0237] In a step 3620, the first processor 710-1 of the computer (here of the exemplary micro-integrated circuit 702) of the server 3600 sends the public key of the server 3600 via a non-tapping-secure channel to the first processor 710-1 of the computer (here of the exemplary micro-integrated circuit 702) of the client 3610. Subsequently, the first processor 710-1 of the computer (here of the exemplary micro-integrated circuit 702) of the client 3610 generates a pseudo-random number PZ or another random number. The first processor 710-1 of the computer (here the exemplary microintegrated circuit 702) of the client 3610 stores the pseudorandom number PZ or the otherwise generated random number in a memory of the computer (here the exemplary microintegrated circuit 702) of the client 3610.The first processor 710-1 of the computer (here the exemplary microintegrated circuit 702) of the client 3610 generates a first private key of the client 3610 and a first public key of the client 3610 using this pseudorandom number PZ or this otherwise generated random number.

[0238] The first processor 710-1 of the computer (here, the exemplary microintegrated circuit 702) of the client 3610 encrypts the first public key of the client 3610 using the public key of the server 3600. The first processor 710-1 of the computer (here, the exemplary microintegrated circuit 702) of the client 3610 then sends the encrypted first public key of the client 3610 to the first processor 710-1 of the computer (here, the exemplary microintegrated circuit 702) of the server 3600.

[0239] The first processor 710-1 of the computer (here, the exemplary microintegrated circuit 702) of the server 3600 now decrypts this message with its first private key. As a result, the first processor 710-1 of the computer (here, the exemplary microintegrated circuit 702) of the server 3600 now has the first public key of the client 3610, without it being known to third parties.

[0240] Subsequently, the first processor 710-1 of the computer (here, the exemplary microintegrated circuit 702) of the server 3600 generates a further, second quantum random number QZ2 using the quantum random number generator 728. The bit width of this second quantum random number is preferably equal to the bit width of the random number PZ of the client 3610.

[0241] The first processor 710-1 of the computer (here, the exemplary microintegrated circuit 702) of the server 3600 now encrypts the second quantum random number QZ2 with the first public key of the client 3610. For example, the first public key of the client 3610 can be the client's. In this case, the first processor 710-1 of the computer (here, the exemplary microintegrated circuit 702) of the server 3600 can encrypt the second quantum random number QZ2, for example, by bitwise XORing the second quantum random number QZ2 with PZ to form an encrypted second quantum random number QZ2'. The first processor 710-1 of the computer (here the exemplary micro-integrated circuit 702) of the server 3600 then preferably sends the encrypted second quantum random number QZ2' to the first processor 710-1 of the computer (here the exemplary micro-integrated circuit 702) of the client 3610 in a step 3640.

[0242] The first processor 710-1 of the computer (here, the exemplary microintegrated circuit 702) of the client 3610 decrypts the encrypted second quantum random number QZ2' using its first private key to form the second quantum random number QZ2. If the first processor 710-1 of the computer (here, the exemplary microintegrated circuit 702) has determined the second encrypted quantum random number QZ2' by bitwise XORing the random number PZ with the second quantum random number QZ2, the first processor 710-1 of the computer (here, the exemplary microintegrated circuit 702) of the client 3610 can decrypt the encrypted second quantum random number QZ2', for example, by bitwise XORing the encrypted second quantum random number QZ2' with the random number PZ known to it to form the second quantum random number QZ2.

[0243] Preferably, the first processor 710-1 of the computer (here, the exemplary microintegrated circuit 702) of the client 3610 uses the second quantum random number QZ2 now available to it as the basis for generating a second private key and a second public key according to an asymmetric encryption method. The asymmetric encryption method can be, for example, the RSA method (APPENDIX). The first processor 710-1 of the computer (here, the exemplary microintegrated circuit 702) of the client 3610 now sends its second public key to the server 3600 via the non-tap-secure channel. In doing so, it preferably encrypts this second public key of the client 3610 with the public key of the server 3600.The server 3600 decrypts the encrypted second public key of the client 3610 and then uses this second client public key to encrypt further messages to the first processor 710-1 of the computer (here the exemplary microintegrated circuit 702) of the client 3610.

[0244] Preferably, after a predetermined time or after sending a predetermined amount of data, the first processor 10-1 of the computer (here of the exemplary microintegrated circuit 702) of the server 3600 generates and sends to the processor 710-1 of the computer (here of the exemplary microintegrated circuit 702) of the client 3610 a new public key based on a new quantum random number of its quantum random number generator 728, encrypted with the second public key of the client 3610. Preferably, the first processor 710-1 of the computer (here of the exemplary microintegrated circuit 702) of the server 3600 and the first processor 710-1 of the computer (here of the exemplary microintegrated circuit 702) of the client then perform the previously described method again, so that the keys change permanently. This makes it impossible for even a quantum computer to break the keys.

[0245] This means that after exchanging these keys, communication can be carried out based on the selected asymmetric encryption method.

[0246] Figure 23 schematically shows an exemplary method 3700 for generating a quantum random number. The method 3700 begins, for example, with the generation 3710 of a random single-photon stream using one or more photon sources, or one or more silicon LEDs, or one or more first SPAD diodes, which are preferably integrally manufactured in a semiconductor material.

[0247] The method 3700 continues with the transmission 3720 of the random single photon stream, for example by means of an optical waveguide different from the semiconductor substrate or by means of the semiconductor substrate as an optical waveguide or by means of direct irradiation to one or more photon detectors or one or more SPAD diodes.

[0248] This is followed in the method 3700 by the conversion 3730 of the random single-photon stream (into a detection signal in the form of a voltage signal 405 of the entropy source 401, which preferably comprises the photon sources or the silicon LEDs or the first SPAD diodes and the optical system for optical coupling and the photon detectors or the second SPAD diodes. In particular, the entropy source 401 can comprise a photon source and a single-photon detector of an iQRNG according to the invention. The optical system can comprise a direct optical coupling of these components and / or comprise an optical waveguide.

[0249] Then, in the method 3700, the processing 3740, in particular an amplification and / or a filtering and / or an analog-to-digital conversion, of the detection signal into a processed detection signal, in particular a digital 14-bit value as output signal 407 of the ADC 403 or a 1-bit analog-to-digital converter, follows.

[0250] Then, in method 3700, the pulses of the conditioned detection signal generated by optical coupling, for example, the emissions of a photon source or a silicon LED or a first SPAD diode on the one hand, and a photon detector or a second SPAD diode on the other hand, are optionally separated 3750 from the pulses of the conditioned detection signal generated by spontaneous emission by comparing the conditioned detection signal with a threshold value, in particular in a comparator, and generating a corresponding output signal, in particular from the comparator. Optionally, the ADC 403 can generate said output signal directly if it is a 1-bit analog-to-digital converter 403. In this respect, this step 3750 is optional and is therefore only shown in dashed lines.

[0251] This is followed by the determination 3760 of a first pseudorandom number as a function of a first time interval between the first pulse and the second pulse of a first pair of two successive pulses of the conditioned detection signal, which pulses are generated by optical couplings, for example, of the emissions of a photon source or a silicon LED or a first SPAD diode on the one hand and a photon detector or a second SPAD diode on the other hand, as the first value of the output of the time-to-pseudorandom number converter 404.3.

[0252] This is followed by the determination of 3765 second first pseudorandom number as a function of a second time interval between the third pulse and the fourth pulse of a second pair of two successive pulses of the conditioned detection signal, which pulses are generated by optical couplings, for example, of the emissions of a photon source or a silicon LED or a first SPAD diode 54 on the one hand and a photon detector or a second SPAD diode on the other hand, as the second value of the output 410 of the time-to-pseudorandom number converter 404.3.

[0253] On this basis, the bit value of a quantum random bit is then determined 3670 at the output 411 of the entropy extraction 404.4 by comparing the value of the first pseudorandom number and the value of the second pseudorandom number.

[0254] In a final check 3680, the first processor 710-1 of the computer (here, the exemplary microintegrated circuit 702) and / or a finite-state machine 404.8 check whether the number n of determined random bits is still smaller than the desired number m of random bits of the desired quantum random number. If this is not the case, the first processor 710-1 of the computer (here, the exemplary microintegrated circuit 702) and / or the finite-state machine 404.8 repeat the above steps 3710 to 3770. Otherwise, the processor 710-1 of the computer (here, the exemplary microintegrated circuit 702) or the finite-state machine 404.8 terminates the process for generating a quantum random number. If necessary, the finite state machine 404.8 makes the quantum random number available to processor 710-1 and preferably signals this availability to processor 710-1, for example, by interrupting via an interrupt signal 420 or by setting a flag. Preferably, processor 710-1 and / or finite state machine 404.8 control this process of generating a quantum random number.

[0255] Figure 24 shows an embodiment of a time-to-pseudorandom number converter 404.3. The key idea here is to use a pseudorandom number generator 404.3 in the quantum random number generator 728 instead of a digital counter as in the prior art, which generates the first and second values ​​for the entropy extraction 404.4. Regarding the corresponding process, reference is made to the preceding FIG. 23. The advantage is that even if a disturbance is successfully introduced into the synchronized voltage signal 415, the randomness of the quantum random bit at the output 411 of the entropy extraction 404.4 is only marginally disturbed, since the attacker would also have to know the feedback polynomial. However, this is also randomly selected according to the proposal. The same applies to the seed value of the pseudorandom number generator 404.3, which the attacker would also have to determine. This is another advantage of a pseudorandom number generator 404.3 instead of a counter is the smaller area requirement of the feedback logic of a simple primitive feedback polynomial compared to a binary counter. If the linear feedback shift register of the pseudorandom number generator 404.3 is long enough, each clock pulse between two pulses of the voltage signal 405 of the entropy source 401 is typically assigned a unique pseudorandom number. Preferably, the shift register controller 2103 of the time-to-pseudorandom number converter 404.3 starts the generation of a pseudorandom number by the shift register of the time-to-pseudorandom number converter 404.3 with a first pulse on the voltage signal 405 of the entropy source 401 and ends the generation of the pseudorandom number with a subsequent second pulse on the voltage signal 405 of the entropy source 401.

[0256] To further complicate tapping, it is useful, for example, for the quantum random number generator 728 to change the feedback polynomial of the linearly feedback shift register of the pseudorandom number generator of the time-to-pseudorandom number converter 404.3 after the complete determination of a number m of random quantum bits at output 411, depending on one or more previously determined random quantum bits at output 411. For example, the following simple primitive feedback polynomials are known from the literature:

[0257] As can easily be seen, the number of XNOR operations is very limited, which makes the linear feedback shift registers very fast. The longest chain listed has a length of 2 168 -1 clocks with a shift register length of n=168 shift register bits. At a GHz=10 9 Hz lasts a period 2 159 seconds or otherwise approx. 2 153 minutes or otherwise about 2147 hours or otherwise approx. 2 142 Days or otherwise (very roughly) about 2 131 Years. Obviously, it takes too long to solve the problem in finite time with a normal computer. Especially when combined with a permanent quantum random number key change, it makes it almost impossible for an attacker to break the corresponding barrier.

[0258] To prevent the protection of the quantum random number generator 728 from being breached, it is also useful if, for example, the quantum random number generator 728 changes the shift register length n of the linear feedback shift register of the pseudorandom number generator of the time-to-pseudorandom number converter 404.3 after the complete determination of a number k of random quantum bits at the output 411, depending on one or more previously determined random bits. For this purpose, it is useful if the shift register controller 2103 of the time-to-pseudorandom number converter 404.3 or a processor (710-1, 710-2) rewrites the value of the feedback polynomial selection register 2112 for this purpose. The value stored in the feedback polynomial selection register 2112 preferably controls the feedback multiplexer 2102 of the time-to-pseudorandom number converter 404.3.

[0259] Thus, the value stored in the feedback polynomial selection register 2112 preferentially selects which feedback polynomial of the m feedback polynomial circuits RKNi to RKNm determines the logical value of the shift register reload value line 2104 of the time-to-pseudorandom number converter 404.3. Preferably, by means of a line 2022 for preventing the use of a quantum random bit at the output 411 by the finite state machine (finite automaton) 404.8, the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 or one of the processors (710-1, 710-2) or another device prevents the forwarding of a generated quantum random bit at the output 411 by the finite state machine (finite automaton) 404.8 when this random bit at the output 411 is used for the feedback polynomial selection register 2112. This prevents

[0260] Dual use, thus increasing security. Instead, the shift register controller 2103 of the time-to-pseudorandom number converter 404.3 (TPRC) or the processor (10-1, 10-2) or the other device preferably uses this random bit at output 411 to generate a random data word for storage in the feedback polynomial selection register 2112. This has the advantage that the feedback polynomial of the m feedback polynomial circuits RKNi to RKNm selected by the feedback polynomial selection register 2112 is completely random. This makes it impossible for an attacker to feed a deterministic bit data stream instead of the data bit stream of the quantum random bits at output 411, even if an attack on the entropy source 401 is successful.

[0261] To further harden the proposed microintegrated quantum random number generator 728, it is also useful if, for example, the quantum random number generator 728 changes the starting value (seed value) of the linear feedback shift register of the pseudorandom number generator of the time-to-pseudorandom number converter 404.3 after the complete determination of a number p of random quantum bits at output 411, depending on one or more previously determined random bits. For this purpose, it is useful if the shift register controller 2103 of the time-to-pseudorandom number converter 404.3 or a processor (710-1, 710-2) rewrites the value of a seed reload register in the shift register controller 2103 of the time-to-pseudorandom number converter 404.3 with random bits for this purpose. The bit width of the seed reload register in the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 preferably corresponds to the number n of the shift register bits SBi to SB nof the time-to-pseudo-random number converter 404.3. The shift register controller 2103 of the time-to-pseudo-random number converter 404.3 preferably counts the number of successfully generated quantum random bits at output 411. For this purpose, the finite-state machine 404.8 preferably signals the generation of a valid random bit to the shift register controller 2103 of the time-to-pseudo-random number converter 404.3. Instead of counting the valid quantum random bits at output 411, the finite-state machine 404.8 can also count the successfully generated quantum random data words 418. The shift register controller 2103 of the time-to-pseudorandom number converter 404.3 preferentially loads the new seed value of the seed reload register in the shift register controller 2103 into the shift register bits SB1 to SBn of the time-to-pseudorandom number converter 404 on one or more of the following events.3: • when a predetermined number of successfully generated quantum random bits is reached at the output 411 and / or.

[0262] • upon reaching a predetermined number of successfully generated random data words 418 and / or

[0263] • when changing the value of the feedback polynomial selection register 2112 of the time-to-pseudo-random number converter 404.3 and thus the selected feedback polynomial of the m feedback polynomials RKNi to RKN m the time-to-pseudorandom number converter 404.3.

[0264] This reliably prevents any kind of predictability.

[0265] Preferably, the circuit components of the quantum random generator 728 are covered with a metal layer to prevent any influence from temperature, electromagnetic radiation, electrostatic fields, or magnetic fields. Preferably, the metal layer also includes a soft magnetic layer to prevent attacks using magnetic fields.

[0266] Preferably, by means of a line for preventing the use of a quantum random bit at output 411 by finite state machine 404.8, the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 or one of the processors (10-1, 10-2) or another device prevents the forwarding of a generated quantum random bit at output 411 by finite state machine 404.8 when this random bit at output 411 is used for the seed reload register in shift register controller 2103 in time-to-pseudo-random number converter 404.3. This prevents double use and thus increases security. Instead, the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 or the processor (10-1, 10-2) or the other device preferably uses this random bit 411 to generate a random data word 418 for storage in the seed reload register in the shift register controller 2103.This has the advantage that the seed value of the linear feedback shift register selected by the seed reload register in the shift register controller 2103 of the n shift register bits SBi to SB. nis completely random. Since a linear feedback shift register has two cycles when using simple primitive feedback polynomials, one of which contains only one shift register value, this must prevent a single-cycle shift register value. If the reload value of the seed reload register in the shift register controller 2103 happens to correspond to the single-cycle seed value of the linear feedback shift register with the current feedback polynomial or the next feedback polynomial, the shift register controller 2103 of the time-to-pseudorandom number converter 404.3 (TPRC) or one of the processors (10-1, 10-2) or another device generates a new random reload value in the seed reload register of the shift register controller 2103.

[0267] The m feedback polynomials RKNi to RKN are preferred mselected so that the one-cycle seed values ​​are equal. This reduces the effort for detecting the one-cycle shift register value, since it is then no longer dependent on the selected feedback polynomial of the feedback polynomials RKNi to RKN m In any case, it is recommended that the time-to-pseudorandom number converter 404.3, in the case of using linear feedback shift registers, has a detection circuit 2113 for detecting an illegal value of the state vector of the n shift register bits SBi to SB n If the state vector of the n shift register bits SBi to SB nin such an illegal state, the detector 2113 preferably signals this illegal state to the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 or one of the processors (10-1, 10-2) or another device. The detector 2113 or the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 or the processor (10-1, 10-2) or the other device then sets the value of the state value of the state vector of the n shift register bits SBi to SB nto a predetermined value and / or the value of the seed reload register in the shift register controller 2103. These reload values ​​are preferably different from the one-cycle shift register value. This preferably also occurs when the watchdog 404.5 and / or the voltage monitor 413 detect a disturbance or a suspected or possible attack. The shift register controller 2103 of the time-to-pseudo-random number converter 404.3 preferably counts the number of these disturbances. The shift register controller 2103 of the time-to-pseudo-random number converter 404.3 preferably reduces this counter value again depending on the number of random quantum bits successfully generated at the output 411 and / or random data words 418, in particular since the last disturbance.If this number and / or the event density of such events exceeds a certain predetermined temporal density and / or a certain numerical value, the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 signals, preferably to the watchdog 404.5 and / or a processor (10-1, 10-2), a defect in the quantum random number generator 728 or a successful attack on the quantum random number generator 728. Typically, the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 then signals to the finite state machine 404.8 that no more random numbers may be generated. Preferably, a processor (10-1, 10-2) must then reactivate the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 by means of a predetermined reactivation password.The processor (10-1, 10-2) then writes this reactivation password via the internal data bus 419 of the quantum random number generator 728 into a special reactivation register of the shift register controller 2103 of the time-to-pseudo-random number converter 404.3. This reactivates the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 and the quantum random number generator 728 and preferably resets all error counters. Preferably, the number of possible reactivations is limited. If the maximum number of reactivations is exceeded, the quantum random number generator 728 can preferably no longer be reactivated. Preferably, the counter for the reactivations of the quantum random number generator 728 can be reset using a special reset command before this maximum value is reached. Preferably, the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 of the quantum random generator 728 or another device of the quantum random generator 728 issues a warning before reaching this blocking limit.

[0268] When the quantum random generator 728 is started, the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 first ensures that the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 first determines a new seed value based on quantum random numbers at the output 411 and a new value of the feedback polynomial selection register 2112 based on quantum random numbers from quantum random bits at the output 411 using a predetermined seed value and a predetermined value of the feedback polynomial selection register 2112. Only when the seed value and the value of the feedback polynomial selection register 2112 are based on quantum random numbers is the initialization phase of the quantum random generator 728 completed and the shift register controller 2103 of the time-to-pseudorandom number converter 404.3 signals the finite state machine 404.8, that it may use and forward the quantum random bits at output 411 and the quantum random data words 418 (quantum random numbers). Preferably, the finite state machine 404.8 signals this fact to one or more processors (10-1, 10-2). This has the advantage that the device only provides quantum random data words 418 generated with full protection.

[0269] By using a time-to-pseudorandom number generator 404.3, it is no longer possible for an attacker to feed a deterministic bit data stream instead of the data bit stream of the quantum random bits at the output 411, even if an attack on the entropy source 401 is actually successful for whatever reason.

[0270] To prevent this, it is also useful if, for example, the quantum random generator 728 changes this number m after the complete determination of a number m of quantum random bits at the output 411 as a function of one or more previously determined random bits.

[0271] Preferably, the finite state machine 404.8 of the quantum random generator 728 does not output these already used quantum random bits at the output 411 and does not use them for generating quantum random data words 418.

[0272] The logic extraction method can also include three borderline cases, which are described below.

[0273] Typically, the time-to-pseudorandom number generator 404.3 uses the logical value of the shift register reload value line 2104 of the time-to-pseudorandom number converter 404.3 as the value of the output 410 of the time-to-pseudorandom number converter 404.3. Optionally, a buffer amplifier may be provided that detects the logical value of the shift register reload value line 2104 of the time-to-pseudorandom number converter 404.3 and outputs it as the value in the output signal 410 of the time-to-pseudorandom number converter 404.3.

[0274] The entropy extraction 404.4 now compares two different pseudorandom numbers generated by the time-to-pseudorandom number converter 404.3 from the output signal 410 of the time-to-pseudorandom number converter 404.3, a first pseudorandom number 410.1 and a second pseudorandom number 410.2.

[0275] If the first pseudorandom number 410.1 and the second pseudorandom number 410.2 are equal, the entropy extraction 404.4 discards one of the two pseudorandom numbers, the first pseudorandom number 410.1 or the second quantum random number 410.2, and replaces it with a new pseudorandom number 410.3 from the time-to-pseudorandom number converter 404.3. Preferably, the entropy extraction 404.4 uses a counter to count the events in which the two pseudorandom numbers, the first pseudorandom number 410.1 and the second pseudorandom number 410.2, are equal, and increments the counter by a first counter step with each such event. Preferably, the entropy extraction 404.4 also counts the events in which the two pseudorandom numbers, the first pseudorandom number 410.1 and the second pseudorandom number 410.2, are unequal by means of this counter and decrements the counter by a second counter step size with each such event, preferably not falling below the value 0.Preferably, the second counter step size is smaller in magnitude than the first counter step size of the counter in the entropy extraction 404.4. If the value of this counter exceeds a predetermined value, the control device of the entropy extraction 404.4 assumes a defect in the time-to-pseudo-random number converter 404.3. Preferably, the control device of the entropy extraction 404.4 then signals to a processor (10-1, 10-2) a defect in the quantum random generator 728 or a successful attack on the quantum random generator 728. Preferably, the entropy extraction 404.4 then no longer signals to the finite state machine 404.8 that a quantum random bit has been successfully generated at the output 411, so that the finite state machine 404.8 can no longer report successful quantum random number generation to a processor (10-1, 10-2) and no longer generates a quantum random data word 418.

[0276] If the first pseudorandom number 410.1 is smaller than the second pseudorandom number 410.2, the entropy extraction 404.4 generates a quantum random bit of a first logical value, for example a logical 1, and signals the successful generation to the finite state machine 404.8.

[0277] If the first pseudorandom number 410.1 is greater than the second pseudorandom number 410.2, the entropy extraction 404.4 generates a quantum random bit of a second logical value, for example a logical 0, which is different from the first logical value, and signals the successful generation to the finite state machine 404.8.

[0278] The finite-state machine 404.8 converts the successfully generated quantum random bits at output 411 into quantum random data words 418, each representing a quantum random number, and makes them available to the processors (10-1, 10-2) via a RAM or a FIFO 404.9 via the internal data bus 419. The finite-state machine 404.8 preferably signals the provision of one or more quantum random numbers to one or more processors (10-1, 10-2).

[0279] One problem can be jitter in the system clock 2106. By using a time-to-time pseudorandom number generator 404.3, a monofrequency or otherwise systematic disturbance in the system clock 2106 is spread in the spectrum with a random spreading code, making detection difficult, if not impossible, for an attacker. This further complicates the vulnerability of the quantum random number generator 728.

[0280] By using quantum random numbers from quantum random bits at output 411 for the seed value of the linear feedback shift register of the time-to-pseudo-random number converter 404.3 and a quantum random number for the selection of the simple primitive feedback polynomial, the behavior of the time-to-pseudo-random number converter 404.2 itself is at the random level of a quantum random number. The regular change of these values ​​further complicates the influencing of the generated quantum random numbers.

[0281] Accordingly, the quantum random generator 728 shown as an example achieves a maximum level of security.

[0282] In particular, this makes it possible to provide a one-piece micro-integrated quantum random generator 728 that guarantees a high degree of entropy, so that it at least passes the statistical tests defined by NIST. Furthermore, this makes it possible to provide a one-piece micro-integrated quantum random generator 728 that enables a high bit rate to be achieved when generating random sequences of quantum random bits at output 411 and / or quantum random data words 418.

[0283] Compared to the prior art quantum random generators, the quantum random generator 728 described here may have a more compact, robust and less complex and, above all, micro-integrated and CMOS compatible structure, allowing for single-piece manufacturing and co-integration into conventional systems such as memories (such as DRAMs, SRAMs, flash memories and the like) or processors (microprocessors and / or microcontrollers and / or SoCs via a processor on the IC).

[0284] A quantum random number generator 728 is described that provides a high degree of security against any attempt to manipulate its internal components. In particular, the use of a time-to-time pseudorandom number generator 404.3 prevents the evaluation of successful attacks on the entropy source 401. Furthermore, the numerous tests enable reliable detection of an attack on the quantum random number generator 728 and thus prevent the use of manipulated numbers as supposedly secure quantum random numbers. The described quantum random number generator 728 is more economical than the generators of the known prior art, particularly due to its ability to be co-integrated into CMOS circuits. Figure 25 shows an exemplary diagram illustrating the detection of the pulses (2201, 2202, 2203, 2204) on the voltage signal 405 of the entropy source 401.The entropy source 401 can, in particular, comprise a photon source and a single-photon detector of an iQRNG according to the invention. The entropy source 401 is preferably fabricated in or on a semiconductor substrate and is thus preferably part of the microintegrated circuit of the quantum random generator 728. The output signal 405 of the entropy source 401 is typically the aforementioned voltage signal 405 of the entropy source 401. The voltage signal 405 of the entropy source 401 is preferably the signal of one or more photon detectors or one or more SPAD diodes of the entropy source 401.

[0285] The voltage signal 405 shows exemplary pulses 2201, 2202, 2203, 2104 for random events of the voltage signal 405. These can be spontaneous voltage pulses of the photon detector or the SPAD diode of the entropy source 401, which are not related to the activity of the photon source or a silicon LED or the SPAD diode of the entropy source 401. The pulses 2201, 2202, 2203, 2204 of the photon detector or the SPAD diode of the entropy source 401 can also be based on stimulated emission, which causes the detection of a photon of the one or more photon sources or the one or more silicon LEDs or the one or more SPAD diodes by the photon detector or by the SPAD diode of the entropy source 401.

[0286] The time interval is random. However, after a photon is received by the photon detector or by the SPAD diode of the entropy source 401, a dead time occurs during which the photon detector or the second SPAD diode of the entropy source 401 is no longer capable of receiving. A pulse lengthening circuit, which is preferably part of the integrated microelectronic circuit, can output a pulse with a minimum length of n cycles of a system clock 2106 of the quantum random generator 728, which is preferably one of the system clocks of the integrated microintegrated circuit, on a synchronized voltage signal 415.

[0287] In the example of FIG. 25, the pulse extension circuit 2023 is designed, for example, to go to a first logic level for at least three subsequent clock pulses of the system clock 2106 and then fall back to the second logic level until the next event, here, for example, with the falling edge of the third clock pulse. Instead of three clock pulses, a to n clock pulses can be used, with a positive integer greater than 0. The falling edges of pulses 2211, 2212, 2213, 2214 of the synchronized voltage signal 415 represent the synchronized signals of the entropy source 401.

[0288] With a falling edge of a first pulse 2211 of the synchronized voltage signal 415, the time-to-pseudorandom number converter 404.3 resets a pseudorandom number generator, for example, to a predefined seed value. For example, the pseudorandom number generator of the time-to-pseudorandom number converter 404.3 can be a feedback shift register that shifts its values ​​one place to the left or right with each clock pulse of the system clock 2106, depending on the design, and feeds the feedback value of the feedback polynomial back into the released bit.

[0289] It is important that, starting with the starting value of the pseudorandom number generator (seed value), each clock pulse of the system clock 2106 is bijectively assigned exactly one pseudorandom number from the pseudorandom number generator starting from the falling edge. This means that the value of the pseudorandom number must be able to be used to determine the temporal position of the respective clock pulse of the system clock 2106 after the falling edge of the synchronized voltage signal 415.

[0290] With the next falling edge of the second pulse 2212 synchronized voltage signal 415, a first pseudorandom number register takes over the last status of the pseudorandom number generator and the time-to-pseudorandom number converter 404.3 preferably resets the pseudorandom number generator to the predefined seed value.

[0291] With the next falling edge of the third pulse 2213 synchronized voltage signal 415, a second pseudorandom number register takes over the last status of the pseudorandom number generator, and the time-to-pseudorandom number converter 404.3 preferably resets the pseudorandom number generator to the predefined seed value. The entropy extraction 401 compares the value in the first pseudorandom number register with the value in the second pseudorandom number register. If the first value in the first pseudorandom number register is greater than the second value in the second pseudorandom number register, for example, the entropy extraction 404.4 can generate a random bit with a first logical level. If the second value in the first pseudorandom number register is greater than the second value in the second pseudorandom number register, for example, the entropy extraction 404.4 can generate a random bit with a second logical level that is different from the first level.With the next falling edge of the fourth pulse 2214 of the synchronized voltage signal 415, the first pseudorandom number register takes over the previous value of a second pseudorandom number register, and the second pseudorandom number register instead takes over the last status of the pseudorandom number generator, and the time-to-pseudorandom number converter 404.3 preferably resets the pseudorandom number generator to the predefined seed value. The entropy extraction 401 then compares the value in the first pseudorandom number register with the value in the second pseudorandom number register. If the first value in the first pseudorandom number register is greater than the second value in the second pseudorandom number register, the entropy extraction 404.4 can, for example, generate another new and, in this case, second quantum random bit at output 411 with a first logic level.If the second value in the first pseudorandom number register is greater than the second value in the second pseudorandom number register, the entropy extraction 404.4 can, for example, generate another new and here second quantum random bit at the output 411 with a second logic level that is different from the first level.

[0292] In this way, the quantum random generator 728 can continue this process of quantum random bit generation and thus produce a continuous, albeit phase-noise-infused stream of quantum random bits at the output 411.

[0293] List of reference symbols (excerpt)

[0294] 10 Carrier substrate

[0295] 22 first area (e.g. NBL)

[0296] 32 second area (e.g. PBL)

[0297] 40 epitaxial layer

[0298] 50 first pn junction (e.g. upper pn junction of a double structure)

[0299] 52 second pn junction (e.g. lower pn junction of a double structure)

[0300] 110 Substrat

[0301] 120 photon source (e.g. single photon source, SPS)

[0302] 122 Cathode (n + , photon source)

[0303] 124 Anode (p + , photon source)

[0304] 128 photons

[0305] 130 Single-photon detector (e.g. single-photon avalanche diode, SPAD)

[0306] 132 Cathode (n + , single-photon detector)

[0307] 134 Anode (p + , single-photon detector)

[0308] 150 light blocking layer

[0309] 152 means of electronic recording

[0310] 154 Means of electronic post-processing

[0311] 200 iQRNG

[0312] 400 quantum random generators (e.g. based on an iQRNG)

[0313] 401 Entropy Source (e.g. iQRNG)

[0314] 403 Analog-to-Digital Converter (ADC)

[0315] 404.3 Time-to-Pseudo-Random Number Converter (TPRC)

[0316] 404.4 Entropy extraction

[0317] 404.5 Watchdog

[0318] 404.6 Pseudo-random number generator (PRNG, e.g. linear feedback shift register)

[0319] 404.7 Signal Multiplexer

[0320] 404.8 Finite State Machine (FSM)

[0321] 404.9 volatile memory (RAM) / FIFO memory (First In - First Out) finish flag

[0322] Voltage signal (entropy source)

[0323] Pulse extension circuit (e.g. monoflop, MF)

[0324] Output signal (ADC)

[0325] Voltage converter

[0326] Output signal (TPRC)

[0327] Output (entropy extraction)

[0328] Seed value S

[0329] Voltage monitor digital input / output signal line(s) synchronized voltage signal (e.g. pulse with a minimum length)

[0330] selection signal

[0331] Pseudorandom signal line

[0332] Quantum random data words internal data bus

[0333] Interrupt signal

[0334] Voltage transformer cable

[0335] Correlation signal (optional) electronic circuit (Integrated Circuit, IC)

[0336] Semiconductor die

[0337] Connection pads (connection surfaces)

[0338] Pad frame

[0339] Wiring area inner area

[0340] Quantum random generator (e.g. based on an iQRNG)

[0341] Entropy source

[0342] Number generator

[0343] Data bus driver (e.g. serial data bus l 2 C)

[0344] Watchdog

[0345] Control logic

[0346] Voltage monitor

[0347] Power supply 609 Voltage regulator (VREG)

[0348] 610 Oscillator (OSO)

[0349] NBL deep n-layer (n-type buried layer)

[0350] PBL deep p-layer (p-type buried layer)

[0351] H(V)PW high-voltage p-type well

[0352] H(V)NW high-voltage n-type well

[0353] PW p-well

[0354] PBODY p-doped region (p-type body)

[0355] NEPI weakly n-doped or (approximately) intrinsic epitaxial region

[0356] MET1 , MET2 metallization

[0357] CONT Contact

[0358] STI isolation region (shallow trench isolation) poly polysilicon layer

[0359] P + p + -Area

[0360] N + n + -Area

[0361] VDD positive supply voltage line

[0362] GND reference potential line

[0363] VENTI first supply voltage line (entropy source)

[0364] V E NT2 second supply voltage line (entropy source)

[0365] VREF Reference voltage line (ADC)

[0366] RN Random number (e.g. 1-bit random number)

[0367] PRN pseudorandom number

[0368] SDA serial data line (e.g. I 2 C)

[0369] SCL serial clock line (e.g. I 2 C)

[0370] TEST Test management

[0371] S Surface (carrier substrate, e.g. a BCD substrate)

[0372] O Surface (substrate, e.g. a BCD substrate)

[0373] R radial axis of symmetry

Claims

Patent claims 1. Integrated quantum random number generator, iQRNG, (200) comprising: a photon source (120) and a single-photon detector (130), characterized in that the photon source (120) and the single-photon detector (130) are arranged vertically one above the other in a common substrate (110) made of a semiconductor material.

2. iQRNG (200) according to claim 1, wherein the photon source (120) is a single photon source, SPS, configured to provide only single or a few photons (128) at a time.

3. iQRNG (200) according to claim 1 or 2, wherein the photon source (120) is a light-emitting avalanche Zener diode, Zener-avLED, operated at an operating point below or near the breakdown voltage, wherein the Zener-avLED preferably has a breakdown voltage of < 10 V.

4. iQRNG (200) according to one of the preceding claims, wherein the single-photon detector (130) is a single-photon avalanche diode, SPAD.

5. iQRNG (200) according to one of the preceding claims, wherein the iQRNG (200) is formed in a BCD substrate (110) using BCD technology.

6. The iQRNG (200) according to claim 5, wherein the BCD substrate (110) comprises a carrier substrate (10); and an epitaxial layer (40) grown on the carrier substrate (10), wherein a deep pn junction (50) lying in the epitaxial layer was created between the carrier substrate (10) and the epitaxial layer (40) by diffusion of dopants introduced into a surface (S) of the carrier substrate (10) below the epitaxial layer (40).

7. iQRNG (200) according to claim 6, wherein the single-photon detector (130) forms an avalanche region in a region around the deep pn junction (50) and comprises an absorption region (PW, NEPI) for converting photons into electron-hole pairs, wherein the absorption region (PW, NEPI) is directly adjacent to the regions (NBL, PBL) forming the deep pn junction (50).

8. iQRNG (200) according to claim 6 or 7, wherein the deep pn junction (50) is formed at least partially between a deep n-layer (NBL) as a cathode (132) and a deep p-layer (PBL) directly adjoining the deep n-layer (NBL), the absorption region (PW, NEPI) directly adjoins the deep p-layer (PBL) and is formed substantially as a p-region, and a p + -area formed anode (134) is directly connected to the absorption region (PW, NEPI).

9. iQRNG (200) according to one of claims 6 to 7, wherein a second deep pn junction (52) formed below the deep pn junction (50) of the single-photon detector (130) located in the epitaxial layer is used as an additional photodetector for monitoring for external attacks.

10. iQRNG (200) according to one of the preceding claims, wherein the top and / or bottom side of the substrate (110) in the region of the iQRNG (200) is mirrored on a surface (O) or comprises a light-blocking layer (150).

11. iQRNG (200) according to claim 10, wherein the surface (O) of the substrate (110) is covered with a silicide layer in the region of the iQRNG (200) and with a metallization above.

12. iQRNG (200) according to one of the preceding claims, wherein an escape of photons (128) provided by the photon source (120) at the surface (O) of the substrate (110) and / or a backside of the substrate (110) is prevented by a combination of at least one element each of metal covers, sidewall contacts and vias.

13. iQRNG (200) according to one of the preceding claims, further comprising an electronic circuit for statistically evaluating the temporal sequence of signals of the single-photon detector (130).

14. iQRNG (200) according to claim 13, further comprising an electronic circuit for generating and outputting a digital random number sequence based on the statistical evaluation of the temporal sequence of signals of the single-photon detector (130).

15. Integrated electronic circuit (500) comprising at least one iQRNG (200) according to one of the preceding claims.

Images