Method for producing a wafer having a spacer

Abstract

The invention relates to a method for producing a wafer (100) having a spacer (150) for protecting metal contacts (132) of the wafer, comprising the following steps: providing a functional wafer (101) comprising a carrier substrate (140, 140'), a functional layer (120) and a passivation layer (130) which is arranged between the carrier substrate (140, 140') and the functional layer (120) and has cut-outs (131); generating the spacer (150) by partly removing the carrier substrate (140, 140') in such a way that the functional layer (120) is in contact with an external environment (102) via at least some of the cut-outs (131) in the passivation layer; and forming the metal contacts (132) electrically contacting the functional layer (120) in at least some of the cut-outs (131) in contact with the external environment.

Description

[0001] Description

[0002] title

[0003] Technical area

[0004] The present invention relates to the field of wafer processing and concerns a method for producing a wafer with a spacer for protecting metal contacts of the wafer. Furthermore, it relates to a corresponding wafer.

[0005] State of the art

[0006] US 2008 / 0303129 A1 discloses a method for preventing damage to sensitive surfaces in MEMS (microelectromechanical system) manufacturing. For this purpose, the use of a chuck with a structured contact surface is proposed. A cover wafer is described in detail, which is to be connected to an interposer wafer during a manufacturing process. The cover wafer is positioned on the chuck, and the structuring ensures that mechanical damage is avoided. DE 10 2015 206 996 A1 discloses the so-called EPyC process (EPyC: epitaxial polysilicon cycle) for manufacturing microelectromechanical structures with large vertical dimensions. This process uses epitaxial polysilicon as the functional and sacrificial material and builds up a layer structure of epitaxial polysilicon layers (EpiPoly layers) using repeated cycles.

[0007] Disclosure of the invention

[0008] According to the invention, a method for producing a wafer with a

[0009] Spacers for protecting metal contacts of the wafer and a corresponding wafer are proposed. According to a first aspect of the invention, a method for producing a semiconductor wafer (also referred to as a wafer for short within the scope of this invention) with a spacer for protecting metal contacts of the wafer is proposed. The method comprises providing a functional wafer with a carrier substrate, a functional layer, and a passivation layer with recesses arranged between the carrier substrate and the functional layer. The passivation layer thus forms a layer of the functional wafer and, with its base surfaces, is preferably in direct contact with both the functional layer and the carrier substrate; in this case, it is located on the surfaces of these layers.

[0010] The carrier substrate and the functional layer typically comprise one or more semiconductors or consist of one or more semiconductors, for example they comprise silicon or consist of silicon. Metals and / or semiconductor oxides can also be contained in the carrier substrate and / or the functional layer. For example, the functional layer can comprise sacrificial regions made of a semiconductor such as silicon and / or a semiconductor oxide such as silicon dioxide. The oxide layer typically comprises a semiconductor oxide such as silicon dioxide or consists of it. The functional layer can, for example, comprise structures for one or more electronic circuits, integrated circuits (ICs), MEMS, electrodes and / or vias such as through-silicon vias (TSVs).The wafer produced by the method can further comprise structures for a plurality of semiconductor chips (also referred to as chips for short in the context of this invention).

[0011] The passivation layer can preferably consist of silicon dioxide (SiO2) and / or a silicon nitride (for example, stoichiometric silicon nitride, i.e., SiAlXk, and / or a non-stoichiometric silicon nitride, i.e., a silicon nitride with a non-stoichiometric composition) or comprise silicon dioxide and / or silicon nitride. In particular, it is conceivable for the passivation layer to consist of a silicon nitride layer and a silicon dioxide layer or to comprise these layers. The use of a double layer as a passivation layer comprising a layer of stoichiometric silicon nitride and a layer of non-stoichiometric silicon nitride is also possible.

[0012] The functional layer can be formed at least partially by growing layers, for example, using the EPyC process, and / or by bonding to a separately provided wafer in which the desired structures have already been implemented. Both options can be combined, meaning that parts of the functional layer can be grown and additional parts can be provided using a separate wafer to be bonded.

[0013] The carrier substrate can temporarily fulfill the function of a handle wafer in the process. The spacer is created by partially removing the carrier substrate, preferably by etching, for example using a resist mask. The resist mask defines a base area of ​​the spacer. The removal takes place in such a way that the functional layer is in contact with an external environment of the functional wafer via at least some of the recesses in the passivation layer, for example via recesses in the carrier substrate formed by the partial removal. The functional layer is therefore in contact with the outside, i.e. with the environment of the wafer to be produced. Furthermore, the creation of the spacer can also comprise thinning the carrier substrate, which can take place, for example, before the partial removal of the carrier substrate. The thinning can be done, for example, by grinding.Chemical mechanical polishing (CMP) is preferably performed next to ensure particularly high accuracy regarding the height of the thinned carrier substrate. The height, i.e., the extension in a direction perpendicular to the new surface of the functional wafer, determines the subsequent height of the spacer and can, for example, be in the range of 20 to 30 pm.

[0014] The spacer can have any shape and consist of a single, continuous element or of several spatially separated elements. An element formed in this way from the carrier substrate, which is part of the spacer, is also referred to as a spacer structure. The spacer can, for example, be produced from the carrier substrate by forming recesses in the carrier substrate. The spacer and / or its spacer structures can, for example, have the shape of continuous or interrupted frames, for example with walls, arches, grids, and / or struts. The spacer structures of a spacer can also have the shape of walls, cuboids, cylinders, angles, and / or crosses. Such frames and support structures are preferably arranged in a grid.In particular, the one or more spacer structures may have the shape of one or more rectangular frames and / or a rectangular grid.

[0015] Finally, the metal contacts to be protected, which electrically contact the functional layer, are formed in at least some of the recesses in contact with the external environment. The metal contacts can be formed by applying a corresponding metal layer in conjunction with suitable structuring. Common methods for this include low-pressure CVD (low-pressure chemical vapor deposition, LPCVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), for example sputtering, or electroplating. Structuring of the metal layer, i.e. removal of unwanted metal, can be achieved using suitable photolithographic processes, for example with thicker resists (thick resist, resist thickness, for example, 100 μm) in combination with a suitable etching process.The resist is applied by spin coating or as spray paint using a resist nozzle that moves in a meandering pattern over the functional wafer. Alternatively, the metal can also be applied in advance using a shadow mask (stencil mask). These metal contacts can be used to electrically contact specific elements within the functional layer, such as electrodes and / or through-silicon vias (TSV), and to establish electrical connections between the functional wafer and other components. The metal contacts, which can represent metal pads, can be made of, for example, an aluminum-copper alloy (AlCu), aluminum (Al), copper (Cu) and / or gold (Au) or can comprise AlCu, Al, Cu and / or Au. The spacer is preferably passivated before or after the metal contacts are formed.In this process, a passivation layer, such as a silicon dioxide layer or a polymer layer, e.g., consisting of a polyimide, is formed on the spacer. This is particularly advantageous if over-pad metallization (OPM) of the metal contacts is to be performed after the formation of the metal contacts, since passivation with a silicon dioxide layer can prevent metallization of exposed semiconductor surfaces, such as the functional layer. Passivation techniques such as plasma-enhanced chemical vapor deposition (PECVD), thermal oxidation, and / or tetraethyl orthosilicate (TEOS) deposition can be used for passivation.When passivating the spacer, it must be ensured that this additional passivation layer does not inadvertently cover areas where the metal contacts have been or are to be formed, i.e., in the recesses of the passivation layer on the functional layer, as otherwise electrical contact between the metal contacts and the structures of the functional layer to be contacted is potentially prevented. For this purpose, a shadow mask, for example, can be used to specifically create the passivation layer in the desired areas, since the spacer structures of the spacer represent comparatively coarse structures that do not require high resolution. Alternatively, the passivation layer can also be removed in unwanted areas after the spacer has been passivated and before the metal contacts are formed.Photolithographic processes, for example, with thicker resists, followed by etching, can be used for this removal. The resist can be applied, for example, by spin coating or as a spray coat using a resist nozzle that moves in a meandering pattern over the functional wafer.

[0016] After the metal contacts have been formed, an over-pad metallization (OPM) can be applied to the metal contacts. The OPM can, for example, be an ENEPIG coating (ENEPIG: electroless nickel, electroless palladium, immersion gold). Areas of the wafer coated with silicon dioxide are not coated. This type of coating is often applied with the metal contacts oriented upwards (i.e., against the direction of gravity). In the case of the optional application of an OPM, the metal contacts serve as a seed layer for the OPM. Before application, the metal contacts can be conditioned to prepare them for the application of the OPM. Conditioning means cleaning and / or roughening the surface of the metal contacts, which may also result in material being removed from the metal contacts.Conditioning can be carried out, for example, by or include cleaning with an O^Ar plasma and / or by back sputtering (removal of material using a sputtering process).

[0017] After applying the OPM, a passivation layer, preferably a silicon dioxide layer, can be applied to the over-pad metallization. This can serve as additional protection to counteract potential chuck and / or environmental contamination, for example, in a production facility. In the case of a silicon dioxide layer, this can later be removed without residue, for example, using HF gas-phase etching, plasma etching, and / or wet-chemical etching. Both when applying this passivation layer and when applying the OPM itself, it is advantageous if they are applied in such a way that the OPM, or the OPM with the passivation layer, does not protrude beyond the spacer. In other words, the height of the spacer is advantageously greater than the height of the OPM, or the OPM and the passivation layer.The term "height" refers to the extension perpendicular to the new surface of the functional wafer. Typical heights for an OPM range from 2 pm to 8 pm, preferably 4 pm to 6 pm.

[0018] Thereafter, possibly after rotating the wafer, for example around a longitudinal axis of the wafer, the wafer can be placed on a support surface, for example a chuck, such that only the spacer is in contact with the support surface. Further processing of the wafer can then take place, for example, by exposing existing MEMS structures in the functional wafer. Such MEMS structures can, for example, be the structures for one or more MEMS components such as MEMS sensors and / or MEMS actuators, for example MEMS inertial sensors, MEMS pressure sensors, MEMS microphones, MEMS micromirrors, and / or MEMS resonators. Exposing MEMS structures in the functional layer can be achieved using plasma-free and / or plasma-assisted etching.In the case of silicon sacrificial regions to be removed, such etching is preferably carried out using sulfur hexafluoride (SFe), xenon difluoride (XeF2), chlorine trifluoride (ClF3), and / or nitrogen trifluoride (NF3). For silicon dioxide sacrificial regions, hydrogen fluoride (HF), for example, can be used as the etching gas.

[0019] Finally, after the ME MS structures have been exposed, one or more passivation layers, for example a passivation layer formed by passivating the spacer, can be at least partially removed from the spacer wafer. The one or more passivation layers can be, for example, oxide layers, in particular silicon dioxide layers. Removal can be carried out, for example, using HF gas-phase etching, plasma etching, and / or wet-chemical etching. In this method step, passivation layers, for example silicon dioxide layers, which may have been applied to an OPM of the metal contacts, can also be removed. For example, a silicon dioxide layer used as a passivation layer on an OPM of the metal contacts is removed residue-free by means of HF gas-phase etching, plasma etching, and / or wet-chemical etching.If desired, specific areas can be protected from RF gas phase etching by applying non-stoichiometric silicon nitride.

[0020] Furthermore, it is conceivable that the metal contacts are connected to one or more components, for example, electronic components such as ASICs (ASIC: application-specific integrated circuit) and / or MEMS components, or a component wafer such as an ASIC wafer or a MEMS wafer, preferably to establish electrical connections. Such a step can be performed, for example, before the wafer is singulated into individual chips and / or MEMS components and is preferably carried out after any MEMS structures have been exposed. Alternatively, however, such a connection can also be performed after the wafer has been singulated.

[0021] Finally, a dicing of the wafer, optionally including a component wafer already connected to the wafer, can be carried out in order to obtain, for example, individual MEMS components and / or chips, wherein a chip can comprise several MEMS components.

[0022] It is particularly advantageous if, in this case, after singulation, at least a portion of one or more spacer structures, for example in the form of a frame and / or individual support structures, for example in corners, at edges, and / or other non-critical areas of the MEMS components and / or chips, remains on the spacer wafer for each formed chip and / or each formed MEMS component. This ensures at least partial protection of the chips and / or MEMS components and their metal contacts even after singulation, particularly if the metal contacts or their OPMs are still exposed, i.e., have not yet been used for connection to components or a component wafer.

[0023] According to a second aspect of the invention, a wafer, preferably produced by a method as described above, is proposed, wherein the wafer comprises a functional wafer with a carrier substrate, a functional layer, metal contacts electrically contacting the functional layer, and a passivation layer with recesses arranged between the carrier substrate and the functional layer. The metal contacts are arranged in the recesses. Furthermore, the wafer comprises a spacer arranged on the passivation layer and connected thereto, wherein the spacer is designed such that at least some of the metal contacts are in contact with an external environment of the functional wafer.

[0024] Advantages of the invention

[0025] The advantages of the invention are manifold. The invention discloses a method for producing a defined spacer and its production and further processing within the scope of chip or MEMS component manufacturing. The approach pursued here is not to completely remove a carrier substrate frequently used in a wafer manufacturing process, which serves, for example, as a handle wafer, but to reshape it into a spacer. The carrier substrate required for the preceding steps of the manufacturing process therefore does not need to be completely removed; instead, the carrier substrate is reshaped, which means that fewer process steps are required in a corresponding manufacturing process, for example, chip manufacturing, thus saving time.

[0026] The spacer according to the invention makes it possible to protect metal contacts extending from the functional wafer while still allowing further processing, thus enabling, in particular, electrical coupling to additional components such as an ASIC or a corresponding component wafer. Even after the wafer has been singulated, spacer structures can be provided for individual chips or MEMS components based on the spacer.

[0027] The method's approach allows for a high degree of flexibility for adaptation to the precise conditions of the manufacturing process in which the invention is to be used. For example, the height of the spacer can be selected to ensure safe handling of the wafer. The wafer can be placed with the spacer wafer facing down and thus further processed in manufacturing systems lying on a chuck without risking chuck or system contamination. Applying an OPM to the metal contacts is also easily achieved thanks to the openings in the form of recesses in the spacer wafer, whereby the height of the spacer can be adapted to the height of the OPM layer.

[0028] Short description of the drawings

[0029] Embodiments of the invention are explained in more detail with reference to the drawings and the following description.

[0030] They show:

[0031] Figures 1 A to 1 F are schematic representations of cross sections of wafers to explain a method according to the invention for producing a wafer according to the invention;

[0032] Figure 2 shows a schematic representation of a wafer according to the invention with spacer from below; and Figure 3 shows, in schematic form as a flow chart, an exemplary method according to the invention for producing a wafer according to the invention.

[0033] Embodiments of the invention

[0034] In the following description of the embodiments of the invention, identical or similar elements are designated by the same reference numerals, whereby a repeated description of these elements is omitted in individual cases. The figures only schematically illustrate the subject matter of the invention.

[0035] Figures 1 A to 1 F show schematic representations of wafers to explain a method according to the invention for producing a wafer according to the invention in cross-sectional views.

[0036] Figure 1A shows a schematic representation of a cross section of a functional wafer 101 in an external environment 102. The functional wafer 101 comprises a carrier substrate 140, a functional layer 120 and a passivation layer 130 with recesses 131 located between the carrier substrate 140 and the functional layer 120. Here, as in the following Figures 1B to 1F, the functional wafer 101 is only shown in detail; it continues to the left and right of the area shown in the figures.

[0037] The functional layer 120 can comprise structures for one or more electronic circuits, integrated circuits, MEMS, electrodes, and / or vias such as silicon vias. It also typically has trenches filled with a passivation layer, which can serve to structure and define functional and sacrificial regions. The functional and sacrificial regions can, for example, implement structures for interconnections, electrodes, actuators, and / or MEMS, i.e., MEMS structures. Figures 1A to 1F show, purely by way of example, three MEMS structures 160, which can, for example, be assigned to chips 105 to be manufactured, wherein each of the chips 105 can have one or more MEMS structures 160. Trenches can, in particular, also serve for later exposure and / or singulation of the functional wafer 101, for example, into individual chips 105.At least parts of the functional layer 120 can be produced, for example, by growing layers, for example, using the EPyC process. Another possibility for providing parts of the functional layer 120 is bonding to a separately provided wafer in which the desired structures are already realized.

[0038] The carrier substrate 140 can temporarily fulfill the function of a handle wafer in a manufacturing process. In the example shown in Figures 1A to 1F, the spacer 150 is created in a first step by thinning the carrier substrate 140, for example, by grinding. The carrier substrate 140 is thus reduced in thickness. The result of such a process is shown in Figure 1B. The thickness of the thinned carrier substrate 140' can be used to determine the thickness of the subsequent spacer 150.

[0039] The creation of the spacer 150 comprises a subsequent partial removal of the thinned carrier substrate 140' such that the first functional layer 120 is in contact with an external environment 102 of the functional wafer 101 via at least a portion of the recesses 131 in the passivation layer 130. In other words, the recesses 131 must have been exposed by removing the thinned carrier substrate 140'. In the example shown in Figure 1C, the thinned carrier substrate 140' was removed in certain regions 141, so that four recesses 131 were exposed in each case. The formed spacer 150 can comprise one or more spacer structures. Thus, the four individual rectangles 152 symbolizing the spacer 150 in Figure 1E can each represent individual, unconnected spacer structures, which could, for example, have the shape of cuboids.However, it may also be the case that the regions 141 have the shape of rectangular recesses in the thinned carrier substrate 140' and the shown rectangles 152 represent a single, connected spacer structure.

[0040] The spacer 150 can now be passivated, whereby, as shown in Figure 1D, a passivation layer 145, for example a silicon dioxide layer or a polymer layer, is formed on the one or more spacer structures. Subsequently (as shown in the figures) or beforehand, metal contacts 132 that electrically contact the functional layer 120 are formed in at least some of the recesses 131 of the passivation layer 130. In this case, before forming the metal contacts 132, it may be necessary to remove deposits that were unintentionally introduced into the recesses 131 of the passivation layer 130 during the passivation of the spacer 150. By forming the metal contacts 132, a wafer 100 according to the invention was created, as shown in Figure 1E.

[0041] Finally, Figure 1F illustrates an optional step, wherein, after the formation of the metal contacts 132, an over-pad metallization 134 is applied 370 to the metal contacts 132. In this case, before the application 370 of the over-pad metallization 134, the metal contacts 132 can preferably be structured and / or conditioned. After the application of the over-pad metallization 134, a passivation layer (not shown), preferably a silicon dioxide layer, can be applied to the over-pad metallization 134 for better protection.

[0042] Finally, the wafer 100 can be placed on a support surface 104, for example, a chuck, with the side protected by the spacer 150, i.e., with the metal contacts 132 facing downward (i.e., in the direction of gravity), without fear of damage to the metal contacts 132, including the over-pad metallization 134. In this case, only the spacer 150 is in contact with the support surface 104.

[0043] Some of the described steps, such as the formation of the metal contacts 132 and the formation of the over-pad metallization 134, are typically performed with the metal contacts 132 oriented upward (i.e., counter to the direction of gravity) (not shown in the figures). In such a case, the wafer 100 must finally be rotated accordingly, for example, about a longitudinal axis 106, before being placed on the support surface 104.

[0044] As part of a further manufacturing process for producing chips 105, any passivation layers applied to the over-pad metallization 134 and / or the spacer 150 may be removed again, for example, by means of RF vapor-phase etching, plasma etching, and / or wet-chemical etching. Typical further steps in the further manufacturing process could be exposing the MEMS structures 160 and singulating them into the chips 105. Finally, before or after singulating into the chips 105, the wafer 100 can be connected to further components such as ASICs or even to wafers for such components, wherein the metal contacts 132 can serve to electrically contact these further components.

[0045] Figure 2 now shows a schematic representation of another wafer 200 according to the invention, which was produced using a method according to the invention, in a view from below, i.e., of the passivation layer 230 in contact with the surroundings of the wafer 200, which has recesses in which metal contacts 232 are arranged. As can be seen, the illustrated part of the wafer 200 consists of four square-shaped regions corresponding to chips 205. Each of the chips 205, in turn, has nine mutually identical components 210, each comprising four metal contacts 232. The spacer 250 consists of several spatially separated spacer structures, each having a cross-shaped base area. Nine of these are shown in Figure 2.They are each located in the corners of a chip 205 and are arranged such that, after the wafer 200 has been singulated into individual chips 205, parts of the spacer structures of the spacer 250 remain with the chips 205, thus protecting the chips 205 and their metal contacts 232. These parts of the spacer structures are shown in dashed lines in Figure 2. Angles, cylinders, or cuboids, for example, are also conceivable as spacer structures instead of crosses. Alternative or additional spacer structures could be isolated walls, which are placed, for example, centrally at the edges of the chips 205. Continuous rectangular frames around the chips 205 are also conceivable as spacer structures.Spacer structures, for example in the form of cuboids or cylinders, can also be placed in the center of the chips 205 and / or the components 210, for example as sole spacer structures or as a supplement to other spacer structures.

[0046] Finally, Figure 3 shows, in schematic form as a flowchart, an exemplary method according to the invention for producing a wafer according to the invention. First, a functional wafer is provided 310, comprising a carrier substrate, a functional layer, and a passivation layer with recesses arranged between the carrier substrate and the functional layer.

[0047] Creating 350 a spacer may comprise, as a first step, a targeted thinning 330 of the carrier substrate, for example, by grinding. The spacer is then created in a second step by partially removing 340 the optionally thinned carrier substrate such that the functional layer is in contact with an external environment of the functional wafer via at least some of the recesses in the passivation layer. Now, optionally, a passivation 355 of the spacer may be performed, thereby forming a passivation layer on the spacer.

[0048] Finally, metal contacts that electrically contact the functional layer are formed 360 in at least some of the recesses in contact with the external environment of the passivation layer applied to the first functional layer. If necessary, a passivation layer that was unintentionally applied in these recesses by the passivation 355 of the spacer must be removed beforehand. Alternatively, the metal contacts can also be formed 360 before the spacer is passivated 355. After the metal contacts have been formed 360, the metal contacts are preferably structured and / or conditioned 365 to improve the electrical contact, followed by the application 370 of an over-pad metallization (OPM) to the metal contacts. This OPM is advantageously provided with a passivation layer, such as a silicon dioxide layer, applied in step 375 for better protection.After the spacer has been produced, the produced wafer can be placed 380 on a support surface, for example a chuck, for further processing, with only the spacer being in contact with the support surface.

[0049] A subsequent exposure 385 of any MEMS structures present in the functional layer of the functional wafer after placement 380 of the wafer on the support surface can be followed by an at least partial removal 390 of passivation layers no longer required, for example, on the spacer and / or the OPM of the metal contacts, preferably by means of RF gas-phase etching. Silicon nitride passivation for RF protection is conceivable in this case in order to locally prevent this removal. Subsequently, the exposed wafer can be connected in step 395 to a component wafer, such as an ASIC wafer, or to individual components, such as ASICs.

[0050] Thereafter, singulation can take place to obtain chips each provided with at least one spacer structure of the spacer.

[0051] Instead of connecting to a component wafer or individual components before singulation, singulation can also be performed before connecting to individual components.

[0052] The invention is not limited to the embodiments described here and the aspects highlighted therein. Rather, numerous modifications are possible within the scope of the claims, which are within the scope of one skilled in the art.

Claims

Claims 1. A method for producing a wafer (100) with a spacer (150, 250) for protecting metal contacts (132, 232) of the wafer (100), comprising the following steps: a. providing (310) a functional wafer (101) comprising a carrier substrate (140, 140'), a functional layer (120), and a passivation layer (130) with recesses (131) arranged between the carrier substrate (140, 140') and the functional layer (120); b. Creating (350) the spacer (150, 250) by partially removing (340) the carrier substrate (140, 140') such that the functional layer (120) is in contact with an external environment (102) of the functional wafer (101) via at least a portion of the recesses (131) in the passivation layer (130); and c. Forming (360) the metal contacts (132, 232) electrically contacting the functional layer (120) in at least a portion of the recesses (131) in contact with the external environment (102).

2. The method according to claim 1, wherein the production (350) of the spacer (150, 250) comprises thinning (330) of the carrier substrate (140).

3. Method according to one of the preceding claims, wherein passivation (355) of the spacer (150, 250) takes place before or after the formation (360) of the metal contacts (132, 232).

4. Method according to one of the preceding claims, wherein after the formation (360) of the metal contacts (132, 232) an application (370) of an over-pad metallization (134) onto the metal contacts (132, 232) takes place.

5. The method according to claim 4, wherein prior to the application (370) of the over-pad metallization (134), structuring and / or conditioning (365) of the metal contacts (132, 232) takes place.

6. The method according to claim 4 or 5, wherein after the application (370) of the over-pad metallization (134), an application (375) of a passivation layer, preferably a silicon dioxide layer, onto the over-pad metallization (134) takes place.

7. Method according to one of the preceding claims, wherein after the production (350) of the spacer (150, 250) a placement (380) of the produced wafer (100) on a support surface (104) takes place such that only the spacer (150, 250) is in contact with the support surface (104).

8. Method according to one of the preceding claims, wherein an exposure (385) of MEMS structures (160) in the functional layer (120) is carried out, preferably by means of a plasma-free and / or a plasma-assisted etching and / or using SF6, XeF2, ClF3 and / or NF3.

9. The method according to claim 8, wherein after the MEMS structures (160) have been exposed (385), at least partial removal (390) of one or more passivation layers (145) from the spacer (150, 250) and / or from an over-pad metallization (134) applied to the metal contacts (132, 232) is preferably carried out by means of HF gas phase etching.

10. Wafer (100), preferably produced by a method according to one of claims 1 to 9, comprising • a functional wafer (101) with a carrier substrate (140, 140'), a functional layer (120), metal contacts (132, 232) electrically contacting the functional layer (120), and a passivation layer (130) with recesses (131) arranged between the carrier substrate (140, 140') and the functional layer (120), wherein the metal contacts (132, 232) are arranged in the recesses (131); and • a spacer (150, 250) arranged on the passivation layer (130) and connected thereto, wherein the spacer (150, 250) is designed such that at least some of the metal contacts (132, 232) are in contact with an external environment (102) of the functional wafer (101) 11. Wafer (100) according to claim 10, wherein the functional layer (120) MEMS structures (160) for one or more MEMS components such as MEMS sensors and / or MEMS actuators, preferably MEMS inertial sensors, MEMS pressure sensors, MEMS microphones, MEMS micromirrors and / or MEMS resonators.

12. Wafer (100) according to claim 10 or 11, wherein the spacer (150, 250) consists of several spatially separated elements.

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