Method and system for managing gate level simulation of an electronic circuit

Abstract

A method and a system for managing gate level simulation of an electronic circuit are provided. The method includes identifying at least one circuit topology from a plurality of circuit topologies in an electronic circuit design, based on a netlist and a timing data file. Further, one or more non-critical pins are determined from the identified circuit topology, based on delay corresponding to each of the pins in the identified circuit topology. Based on determination of the one or more non-critical pins, a modified timing data file is generated. The delay associated with each of the non-critical pins is set to zero in the modified timing data file. The method may further include performing a gate-level simulation based on the modified timing data file

Description

METHOD AND SYSTEM FOR MANAGING GATE LEVEL SIMULATION OF AN ELECTRONIC CIRCUITFIELD OF TECHNOLOGY

[0001] The present disclosure generally relates to a field of simulation of electronic circuits, and more particularly to a method and system for performing timing-aware gate level simulation of an electronic circuit.BACKGROUND

[0002] Gate level simulations are performed based on netlist corresponding to an electronic circuit design in order have a certain level of confidence on implementation of the electronic circuit design. An electronic circuit design may include a plurality of circuit topologies based on number of endpoints (I / O pins) present in the electronic circuit design. Each circuit topology may include a plurality7of design elements such as gates, latches, flip flops, etc. Each such design element may have input and output pins that enable the design element to be connected to other design elements in the circuit topology, for achieving a desired function of the electronic circuit design. The pins in the circuit topology7may have predefined constraints or timing checks that help in timing the signals passing through the design elements, for achieving specific functions. However, performing each of the timing checks corresponding to each of the pins increases time required for performing the gate level simulation. For example, there may exist pins within the circuit topology for which timing checks may be skipped in order to reduce the overall time required for performing the gate level simulation.

[0003] In light of the above, there exists a need for a system and method that helps in optimizing time required for gate level simulation of the circuit topology by identifying pins for which timing check may be skipped.SUMMARY

[0004] A method and system for managing gate level simulation of an electronic circuit is disclosed. In one aspect, a method includes identifying, by a processing unit, at least one circuit topology from a plurality7of circuit topologies in an electronic circuit design, based on a netlist and a timing data file. In an embodiment, the at least one circuit topology is identified from the plurality of circuit topologies in the circuit design, based on presence of a common source pin.

[0005] The method further includes determining one or more non-critical pins from the identified circuit topology, based on delay corresponding to each of the pins in the identifiedcircuit topology'. In an embodiment, determining the one or more non-critical pins present in the circuit topology includes predicting arrival time of a signal at each pin along at least one levelized signal path associated with the circuit topology, based on the delay corresponding to each of the pins along the levelized signal path. The levelized signal path is a signal path between the common source pin and a destination pin associated with the circuit topology', and the arrival time of the signal at each pin is predicted with reference to the common source pin. In a further embodiment, predicting arrival time of the signal at each pin along the at least one levelized signal path associated with the circuit topology includes tagging each of the pins in the circuit topology' to a unique identifier, where the unique identifier identifies a relative position of the tagged pin, within the circuit topology. Further, each of the unique identifiers is stored against the delay associated with the respective pin, within a predetermined data structure. The unique identifiers corresponding to each of the pins in the levelized signal path is further used to annotate delays corresponding to each of the pins. Further, the arrival time of the signal at each of the pins in the levelized signal path is predicted, based on a cumulative delay at the pin, with reference to the common source pin.

[0006] If the arrival time predicted for the pin in the levelized signal path is greater than an expected arrival time for the pin, the pin is determined to be a critical pin. Otherwise, the pin is determined to be a non-critical pin. In an embodiment, the expected arrival time is determined based on one or more constraints defined for the pins present along the levelized signal path, in the timing data file.

[0007] The method further includes generating a modified timing data file based on determination of the one or more non-critical pins, where the delay associated with each of the non-critical pins is set to zero in the modified timing data file. In an embodiment, the method further includes performing a gate-level simulation for the at least one circuit topology based on the modified timing data file.

[0008] In another aspect, a system includes a processing unit and a memory7unit communicatively coupled to the processing unit. The memory unit includes a delay optimization module configured to identify at least one circuit topology’ from a plurality’ of circuit topologies in an electronic circuit design, based on a netlist and a timing data file. In an embodiment, the delay optimization module identifies the at least one circuit topology from the plurality7of circuit topologies in the circuit design, based on presence of a common source pin.

[0009] The delay optimization module is further configured to determine one or more non- critical pins from the identified circuit topology7, based on delay corresponding to each of thepins in the identified circuit topology. In an embodiment, the delay optimization module determines the one or more non-critical pins present in the circuit topology by predicting arrival time of a signal at each pin along at least one levelized signal path associated with the circuit topology, based on the delay corresponding to each of the pins along the levelized signal path. The levelized signal path is a signal path between the common source pin and a destination pin associated with the circuit topology, and the arrival time of the signal at each pin is predicted with reference to the common source pin. In a further embodiment, predicting arrival time of the signal at each pin along the at least one levelized signal path associated with the circuit topology includes tagging each of the pins in the circuit topology to a unique identifier, where the unique identifier identifies a relative position of the tagged pin, within the circuit topology. Further, each of the unique identifiers is stored against the delay associated with the respective pin, within a predetermined data structure. The unique identifiers corresponding to each of the pins in the levelized signal path is further used to annotate delays corresponding to each of the pins. Further, the arrival time of the signal at each of the pins in the levelized signal path is predicted, based on a cumulative delay at the pin, with reference to the common source pin.

[0010] If the arrival time predicted for the pin in the levelized signal path is greater than an expected arrival time for the pin, the delay optimization module determines the pin to be a critical pin. Otherwise, the delay optimization module determines the pin to be a non-critical pin. In an embodiment, the expected arrival time is determined based on one or more constraints defined for the pins present along the levelized signal path, in the timing data file.

[0011] The delay optimization module is further configured to generate a modified timing data file based on determination of the one or more non-critical pins, where the delay associated with each of the non-critical pins is set to zero in the modified timing data file. In an embodiment, delay optimization module is further configured to perform a gate-level simulation for the at least one circuit topology based on the modified timing data file.

[0012] In yet another aspect, a non-transitory computer-readable storage medium having machine-readable instructions stored therein, that when executed by a system, cause the system to perform a method of managing gate level simulation of an electronic circuit design as described above, is provided.

[0013] This summary is provided to introduce a selection of concepts in a simplified form that are further described below7in the following description. The summary is not intended to identify features or essential features of the claimed subject matter. Further, the claimed subject matter is not limited to implementations that solve any or all disadvantages noted in any part of this disclosure.BRIEF DESCRIPTION OF THE FIGURES

[0014] Figure 1 is a block diagram of a data processing system for managing gate level simulation of an electronic circuit, according to one embodiment.

[0015] Figure 2 is a process flowchart of an example method of managing gate level simulation of an electronic circuit, according to one embodiment.

[0016] Figures 3 A-C illustrate an example of predicting arrival time of a signal at a pin within a circuit topology, according to one embodiment.

[0017] Figure 4 is a block diagram of a data processing system for managing gate level simulation of an electronic circuit, according to another embodiment.

[0018] Figure 5 is a block diagram of a data processing system for managing gate level simulation of an electronic circuit, according to yet another embodiment.DETAILED DESCRIPTION

[0019] A method and system for managing gate level simulation of an electronic circuit is disclosed. Various embodiments are described with reference to the drawings, where like reference numerals are used in reference to the drawings. Like reference numerals are used to refer to like elements throughout. In the following description, numerous specific details are set forth in order to provide a thorough understanding of embodiments. These specific details need not be employed to practice embodiments. In other instances, well known materials or methods have not been described in detail in order to avoid unnecessarily obscuring embodiments. While the disclosure is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. There is no intent to limit the disclosure to the particular forms disclosed. Instead, the disclosure is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure.

[0020] Figure 1 is a block diagram of an example data processing system 100 for managing gate level simulation of an electronic circuit, according to one embodiment. The data processing system 100 may be a personal computer, workstation, laptop computer, tablet computer, and the like. In Figure 1. the data processing system 100 includes a processing unit 102, a memory 104, a storage unit 106, a bus 108, an input unit 110, and a display unit 112. The data processing system 100 is a specific purpose computer configured to manage gate level simulation of the electronic circuit.

[0021] The processing unit 102, as used herein, may be any type of computational circuit, such as, but not limited to, a microprocessor, microcontroller, complex instruction setcomputing microprocessor, reduced instruction set computing microprocessor, very long instruction word microprocessor, explicitly parallel instruction computing microprocessor, graphics processor, digital signal processor, or any other type of processing circuit. The processing unit 102 may also include embedded controllers, such as generic or programmable logic devices or arrays, application specific integrated circuits, single-chip computers, and the like.

[0022] The memory 104 may be non-transitory volatile memory and non-volatile memory. The memory 104 may be coupled for communication with the processing unit 102, such as being a computer-readable storage medium. The processing unit 102 may execute instructions and / or code stored in the memory 104. A variety of computer-readable instructions may be stored in and accessed from the memory 104. The memory 104 may include any’ suitable elements for storing data and machine-readable instructions, such as read only memory, random access memory', erasable programmable read only memory', electrically erasable programmable read only memory', a hard drive, a removable media drive for handling compact disks, digital video disks, diskettes, magnetic tape cartridges, memory cards, and the like.

[0023] In the present embodiment, the memory 104 includes a delay optimization module 114 stored in the form of machine-readable instructions on any of the above-mentioned storage media and may be in communication with and executed by the processing unit 102. When the machine-readable instructions are executed by the processing unit 102, the delay optimization module 114 causes the processing unit 102 to: identify at least one circuit topology from a plurality of circuit topologies in an electronic circuit design, based on a netlist and a timing data file, to determine one or more non-critical pins from the identified circuit topology, based on delay corresponding to each of the pins in the identified circuit topology'; and generate a modified timing data file based on determination of the one or more non-critical pins. The delay associated with each of the non-critical pins is set to zero in the modified timing data file. Method acts performed by the processing unit 102 to achieve the above functionality are described in greater detail in Figure 2.

[0024] The storage unit 106 may be a non-transitory storage medium that stores a netlist file database 116 and the timing data file database 118. The netlist file database 116 stores netlists including circuit topologies corresponding to one or more electronic circuit designs. The timing data file database 118 is for timing data files (e.g., SDF files) corresponding to the one or more electronic circuit designs. The input unit 110 may include input devices such as keypad, touch-sensitive display, camera (e.g., a camera receiving gesture-based inputs), etc. capable of receiving input signals such as a command for generating optimized simulationmodels. The display unit 112 may be a device with a graphical user interface displaying an output indicative of an optimized simulation model, simulation time corresponding to the optimized simulation model, etc. The graphical user interface may also enable users to select or upload netlist files or timing data files corresponding to an electronic circuit design. The bus 108 acts as interconnect between the processing unit 102, the memory 104, the storage unit 106, the input unit 110, and the display unit 112.

[0025] Those of ordinary skilled in the art will appreciate that the hardware depicted in F igure 1 may vary for particular implementations. For example, other peripheral devices such as an optical disk drive and the like, Local Area Network (LAN) / Wide Area Network (WAN) / Wireless (e.g., Wi-Fi) adapter, graphics adapter, disk controller, input / output (I / O) adapter also may be used in addition to or in place of the hardware depicted. The depicted example is provided for the purpose of explanation only and is not meant to imply architectural limitations with respect to the present disclosure.

[0026] The data processing system 100 in accordance with an embodiment of the present disclosure includes an operating system employing a graphical user interface. The operating system permits multiple display windows to be presented in the graphical user interface simultaneously with each display window providing an interface to a different application or to a different instance of the same application. A cursor in the graphical user interface may be manipulated by a user through the pointing device. The position of the cursor may be changed and / or an event such as clicking a mouse button may be generated to actuate a desired response.

[0027] One of various commercial operating systems, such as a version of Microsoft Windows™, a product of Microsoft Corporation located in Redmond, Washington may be employed if suitably modified. The operating system is modified or created in accordance with the present disclosure as described.

[0028] Figure 2 is a process flowchart 200 of an example method of managing gate level simulation of an electronic circuit, according to one embodiment.

[0029] At act 202, at least one circuit topology is identified, by a processing unit, from a plurality of circuit topologies in an electronic circuit design, based on a netlist and a timing data file. In an embodiment, the at least one circuit topology is identified from the plurality of circuit topologies in the electronic circuit design, based on presence of a common source pin. The common source pin serves as a reference to all timing events in the circuit topology. In other words, the common source pin acts a source of a common input to the circuit in the circuit topology. However, a circuit topology may have one or more destination pins that serve as output points from the circuit. For example, in Figure 3A, the input pin to the gate bO serves asthe common source pin for the circuit topology 300 shown. However, if the gate bO were not connected to gate bl, and if both bO and bl were configured to receive different inputs, then the electronic circuit design may include two circuit topologies: a first circuit topology with the input pin to bO as source pin; and a second circuit topology with the input pin to bl as source pin. However, outputs from the latches uO, ul, u2 and u3 may act as destination pins.

[0030] At act 204, one or more non-critical pins present in the circuit topology are determined, based on delay corresponding to each of the pins in the identified circuit topology. In an embodiment, determining the non-critical pins includes, first, predicting arrival time of a signal at each pin along at least one levelized signal path associated with the circuit topology7, based on the delay corresponding to each of the pins along the levelized signal path. The levelized signal path is a signal path between the common source pin and a destination pin associated with the circuit topology. The arrival time of the signal at each pin is predicted with reference to the common source pin.

[0031] To predict the arrival time at each of the pins, first, each of the pins in the circuit topology is tagged to a unique identifier. The unique identifier identifies a relative position of the tagged pin, within the circuit topology. In an embodiment, the unique identifier is a path key integer computed based on data present in the timing data file and the netlist file. Since a pin (e.g., the output pin of gate bO in Figure 3A) may be associated with a plurality7of levelized paths within the circuit topology, the pin may have a plurality of path key integers corresponding to each of the levelized paths. For example, the number of path keys corresponding to a pin may equal to the fan in value for input pins and fan out values for output pins. In an implementation, the path key integer ‘path_key’ corresponding to a pin for a specific levelized path is computed as below: path_key = DC*def_id + SIC*src_rel_lwt_id +DIC*dst_rel_lwt_id + SPC*src_pin_id + DPC*dst_pin_id + path ty pe where, DC, SIC, DIC, SPC, DPC are definitional variant properties identified from the netlist file, and are defined as below: DC -DC- Design Coefficient SIC- Source Instance CoefficientDIC- Destination Instance CoefficientSPC- Source Pin CoefficientDPC- Destination Pin Coefficient

[0032] The variables def id, src rel lwt id and dst rel lwt id are obtained from the netlist file, and are defined as below: def_id - Delay definition identifier or an identifier of the timing data file. It may also be an order in which a plurality' of timing data files are provided via the input device. src_rel_lwt_id - offset of an index of the source instance data in a light-weight tree (LWT) array of signal path with respect to the first child of its parent. The LWT array is a data structure used to represent the design hierarchy present in the netlist, as shown in Figure 3B. dst_rel_lwt_id - offset of the index of the destination instance data in the LWT array of signal path with respect to the first child of its parent.

[0033] The variables src_pin_id, dst_pin_id and path type are obtained from the timing data file, and are defined as below: src_pin_id - source pin identifier dst_pin_id - destination pin identifier path type - delay t pe of the signal path

[0034] Each of the variables def id, src rel lwt id. dst rel lwt id, src _pin_id, ds I _pin_id and path type are integer variables. For example, src _pin_id = 0 indicates a D input, whereas src_pin_id = 2 indicates a clock (CLK) input. The path key integer is, therefore, a unique linear combination of information obtained from the netlist file and the timing data file.

[0035] Each of the unique identifiers is stored against the delay associated with the respective pin, within a predetermined data structure. In an embodiment, the predetermined data structure is a graph data structure. The graph data structure may be, for example, the light-weight tree (LWT) structure that is used to represent the design hierarchy based on the netlist file. In an example, each node on the LWT is representative of a design element (e.g., latch, gate, or flipflop) within the circuit topology. The unique identifiers corresponding to each of the pins in the levelized signal path is used to annotate delays corresponding to each of the pins. In the present example of the LWT, each of the nodes includes path keys and delay corresponding to input or output pins of the design element. Figure 3B shows an example of a LWT for the circuit topology in Figure 3A. The LWT corresponds to a ‘top' node that has two child nodes ‘dul ’ and ‘du2’. each of which represents a different electronic circuit design including the design elements bO, bl, uO, ul, u2, and u3. The first node corresponding to electronic circuitdesign ‘dul' corresponds to the gate bO, and includes an array of values [2856:0.010, 3162:0.010, 6460:0.051], Here, 6460 represents path key corresponding to input pin of bO and is tagged with a delay of 0.051, whereas 2856 represents path key corresponding to output pin of bO on the levelized signal path between bO and ul, and is tagged with a delay of 0.010. Similarly, the output pin of bO has another path key 3162 and delay 0.010 for the levelized signal path between (e.g., between bO and u2). Figure 3C shows a levelized path between bO and ul. Based on the unique identifiers and corresponding delays in the LWT, the arrival time of the signal at of the pins in the levelized signal path is predicted, based on cumulative delays at the pin, with reference to the common source pin. In the present example, the common source pin corresponds to the input pin to bO. For ease of explanation, the pins may be identified using the respective path key / unique identifier. The delay at the input pin of bO (e.g., pin 6460 is 0.051). However, as the pin 6460 is the common source pin (e.g., the reference for all signals in the circuit topology), the arrival time at the pin 6460 is zero. The next pin along the levelized path is the output pin of bO (e.g., pin 2856), with corresponding delay as 0.010. Therefore, the arrival time at the output pin of bO is 0.051+0.01 = 0.061 (e.g., the cumulative delay based on delays at the input and output pins of bO). Similarly, the cumulative delay at the output pm of bl is 0.112 and so on. The cumulative delay at each of the pins equal the arrival time of the signal at the pin.

[0036] The netlist file only includes relationships between pins in the electronic circuit design, and no information on the delays corresponding to the pins, whereas the timing data file includes information related to delays and constraints corresponding to the pins. Therefore, it is necessary to correlate pins from the netlist file and the respective delays of the pins from the timing data file, to predict the arrival time of a signal at a pin with respect to the common source pin. The present embodiments establish the correlation between pins and delays by tagging the unique identifier of the pin to the respective delay within the predetermined data structure, in order to enable prediction of arrival time of a signal at different pins along a levelized signal path, before the simulation happens.

[0037] The arrival time at each pin is advanced with the delay at the previous pin. If there is a timing check associated with the pin in the timing data file, a slack value is computed based on the arrival time at the pin and an expected arrival time in the timing check. For example, the slack value is computed as a difference between the expected arrival time and the arrival time predicted for the pin. If the slack value is negative (e.g., ETA is less than AT), the pin is identified as a critical pin. In other words, if the arrival time predicted for the pin in the levelized signal path is greater than the expected arrival time for the pin, the pin is a critical pin.Otherwise, the pin is determined to be a non-critical pin. In an embodiment, the expected arrival time is determined based on one or more constraints defined for the pins present along the levelized signal path, in the timing data file.

[0038] At act 206, a modified timing data file is generated based on determination of the one or more non-critical pins, where the delay associated w ith each of the non-critical pins is set to zero in the modified timing data file. In an embodiment, delay for all non-critical pins is reset to zero, in the timing data file, in order to generate the modified timing data file. This removes dependency on timing checks for the non-critical pins, thereby reducing overall time required for performing the gate-level simulation. In a further embodiment, the netlist file is also updated with respect to the modified timing data file to update the simulation model to reflect the zero delays.

[0039] In a further embodiment, gate level simulation is performed on one or more circuit topologies of the plurality of circuit topologies using the generated modified timing data file in such a manner that gate level simulation is optimized by skipping timing checks for non-critical pins.

[0040] Figure 4 is a schematic representation of a data processing system 400 for managing gate level simulation of an electronic circuit, according to another embodiment. For example, the data processing system 400 includes a cloud computing system 402 configured for providing cloud services for designing geometric components.

[0041] The cloud computing system 402 includes a cloud communication interface 406, cloud computing hardware and OS 408, a cloud computing platform 410, the delay optimization module 114, the netlist file database 116, and the timing data file database 118. The cloud communication interface 406 enables communication between the cloud computing platform 410, and user devices 412A-N such as smart phone, tablet, computer, etc. via a network 404.

[0042] The cloud computing hardware and OS 408 may include one or more servers on which an operating system (OS) is installed and includes one or more processing units, one or more storage devices for storing data, and other peripherals required for providing cloud computing functionality. The cloud computing platform 410 is a platform that implements functionalities such as data storage, data analysis, data visualization, data communication on the cloud hardware and OS 408 via APIs and algorithms, and delivers the aforementioned cloud services using cloud-based applications (e.g., timing aware gate level simulation applications). The cloud computing platform 410 employs the delay optimization module 114 for generating a modified timing data file for a given circuit topology as described in Figure 2.

[0043] In accordance with the foregoing embodiments, the cloud computing system 402 mayenable users to generate updated netlists based on the modified timing data file. For example, the delay optimization module 114 identifies non-critical pins in the circuit topology based on delays in signal paths within the circuit topology. If there are non-critical pins, the delay associated with such pins are reduced to zero, so that timing checks associated with the pins may be skipped during the gate-level simulation.

[0044] The user devices 412A-N include graphical user interfaces 414A-N for receiving inputs required for generation of modified timing data file. Each of the user devices 412A-N may be provided with a communication interface for interfacing with the cloud computing system 402. Users of the user devices 412A-N may access the cloud computing system 402 via the graphical user interfaces 414A-N. For example, the users may send request to the cloud computing system 402 to generate modified timing data file. The graphical user interfaces 414A-N may be specifically designed for accessing the delay optimization module 114 in the cloud computing system 402.

[0045] Figure 5 illustrates a block diagram of a data processing system 500 for managing gate level simulation of an electronic circuit, according to yet another embodiment. For example, the data processing system 500 includes a server 502 and a plurality of user devices 506A-N. Each of the user devices 506A-N is connected to the server 502 via a network 504 (e.g., Local Area Network (LAN), Wide Area Network (WAN), Wi-Fi, etc.). The data processing system 500 is another implementation of the data processing system 100 of Figure 1, where the delay optimization module 114 resides in the server 502 and is accessed by user devices 506A-N via the network 504.

[0046] The server 502 includes the delay optimization module 114, the netlist file database 116, and the timing data file database 118. The server 502 may also include a processor, a memory, and a storage unit. The delay optimization module 114 may be stored on the memory in the form of machine-readable instructions and executable by the processor. The netlist file database 116 and the timing data file database 118 may be stored in the storage unit. The server 502 may also include a communication interface for enabling communication with client devices 506 A-N via the network 504.

[0047] When the machine-readable instructions are executed, the delay optimization module 1 14 causes the server 502 to generate modified timing data file for a given circuit topology, and / or perform timing-aware gate level simulation for the circuit topology' based on the modified timing data file. Method acts performed by the server 502 to achieve the above- mentioned functionality are described in greater detail in Figure 2.

[0048] The user devices 506A-N include graphical user interfaces 508A-N for receivinginputs required for generation of modified timing data files. Each of the user devices 506A-N may be provided with a communication interface for interfacing with the server 502. Users of the user devices 506A-N may access the server 502 via the graphical user interfaces 508A-N. For example, the users may send request to the serv er 502 to generate a modified timing data file for a given circuit topology. The graphical user interfaces 508A-N may be specifically designed for accessing the delay optimization module 114 in the server 502.

[0049] The present embodiments enable calculation of arrival time corresponding to different pins, by mapping pins from a design hierarchy indicated by the netlist to delays present in the timing data file. Further, the present embodiments reduce time required for gate level simulation of an electronic circuit design compared to existing art, by removing dependency on timing checks for non-critical pins. For example, timing checks corresponding to the pins are automatically analyzed prior to the gate level simulation, without the need for manual intervention, in order to identify the non-critical pins.

[0050] Those skilled in the art will recognize that, unless specifically indicated or required by the sequence of operations, certain acts in the processes described above may be omitted, performed concurrently or sequentially, or performed in a different order.

[0051] Those skilled in the art will recognize that, for simplicity and clarity, the full structure and operation of all data processing systems suitable for use with the present disclosure is not being depicted or described herein. Instead, only so much of a data processing system as is unique to the present disclosure or necessary for an understanding of the present disclosure is depicted and described. The remainder of the construction and operation of the data processing system may conform to any of the various current implementation and practices know n in the art.

[0052] It is to be understood that the system and methods described herein may be implemented in various forms of hardware, software, firmw are, special purpose processors, or a combination thereof. One or more of the present embodiments may take a form of a computer program product including program modules accessible from computer-usable or computer- readable medium storing program code for use by or in connection with one or more computers, processors, or instruction execution system. For the purpose of this description, a computer- usable or computer-readable medium may be any apparatus that may contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The medium may be electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus or device), or propagation mediums in and of themselves as signal carriers are not included in the definitionof physical computer-readable medium including a semiconductor or solid state memory, magnetic tape, a removable computer diskette, random access memory (RAM), a read only memory (ROM), a rigid magnetic disk and optical disk such as compact disk read-only memory (CD-ROM), compact disk read / write, and digital versatile disc (DVD). Both processors and program code for implementing each aspect of the technology may be centralized or distributed (or a combination thereof) as known to those skilled in the art.

[0053] While the present disclosure has been described in detail with reference to certain embodiments, it should be appreciated that the present disclosure is not limited to those embodiments. In view of the present disclosure, many modifications and variations would be present themselves, to those skilled in the art without departing from the scope of the various embodiments of the present disclosure, as described herein. The scope of the present disclosure is, therefore, indicated by the following claims rather than by the foregoing description. All changes, modifications, and variations coming within the meaning and range of equivalency of the claims are to be considered within their scope.

Claims

CLAIMS:1 . A method for managing gate level simulation, the method being computer-implemented and comprising: identifying, by a processing unit, at least one circuit topology from a plurality of circuit topologies in an electronic circuit design, based on a netlist and a timing data file; determining one or more non-critical pins from the identified at least one circuit topology, based on delay corresponding to each of the one or more non-critical pins in the identified at least one circuit topology; and generating a modified timing data file based on the determining of the one or more non- critical pins, wherein the delay associated with each of the one or more non-critical pins is set to zero in the modified timing data file.

2. The method of claim 1, wherein the at least one circuit topology is identified from the plurality of circuit topologies in the electronic circuit design, based on presence of a common source pin.

3. The method of claim 2, wherein determining the one or more non-critical pins comprises: predicting arrival time of a signal at each pin of the one or more non-critical pins along at least one levelized signal path associated with the at least one circuit topology, based on the delay corresponding to each of the one or more non-critical pins along the at least one levelized signal path, wherein the at least one levelized signal path is at least one signal path between the common source pin and a destination pin associated with the at least one circuit topology, and wherein the arrival time of the signal at each pin of the one or more non-critical pins is predicted with reference to the common source pin; when the arrival time predicted for the respective pin in the levelized signal path is greater than an expected arrival time for the respective pin, determining that the respective pin is a critical pin; and when the arrival time predicted for the respective pin in the levelized signal path is less than the expected arrival time for the respective pin, determining that the respective pin is a non-critical pin.

4. The method of claim 3, wherein the expected arrival time is determined based on one or more constraints defined for the one or more non-critical pins present along the at least one levelized signal path, in the timing data file.

5. The method of claim 3, wherein predicting the arrival time of the signal at each pin along the at least one levelized signal path associated with the at least one circuit topology, based on the delay corresponding to each of the one or more non-critical pins along the at least one levelized signal path comprises: tagging each of the one or more non-critical pins in the at least one circuit topology7to a unique identifier, wherein the unique identifier identifies a relative position of the respective tagged pin within the at least one circuit topology; storing each of the unique identifiers against the delay associated with the respective pin, within a predetermined data structure; using the unique identifiers corresponding to each of the one or more non-critical pins in the at least one levelized signal path to annotate delays corresponding to each of the one or more non-critical pins; and predicting the arrival time of the signal at each of the one or more non-critical pins in the at least one levelized signal path, based on a cumulative delay at the respective pin, with reference to the common source pin.

6. The method of claim 1 , further comprising: performing a gate-level simulation for the at least one circuit topology based on the modified timing data file.

7. A system comprising: a processing unit; and a memory unit communicatively coupled to the processing unit, wherein the memory unit comprises: a delay optimization module configured to: identify at least one circuit topology from a plurality of circuit topologies in an electronic circuit design, based on a netlist and a timing data file; determine one or more non-critical pins from the identified at least one circuit topology, based on delay corresponding to each of the one or more non-critical pins in the identified at least one circuit topology; andgenerate a modified timing data file based on the determination of the one or more non-critical pins, wherein the delay associated with each of the one or more non- critical pins is set to zero in the modified timing data file.

8. The system of claim 7, wherein the at least one circuit topology' is identified from the plurality of circuit topologies in the electronic circuit design based on presence of a common source pin.

9. The system of claim 8, wherein the delay optimization module being configured to determine the one or more non-critical pins comprises the delay optimization module being configured to: predict arrival time of a signal at each pin of the one or more non-critical pins along the at least one levelized signal path associated with the at least one circuit topology, based on the delay corresponding to each of the one or more non-critical pins along the at least one levelized signal path, wherein the at least one levelized signal path is at least one signal path between the common source pin and a destination pin associated with the at least one circuit topology, and wherein the arrival time of the signal at each pin of the one or more non-critical pins is predicted with reference to the common source pin; when the arrival time predicted for the respective pin in the at least one levelized signal path is greater than an expected arrival time for the respective pin, determine that the respective pin is a critical pin; and when the arrival time predicted for the respective pin in the at least one levelized signal path is less than an expected arrival time for the respective pin, determine that the respective pin is a non-critical pin.

10. The system of claim 9, wherein the expected arrival time is determined based on one or more constraints defined for the one or more non-critical pins present along the at least one levelized signal path, in the timing data file.1 1. The system of claim 7, wherein the delay optimization module being configured to predict the arrival time of the signal at each pin of the one or more non-critical pins along the at least one levelized signal path associated with the at least one circuit topology comprises the delay optimization module being configured to: tag each of the one or more non-critical pins in the at least one circuit topology to aunique identifier, wherein the unique identifier identifies a relative position of the respective tagged pin. within the at least one circuit topology; store each of the unique identifiers against the delay associated with the respective pin, within a predetermined data structure; use the unique identifiers corresponding to each of the one or more non-critical pins in the at least one levelized signal path to annotate delays corresponding to each of the one or more non-critical pins; and predict the arrival time of the signal at each of the one or more non-critical pins in the at least one levelized signal path, based on a cumulative delay at the respective pin, with reference to the common source pin.

12. The system of claim 7, wherein the delay optimization module is further configured to: perform a gate-level simulation for the at least one circuit topology' based on the modified timing data file.

13. A non-transitory computer-readable storage medium that stores machine-readable instructions executable by a system to manage gate level simulation, the machine-readable instructions comprising: identifying at least one circuit topology from a plurality of circuit topologies in an electronic circuit design, based on a netlist and a timing data file; determining one or more non-critical pins from the identified at least one circuit topology, based on delay corresponding to each of the one or more non-critical pins in the identified at least one circuit topology; and generating a modified timing data file based on the determining of the one or more non- critical pins, wherein the delay associated with each of the one or more non-critical pins is set to zero in the modified timing data file.

14. The non-transitory computer-readable storage medium of claim 13, wherein the at least one circuit topology is identified from the plurality7of circuit topologies in the electronic circuit design based on presence of a common source pin.

15. The non-transitory computer-readable storage medium of claim 14, wherein determining the one or more non-critical pins comprises:predicting arrival time of a signal at each pin of the one or more non-critical pins along at least one levelized signal path associated with the at least one circuit topology, based on the delay corresponding to each of the one or more non-critical pins along the at least one levelized signal path, wherein the at least one levelized signal path is at least one signal path between the common source pin and a destination pin associated with the at least one circuit topology', and wherein the arrival time of the signal at each pin of the one or more non-critical pins is predicted with reference to the common source pin; when the arrival time predicted for the respective pin in the at least one levelized signal path is greater than an expected arrival time for the respective pin, determining that the respective pin is a critical pin; and when the arrival time predicted for the respective pin in the at least one levelized signal path is less than the expected arrival time for the respective pin, determining that the respective pin is a non-critical pin.

16. The non-transitory computer-readable storage medium of claim 15, wherein the expected arrival time is determined based on one or more constraints defined for the one or more non-critical pins present along the at least one levelized signal path, in the timing data file.

17. The non-transitory computer-readable storage medium of claim 15, wherein predicting the arrival time of the signal at each pin of the one or more non-critical pins along the at least one levelized signal path associated with the at least one circuit topology, based on the delay corresponding to each of the one or more non-critical pins along the at least one levelized signal path comprises: tagging each of the one or more non-critical pins in the at least one circuit topology to a unique identifier, wherein the unique identifier identifies a relative position of the respective tagged pin, within the at least one circuit topology ; storing each of the unique identifiers against the delay associated with the respective pin, within a predetermined data structure; using the unique identifiers corresponding to each of the one or more non-critical pins in the at least one levelized signal path to annotate delays corresponding to each of the one or more non-critical pins; and predicting the arrival time of the signal at each of the one or more non-critical pins in the at least one levelized signal path, based on a cumulative delay at the respective pin, withreference to the common source pin.

18. The storage medium of claim 13, wherein the system is further configured to perform a gate-level simulation for the at least one circuit topology based on the modified timing data file.

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