Semiconductor device

Abstract

According to one embodiment, a semiconductor device 1 comprises a stack of layers including a conductive substrate CS containing a semiconductor material and comprising a first main surface S1 having one or more recesses TR and a second main surface S2 opposite the first main surface S1, a conductive layer 20b covering at least a portion of the first main surface S1 and the side walls and lower surfaces of the recess(es) TR, and a dielectric layer 30 interposed between the conductive substrate CS and the conductive layer 20b, the conductive layer 20b and a portion of the conductive substrate CS adjacent to the dielectric layer 30 being an upper electrode and a lower electrode of a capacitor C, respectively, an insulating layer 60a disposed on the capacitor C or on the second main surface S2,and an inductance L1 disposed on the insulating layer 60a at a position of the capacitor C. Figure 2,

Description

Description Title of the invention: Semiconductor device Domain The embodiments described here generally relate to a semiconductor device. Background A combination of a capacitor and an inductor is sometimes used in an LC filter. An LC filter allows components in a specific frequency band of an electrical signal from or to an integrated circuit (IC) to pass through while blocking components in the other frequency band as noise. Brief description of the drawings [Fig.1] Fig.1 is a top view of a semiconductor device according to one embodiment: [Fig.2] The [Fig.2] is a cross-sectional view of the semiconductor device shown in the [Fig.1], taken along line II-II; [Fig.3] Fig.3 is a cross-sectional view showing an example of an integrated circuit package including the semiconductor device shown in Figures 1 and 2: [Fig.4] The [Fig.4] is an equivalent circuit diagram of the integrated circuit package shown in the [Fig.3]; [Fig.5] The [Fig.5] is a cross-sectional view showing a process in the fabrication of the semiconductor device shown in Figures 1 and 2; [Fig.6] The [Fig.6] is a cross-sectional view showing another process in the manufacture of the semiconductor device shown in Figures 1 and 2; [Fig.7] Fig.7 is a cross-sectional view showing yet another process in the fabrication of the semiconductor device shown in Figures 1 and 2: [Fig. 8] Fig. 8 is a plan view showing an inductor according to a modification; and [Fig.9] The [Fig.9] is an equivalent circuit diagram of an integrated circuit package according to a modification. Detailed description Embodiments will be described in detail below with reference to the accompanying drawings. Component elements that have the same function or similar functions are assigned the same reference numbers in all drawings, and the des- Redundant descriptions will be omitted. <Dispositif semi-conducteur> A semiconductor device according to an embodiment comprises a stack of layers including a conductive substrate containing a semiconductor material and comprising a first principal surface having one or more recesses and a second principal surface opposite the first principal surface, a conductive layer covering at least a portion of the first principal surface and the side walls and bottom surfaces of the recess or recesses, and a dielectric layer interposed between the conductive substrate and the conductive layer, the conductive layer and a portion of the conductive substrate adjacent to the dielectric layer constituting an upper electrode and a lower electrode of a capacitor, respectively, an insulating layer disposed on the capacitor or on the second principal surface, and an inductor disposed on the insulating layer at a certain position of the capacitor. Figures 1 and 2 show a semiconductor device according to one embodiment. A semiconductor device 1 shown in Figures 1 and 2 comprises a conductive substrate CS, a conductive layer 20b, and a dielectric layer 30, as shown in [Fig. 2]. The conductive layer 20b and a portion of the conductive substrate CS adjacent to the dielectric layer 30 constitute, respectively, an upper electrode and an electrode of a capacitor C. In each figure, the X direction is parallel to a principal surface of the conductive substrate CS, and the Y direction is perpendicular to the X direction and parallel to the principal surface of the conductive substrate CS. The Z direction is the direction of the thickness of the conductive substrate CS, that is, a direction perpendicular to both the X and Y directions. The CS conductive substrate contains a semiconductor material such as silicon. The CS conductive substrate is a substrate with electrical conductivity, at least on its surface facing the conductive layer 20b. As mentioned above, a portion of the CS conductive substrate serves as the lower electrode of capacitor C. The conductive substrate CS has a first principal surface S1, a second principal surface S2, which is opposite the first principal surface S1, and an end surface extending from an edge of the first upper surface S1 to an edge of the second principal surface S2. Here, the conductive substrate CS has a flat shape and is approximately a rectangular parallelepiped. The conductive substrate CS can have other shapes. The first principal surface S1, which here is the upper surface of the conductive substrate CS, comprises a first region A1 and a second region A2. The first region A1 and the second region A2 are adjacent to each other. Here, the first region A1 is rectangular, and the second region A2 surrounds the first region A1. In the first region A1, a plurality of TR recesses, each with a shape extending in a certain direction and arranged in the width direction, are present. The TR recesses are spaced apart. Here, these TR recesses constitute a plurality of trenches extending in the Y direction and arranged in the X direction. Portions of the conductive substrate, each sandwiched between two adjacent recesses TR, constitute protrusions. Each protrusion has a shape extending in the Y direction and is arranged in the X direction. Specifically, in the first region Al, a plurality of wall portions, each having a shape extending in the Y and Z directions and arranged in the X direction, are present as protrusions. The "length direction" of the recesses or projections is the length direction of orthogonal projections of the recesses or projections onto a plane perpendicular to the thickness direction of the conductive substrate. The length of an opening of each TR recess is located in the range from 5 µm to 500 µm according to one example, and in the range from 50 µm to 100 µm according to another example. The width of the TR recess opening, that is, the distance between adjacent protrusions in the width direction, is preferably 0.3 µm or greater. Reducing this width or distance allows for greater electrical capacitance. However, reducing this width or distance makes it difficult to form a stacked structure comprising the dielectric layer 30 and the conductive layer 20b within the TR recesses. The depth of the TR recesses or the height of the protrusions is located in the range from 5 µm to 300 µm according to one example, and in the range from 50 µm to 100 µm according to another example. The distance between adjacent TR recesses in the width direction, i.e., the thickness of each protrusion, is preferably 0.1 µm or more. Reducing this distance or thickness can result in higher electrical capacitance. However, reducing this distance or thickness also increases the susceptibility of the protrusions to damage. Here, the cross-sections of the TR recesses perpendicular to the length direction are rectangular. However, these cross-sections do not need to be rectangular. For example, these cross-sections can have a tapered shape. Here, a plurality of trenches are present as TR recesses; However, one or more recesses may be present in such a way that a plurality of pillar-shaped projections are formed. The CS conductive substrate comprises a substrate 10 and a conductive layer 20a. Substrate 10 has a shape similar to that of the CS conductive substrate. Substrate 10 is a substrate containing a semiconductor material, such as a semiconductor substrate. Substrate 10 is preferably a substrate containing silicon, such as a silicon substrate. Such a substrate can be transformed using semiconductor processing. The conductive layer 20a is arranged on the substrate 10. The conductive layer 20a serves as the lower electrode of the capacitor C. The conductive layer 20a is made, for example, of silicon or polysilicon doped with impurities to improve electrical conductivity, or of a metal such as molybdenum, aluminum, gold, tungsten, platinum, nickel, or copper, or an alloy thereof. The conductive layer 20a can have a monolayer or multilayer structure. The thickness of the conductive layer 20a is preferably in the range of 0.05 µm to 10 µm, and even better in the range of 0.1 µm to 5 µm. If the conductive layer 20a is thin, a discontinuous portion may be created within it, or the foil resistance of the conductive layer 20a may become excessively high. If the conductive layer 20a is thickened, manufacturing costs increase. For example, let us assume that substrate 10 is a semiconductor substrate such as a silicon substrate, and that the conductive layer 20a is a highly concentrated doped layer obtained by doping a surface region of the semiconductor substrate with impurities at a high concentration. In this case, the protrusions, if sufficiently thin, can be completely doped with impurities at a high concentration. The conductive layer 20b serves as the upper electrode of the capacitor. The conductive layer 20b is located on the first region A1, and covers the side walls and lower surfaces of the recesses TR. The conductive layer 20b is made, for example, of polysilicon doped with impurities to improve electrical conductivity, or of a metal such as molybdenum, aluminum, gold, tungsten, platinum, nickel, or copper, or an alloy thereof. The conductive layer 20b can have a single-layer or multi-layer structure. The thickness of the conductive layer 20b is preferably in the range of 0.05 µm to 3 µm, and even better in the range of 0.1 µm to 1.5 µm. If the conductive layer 20b is thin, a discontinuous portion may be generated in the The conductive layer 20b, or the foil resistance of the conductive layer 20b, may become excessively high. If the conductive layer 20b is thick, it may be difficult to form the conductive layer 20a and the dielectric layer 30 with sufficient thicknesses. In [Fig. 2], the conductive layer 20b is arranged so that the recesses TR are completely filled with both the conductive layer 20b and the dielectric layer 30. The conductive layer 20b can conform to the surface of the conductive substrate CS. Specifically, the conductive layer 20b can have an approximately uniform thickness. In this case, the recesses TR are not completely filled with both the conductive layer 20b and the dielectric layer 30. The dielectric layer 30 is positioned between the conductive substrate CS and the conductive layer 20b. The dielectric layer 30 conforms to the surface of the conductive substrate CS. The dielectric layer 30 electrically isolates the conductive substrate CS and the conductive layer 20b from each other. The capacitor C is a stack of the conductive layer 20a, the dielectric layer 30, and the conductive layer 20b. The dielectric layer 30 is made, for example, of an organic or inorganic dielectric. As an organic dielectric, for example, polyimide can be used. As an inorganic dielectric, a ferroelectric can be used; however, paraelectrics such as silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, and tantalum oxide are preferable. These paraelectrics exhibit a small change in dielectric constant with temperature. Therefore, when paraelectrics are used for the dielectric layer 30, the heat resistance of the semiconductor device 1 can be improved. The thickness of the dielectric layer 30 is preferably in the range of 0.005 µm to 0.5 µm, and even better in the range of 0.01 µm to 0.1 µm. If the dielectric layer 30 is thin, a discontinuous portion may be generated within it, and the conductive substrate CS and the conductive layer 20b may be short-circuited. Furthermore, if the dielectric layer 30 is thinned, the withstand voltage drops even without a short circuit, and the possibility of a short circuit occurring when a voltage is applied increases. If the dielectric layer 30 is thickened, the withstand voltage increases, but the electrical capacitance decreases. The dielectric layer 30 is open at a certain position in the second region A2. Specifically, the dielectric layer 30 allows the conductive layer 20a to be exposed at this position. Here, a portion of the dielectric layer 30, located on the first main surface S1, is open under a form of frame. The semiconductor device 1 further comprises an insulating layer 60a, a first internal electrode 70a, a second internal electrode 70b, an inductor LI, an insulating layer 60b, a first external connection terminal PI, a second external connection terminal P2, and a third external connection terminal P3, as shown in Figures 1 and 2. In one embodiment, the first external connection terminal, the second external connection terminal and the third external connection terminal are arranged so as to face the first main surface. The second internal electrode 70b is located on the first Al region. The second internal electrode 70b is electrically connected to the conductive layer 20b. Here, the second internal electrode 70b is a rectangular electrode located at the center of the first principal surface S1. The first internal electrode 70a is located on the second region A2. The first internal electrode 70a is in contact with the conductive substrate CS at a specific position within the opening formed in the dielectric layer 30. The first internal electrode 70a is thus electrically connected to the conductive substrate CS. Here, the first internal electrode 70a is a frame-shaped electrode arranged to surround the second internal electrode 70b. The first internal electrode 70a and the second internal electrode 70b may have a monolayer or a multilayer structure. Each layer constituting the first internal electrode 70a and the second internal electrode 70b is made, for example, of a metal such as molybdenum, aluminum, gold, tungsten, platinum, copper, or nickel, or an alloy containing one or more of the metals. The insulating layer 60a covers portions of the conductive layer 20b and the dielectric layer 30 located on the first main surface S1, as well as the first internal electrode 70a and the second internal electrode 70b. The insulating layer 60a is open at positions corresponding to a portion of the first internal electrode 70a and a portion of the second internal electrode 70b. The insulating layer 60a can have a single-layer or multi-layer structure. Each layer constituting the insulating layer 60a is made, for example, of an inorganic insulator such as silicon nitride or silicon oxide, or of an organic insulator such as polyimide or novolac resin. The insulating layer 60a is preferably made of an inorganic insulator. The thickness of the insulating layer 60a is preferably in the range of 0.1 µm to 20 µm, and even better in the range of 1 µm to 3 µm, at the position of capacitor C. If the insulating layer 60a is thinned, a short circuit between the second internal electrode 70b and the inductor L1 is likely to occur. to produce, or the parasitic capacitance between them will increase. A thick 60a insulating layer is expensive. The inductor LI is located on the insulating layer 60a at the position of capacitor C. Here, the inductor LI is a meandering inductor. That is, the inductor LI is a conductive layer with a pattern to form a meandering conductive path. The meandering inductor is also called meander wiring. The inductor L1 can have a single-layer or multi-layer structure. For example, when formed by plating, the inductor L1 may contain an adhesive layer, a seed layer, and a plating layer. The inductor L1, or one or more of its layers, is made of a metal such as aluminum, copper, or nickel, or an alloy containing one or more of these metals. When the inductor L1 is formed by plating, the adhesive layer may contain a metal such as titanium or molybdenum. The seed layer may contain a metal such as copper. The plating layer may contain a metal such as copper or nickel. The thickness of the conductive layer constituting the inductor LI is preferably in the range of 0.1 µm to 10 µm, and even better in the range of 1 µm to 3 µm. If this conductive layer is thickened, the resistance value of the inductor LI is reduced. However, a thick conductive layer is expensive. The width of the conductive path constituting the inductor L1 is preferably in the range of 1 µm to 100 µm, and even better in the range of 5 µm to 50 µm. If the width is increased, the resistance value of the inductor LI is reduced. However, if the width is increased, it becomes difficult to form a long conductive path. The length of the conductor path constituting the inductance L1 is preferably in the range of 1 mm to 1000 mm, and even better in the range of 20 mm to 200 mm. If the conductor path is lengthened, the inductance of the inductance LI is increased. However, if the conductor path is lengthened, it may be necessary to reduce the width or spacing of the conductor path. The insulating layer 60b covers the insulating layer 60a and the inductance LI. The insulating layer 60b is open at the positions of the two openings formed in the insulating layer 60a, at the position of one end of the inductance L1, and at the position of the other end of the inductance L1. The insulating layer 60b can have a single-layer or multi-layer structure. For each layer constituting the insulating layer 60b, for example, the materials described as examples for the insulating layer 60a can be used. The first external connection terminal P1, the second external connection terminal P2, and the third external connection terminal P3 are pad electrodes which allow the circuits included in the semiconductor device 1 to be connected to external circuits. The first external connection terminal P1 is located on the insulating layer 60b. The first external connection terminal P1 is in contact with the first internal electrode 70a at the location of an opening formed in the insulating layer 60b. The first external connection terminal P1 is also in contact with one end of the inductor LI at the location of another opening formed in the insulating layer 60b. The first external connection terminal P1 is thus electrically connected to the first internal electrode 70a and to one end of the inductor LI. In [Fig. 1], region R1 is where the first external connection terminal P1 is in contact with the first internal electrode 70a. Region R3 is where the first external connection terminal P1 is in contact with one end of the inductor LI. The second external connection terminal P2 is located on the insulating layer 60b. The second external connection terminal P2 is in contact with the second internal electrode 70b at a position corresponding to yet another opening formed in the insulating layer 60b. The second external connection terminal P2 is thus electrically connected to the second internal electrode 70b. In [Fig. 1], region R2 is where the second external connection terminal P2 is in contact with the second internal electrode 70b. The third external connection terminal P3 is located on the insulating layer 60b. The third external connection terminal P3 is in contact with the other end of the inductor LI at the position of the remaining opening formed in the insulating layer 60b. The third external connection terminal P3 is thus electrically connected to the other end of the inductor LI. In [Fig. 1], region R4 is where the third external connection terminal P3 is in contact with the other end of the inductor LI. Each of the first external connection terminal P1, the second external connection terminal P2, and the third external connection terminal P3, constitutes a part of the conductive layer 80. The present conductive layer 80 has a stacked structure comprising a first metallic layer 80a and a second metallic layer 80b. The first metallic layer 80a is made, for example, of copper or nickel. The second metallic layer 80b covers the upper and end surfaces of the first metallic layer 80a. The second metallic layer 80b consists, for example, of a stack of layers: a layer of nickel or a nickel alloy and a layer of gold. The second metallic layer 80b may be omitted. The conductive layer 80 may further contain a barrier layer containing a metal such as titanium on its surface in contact with the insulating layer 60a, the insulating layer 60b, or the like. When the conductive layer 80 is formed by plating, an adhesion layer may be used as a barrier layer. In this case, the conductive layer 80 may further contain a seeding layer comprising a metal, such as copper, between the adhesion layer and the first metallic layer 80a. The semiconductor device 1 may further contain a connecting conductor on each of the first external connection terminal P1, the second external connection terminal P2, and the third external connection terminal P3. As a connecting conductor, a metal bead, such as a gold bead or a solder bead, may be provided. <Boîtier de circuit intégré > An integrated circuit package according to an embodiment includes a semiconductor chip comprising an integrated circuit, and the semiconductor device according to the embodiment described above, the first external connection terminal being connected to the integrated circuit. Figure [Fig. 3] shows an integrated circuit package according to one embodiment. An integrated circuit package 100 shown in [Fig.3] contains the semiconductor device 1 described above, a semiconductor chip 110, and a wiring board 140. The 140 wiring board is an interposer that mediates the mounting of the 110 semiconductor chip onto a motherboard or similar device. In this case, the 140 wiring board is for a ball-gate package (BGA). The wiring board 140 contains a multilayer interconnect structure 141 and electrode pads 142 and 143. The multilayer interconnect structure 141 contains an insulating layer, a conductive pattern, and a through-electrode for interlayer connection. The electrode pads 142 are arranged on one main surface of the multilayer interconnect structure 141 and are electrically connected to the conductive pattern of the multilayer interconnect structure 141. The electrode pads 143 are arranged on the other main surface of the multilayer interconnect structure 141 and are electrically connected to the conductive pattern of the multilayer interconnect structure 141. The semiconductor chip 110 contains an integrated circuit such as a large-scale integrated circuit. At least part of the integrated circuit may constitute a microprocessor such as a central processing unit, or a microcontroller. The semiconductor chip 110 also contains an external connection terminal for The power supply, an external grounding terminal, external signal input terminals, and external signal output terminals. These external terminals are electrically connected to the integrated circuit. The semiconductor chip 110 also contains, on its surface, a conductive pattern electrically isolated from the integrated circuit. The semiconductor chip 110 is mounted on the wiring board 140. Specifically, the semiconductor chip 110 is attached to the wiring board 140 by an adhesive layer 160 made from a chip-fixing agent. The external connection terminals of the semiconductor chip 110 are connected to the electrode pads 142 via connecting conductors 150, which are metallic wires. The semiconductor device 1 is mounted on the semiconductor chip 110. Specifically, the semiconductor device 1 is attached to the semiconductor chip 110 by an adhesive layer 130 made of an underfilling agent. The first external connection terminal P1, the second external connection terminal P2, and the third external connection terminal P3 of the semiconductor device 1 are connected, via connecting conductors 120, to the external connection terminal for power supply, the external connection terminal for grounding, and the conductive motif, which is electrically isolated from the integrated circuit, of the semiconductor chip 110, respectively. The integrated circuit package 100 also contains connecting conductors 170 and a sealing resin layer 180. The connecting conductors 170 are arranged on the electrode pads 143. The connecting conductor 170 consists, for example, of solder balls. The sealing resin layer 180 is an insulating layer that seals the semiconductor device 1, the semiconductor chip 110, the connecting conductors 150, and similar components. [Fig.4] is an equivalent circuit diagram of the integrated circuit package 100 re- shown in [Fig.3]. One end of the inductor LI of semiconductor device 1 is connected to a VDD power supply mounted on the motherboard, via the third external connection terminal P3 of semiconductor device 1, the conductive pattern of semiconductor chip 110, the connecting conductor 150, the wiring board 140, and the like. As described above, the other end of the inductor LI is connected to the first external connection terminal PI and to the conductive layer 20a, which is the lower electrode of capacitor C. The conductive layer 20b, which is the upper electrode of capacitor C, is connected to a grounding terminal on the motherboard via the second internal electrode 70b of semiconductor device 1, the second external connection terminal P2 of semiconductor device 1, the external grounding connection terminal of semiconductor chip 110, the connecting conductor 150, wiring card 140, and similar. The first external connection terminal P1 is connected to the semiconductor chip integrated circuit 110 via the external connection terminal for the power supply of the semiconductor chip 110, and similarly. A conductive path L2 connecting the first external connection terminal P1 to the semiconductor chip integrated circuit 110 has some inductance, although it is much lower than the inductance LI. Thus, the symbol for inductance is used for the conductive path L2 in [Fig. 4]. The external L / O signal input / output connection terminals of the semiconductor chip 110 are connected to signal input / output terminals on the motherboard via the connecting conductors 150, the wiring board 140, and similar. <Procédé de fabrication> The semiconductor device 1 described with reference to Figures 1 and 2 is manufactured, for example, by the following process. An example of the manufacturing process for semiconductor device 1 will be described below with reference to Figures 5 to 7. In this process, the substrate 10 shown in [Fig. 5] is first prepared. Here, as an example, the substrate 10 is assumed to be a single-crystal silicon wafer. The plane orientation of the single-crystal silicon wafer is not particularly limited, but a silicon wafer whose principal surface is a (100) plane is used in this example. A silicon wafer whose principal surface is a (110) plane can also be used as substrate 10. Next, recesses are formed on the substrate 10 by metal-assisted chemical etching (MacEtch). Namely, as shown in [Fig.5], a layer of catalyst 210 containing a noble metal is first formed on the substrate 10. The layer of catalyst 210 is formed so as to partially cover a main surface (hereafter referred to as a "first surface") of the substrate 10. Specifically, a 220 mask layer is first formed on the first surface of the substrate 10. The mask layer 220 is open at positions corresponding to the recesses TR. The mask layer 220 prevents portions of the first surface covered by the mask layer 220 from coming into contact with a noble metal which will be described later. Examples of 220 mask layer material include organic materials such as polyimide, fluorinated resin, phenolic resin, acrylic resin, and novolac resin, and inorganic materials such as silicon oxide and silicon nitride. The 220 mask layer can be formed, for example, by semi-processes existing conductors. The mask layer 220 made of an organic material can be formed, for example, by photolithography. The mask layer 220 made of an inorganic material can be formed, for example, by forming a layer of inorganic material using a vapor deposition process, forming a mask using photolithography, and forming a pattern on the inorganic material layer using etching. Alternatively, the mask layer 220 made of an inorganic material can be formed by oxidizing or nitriding the surface region of the substrate 10, forming a mask using photolithography, and forming a pattern on an oxide or nitride layer using etching. The mask layer 220 can be omitted. Next, the catalyst layer 210 is formed on the regions of the first surface that are not covered by the mask layer 220. The catalyst layer 210 is, for example, a discontinuous layer containing a noble metal. Here, as an example, it is assumed that the catalyst layer 210 is a particulate layer formed from catalyst particles 211 containing a noble metal. The noble metal is, for example, one or more of the following: gold, silver, platinum, rhodium, palladium, and ruthenium. The catalyst layer 210 and the catalyst particles 211 may also contain a metal other than a noble metal, such as titanium. The catalyst layer 210 can be formed, for example, by electroplating, reduction plating, or displacement plating. The catalyst layer 210 can be formed by applying a dispersion containing noble metal particles, or by a vapor-phase deposition process such as evaporation or sputtering. Among these processes, displacement plating is particularly advantageous because it allows for the direct and uniform deposition of a noble metal onto the regions of the first surface that are not covered by the mask layer 220. Next, the substrate 10 is etched with the assistance of a noble metal serving as a catalyst to form recesses on the first surface. Specifically, as shown in [Fig.6], the substrate 10 is etched with an etching agent 230. For example, the substrate 10 is immersed in the etching agent 230 in liquid form so that the etching agent 230 comes into contact with the substrate 10. Etching agent 230 contains an oxidant and hydrogen fluoride. The concentration of hydrogen fluoride in etching agent 230 is preferably in the range of 1 mol / L to 20 mol / L, even better in the range of 5 mol / L to 10 mol / L, and more particularly in the range of 3 mol / L to 7 mol / L. When the concentration of hydrogen fluoride is low, it is difficult to achieve a high etching speed. When the concentration of hydrogen fluoride is high, excessive secondary etching can occur. The oxidant can be chosen, for example, from hydrogen peroxide, nitric acid, AgNO₃, KAuCl₂, HAuCl₂, K₂PtCl₂, H₂PtCl₂, Fe(NO₃)₅, Ni(NO₃), Mg(NO₃), Na₂S₂O₅, K₂S₂O₅, KMnO₄, and KCr₂O₅. Hydrogen peroxide is advantageous as an oxidant because no harmful byproducts are produced, and a semiconductor element is not contaminated. The concentration of the oxidant in the etching agent 230 is preferably in the range of 0.2 mol / l to 8 mol / l, better still in the range of 2 mol / l to 4 mol / l], and more particularly in the range of 3 mol / l to 4 mol / l. The etching agent 230 may also contain a buffer. The buffer contains, for example, at least one of ammonium fluoride and ammonia. In one example, the buffer is ammonium fluoride. In another example, the buffer is a mixture of ammonium fluoride and ammonia. The etching agent 230 may also contain other components such as water. When such an etching agent 230 is used, the substrate material 10, which in this case is silicon, is oxidized only in regions of the substrate that are close to the catalyst particles 211. The oxygen thus generated is dissolved and removed by hydrofluoric acid. Consequently, only the portions close to the catalyst particles 211 are selectively etched. The catalyst particles 211 move towards the other main surface (hereafter referred to as a "second surface") of the substrate 10 as the etching progresses, where an etching similar to the one described above is carried out. As a result, as shown in [Fig. 5], at the position of the catalyst layer 210, the etching occurs from the first surface to the second surface in a direction perpendicular to the first surface. In this way, the TR recesses shown in [Fig.7] are formed on the first surface. After that, the mask layer 220 and the catalyst layer 210 are removed from the substrate 10. Next, the conductive layer 20a shown in [Fig. 2] is formed on the substrate 10 to obtain the conductive substrate CS. The conductive layer 20a can be formed, for example, by doping the surface region of the substrate 10 with impurities at a high concentration. A conductive layer 20a made of polysilicon can be formed, for example, by low-pressure chemical vapor deposition (LPCVD). A conductive layer 20a made of a metal can be formed, for example, by electroplating, reduction plating, or displacement plating. A plating solution is a liquid containing a salt of a metal to be deposited by plating. General plating solutions include copper sulfate plating solutions containing copper sulfate pentahydrate and sulfuric acid, copper pyrophosphate plating solutions containing copper pyrophosphate and potassium pyrophosphate, and nickel sulfamate plating solutions containing nickel sulfamate and boron. The conductive layer 20a is preferably formed by a plating process using a plating solution containing a salt of the metal to be plated, a surfactant, and supercritical or subcritical carbon dioxide. In this plating process, the surfactant is interposed between particles of supercritical carbon dioxide and a continuous phase of a solution containing a salt of the metal to be plated. Specifically, the surfactant is allowed to form micelles in the plating solution, and supercritical carbon dioxide is incorporated into these micelles. In a standard plating process, the amount of metal deposited by plating may be insufficient near the bottom portions of the recesses. This is particularly noticeable when the ratio D / W of the depth D to the width or diameter W of the recesses is large. Micelles incorporating supercritical carbon dioxide can easily enter narrow spaces. As the micelles move, the solution containing a salt of the metal to be plated also moves. Therefore, according to the plating process using a plating solution containing a salt of the metal to be plated, a surfactant, and carbon dioxide in a supercritical or subcritical state, a conductive layer 20a of uniform thickness can be readily formed. Next, the dielectric layer 30 is formed on the conductive layer 20a. The dielectric layer 30 can be formed, for example, by chemical vapor deposition (CVD). Alternatively, the dielectric layer 30 can be formed by oxidation, nitriding, or oxynitriding of the surface of the conductive layer 20a. Next, the conductive layer 20b is formed on the dielectric layer 30. For example, a conductive layer made of polysilicon or a metal is formed as the conductive layer 20b. Such a conductive layer 20b can be formed, for example, by a process similar to that described above for the conductive layer 20a. Next, an opening is formed in the dielectric layer 30. Here, a portion of the dielectric layer 30 that is located on the first principal surface S1 is open in the form of a frame. This opening can be formed, for example, by creating a mask using photolithography and creating a pattern using engraving. Next, a metallic layer is formed and patterned to obtain the first internal electrode 70a and the second internal electrode 70b. The first internal electrode 70a and the second internal electrode 70b can be formed, for example, by a combination of film formation by means of sputtering or plating, and photolithography. Next, the insulating layer 60a is formed. The insulating layer 60a is formed, for example, by CVD. Next, the LI inductance is formed on the insulating layer 60a. The LI inductance can be formed, for example, by a combination of film formation using sputtering or plating, and photolithography. Next, the insulating layer 60b is formed on the insulating layer 60a and the inductor LI. The insulating layer 60b is formed, for example, by CVD. Openings are formed in the insulating layer 60b at the positions of regions R1, R2, R3, and R4 by photolithography. At this point, openings are also formed in the insulating layer 60a at the positions of regions R1 and R2. Next, the first external connecting electrode P1, the second external connecting terminal P2, and the third external connecting terminal P3 are formed on the insulating layer 60b. Specifically, the first metallic layer 80a is formed first, and the second metallic layer 80b is formed afterward. The first metallic layer 80a and the second metallic layer 80b can be formed, for example, by a combination of film formation using sputtering or plating, and photolithography. Next, the resulting structure is cut into cubes. In this way, the semiconductor device 1 shown in Figures 1 and 2 is obtained. <Effets avantageux> In the semiconductor device 1 described above, the recesses TR are formed on the first principal surface S1, and the stacked structure comprising the dielectric layer 30 and the conductive layer 20b is arranged not only on the first principal surface S1 but also within the recesses TR. Thus, the capacitor C can achieve a large electrical capacitance even when the dimension of the semiconductor device 1 in the direction perpendicular to the thickness direction is small. In the semiconductor device 1, the inductor LI faces the capacitor C with the insulating layer 60a interposed between them. That is, the inductor LI and the capacitor C are stacked in the direction of the thickness of the semiconductor device. conductor | with the insulating layer 60a interposed between them. This arrangement can minimize the increase, due to the presence of the inductance LI, in the dimension of the semiconductor device 1 in the direction perpendicular to the direction of the thickness. The size of the semiconductor device 1 can therefore be reduced. Furthermore, the inductance LI is a patterned conductive layer. Thus, the increase in thickness of the semiconductor device 1 due to the presence of the inductance LI is small. Since the CS and similar conductive substrates are thin, the semiconductor device 1 can have a low weight. As described above, the size of the semiconductor device 1 can be reduced. In the integrated circuit package 100, such a semiconductor device 1 and the semiconductor chip 110 are stacked in the thickness direction. Thus, the size of the integrated circuit package 100, which contains the semiconductor device 1, can also be reduced, and the size of a semiconductor module obtained by mounting the integrated circuit package 100 and similar components on the motherboard can also be reduced. Furthermore, the semiconductor device 1 can have a low height, as described above. Thus, although it contains the semiconductor device 1 and the semiconductor chip 110 stacked in the thickness direction, the integrated circuit package 100 can have a low weight. In the semiconductor device 1, the conductive layer 20b, which is the upper electrode of capacitor C, is connected to the second external connection terminal P2 via the second internal electrode 70b only. Thus, the conductive path connecting the upper electrode of capacitor C to the second external connection terminal P2 is short; consequently, the parasitic inductance of this conductive path is low. As the inductance of the conductive path L2 in the equivalent circuit shown in [Fig. 4] becomes lower, the effect of allowing noise generated in the semiconductor chip 110 to leak to the ground electrode—that is, the effect of suppressing noise leakage generated in the semiconductor chip 110 to the power supply VDD—increases. Capacitor C with the configuration described above also has a low parasitic inductance (or equivalent series inductance).Thus, the semiconductor device 1 exhibits excellent performance as an LC filter. Furthermore, in the integrated circuit package 100, the semiconductor device 1 is joined to the semiconductor chip 110 by a flip-chip junction. This is why the conductor path L2 in the equivalent circuit shown in [Fig. 4] is shorter than in the case where the semiconductor device 1 is joined to the semiconductor chip 110 by microwiring. This means that the inductance of the conductor path L2 is lower. Consequently, when the configuration described above- above is adopted for the integrated circuit package 100, the noise blocking effect is greater than in the case where the semiconductor device 1 is joined to the semiconductor chip 110 by microwiring. Furthermore, in the semiconductor device, the inductor LI is adjacent to the capacitor C, with the insulating layer and the second internal electrode 70b interposed between them. Thus, the heat generated in the inductor LI is rapidly transferred to the capacitor C. The heat transferred from the inductor LI to the capacitor C is then rapidly transferred in the direction of the depth of the recesses TR. This endows the semiconductor device with excellent radiation resistance, and therefore the available current is significant. In the integrated circuit package 100, the inductance LI is interposed between the semiconductor chip 110 and the capacitor C. Thus, the heat transferred to the capacitor C can be rapidly transferred outside the integrated circuit package 100. Semiconductor device 1 also has excellent heat resistance. Furthermore, semiconductor device 1 can have virtually the same coefficient of thermal expansion as semiconductor chip 110. Thus, integrated circuit package 100 can achieve excellent heat resistance. <modifications> Various modifications can be made to the semiconductor device 1 and the integrated circuit package 100. For example, in the configuration described with reference to Figures 1 and 2, the conductive layer 20a, which is the lower electrode of capacitor C, is connected to one end of inductor LI, and the conductive layer 20b, which is the upper electrode of capacitor C, is connected to the second external connection terminal P2. Alternatively, it is possible to connect the conductive layer 20b, which is the upper electrode of capacitor C, to one end of inductor LI and to connect the conductive layer 20a, which is the lower electrode of capacitor C, to the second external connection terminal P2. When this configuration is used, the parasitic capacitance that occurs between capacitor C and inductor LI can be reduced. In the configuration described with reference to Figures 1 and 2, the insulating layer 60a and the inductance LI are formed on the first main surface S1. It is possible to form the insulating layer 60a and the inductance LI on the second main surface S2, to form through holes in the substrate 10 and similar, and to connect the inductance L1 to the first external connection terminal P1 and the third external connection terminal P3 via the through holes. The semiconductor device 1 can be joined to the semiconductor chip 110 by microwiring instead of a flip-chip junction. The semiconductor chip 110 can be joined to the wiring board 140 by flip-chip junction instead of microwiring. The integrated circuit package 100 can be a package other than the BGA, such as a square flat panel package (QFP). In this case, the integrated circuit package 100 can contain a connection grid instead of the wiring board 140. The inductance LI] can be an inductance other than the meander inductance. For example, the inductance L1 can be a spiral inductance shown in [Fig.8]. The LC filter formed by the semiconductor device 1 is not limited to the type L filter shown in [Fig. 4]. For example, the semiconductor device 1 can form a type II filter shown in [Fig. 9]. In this case, the semiconductor device 1 contains two capacitors C1 and C2, which are similar to capacitor C, instead of a single capacitor C. Although certain embodiments have been described, these embodiments have been presented by way of example only and are not intended to limit the scope of the invention. Moreover, the new embodiments described herein can be implemented in various other forms; furthermore, various omissions, substitutions, and changes in the form of the embodiments described herein can be made without departing from the spirit of the invention. The attached claims and their equivalents are intended to cover such forms or modifications as fall within the scope and spirit of the invention.< / modifications>

Claims

Demands

1. Integrated circuit package comprising: a semiconductor chip comprising an integrated circuit; and a semiconductor device comprising: a stack of layers comprising a conductive substrate containing a semiconductor material and comprising a first principal surface having one or more recesses and a second principal surface opposite the first principal surface, a conductive layer covering at least a portion of the first principal surface and the side walls and bottom surfaces of the recess(es), and a dielectric layer interposed between the conductive substrate and the conductive layer, the conductive layer and a portion of the conductive substrate adjacent to the dielectric layer being an upper electrode and a lower electrode of a capacitor, respectively; an insulating layer disposed on the capacitor or on the second principal surface;and an inductance disposed on the insulating layer at a position of the capacitor; a first external connection terminal connected to one end of the inductance and to one of the upper and lower electrodes; a second external connection terminal connected to another of the upper and lower electrodes; and a third external connection terminal connected to another end of the inductance, the first external connection terminal being connected to the integrated circuit.

2. Integrated circuit package according to claim 1, wherein the first principal surface of said semiconductor device is provided with a plurality of recesses as recesses, or is provided with one or more recesses such that a plurality of pillar-shaped protrusions are formed.

3. Integrated circuit package according to claim 1, wherein the first principal surface of said semiconductor device is provided of a plurality of trenches arranged in the direction of the width as the recess(es).

4. Integrated circuit package according to any one of claims 1 to 3, wherein the inductance of said semiconductor device is a meander inductance or a spiral inductance.

5. Integrated circuit package according to any one of claims 1 to 4, wherein the insulating layer of said semiconductor device is disposed on the capacitor, and the inductor faces the capacitor with the insulating layer interposed between them.

6. Integrated circuit package according to any one of claims 1 to 5, wherein the first external connection terminal, the second external connection terminal, and the third external connection terminal are arranged to face the first main surface.

7. Integrated circuit package according to any one of claims 1 to 6, further comprising connecting conductors arranged on the first external connection terminal, the second external connection terminal and the third external connection terminal.

8. Integrated circuit package according to any one of claims 1 to 7, wherein the semiconductor device is joined to the semiconductor chip by a flip-chip junction.

9. Integrated circuit package according to any one of claims 1 to 8, further comprising a wiring board on which the semiconductor chip is mounted.

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