Global Shutter Analog Summation Pixel Matrix

Abstract

The invention relates to a pixel matrix comprising a submatrix of four adjacent pixels. Each pixel of the submatrix includes: a photoelectric element and a memory pixel, a detection node, and a transfer grid. The summation stage is connected to said element and is common with an adjacent pixel of the submatrix. At least one detection node per submatrix is ​​common to two adjacent pixels of the submatrix. The pixel matrix further includes at least one readout stage per submatrix, connected to the common detection node. Figure for the abstract: Fig. 1

Description

Title of the invention: Global Shutter Analog Summation Pixel Matrix

[0001] The invention relates to image sensors based on an active pixel matrix in CMOS technology.

[0002] This type of sensor exploits the photoelectric effects in semiconductor materials to convert received photons into electrical signals that allow the captured image to be reconstructed. There are two main families of image sensors: sensors based on CCD (Charge-Coupled Device) technology and sensors based on CMOS (Complementary Metal-Oxide-Semiconductor) technology.

[0003] CMOS sensors offer easier integration into large-scale integrated circuits combined with lower manufacturing costs compared to CCD sensors. Furthermore, they enable higher processing speeds with lower power consumption, which explains the adoption of this technology for mass-market products such as mobile phones. Therefore, there is a strong interest in improving these CMOS technologies by incorporating the advantages of CCD technology to achieve or even surpass the performance of benchmark CCD technologies, while maintaining the advantages of CMOS technology described above.

[0004] Pixel binning consists of summing the output signals of a group of adjacent pixels to form a larger virtual macropixel composed of n*m pixels, where at least one of the two positive integers n or m is greater than or equal to 2. This technique improves the sensitivity of the image sensor incorporating this feature and thus improves the signal-to-noise ratio of the image sensor by reconstructing the signal from a group of individual pixels. Pixel binning is commonly used in CCD sensors based on the addition of electrical charges generated during the transfer of these charges. However, in CMOS image sensors, the implementation of this feature is more complex because the addition of the pixel output signals is performed conventionally in the voltage domain, rather than the charge domain.In the voltage domain, the summed signal thus undergoes the quadratic addition of the noises generated by each pixel, noises associated with their respective reading chain, which degrades the signal-to-noise ratio of the summed pixel by a factor of square root of n*m, compared to the signal-to-noise ratio of an equivalent pixel of the same size as the unsummed macro pixel.

[0005] The technological and economic context of the field of image sensors justifies the interest in developing solutions to implement the summation of pixels (Binning) in image sensors based on an active pixel matrix in CMOS technology.

[0006] New applications for image sensors are emerging, such as machine vision, robotics and autonomous vehicles, and night vision. These applications demand superior performance from CMOS image sensors in low-light conditions and / or with moving targets. These new applications also require high dynamic range (HDR) imaging, which reflects the sensor's ability to integrate a large number of loads while exhibiting low read noise compared to conventional techniques.

[0007] Based on the preceding explanation, it can be deduced that the implementation of the pixel summation functionality in image sensors based on CMOS technology presents a technical challenge because a compromise must be respected between the advantages of this functionality, namely greater sensitivity and a higher signal-to-noise ratio, and its disadvantages related to a greater chain noise resulting if this summation is carried out in the domain of electrical voltages.

[0008] Furthermore, CMOS image sensors can be used in two different operating modes. The first operating mode is rolling shutter, in which the integration, charge transfer, and readout phases are staggered in time from one line to the next. The second operating mode is global shutter, which allows simultaneous capture of photons in all pixels of the array. This operating mode is better suited to moving targets. Thus, another constraint arises in the same context, which consists of adapting the summation solution in the pixel charge domain of CMOS image sensors while remaining compatible with global shutter operation.

[0009] Consequently, there is a need to implement the pixel summation functionality in the charge domain of CMOS image sensors while retaining the advantages offered by CMOS technologies using pinch-pin photodiodes and remaining compatible with global shutter operation. This is in order to achieve the signal-to-noise ratio performance of a pixel of equivalent size to the summed macro pixel.

[0010] US patent application US 2014 / 0263964 A1 describes a CMOS image sensor containing a pixel array capable of performing pixel summation by sharing the detection node of a set of n*n pixels. The drawback of this solution is that sharing the detection node for a large number of pixels increases the capacitance value on that node compared to The overall mass is obtained through the accumulation of intrinsic parasitic capacitances in the various MOS transistors that make up the pixels. This results in a decrease in the image sensor's conversion factor (commonly denoted CVF, which represents the gain in converting electrons into voltage), but consequently, an increase in the input noise brought back by this conversion factor. Thus, this solution has the disadvantage of degrading the image sensor's performance in low-light conditions, in terms of signal-to-noise ratio.

[0011] US patent application US 2014 / 00218580 A1 describes a CMOS image sensor containing a pixel array capable of performing pixel summation using a temporary charge storage grid, of asymmetrical shape, arranged between the photodiode of the first pixel and the photodiode of the second pixel. However, the solution proposed by US 2014 / 00218580 A1 is not compatible with a global shutter mode of operation and is limited to rolling shutter operation.

[0012] To overcome the limitations of existing solutions regarding the implementation of pixel summation functionality to improve the sensitivity of the CMOS image sensor, the invention proposes an improved pixel matrix structure. The proposed solution consists of a pixel matrix implemented using CMOS technology integrated into an image sensor and comprising at least one 2x2 pixel sub-matrix equipped with electrical charge summation means enabling it to perform pixel summation in the charge domain.

[0013] This solution stands out from previously developed pixel summation solutions due to its superior conversion capability combined with low chain noise and a more compact physical implementation. This improves image sensor performance in low-light conditions requiring high sensitivity and a high signal-to-noise ratio.

[0014] The invention also has the advantage of allowing the pixel summation functionality to be combined with global shutter operation, thus offering superior performance in the case of a moving target.

[0015] Furthermore, the invention remains compatible with operation without summation of the macro-pixels' charges in the pixel matrix by adapting the control signals that govern the reading phase of the output signals from all the pixels in the matrix. This offers those skilled in the art flexibility in using this feature depending on the image capture conditions and environment.

[0016] The invention relates to a pixel matrix of N rows and M columns made in a semiconductor substrate, the matrix comprising at least one sub-matrix of four adjacent pixels.

[0017] Each pixel of the submatrix comprises: a photoelectric element for generating electric charges in response to incident electromagnetic radiation and a memory point connected to the output of the photoelectric element for storing the generated electric charges; a detection node; a transfer grid connected between the output of the memory point and the detection node; and a summation stage. The summation stage is connected to said element and is common with an adjacent pixel of the submatrix. At least one detection node per submatrix is ​​common to two adjacent pixels of the submatrix. The pixel matrix further comprises at least one readout stage per submatrix, connected to the common detection node.

[0018] According to a particular aspect of the invention, Each of the photoelectric effect elements is a pinched photodiode.

[0019] According to a particular aspect of the invention, each of the summation stages is achieved by a pair of deep isolation trenches arranged in parallel.

[0020] According to a particular aspect of the invention, each of the memory points is realized by an arrangement of deep isolation trenches. The deep isolation trenches form two confinements of the electrical charges: the first confinement constitutes the entrance of the memory point and the second confinement, doped with charge carriers at a higher dose than the first confinement, constitutes the body of the memory point.

[0021] According to a particular aspect of the invention, each memory point is realized by an arrangement of two pairs of deep insulating trenches. The deep insulating trenches form two confinements of the electrical charges: the first confinement constitutes the entrance of the memory point and is formed by the first pair of trenches arranged parallel and separated by a first distance; the second confinement constitutes the body of the memory point and is formed by the second pair of trenches arranged parallel and separated by a second distance. The first distance is less than the second distance.

[0022] According to a particular aspect of the invention, the summation stage is connected between the output of the photoelectric effect element and the output of the photoelectric effect element of the adjacent pixel of the submatrix belonging to the same row. Furthermore, the pixels of the submatrix belonging to the same column have a common detection node and a common readout stage.

[0023] According to a particular aspect of the invention, the control means in the preceding embodiment are configured to apply, for each pixel of the same column: a high potential on the deep insulating trenches forming the memory point to receive the electrical charges generated by the photoelectric element; a low potential on the deep insulating trenches forming the memory point belonging to the adjacent pixel of the submatrix belonging to the same row and a low potential on the deep isolation trenches forming the summation stage.

[0024] According to a particular aspect of the invention, the control means in the preceding embodiment are configured to apply simultaneously to each pixel of the same column: a high potential on the deep isolation trenches forming the memory point; a low potential on the deep isolation trenches forming the memory point belonging to the adjacent pixel of the submatrix belonging to the same row and a high potential on the deep isolation trenches forming the summation stage, to perform a summation of the electrical charges generated by the pixels belonging to the same row of the submatrix.

[0025] According to a particular aspect of the invention, the summation stage of a pixel in the submatrix is ​​connected between the output of the memory point and the output of the memory point of the pixel in the submatrix belonging to the same row. Furthermore, the pixels in the submatrix belonging to the same column have a common detection node and a common read stage.

[0026] According to a particular aspect of the invention, the summation stage of a pixel of the submatrix is ​​connected between the output of the memory point and the output of the memory point of the pixel of the submatrix belonging to the same column. A first pair of pixels of the submatrix belonging to the same row share a common detection node and a common read stage.

[0027] A second pair of pixels from a submatrix belonging to the same column are shared with another adjacent submatrix. The first pair of pixels from the adjacent submatrix is ​​arranged on a different row from the first pair of pixels from the submatrix.

[0028] According to a particular aspect of the invention, the control means are configured to apply for each pixel of the submatrix: a high potential on the deep isolation trenches forming the memory point to receive the electrical charges generated by the photoelectric effect elements and a low potential on the deep isolation trenches forming the summation stages.

[0029] According to a particular aspect of the invention, the control means are configured to simultaneously apply to a pair of adjacent pixels in a first direction: a high potential on the deep isolation trenches forming the memory point and a low potential on the deep isolation trenches forming the memory point belonging to the adjacent pixel of the submatrix in a second direction different from the first direction, and a high potential on the deep isolation trenches forming the summation stages. This serves to summate the electrical charges generated by the adjacent pixels in the second direction.

[0030] According to a particular aspect of the invention, the control means are configured to apply, on the pair of adjacent pixels in a first direction, for example on two pixels in the same column, a high potential on the transfer grids to achieve a summation of the electrical charges generated in the common reading stage.

[0031] According to a particular aspect of the invention, each reading stage comprises a reset transistor connected to the detection node to reset the detection node to a selected supply voltage; a common-drain mounted amplification transistor whose gate is connected to the detection node; and a selection transistor connected to the output of the amplification transistor to sample the output signal.

[0032] The invention relates in particular to an image sensor comprising: a pixel matrix according to the various embodiments of the previous invention; a circuit for generating the control signals of the pixels; a sampling circuit arranged at the foot of each column of the pixel matrix connected to the output of the reading stage of each pixel of the corresponding column and a power supply circuit to supply each column of the pixel matrix.

[0033] According to a particular aspect of the invention, the sampling circuit is a correlated double sampling circuit.

[0034] According to a particular aspect of the invention, the sensor being adapted for operation in global shutter.

[0035] Other features and advantages of the present invention will become more apparent from the following description in relation to the following accompanying drawings.

[0036] [Fig-1] [Fig.1] represents a functional diagram of a pixel submatrix according to a first embodiment of the invention.

[0037] [Fig.2a] [Fig.2a] represents a cross-sectional view of an embodiment of a floor summation carried out with deep capacitive isolation trenches facing each other.

[0038] [Fig.2b] [Fig.2b] represents a top view of the summation stage according to the method of implementation of [Fig.2a].

[0039] [Fig.2c] [Fig.2c] represents electrostatic potential diagrams in the summation stage illustrated in [Fig.2a] in horizontal section.

[0040] [Fig. 3a] [Fig. 3a] represents a top view of a first embodiment from a memory point achieved with deep capacitive isolation trenches facing each other.

[0041] [Fig.3b] [Fig.3b] represents a top view of a second embodiment from a memory point achieved with deep capacitive isolation trenches facing each other.

[0042] [Fig. 3c] [Fig. 3c] represents electrostatic potential diagrams in the confinements of the memory point illustrated in [Fig.3a].

[0043] [Fig.4] [Fig.4] represents an example of an electrical diagram of a reading stage.

[0044] [Fig. 5] [Fig. 5] represents a top view of an example implementation physics of the pixel sub-matrix according to a first embodiment of the invention.

[0045] [Fig.6a] [Fig.6a] represents a timing diagram of the operation of the sub- matrix illustrated in [Fig.1] during a summation of electric charges.

[0046] [Fig.6b] [Fig.6b] represents the first step in the summation of the charges electrical in a sub-matrix according to the first embodiment illustrated in [Fig.1].

[0047] [Fig. 6c] [Fig. 6c] represents an electrostatic potential diagram illustrating the first step of the summation of electric charges in a submatrix according to the first embodiment illustrated in [Fig.1].

[0048] [Fig.6d] [Fig.6d] represents the second step of the summation of electric charges in a submatrix according to the first embodiment illustrated in [Fig.1].

[0049] [Fig. 6e] [Fig. 6e] represents an electrostatic potential diagram illustrating the second step of the summation of electric charges in a submatrix according to the first embodiment illustrated in [Fig.1].

[0050] [Fig.6f] [Fig.6f] represents the third step of the summation of electric charges in a submatrix according to the first embodiment illustrated in [Fig.1].

[0051] [Fig.6g] [Fig.6g] represents an electrostatic potential diagram illustrating the third step of the summation of electric charges in a submatrix according to the first embodiment illustrated in [Fig.1].

[0052] [Fig.6h] [Fig.6h] represents the fourth step of the summation of electric charges in a submatrix according to the first embodiment illustrated in [Fig.1].

[0053] [Fig.6i] [Fig.6i] represents an electrostatic potential diagram illustrating the fourth step of the summation of electric charges in a submatrix according to the first embodiment illustrated in [Fig.1].

[0054] [Fig.7] [Fig.7] represents a timing diagram of the operation of the sub-matrix illustrated in [Fig.1] for operation without summation of electrical charges.

[0055] [Fig.8] [Fig.8] represents a functional diagram of a pixel submatrix according to a second embodiment of the invention.

[0056] [Fig.9a] [Fig.9a] represents a timing diagram of the operation of the sub- matrix illustrated in [Fig.8] during a summation of electric charges.

[0057] [Fig.9b] [Fig.9b] represents the first step of an operation with the summation of electric charges in a sub-matrix according to the second embodiment illustrated in [Fig.8].

[0058] [Fig.9c] [Fig.9c] represents the second stage of an operation with the summation of electric charges in a sub-matrix according to the second embodiment illustrated in [Fig.8].

[0059] [Fig.9d] [Fig.9d] represents the third stage of an operation with the summation of electric charges in a submatrix according to the second embodiment illustrated in [Fig.8].

[0060] [Fig.9e] [Fig.9e] represents the fourth step of an operation with the summation of electric charges in a submatrix according to the second embodiment illustrated in [Fig.8].

[0061] [Fig. 10] [Fig. 10] represents a functional diagram of a sub-matrix of pixels according to a third embodiment of the invention.

[0062] [Fig. 11] [Fig. 11] represents an example of implementation of a pixel matrix containing sub-matrices of pixels according to the first embodiment of the invention illustrated in [Fig. 1].

[0063] [Fig. 12] [Fig. 12] represents an example of implementation of a pixel matrix containing sub-matrices of pixels according to a variant of the second embodiment of the invention illustrated in [Fig. 8].

[0064] [Fig. 13] [Fig. 13] represents a functional diagram of an image sensor integrating a pixel matrix according to any one of the embodiments of the invention.

[0065] [Fig. 1] is a functional diagram representing the architecture of a set of four pixels belonging to a pixel matrix composed of N rows L of rank i with i=1 to N and M columns Q of rank j with j=1 to M, implemented on a semiconductor substrate. The four pixels are denoted respectively Pxlÿ, Pxl(i+i)j, Pxli>(j+i) and Pxl (j+i) according to their coordinates in the pixel matrix.

[0066] The four pixels Pxl;, j, Pxli+ij, Pxli j+iet Pxl i+i j+1 are identical and form a symmetric submatrix denoted S of dimension 2*2 assimilated to a virtual macro-pixel.

[0067] The four pixels of the submatrix S each have means for transferring electrical charges, enabling a first operation of summing the electrical charges generated by the two pixels (e.g., Pxlijet Pxlij+i) of the submatrix S belonging to the same row, and a second operation of summing the electrical charges generated by the two pixels (e.g., Pxlijet Pxli+i j) of the submatrix belonging to the same column. The symmetry of the submatrix structure S offers the possibility of performing summation along a direction from one unit pixel to another in both directions.

[0068] To illustrate the architecture of the pixels Pxlr Pxli+ij, Pxll|+,ct Pxl i+ij+i which form the submatrix S, we will detail in what follows the composition of the pixel Pxlij as an example.

[0069] The pixel Pxl;j comprises a photoelectric effect element EPE;j to generate and store electric charges in response to incident electromagnetic radiation, a memory point POINT_MEMij connected to the output of the photoelectric effect element EPELJ and controlled by the signal MEM1 to store the generated electric charges; a transfer grid T3 controlled by the signal TG; which connects a detection node SN;, j common with the adjacent pixel Pxli+ij belonging to the same column of the submatrix S; and a summation stage SOM1 controlled by the signal BIN common with the adjacent pixel Pxll|+, belonging to the same row of the submatrix S.

[0070] In addition, a LECT^ readout stage is connected to the SNLJ detection node, which performs the transition from the charge domain to the voltage domain. The LECTij readout stage shapes the signal corresponding to the charges collected in the associated pixel. The LECTij readout stage is shared with the pixel Pxli+ij belonging to the same column of the submatrix S.

[0071] As mentioned previously, the photoelectric effect element (PEE) is used to generate electric charges in response to incident electromagnetic radiation. An example of such an element is a pinched photodiode. The photodiode is generally constructed by joining a P+-doped thin film with an N-doped scattering region in a P-doped semiconductor substrate. Upon exposure to electromagnetic radiation, the incident photons interact with the semiconductor substrate to generate electron-hole pairs, which are collected in the space charge region of the junction, and more specifically in the cathode in the case of electrons. This is referred to as the charge integration phase.

[0072] The summing stage SOM1 behaves as a switch controlled by the BIN signal and connects the outputs of the photoelectric element EPEij with the photoelectric element EPEij+i belonging to line L of the submatrix S. Applying a positive pulse to the BIN signal activates the summing stage, thus establishing an electrical connection between the outputs of the two adjacent photoelectric elements EPEij and EPEij+i. Establishing this connection allows the electrical charges generated by the photoelectric element to photoelectric EPE^ +i following an integration phase to migrate towards the adjacent photoelectric effect element EPEij+iet vice versa.

[0073] A second summation stage SOM2, identical to the first summation stage SOM1 and controlled by the same BIN signal, is connected between the outputs of the two photoelectric effect elements EPEi+i jet EPEi+ij+i both belonging to the following line Li+i of the submatrix S to ensure the same function of summation of charges between the photoelectric effect elements EPEi+i jet EPEi+i j+iet and thus between the two adjacent pixels of the line Pxli+ijet Pxli+ij+i.

[0074] The memory point POINT_MEMi,j, controlled by the signal MEM1, is designed to store the electrical charges collected in the substrate of the photoelectric element EPEij following the application of a pulse to the signal MEM1. Each pixel of the sub-matrix S contains a memory point identical to the memory point POINT_MEMij connected to the output of the corresponding photoelectric element. The implementation of the memory points POINT_MEMi,j, POINT_MEMij+l, POINT_MEMi+l,j, and POINT_MEMi+l j+1 ensures global shutter operation of the image sensor, allowing the integration phase of the electrical charges of all pixels to be carried out simultaneously and stored in the memory points, subsequently triggering a sequential, line-by-line reading of the stored charges.

[0075] The memory points P0INT_MEM; jet POINT_MEMi+i jbelonging to the pixels of column of rank j Cj are controlled by the same signal MEM1 while the memory points POINT_MEMij+iet POINT_MEMi+ij+ibelonging to the pixels of column of rank j+1 Cj+i are controlled by the same signal MEM2.

[0076] The transfer gate T3 is connected between the output of the memory point POINT_MEMi j and the detection node SNij. This gate controls the transfer of electrical charges to the detection node SN; j. Indeed, when the external signal to the pixel TG; connected to the transfer gate is at a high level, the generated charges can diffuse towards the detection node SN; j. The gate generally corresponds to a poly-silicon gate connected to the detection node SN; j, which is a floating diffusion area of ​​type N. This refers to the phase of charge transfer to the detection node and thus to the input of the read stage LECTU.

[0077] By symmetry, the transfer grids T5, T6, and T4 belong respectively to pixels Pxlj, Pxli+ij+i, and Pxli+ij. The control signal TG; is addressed inline on the transfer grids T3 and T5 belonging to the i-th row L;. The control signal TGi+i is shared between the transfer grids T4 and T6 belonging to the i+1 row Li+i. Since the detection node SN; j is common between pixels Pxlij and Pxli+ij, the simultaneous activation of both transfer grids T4 and T3 allows to accumulate the electrical charges from these two pixels in the common detection node SNij to be read subsequently via the common reading stage LECTlj. This then allows for the summation of the charges generated by the pixels belonging to the column of rank j Q.

[0078] By symmetry, the same vertical summation functionality can be achieved for pixels Pxl; j +iet Pxli+ij+i belonging to column of rank j+1 Cj+i via the simultaneous activation of transfer grids T5 and T6.

[0079] The main role of the LECT and LECTij+i read stages is to adapt the signals converted at the SN^ and SNij+i detection nodes for propagation in the associated columns. They also provide reset and sequential addressing functionalities when reading the different pixels of the matrix.

[0080] Figures 2a and 2b describe an example of physical implementation of the summation stage SOM1 or SOM2 in section along the x-axis and in top view.

[0081] Figure 2b shows a top view of the SOM1 or SOM2 summing stage fabricated on a semiconductor substrate using an arrangement of deep trench isolation (DTI). Deep trench isolation is a component compatible with microelectronic manufacturing processes used to isolate an area of ​​the semiconductor substrate to limit leakage current in an integrated circuit, for example. A variant of this type of component called capacitive deep trench isolation (CDTI) exists. This variant is used to illustrate the invention without loss of generality.

[0082] To better understand the implementation of a summation stage using CDTI capacitive deep isolation trenches, [Fig. 2a] shows a cross-sectional view along the x-axis of [Fig. 2b] of a pair of CDTI capacitive deep isolation trenches, denoted respectively dtilet and dti2. The structure of a CDTI trench is fabricated by etching the semiconductor substrate 4 to create a trench a few micrometers deep (between 3 pm and 6 pm) and a few hundred nanometers wide (between 100 nm and 300 nm). An insulating layer 2, for example an oxide, is created on the inner wall of the trench by an oxidation process, and then the trench is filled with polysilicon 3. A metallic contact 1 is deposited on the surface of the fabricated CDTI trench to apply a potential to the resulting structure.

[0083] By placing a pair of CDTI trenches face to face as shown in Figures 2a and 2b for dtilet and dti2, by applying the same electrical potential to the metallic contacts of each of the trenches and with N-type doping of the space between the two CDTI trenches, an electrostatic potential well is obtained between The two trenches along the x-axis can accumulate electrical charges, namely electrons in the case presented with N-type doping. The depth of the potential well obtained by arranging two CDTI trenches facing each other depends on two factors: the distance dl between the two trenches and the doping level in the confined space between the trench pair dtilet dti2. Increasing the distance dl leads to an increase in the depth of the potential well created. The stronger the N-type doping, the greater the depth of the potential well.

[0084] In [Fig. 2c], the electrostatic potential well 21 is visualized in a cross-section along the x-axis between the two CDTI trenches (dtil and dti2) which form a summation stage following the application of a low potential to these CDTI trenches via the BIN signal. [Fig. 2c] also represents the electrostatic potential well 21 in a cross-section along the x-axis between the two CDTI trenches (dtil and dti2) which form a summation stage following the application of a high potential to these CDTI trenches. According to the convention usually chosen, increasing potentials are represented along the electrostatic potential axis going from top to bottom. A potential well for electrons thus corresponds to a parabolic function of the electrostatic potential pointing downwards, the maximum of which is the bottom of the potential well according to the adopted convention. The higher the maximum potential, the deeper the potential well for electrons.Applying a positive pulse to the CDTI dtil and dti2 trenches via the BIN signal shifts the level of the electrostatic potential well 21 towards the position of the electrostatic potential well 22. This corresponds to a displacement of a potential barrier, thus allowing electric charges to migrate through the summation stage designed by the structure described above, if the electrostatic well of the diode is suitably positioned.

[0085] The implementation of this CDTI dtil and dti2 trench structure between two photodiodes corresponding to photoelectric effect elements allows control of the migration of charges from one pixel to another, which constitutes a step in the process of summing charges in a 2*2 dimension sub-matrix S.

[0086] Fig. 3a represents a top view of an example of a physical implementation of a memory point used in the pixels of the submatrix S according to the invention.

[0087] A memory point P0INT_MEM; jtel as described in [Fig. 3a] is composed of an arrangement of two pairs of CDTI trenches placed opposite each other, namely (dti3, dti4) and (dti5, dti6). The deep isolation trenches form two confinements of the electrical charges in two perpendicular directions. The first confinement constitutes the entrance of the memory point, doped with N-type charge carriers, and the second confinement, doped with a higher dose of charge carriers to achieve N+-type doping, constitutes the body of the memory point. All the CDTI trenches that form the memory point, namely dti1, dti2, dti3, and dti4, are controlled by the same control signal MEM1 (or MEM2). The difference in doping between the input of the memory point and the body of the memory point creates an electrostatic potential difference between the confinements created by the two areas and results in the electrostatic potential diagram 31 shown in [Fig.3c].

[0088] Alternatively, it is possible to implement the memory point input in a different direction but not perpendicular to that of the memory point body, while keeping the doping difference between the two regions.

[0089] Alternatively, it is possible to implement the memory point input in the same direction as that of the memory point body as illustrated in [Fig.3b], while keeping the difference in doping dose between the two regions.

[0090] Alternatively, it is possible to realize the memory point P0INT_MEM;j consisting of an input and a body based on a difference in the distance between the trenches that constitute each region (input and body) and not on a difference in substrate doping. Indeed, let d2 be the distance between the trenches dti3 and dt4 that form the input of the memory point, and let d3 be the distance between the trenches dti5 and dt6 that form the body of the memory point. We recall that for a pair of trenches arranged opposite each other, increasing the distance between the two trenches leads to an increase in the depth of the potential well created between the two trenches. Thus, at an equivalent doping dose, if the distance d3 separating the trenches that form the input of the memory point is less than the distance d4 between the trenches that form the body of the memory point, we obtain the same electrostatic potential diagram described in [Fig. 3c].A memory point is thus created based on geometric variations in the structure and not on variations in the doping dose.

[0091] In a manner similar to the principle explained for CDTI trench-based summation stages, the application of a high potential on the trenches which constitute the memory point shifts the potential barrier 31 towards the position of the barrier illustrated by diagram 32, thus allowing the migration of electrical charges through the confinement of the memory point's input, which will then be stored in the confinement of the body region, thereby realizing the memory function.

[0092] Fig. 4 illustrates an electrical diagram of an example implementation of the LECT read stage; j used in the submatrix S according to one of the embodiments of the invention.

[0093] The LECT; j read stage receives two input signals RST; and SEL; common to all other read stages of the pixel matrix belonging to the same row of rank i L;. The LECT; j read stage is also powered by a reference voltage VREF. The LECT reading stage; j converts the charges collected by the SN detection node,. j into an output voltage Vout propagated in the COLj conducting line.

[0094] The LECT readout stage includes a reset transistor Q1 connected between the detection node SNLJ and the external reference voltage VREF to reset the detection node and enable double sampling correlated to the global scale of the image sensor.

[0095] The LECT reading stage; also includes a common drain amplification transistor Q2 to adapt the output signal to the conductive line of the associated column.

[0096] The LECT read stage also includes a selection transistor Q3 connected to the output of the amplification transistor Q2 to sample the output signal of the amplification transistor Q2. The selection switch T5 is controlled by a line selection signal denoted SEL. When the line to which the pixel belongs is selected for reading, transistor Q3 is conducting, thus allowing the signal Vout to propagate to the output of the read stage in the column via the conductive line COL.

[0097] Figure 5 illustrates a top view of an example of a physical layout of the submatrix S according to the first embodiment described in Figure 1. Those skilled in the art will be able to distinguish the different components of the submatrix S detailed in the description of Figure 1 in this specific view, which represents the mask used during the various stages of the microelectronic fabrication process in a semiconductor substrate.

[0098] [Fig.6a] represents a timing diagram of the operation of the sub-matrix illustrated in [Fig.1] with summation of the electrical charges.

[0099] Figures 6b to 6i illustrate the different stages of operation with the summation of electrical charges in a submatrix according to the first embodiment illustrated in [Fig. 1]. For each stage, the path of the electrical charges generated by the pixels of the submatrix S is traced at the scale of the electrical diagram of the submatrix S, but also at the scale of the potential diagrams in the semiconductor substrate of the different components of the pixel submatrix S. This approach allows for a better understanding of the physical phenomena that govern the operation with summation in the structure described according to the invention.

[0100] In [Fig.6a] it is possible to distinguish the following steps: 1. The PH0 step: Resetting the reading stage. 2. The PHI stage: Integration of electrical charges by the photodiodes. 3. The PH2 step: Storage of the electrical charges of the pixels Pxl; jet Pxli+ij of the receiving column. 4. Step PH3: Horizontal summation of electric charges. 5. Step PH4: Vertical summation of electric charges and reading. We will describe this process step by step.

[0101] At tO, the rising edge on the external control signal RST triggers the reset step PHO, which forces the value of the detection node SN of each pixel to a predetermined voltage. This step does not directly affect the functionality of summing the electrical charges of the pixels, but it is clear to those skilled in the art that the reset is essential for operation compatible with correlated double sampling.

[0102] Next, the PHI charge integration phase is triggered and all control signals are set to a low potential (corresponding to a logic level 0) for a sufficient duration to accumulate electrical charges in the photodiodes following exposure to incident light.

[0103] Fig. 6b illustrates the generation of packets of electric charges (dotted ellipses CH; j, CHij+i, CHi+ij, CHi+ij+i) by the different photoelectric effect elements which belong to the pixels constituting the submatrix S.

[0104] Figure 6c represents the state of the electrostatic potential diagram during the PHI integration step in the volume of the semiconductor substrate of the different components of the submatrix S as shown in Figure 6b. Applying a low potential (with MEM1=0 and MEM2=0) to the CDTI trenches that constitute the memory points POINT_MEM; j and POINT_MEMij+i induces the establishment of a potential barrier at the entrance of the memory points. Applying a low potential (with BIN=0) to the CDTI trenches that constitute the summation stage SOM1 also establishes a potential barrier, making the summation stage blocking for charge propagation. A potential well is thus obtained in the volume of the photoelectric effect elements EPE; jet EPEij+it as shown in Figure 6c. It is clearly observed that the generated charges CH; j and CHij+i are trapped in the potential wells at the photodiodes.By symmetry, during the integration step, the same electrostatic potential diagram is obtained for both pixels Pxli+ij and Pxli+lj+1-.

[0105] After a certain delay, the PHI integration phase ends and the rising edge on the MEM1 signal triggers the electrical charge storage step of the pixels Pxl j and Pxli+ij of the receiving column Cj, denoted PH2. Simultaneously, the MEM2 control signal is held at a low logic level, thus maintaining the potential barrier between the photodiodes of pixels Pxl; j +1 and Pxli+ij+ide the receiving column Q and the inputs of the memory points belonging to the same pixels.

[0106] Figures 6d and 6e show the displacement of electric charges from pixels Pxli j and Pxli+i j of the receiving column Q towards the memory points POINT_MEMij and POINT_MEMij following the rising edge of the signal MEM1. The electrostatic potential diagram of [Fig. 6e] shows this displacement of charges towards the memory points in the pixels of column Cj with MEM1=1 (logic high state) (lowering the potential barriers between the memory points and the photodiodes of Q) and the confinement of electric charges in the photodiodes of the pixels of column Cj+i with MEM2=0 (logic low state) (maintaining the potential barriers between the memory points and the photodiodes of Cj+i).

[0107] Activation of the BIN control signal, which controls the SOM1 and SOM2 summation stages, and maintaining MEM2 at a low potential level, triggers step PH3. The electrical charges CH1 and CH1j+i, which were generated and then confined in the photodiodes of pixels Pxfj+i and Px1j+i, respectively, pass through the SOM1 and SOM2 summation stages. Since the MEM1 control signal is maintained at a high potential (the inputs of POINT_MEM; j and POINT_MEM; +i+j are conducting), the electrical charges that pass through the summation stages from column j+1 Cj+i are in turn stored in the memory points of the pixels of column j Q, as illustrated in [Fig. 6f].

[0108] The electrostatic potential diagram 601 of [Fig. 6g] shows the migration of electric charges from the photoelectric effect element EPEij+i through the summation stage SOM1 to reach, in an intermediate step, the photoelectric effect element EPE^ and then continue towards the body of the MEM_POINTij, as illustrated in diagram 602 of [Fig. 6g]. By symmetry, the same arrangement of potential barriers is obtained in the substrate of the row of rank i+1 allowing the migration of electric charges from the photodiode of pixel Pxl; j + towards the memory point of pixel Pxll|+,.

[0109] Thus, upon completion of phase PH3, horizontal summation in the submatrix S is performed for each row. The symmetry of the structure allows a person skilled in the art to perform horizontal summation in both directions by adapting the sequence of control signals BIN, MEM1, and MEM2.

[0110] The falling edge on the MEM1 control signal at t4 triggers the next PH4 horizontal summation and readout phase. Being compatible with correlated double sampling, the reset value is sampled just before the falling edge of the reset signal RST. At t6, two simultaneous (or consecutive, depending on the programming) pulses, as long as RST is maintained at a constant frequency, are applied. (low logic state) on the two signals TG; and TGi+i activate the two transfer gates T3 and T4 by lowering their potential barriers as illustrated in [Fig. 6h] and 6i. Thus, the charges previously stored in the memory points POINT_MEM; and POINT_MEMi+ij are grouped at the detection node SN;,j. All the charges generated by the four pixels of the sub-matrix S are summed and accumulated in the same detection node SNi,j and converted into an electrical voltage, and adapted by the readout stage LECTij, and the useful signal is sampled to perform double-correlated sampling subsequently at the system level in the image sensor.

[0111] The details of the correlated double sampling procedure are not described here to simplify understanding of the process of summing the electrical charges of the pixels in the submatrix (Binning). Those skilled in the art have all the necessary elements to implement the summing of the electrical charges of pixels according to the invention with this type of sampling.

[0112] [Fig.7] represents a timing diagram of the operation of the sub-matrix illustrated in [Fig.1] without summation of the electrical charges.

[0113] The reset and integration phases PH'O and PH'1 are identical to the timing diagram in [Fig.6a].

[0114] At t' 1, the two pulses on the control signals MEM1 and MEM2 open access to all the memory points belonging to the pixels that form the sub-matrix S. Thus, the charges generated by each of the photodiodes migrate to the associated memory points, thereby performing the PH'2 phase of electrical charge storage in a global shuttered operation. The BIN signal is maintained at a low logic state to preserve the potential barrier between two adjacent photoelectric elements belonging to the same row.

[0115] From t'2, the two consecutive pulses on the control signals TG; and TGi+i allow the successive activation of the transfer gates T3, T4, T5 and T6 and thus accumulate the charges of the pixel Px^ on the detection node SN. ^t of PxLJ +[ on the detection node SNij+i (to be propagated respectively to the reading stages LECT^ct LECTI |+,) then in a second step to accumulate the charges of the pixel Pxli+ijSOn the detection node SN. ^t of Pxli+ij+i on the detection node SNij+i (to be propagated respectively to the reading stages LECTijet LECTij+i).

[0116] This results in operation without summation within the pixels that form the sub-matrix S in global shutter.

[0117] One advantage of the invention is that the proposed implementation allows operation with or without summation of loads.

[0118] Figure [Fig.8] represents a functional diagram of a sub-matrix of pixels according to a second embodiment of the invention.

[0119] The second embodiment of the submatrix S differs from the first embodiment by the connection of the summation stage SOM1 between the outputs of the memory points POINT-MEM^ and POINT_MEMij+i belonging to the row of rank i L; of the submatrix S and the connection of the summation stage SOM2 between the outputs of the memory points POINT_MEMi+ijet POINT_MEMi+i j+i belonging to the row of rank i+1 Li+i of the submatrix S.

[0120] The second embodiment described in [Fig. 8] has the technical advantage of allowing the rows and columns to be interchanged during its implementation. It also allows increasing the amount of charge that can be stored in memory points POINT_MEMi and POINT_MEMij+i belonging to the same row, since they will be isolated from each other by the summation stage SOM1. (The same applies to memory points POINT_MEMi and POINT_MEMi>j+1).

[0121] [Fig.9a] represents a timing diagram of the operation of the submatrix illustrated in [Fig.8] with summation of electrical charges according to the second embodiment of the invention.

[0122] Figures 9b to 9e illustrate the path of electric charges during the different summation stages in the submatrix S according to the second embodiment.

[0123] The reset and integration phases PH' 'O and PH' '1 are identical to those in the timing diagram of [Fig.6a] (namely PH0 and PHI).

[0124] Following the integration of the charges by the photodiodes of the pixels of the submatrix S, as illustrated in [Fig.9b], and at time t”1, the two pulses on the signals MEM1 and MEM2 open the potential barriers at the inputs of the memory points of all the pixels of the submatrix S. Thus the charges are stored in the different memory points as represented in [Fig.9c] and the step PH”2 is accomplished with the falling edges on the signals MEM1 and MEM2 at t”2.

[0125] At t”3, the horizontal summation phase PH”3 is triggered with two simultaneous pulses on the BIN and MEM1 signals, allowing the charges stored in the memory points POINT_MEM; j +iet POINT_MEMi+i j+ide to migrate respectively to the memory points POINT_MEMi and POINT_MEMI+, based on the same physical mechanism described previously. Thus, horizontal summation is performed after the PH”3 phase as shown in [Fig. 9d].

[0126] At t”4, the last phase of vertical reading and summation PH”4 is identical to the phase PH4 described in the summation operation for the first embodiment. The result of this phase is illustrated in [Fig.9e].

[0127] Figure 10 represents a third embodiment of a pixel sub-matrix according to the invention. Each pixel also incorporates an anti-glare transistor T7 controlled by an input signal AB and connected to the photoelectric element belonging to the same pixel. The control signal AB is common to all the anti-glare transistors of the pixels in the sub-matrix S. This transistor allows the photodiode to be reset to zero without passing through the detection nodes SN; jet SNij+i. It also allows the integration of the next image to be triggered before the current image has finished reading. This is referred to as "Integration While Read" (IWR).

[0128] Figure 11 illustrates an example of implementing the submatrices S according to the first embodiment of the invention to obtain a pixel matrix MP capable of performing a 2x2 pixel summation to obtain virtual macro-pixels of the same size and square aspect ratio. The butting of submatrices S belonging to the same column allows the connection of the conductive lines (COL; j, COUj+i...) that retrieve the signals at the outputs of the read stages (LECT, ,, LECTi+Lj...) for all j from 1 to M to form a main conductive line COLj. By repeating the butting operation in both spatial dimensions, the pixel matrix MP is obtained.

[0129] [Fig. 12] represents an example of implementation of a pixel matrix containing sub-matrices of pixels according to a variant of the second embodiment of the invention illustrated in [Fig. 8].

[0130] The submatrices are not abutted to one another but share common parts, as can be observed in submatrices SI and S2 in [Fig. 12]. Submatrix SI is composed of the pixels in columns C'j1 and C'j2. Submatrix S2 is composed of the pixels in columns C'j1 and C'j2. Submatrix S3 is composed of the pixels in columns C'j1 and C'j2.

[0131] Taking the example of submatrix SI, the summation stages 121 and 122 connect pixels belonging to the same column, not the same row, as described in [Fig. 8]. Furthermore, submatrix S2 comprises a single read stage 123 connected to the common detection node 124 of the two pixels belonging to row i+1 Li+i of submatrix S2. On the other hand, the adjacent submatrix SI comprises a single read stage 125 connected to the detection node 126 common to the two pixels of row i Li+i belonging to submatrix SL. The same arrangement is obtained for submatrix S3, creating an alternating symmetrical structure between the adjacent submatrices SI, S2, and S3.

[0132] It should be emphasized that this embodiment does not allow summation in both directions between lines within the same sub-matrix of pixels, but it represents the advantage of obtaining a more compact implementation compared to other embodiments.

[0133] Figure 13 shows a functional diagram of an IMG image sensor incorporating a pixel array according to one of the embodiments of the invention. The active pixel image sensor described in Figure 13 comprises the following elements.

[0134] An active pixel matrix MP contains at least one submatrix S implemented according to the invention. The matrix consists of rows and columns of pixels. In [Fig. 13], only one submatrix S has been shown in the matrix for simplicity.

[0135] The IMG image sensor also includes a CONT circuit for generating pixel control signals. This circuit controls the different operating phases of the active pixels in the MP array by generating, for each pixel, the signals SEL (with i from 1 to N / 2) for the read phase, TG (with i from 1 to N) for the charge transfer phase, and RST (with i from 1 to N / 2) for the reset of the detection nodes. The CONT control circuit also generates the MEM1, MEM2, and BIN signals, which manage the horizontal and vertical summation phases. In addition, this block generates two other control signals, namely SHR and SHS, which control the sampling phase.

[0136] The image sensor further includes a sampling circuit B1 arranged at the base of each column of the pixel matrix and connected to the output of the readout stage for each pixel in the corresponding column. A correlated double-sampling circuit B1 can be used to implement this function. This correlated double-sampling solution allows the signals to be read while eliminating the kTC noise generated in the pixels of the relevant column. First, the output signal of the pixel sampled after a reset is recorded. The recorded sample corresponds to the reset signal. Second, the signal sampled after the pixel has been exposed to light is recorded. The recorded sample corresponds to the desired signal. A subtraction between the two sampled signals eliminates the kTC noise.The result of this differential measurement, out_diff, is transmitted to an analog-to-digital converter not shown in [Fig. 13] for the sake of simplicity. It should be noted that the samples are always read line by line in the case of global or rolling shuttering.

[0137] The image sensor also includes a power supply circuit B2 to power each column of the pixel array. In [Fig. 13], this is a current source connected to the column conductor. This current source, common to all pixels in a column, is used to bias the transistors of the amplification stage when the pixel is read.

[0138] Other variants of the image sensor including an active pixel array according to the invention can be easily designed by a person skilled in the art.

[0139] The described invention enables the implementation of a CMOS image sensor whose matrix array is implemented using 2x2 submatrices, allowing the implementation of pixel binning functionality in the charge domain. This feature improves the sensitivity of the image sensor in low-light conditions and also reduces chain noise in the pixel array. This, in turn, increases the signal-to-noise ratio of the image sensor.

[0140] Thus, the solution described by the invention differs from the prior art, at least in that it performs pixel summation in the charge domain while remaining compatible with global shutter operation. Furthermore, the invention has the advantage of reducing the capacity of the detection node compared to the technique of sharing four pooled output nodes used by prior art implementations. The image sensor according to the invention still allows for operation without electrical charge summation, which gives those skilled in the art the flexibility to adapt the sensor operation to the image capture environment by modifying the sequence of control signals that govern the activation of analog pixel summation.

Claims

1. Claims A pixel matrix (MP) of N rows (L;) and M columns (Q) made in a semiconductor substrate, the matrix comprising at least one sub-matrix (S) of four adjacent pixels (Pxlÿ, Pxl^+^j, Pxli ,(j+i), Pxl each of the pixels of the sub-matrix (S) comprising: a set of a photoelectric effect element (EPE^, EPE; +1 j, EPEij+i, EPEi+ij+i) for generating electric charges in response to incident electromagnetic radiation and a memory point (POINTMEM,,, POINT_MEMi>j+1, POINT_MEMi+1>j, POINT_MEMi+i j+i) controlled by a first signal (MEM1) and connected to the output of the photoelectric effect element (EPEij, EPEi +l,j, EPEi,j+l, EPEi+l,j+l) for storing the generated electric charges, - a detection node (SNÿ,SNi,j+i), - a transfer grid (T3, T5, T6, T4), connected between the output of the memory point (POINT_MEM;j, POINT_MEM;j +b POINT_MEMi+1>j, POINT_MEMi+1,j+i) and the detection node (SN y,SN ij+i), - a summing stage (S0M1, S0M2), the summing stage being a switch controlled by a second signal (BIN) and connecting said pixel (Pxlÿ) to an adjacent pixel (PxlLJ +i) of the sub-matrix (S) belonging to the same line (Li) of said pixel (Pxlÿ); the summing stage being common with an adjacent pixel (Pxlij+i) of the sub-matrix (S) belonging to the same line (L;) of said pixel (Pxlÿ), said pixel matrix (MP) further comprising control means (CONT) configured to simultaneously apply a pulse to the first signal (BIN) and to the second signal (MEM1) so as to transfer the charges generated by said pixel (Pxlÿ) to the memory point (POINT_MEMij+i) of said adjacent pixel (Pxlij+1); at least one detection node (SNÿ,SNij+i) per sub-matrix (S) being common to two adjacent pixels (Pxlÿ, Pxl(i+i)j,) of the sub-matrix (S) belonging to the same column (Cj), the pixel matrix further comprising at least one reading stage (LECTijUECTij+i) per sub-matrix (S), connected to the common detection node (SNÿ,SNij+i).

2. A pixel array (MP) according to claim 1, wherein each of the photoelectric effect elements (EPE^, EPEi+ij, EPEij+i, EPEi+i j+i) is a pinched photodiode.

3. A pixel matrix (MP) according to any one of the preceding claims, wherein each of the summing stages (S0M1, S0M2) is realized by a pair of deep isolation trenches (dtil, dti2) arranged in parallel

4. A pixel matrix (MP) according to any one of the preceding claims, wherein each of the memory points (POINT_MEM; j) is produced by an arrangement of deep isolation trenches (dti3, dti4, dti5, dti6), the deep isolation trenches forming two confinements of the electric charges, the first confinement constituting the entrance of the memory point and the second confinement, doped with charge carriers at a dose greater than that of the first confinement, constituting the body of the memory point.

5. A pixel matrix (MP) according to any one of claims 1 to 3, in which each of the memory points (POINT_MEMij) is produced by an arrangement of two pairs of deep isolation trenches (dti3, dti4, dti5, dti6), the deep isolation trenches forming two confinements of the electric charges, the first confinement constituting the entrance of the memory point being formed by the first pair of trenches arranged in parallel and separated by a first distance, and the second confinement constituting the body of the memory point being formed by the second pair of trenches arranged in parallel and separated by a second distance; the first distance being less than the second distance.

6. A pixel matrix (MP) according to any one of claims 4 or 5, wherein: the summing stage (S0M1, S0M2) is connected between the output of the photoelectric effect element (EPEij) and the output of the photoelectric effect element of the adjacent pixel of the sub-matrix (S) belonging to the same row, the pixels (Pxlÿ, Px^+ijj, Pxli>(j+i), Pxl (i+i)j(j+i)) of the sub-matrix (S) belonging to the same column have a common detection node (SNij,SNij+i ) and a reading stage (LECT^LECTij+i).

7. A pixel matrix (MP) according to claim 6, wherein the control means (CONT) configured to apply for each pixel of the same column (Cj): - a high potential on the deep isolation trenches forming the memory point (POINT_MEM; j,POINT_MEM i+ij) to receive the electrical charges generated by the photoelectric effect element (EPEij); - a low potential on the deep isolation trenches forming the memory point (POINT_MEM; j +b POINT_MEMi+i j+i) belonging to the adjacent pixel (Pxlij+i) of the sub-matrix (S) belonging to the same row; - a low potential on the deep isolation trenches forming the summing stage (S0M1).

8. A pixel matrix (MP) according to claim 7, wherein the control means (CONT) are configured to apply simultaneously for each pixel of the same column (Cj): - a high potential on the deep isolation trenches forming the memory point (POINT_MEM; j, POINT_MEM; +ij); - a low potential on the deep isolation trenches forming the memory point (POINT_MEM; j +b POINT_MEMi+ij+i) belonging to the adjacent pixel (Pxll |+,) of the sub-matrix (S) belonging to the same row (L;); - a high potential on the deep isolation trenches forming the summing stage (S0M1, S0M2), to carry out a summation of the electric charges generated by the pixels (Pxl; j +i, Pxlij+i) belonging to the same row (L;, Li+i) of the sub-matrix (S).

9. A pixel matrix (MP) according to any one of claims 4 or 5, wherein the summing stage (S0M1, S0M2) of a pixel of the sub-matrix (S) is connected between the output of the memory point (POINT_MEM;j, POINT_MEMijj+1, POINT_MEMi+ljj, POINT_MEMi+1>j+1) and the output of the memory point of the pixel of the sub-matrix (S) belonging to the same row; the pixels (Pxly, Px^+py, Pxli>(j+i), Pxl (i+i)j(j+i)) of the sub-matrix (S) belonging to the same column have a common detection node (SNy) and a reading stage (LECTy).

10. A pixel matrix (MP) according to any one of claims 4 or 5, wherein the summing stage (SOM1, SOM2) of a pixel of the sub-matrix (S2) is connected between the output of the memory point (POINT_MEM;y, POINT_MEMij+1, POINT_MEMi+1 j, POINT_MEMi+1>j+1) and the output of the memory point of the pixel of the sub-matrix (S2) belonging to the same column, a first pair of pixels (Pxli+iy, Pxli+iy+i) of the sub-matrix (S2) belonging to the same row share a common detection node (SNy) and a reading stage (LECTy), a second pair of pixels (Pxly, Pxli+iy) of a sub-matrix (S2) belonging to the same column are shared with an adjacent sub-matrix (SI), the first pair of pixels (Pxl, j, Pxl +1 j+i) of the adjacent sub-matrix (SI) being arranged on a different line from the first pair of pixels of the sub-matrix (S2)

11. A pixel matrix (MP) according to one of claims 9 or 10, in which the control means (CONT) are configured to apply for each pixel of the sub-matrix (S) - a high potential on the deep isolation trenches forming the memory point (POINT_MEM;y, POINT_MEM; +ijPOINT_MEMij +i, POINT_MEMi+ij +[) to receive the electrical charges generated by the photoelectric effect elements (EPE;y, EPEi+iy, EPE;y+i, EPEi+iy+i); - a low potential on the deep isolation trenches forming the summing stages (SOM1, SOM2).

12. A pixel matrix (MP) according to claim 11, in which the control means (CONT) are configured to apply simultaneously to a pair of adjacent pixels in a first direction - a high potential on the deep isolation trenches forming the memory point (POINT_MEM; y, POINT_MEM; +ij); - a low potential on the deep isolation trenches forming the memory point (POINT_MEM; y +b POINT_MEMi+i j+i) belonging to the adjacent pixel (Pxl ij+i) of the sub-matrix (S) in a second direction different from the first direction; - a high potential on the deep isolation trenches forming the summing stages (S0M1, S0M2); to perform a summation of the electric charges generated by the adjacent pixels in the second direction.

13. A pixel matrix (MP) according to one of claims 8 or 12, in which the control means (CONT) are configured to apply, to the pair of adjacent pixels in a first direction, for example to two pixels of the same column (Cj), a high potential on the transfer gates (T3, T4) to carry out a summation of the electrical charges generated in the common reading stage (LECTi j).

14. A pixel matrix (MP) according to any one of the preceding claims, wherein each reading stage (LECTij,LECTij+i) comprises a reset transistor (T7) connected to the detection node for resetting the detection node (SNy) to a chosen supply voltage (VREF); an amplification transistor (T8) connected in common drain whose gate is connected to the detection node (SNy); a selection transistor (T9) connected to the output of the amplifier transistor (T8) for sampling the output signal.

15. Image sensor (IMG) comprising a pixel matrix (MP) according to any one of the preceding claims, a circuit for generating pixel control signals (CONT), a sampling circuit (Bl) arranged at the foot of each column of the pixel matrix connected to the output of the reading stage of each pixel of the corresponding column, a power supply circuit (B2) for powering each column of the pixel matrix.

16. Image sensor (IMG) according to claim 15 wherein the sampling circuit (Bl) is a correlated double sampling circuit.

17. Image sensor (IMG) according to one of claims 15 or 16, the sensor being adapted to global shutter operation.

Images