Method for manufacturing a system in a multi-layered package and associated manufacturing installation

Abstract

Method for manufacturing a system in a multi-layer package and associated manufacturing installation. The present invention relates to a method for manufacturing a system in a multi-layer package (SiP), comprising for each current layer the following steps: - fabrication (A) of a dielectric substrate by an additive manufacturing technique; - deposition (B) of an adhesive in receiving areas; - deposition (C) of electronic components in the corresponding receiving areas; - deposition (E) of interconnecting elements between the electronic components; - creation (F) of at least one interconnect with an adjacent layer; - encapsulation (G) of the current layer by a filler material, the filler material forming an outer surface; - preparation (H) of the outer surface for receiving the next layer. Figure for the abstract: Figure 2

Description

Title of the invention: Method for manufacturing a system in a multi-layered package and associated manufacturing installation

[0001] The present invention relates to a method of manufacturing a system in a multi-layered package.

[0002] The present invention also relates to a manufacturing installation associated with such a manufacturing process.

[0003] For the purposes of this invention, the term "system in a package" refers to any system more commonly known as a SiP (System in Package). Such a system is also known as a System-in-a-Package or Multi-Chip Module (or MCM).

[0004] As is known, a SiP refers to a system of integrated circuits that are confined within a single package. This type of system is widely used in the field of microelectronics, particularly in mobile telephony, computers, sensors, etc. In some cases, a SiP may comprise a stack of layers, which makes it particularly compact and therefore attractive for this type of application.

[0005] Generally, the realization of a SiP requires large investments in p-technology machines to assemble chips in three dimensions and thus compact the electronic functions in a block or package rather than on a flat surface.

[0006] These blocks are intended to be assembled onto a printed circuit board (PCB) so that they can be interconnected with other blocks or other discrete components. External connections are, for example, made by metallization in chemical deposition baths.

[0007] Several prior art methods aim to simplify the manufacture of a SiP or at least to make this manufacture more universal in order to be able to produce different SiPs.

[0008] Thus, methods are known, for example, for making the design of a SiP more flexible. According to some of these methods, the substrate on which different electronic components are placed has an interconnection matrix. This matrix presents a large number of possible interconnections, which are then chosen according to the electronic components placed and the requirements of their interconnection.

[0009] There are also methods for miniaturizing cards. Among these methods is the method known as Flip Chip. In the final stage of production, the chip is flipped over, and solder bumps are deposited on the chip's leads on the inverted surface. To connect it to other components, the chip is flipped over again, its leads are aligned with corresponding leads on the substrate, and they are heated to bond it to the rest of the substrate. This method is therefore the opposite of wire bonding, where the interconnections between the chips and the substrate are made using wires.

[0010] Among the methods for miniaturizing circuit boards, there is also the method known as Wafer-Level Packaging (WLP), in which the chips are encapsulated while remaining connected to one another, solder balls are added, and only then is the wafer cut to separate the chips. The encapsulated chip has the same surface area as the chip alone, which saves space on the circuit board compared to a conventional manufacturing method.

[0011] Finally, there are also 3D stacking methods for manufacturing multi-layer SiPs. For example, the method known as 3D integrated circuit (3D IC) allows for stacking multiple chips. Interconnections are most often achieved using a through-silicon via (TSV), which connects the chips internally, unlike techniques that connect the chips externally, for example, using wires.

[0012] Current SiP manufacturing methods therefore require expensive facilities that are difficult to adapt to the manufacture of other types of SiP and / or other types of electronic components. These methods cannot therefore be used to manufacture SiP in runs of thousands of parts.

[0013] To this end, the invention relates to a method for manufacturing a system in a multi-layered housing comprising, for each current layer, the following steps:

[0014] - fabrication of a dielectric substrate by an additive manufacturing technique, the substrate comprising a receiving surface the receiving surface comprising receiving areas configured to receive electronic components;

[0015] - depositing an adhesive in the receiving areas;

[0016] - depositing electronic components in the corresponding receiving areas;

[0017] - deposit of interconnection elements between electronic components;

[0018] - creation of at least one interconnection with an adjacent layer;

[0019] - encapsulation of the current layer by filling material, the rem material pleating forming an outer surface; and

[0020] - preparation of the outer surface for receiving the next layer.

[0021] The manufacturing process according to the invention thus makes it possible to use a single installation for all the manufacturing steps. Furthermore, an additive manufacturing technique implemented by this process makes it possible to manufacture a variety of SiP without any changes between each series produced, which makes the unit cost of each SiP very competitive.

[0022] According to other advantageous aspects of the invention, the method comprises one or more of the following features, taken individually or in all technically possible combinations:

[0023] - the step of producing the dielectric substrate includes its polymerization, of preferentially its photopolymerization;

[0024] - the additive manufacturing technique includes the stereolithography or the fused wire deposition technique;

[0025] - the glue application step is carried out by a screw conveyor or by a system of time pressure distribution;

[0026] - the electronic component deposition step is carried out by a deposition head, of Preferably, the electronic component deposition step also includes the placement of thermal drains glued onto the electronic components;

[0027] - the process further comprising a polymerization step of the glue put in work after the electronic component deposition stage and before the interconnect element deposition stage;

[0028] - the interconnecting element deposition step includes the deposition of conductive wires or conductive ink between electronic components;

[0029] - the step of creating at least one interconnection with an adjacent layer includes the application of a conductive adhesive or a plastic loaded with conductive particles;

[0030] - the current layer encapsulation step includes filling a volume delimited by the dielectric substrate by the filling material;

[0031] - the step of preparing the outer surface includes the implementation of a stripping technique;

[0032] - the method further comprising an optical inspection step implemented between at least some of those steps.

[0033] The present invention also relates to an installation for manufacturing a system in a multi-layered package (SiP), the installation comprising a plurality of modules adapted for implementing the process as described above.

[0034] These features and advantages of the invention will become apparent from the following description, given solely by way of non-limiting example, and made with reference to the accompanying drawings, in which:

[0035] - [Fig. 1] [Fig. 1] is a schematic view of a manufacturing installation according to the invention; and

[0036] - [Fig.2] [Fig.2] is a schematic view of the implementation of different steps of a manufacturing process according to the invention, the process being implemented by the installation of the [Fig.1].

[0037] Figure 1 illustrates a manufacturing installation 10 for a system-in-a-package, known as a SiP. In particular, such a manufacturing installation 10 makes it possible to produce multi-layered SiPs of different types.

[0038] To this end, with reference to [Fig.1], the manufacturing installation 10 includes an additive manufacturing module 12, a chip fixing module 14, a deposition module 16, an interconnection module 18, an encapsulation module 20 and a stripping module 22.

[0039] According to different embodiments of the manufacturing process, the manufacturing installation 10 may include other functional modules implementing at least partially at least certain steps of this process. For example, the manufacturing installation 10 may further include a heating module and / or a control module for controlling the deposition or placement of components.

[0040] The manufacturing installation 10 also includes mechanical means implementing the operation of these different modules 12 to 22, their interconnection as well as their connection to external sources.

[0041] Finally, the manufacturing installation 10 also includes a base suitable for receiving the SiP after its manufacture. In particular, each SiP can be produced on this base by activating the aforementioned modules 12 to 22, in accordance with the manufacturing process explained below.

[0042] The additive manufacturing module 12 presents a 3D printing machine capable of implementing an additive manufacturing technique to produce a dielectric substrate. The additive manufacturing technique includes, for example, stereolithography or fused deposition modeling (FDM). Thus, for example, this module 12 can operate by depositing ink layer by layer in the form of fine droplets.

[0043] The chip fixing module 14 includes, for example, a machine known as a die bonding machine. Such a machine may, for example, include a robot for depositing glue using a screw conveyor or a time-pressure dispensing system. In particular, such a dispensing system makes it possible to obtain a drop of glue of a repeatable size by controlling the pressure applied to a syringe containing the glue. By varying the application time, the size of the droplet can be adjusted. Under pressure, the size of the glue droplet can be controlled (larger or smaller).

[0044] The deposition module 16 includes, for example, a volumetric deposition head capable of picking up an electronic component and placing it on a substrate. Such a head can be made by a machine known as a Pick and Place machine, or can be part of the Die Bonding machine mentioned above.

[0045] The interconnection module 18 includes, for example, a machine known as a Wire Bonding machine configured to connect different electronic components using a wire. Alternatively, the interconnection module 18 includes a machine for depositing conductive ink. Such a machine can, for example, be adapted for implementing the flip-chip technique.

[0046] The encapsulation module 20 includes, for example, a machine known in English as Dam and FUI allowing the filling of a structure with a filling material.

[0047] Finally, the stripping module 22 includes a stripping head allowing a surface to be stripped using, for example, a plasma.

[0048] The manufacturing process of a SiP implemented by the manufacturing facility 10 will henceforth be explained with reference to [Fig.2].

[0049] The steps of this process are implemented consecutively for each layer forming the SiP.

[0050] In certain embodiments, between each step explained below or at least between some of these steps, a control step may be implemented during which the imaging control module may be used to check the deposits or the placement and orientation of the components.

[0051] In an initial step A, the additive manufacturing module 12 produces a dielectric substrate by implementing an additive manufacturing technique, as explained previously. This substrate is produced directly on the base when it is a first layer of SiP or on a surface stripped of another layer when it is an intermediate or final layer.

[0052] The substrate formed during this step includes a receiving surface comprising receiving areas configured to receive electronic components.

[0053] In particular, each receiving area has, for example, a cavity whose dimensions are adapted to receive a given electronic component. The locations of the receiving areas, as well as their dimensions, are determined, for example, according to a configuration file specific to each layer. In other words, such a configuration file forms a "map" of each layer. The additive manufacturing module 12 is therefore adapted to read such a file and deposit layers according to this file.

[0054] The substrate formed may further comprise a wall extending along the periphery of the substrate and forming part of the lateral surface of the SiP. Such a wall may further delimit an internal volume of the substrate receiving the electrical components as well as the filler material, as will be explained later.

[0055] The dielectric substrate can be deposited on a printed circuit board type substrate.

[0056] At the end of step A, the dielectric substrate can be polymerized, preferably by photopolymerization, to acquire its final properties.

[0057] During step B, the chip fixing module 14 deposits an adhesive into the receiving areas formed in the substrate. The adhesive can, for example, be chosen so as to have low expansion or at least an expansion adapted to the substrate.

[0058] During step C, the deposition module 16 deposits electronic components into the corresponding receiving areas. An electronic component is understood to mean, in particular, a chip or any other electronic element forming part of a SiP.

[0059] This step C may also include the installation of thermal drains, for example of a solid type (copper substrate, heat pipes), glued onto the electronic components.

[0060] During step D, the adhesive is polymerized. This polymerization is, for example, carried out by a heating module that provides local or global heating. Alternatively, the polymerization is performed at room temperature, without heating.

[0061] During step E, the interconnection module 18 deposits interconnection elements between the electronic components. The interconnection elements may then comprise conductive wires or conductive ink.

[0062] During step F, the interconnection module 18 creates an interconnection with at least one upper or lower layer, for example with conductive glue with a glue deposition module (syringes with glue) or a plastic, for example photopolymerizable polymer, loaded with metallic particles and this deposited with the additive manufacturing module 12.

[0063] During step G, the encapsulation module 20 encapsulates the current layer, for example by filling the volume delimited by the walls of the substrate to reach the same level as these walls. After filling, the filling material then forms an outer surface.

[0064] During step H, the stripping module 22 prepares the outer surface for receiving the next layer. In particular, as explained previously, this step may include stripping the outer surface.

[0065] Then, when a subsequent layer is to be created, steps A to H are therefore implemented again.

[0066] Of course, other embodiments of the invention are also possible.

Claims

Demands

1. A method for manufacturing a multi-layered system-in-a-package (SiP), the manufacturing method comprising, for each current layer, the following steps: - fabrication (A) of a dielectric substrate by an additive manufacturing technique, the substrate comprising a receiving surface, the receiving surface comprising receiving areas configured to receive electronic components; - deposition (B) of an adhesive in the receiving areas; - deposition (C) of electronic components in the corresponding receiving areas; - deposition (E) of interconnecting elements between the electronic components; - creation (F) of at least one interconnect with an adjacent layer; - encapsulation (G) of the current layer by filler material, the filler material forming an outer surface; - preparation (H) of the outer surface for receiving the next layer.

2. A method according to claim 1, wherein step (A) of making the dielectric substrate includes its polymerization, preferably its photopolymerization.

3. A method according to claim 1 or 2, wherein the additive manufacturing technique comprises the stereolithography technique or the fused filament deposition technique.

4. A method according to any one of the preceding claims, wherein the glue deposition step (B) is carried out by a screw conveyor or by a time-pressure distribution system.

5. A method according to any one of the preceding claims, wherein the step (C) of depositing the electronic components is carried out by a deposition head; preferably, the step (C) of depositing the electronic components further comprises the placement of thermal drains bonded to the electronic components.

6. A method according to any one of the preceding claims, further comprising a step (D) of polymerizing the adhesive carried out after step (C) of depositing the electronic components and before step (E) of depositing interconnection elements.

7. A method according to any one of the preceding claims, wherein the interconnect element deposition step (E) comprises the deposition of conductive wires or conductive ink between electronic components.

8. A method according to any one of the preceding claims, wherein the step (F) of creating at least one interconnection with an adjacent layer includes the deposition of a conductive adhesive or a plastic loaded with conductive particles.

9. A method according to any one of the preceding claims, wherein the current layer encapsulation step (G) comprises filling a volume delimited by the dielectric substrate with the filling material.

10. A method according to any one of the preceding claims, wherein the step (H) of preparing the outer surface includes the implementation of a stripping technique.

11. A method according to any one of the preceding claims, further comprising an optical inspection step carried out between at least some of said steps.

12. A manufacturing installation (10) for a multi-layered system-in-a-package (SiP), the installation comprising a plurality of modules (12, ..., 22) adapted for carrying out the process according to any one of the preceding claims

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