Method for manufacturing an organic electroluminescent device

Abstract

Method for manufacturing an organic electroluminescent device on a stack comprising successively: - a substrate (1), integrating thin-film n-type transistors (10), each comprising a drain (D), a source (S), and a gate (G); - an interconnection structure (2), electrically connected to the n-type transistors (10), and comprising: a common anode (20), electrically connected to the sources (S) of the n-type transistors (10); interconnection holes (21), each electrically connected to a drain (D) of an n-type transistor (10); the organic electroluminescent device being formed according to a direct architecture with a single cathode (6) at the pixel scale, controllable by means of a dedicated electrical contact pad (4) for a pixel. Figure 8

Description

Title of the invention: Method for manufacturing an organic electroluminescent device technical field

[0001] The invention relates to the technical field of manufacturing an organic electroluminescent device, in particular an organic light-emitting diode micro-screen.

[0002] The invention finds its application in particular in the manufacture of virtual or augmented reality glasses and headsets, camera viewfinders, head-up displays, pico-projectors etc. State of the art

[0003] A process for manufacturing an organic electroluminescent device known from the prior art, in particular from the document H.-H. Hsieh et al., "A 2.4 in. AMOLED with IGZO TFTs and inverted OLED Devices", SID, vol. 40, Issue 1, 2010, comprises the steps: aOi) use a stacking structure consisting successively of: - a substrate, integrating thin-film n-type transistors, each comprising a drain, a source and a gate; - an interconnection structure, electrically connected to the n-type transistors, and comprising: the first interconnection holes, each being electrically connected to a source of an n-type transistor; second interconnection holes, each being electrically connected to a drain of an n-type transistor; bOi) form: - a set of anodic layers on the interconnection structure, spaced apart to form a network of rows and columns, each anodic layer being electrically connected to a first interconnection hole, - an electrical contact pad on the interconnection structure, adjacent to the set of anodic layers, and electrically connected to the second interconnection holes; (Cqi) form a set of stacks of organic semiconductor layers, each stack of organic semiconductor layers extending over and around an anodic layer; doi) form a common cathode extending over the interconnection structure, over the entire stack of organic semiconductor layers and over the pad of electrical contact.

[0004] It appears advantageous to use thin-film transistors (TFTs), with the channel being made of a transparent conductive oxide (TCO) or a transparent semiconducting oxide (TSO) such as indium-gallium-zinc In-Ga-Zn oxide (IGZO). In particular, IGZO has shown better current stability for driving organic light-emitting devices such as organic light-emitting diode (OLED) microdisplays. TFTs are typically arranged to form a 2T-1C pixel power supply and addressing scheme, i.e., two TFT transistors and a capacitor drive one pixel.

[0005] However, such a prior art method is not entirely satisfactory insofar as a drift of the voltage VGs (voltage between the grid and the source) has been observed which leads to significant marking and an afterimage.

[0006] A method for manufacturing an organic electroluminescent device known from the prior art, in particular from the document H.-H. Hsieh et al., "A 2.4 in. AMOLED with IGZO TFTs and inverted OLED Devices", SID, vol. 40, Issue 1, 2010, comprises the steps: a02) Use a stacking structure consisting successively of: - a substrate, integrating thin-film n-type transistors, each comprising a drain, a source and a gate; - an interconnection structure, electrically connected to the n-type transistors, and comprising: the first interconnection holes, each being electrically connected to a source of an n-type transistor; second interconnection holes, each being electrically connected to a drain of an n-type transistor; b02) former: - a set of cathode layers on the interconnection structure, spaced apart to form a network of rows and columns, each cathode layer being electrically connected to a first interconnection hole, - an electrical contact pad on the interconnection structure, adjacent to the cathode layer assembly, and electrically connected to the second interconnection holes; CO2) form a set of stacks of organic semiconductor layers, each stack of organic semiconductor layers extending over and around a cathode layer; dta) form a common anode extending over the interconnection structure, on the assembly of stacks of organic semiconductor layers and on the electrical contact pad.

[0007] Such a prior art method forms the electroluminescent device (i.e., the stacks of semiconductor layers, the cathode layers, and the common anode) in reverse, meaning that the anode is in the upper position of the stack relative to the cathode. This inverted architecture drastically reduces marking.

[0008] However, such a prior art method is not entirely satisfactory with a significant series resistance due to a carrier injection problem between the cathode layer and the stack of organic semiconductor layers (more precisely with the electron injection layer), cf. J. Wang et al., “Efficient inverted organic light-emitting devices using a charge-generation unit as electron-injection layers”, Organic Electronics, vol. 96, 106202, 2021 and S. Madasamy et al, “An overview about the use of electrical doping of charge carrier transport layers in OLEDs andfurther organic electronic applications”, Proc. SPIE 6999, Organic Optoe-electronics and Photonics III, 69991E, 2008. Description of the invention

[0009] The invention aims to remedy, in whole or in part, the aforementioned drawbacks. To this end, the invention relates to a method for manufacturing an organic electroluminescent device, comprising the following steps: a) use a stacking structure consisting successively of: - a substrate, integrating thin-film n-type transistors, each comprising a drain, a source and a gate; - an interconnection structure, electrically connected to the n-type transistors, and comprising: a common anode, electrically connected to the sources of the n-type transistors; interconnection holes, each being electrically connected to a drain of an n-type transistor; b) form a set of anodic layers and a set of electrical contact pads on the interconnection structure, the anodic layers being spaced apart to form a network of rows and columns, each anodic layer being electrically connected to the common anode; each electrical contact pad being adjacent to an anodic layer and being electrically connected to an interconnection hole; c) form a set of stacks of organic semiconductor layers, each stack of organic semiconductor layers extending over a anodic layer and around said anodic layer, at a distance from the electrical contact pad adjacent to said anodic layer; d) form a cathode layer extending over the interconnection structure, over the entire stack of organic semiconductor layers and over the entire set of electrical contact pads; e) successively form an optical overlay layer and an encapsulation layer on the cathode layer; f) locally etch the encapsulation layer, the optical overlay layer and the cathode layer so as to electrically isolate the anodic layers from each other and form a pixel matrix; each pixel comprising an anodic layer and an electrical contact pad, adjacent to said anodic layer.

[0010] Thus, such a method according to the invention makes it possible to maintain a direct (i.e., non-inverted) common-anode architecture, with the cathode located in the uppermost position of the stack relative to the anode. The method according to the invention, thanks to step f), allows the cathode to be singled out at the pixel level, whereas it is very difficult, if not impossible, to locally deposit a cathode on a stack of semi-organic conductive layers corresponding to a pixel, particularly when the pitch is less than or equal to 10 pm. Each pixel can be driven by its corresponding electrical contact pad. Marking is reduced compared to the prior art thanks to this singled-out cathode at the pixel level, which helps to mitigate crosstalk between adjacent pixels.

[0011] The method according to the invention may include one or more of the following features.

[0012] According to one feature of the invention, step f) is performed by ion beam etching.

[0013] According to one feature of the invention, step f) is preceded by a step consisting of forming a photosensitive etching mask on the encapsulation layer formed during step e), the photosensitive etching mask being adapted to delimit the pixel matrix.

[0014] According to one feature of the invention, step b) is carried out so that the network of rows and columns has a pitch less than or equal to 10 pm.

[0015] According to one feature of the invention, step f) forms engraved areas; and step f) is followed by a step g) consisting of filling the engraved areas with an encapsulation material, preferably alumina A12O3. Thus, one advantage provided is the protection of pixels from air and humidity.

[0016] According to one feature of the invention, step e) is carried out so that the optical coating layer is made of silicon monoxide SiO.

[0017] According to a feature of the invention, step e) is carried out so that the encapsulation layer is made of alumina A12O3.

[0018] According to one feature of the invention, step d) is carried out so that the cathode layer is made of silver Ag.

[0019] According to one feature of the invention, steps d) and e) are carried out so that the cathode layer, the optical overlay layer and the encapsulation layer have a total thickness less than or equal to 75 nm. Thus, one advantage provided is to facilitate engraving during step f).

[0020] According to a feature of the invention: - step c) is executed with a shadow mask; - step d) is executed without a shadow mask. Thus, one advantage provided is in particular to reduce maintenance problems related to particulate contamination caused by the handling of shadow masks.

[0021] According to one feature of the invention, step c) is followed by a step consisting of removing the shadow mask in an inert atmosphere. Definitions

[0022] - By "substrate", we mean a self-supporting physical support, made of a material a base from which an electroluminescent device can be formed. A substrate can be a "slice" (also called a "wafer" in English) which is generally in the form of a disc cut from an ingot of crystalline material.

[0023] - By "stacking", we mean a succession of layers following a direction vertical (i.e. along the normal to the surface of the substrate where the interconnection structure is formed).

[0024] - By "interconnection structure", we mean a stacking of levels interconnections comprising metallic tracks embedded in a dielectric material. An interconnection structure is classically formed on the substrate by an initial BEOL (Back-End-Of-Line) fabrication unit.

[0025] - By "common anode" is meant an anode intended to be common to all the pixels.

[0026] - By "interconnection hole" ("via" in English), we mean a hole metallized allowing an electrical connection to be established, particularly between interconnection levels.

[0027] - By "cathodic layer", we mean a layer adapted to form a cathode, that is, an electrode that gives off electrons when the electroluminescent device is polarized.

[0028] - By "anodic layer", we mean a layer adapted to form an anode, that is, an electrode that gives holes (or receives electrons) when the electroluminescent device is polarized.

[0029] - By "optical capping layer", we refers to a layer whose optical index and thickness are adapted to optimize the extraction of light from the electroluminescent device.

[0030] - By "encapsulation layer", we mean a layer adapted to protect the electroluminescent device for air and humidity.

[0031] - The term "shadow mask" is also known as a stencil. Brief description of the drawings

[0032] Other features and advantages will become apparent in the detailed description of different embodiments of the invention, the description being accompanied by examples and references to the accompanying drawings.

[0033] [Fig-1] is a schematic cross-sectional view, illustrating step a) of a process according to the invention.

[0034] [Fig.2] is a schematic cross-sectional view, illustrating step b) of a method according to the invention.

[0035] [Fig. 3] is a schematic cross-sectional view illustrating step c) of a method according to the invention. For simplicity, each stack of organic semiconductor layers is represented by a single layer.

[0036] [Fig.4] is a schematic cross-sectional view, illustrating step d) of a method according to the invention.

[0037] [Fig. 5] is a schematic cross-sectional view illustrating step e) of a method according to the invention. For simplicity, the optical coating layer and the encapsulation layer are represented by a single layer.

[0038] [Fig.6] is a schematic cross-sectional view, illustrating a step in the formation of a photosensitive etching mask preceding step f).

[0039] [Fig.7] is a schematic cross-sectional view, illustrating step f) of a method according to the invention with the engraving mask illustrated in [Fig.6].

[0040] [Fig.8] is a schematic cross-sectional view, illustrating step g) of a method according to the invention following step f) illustrated in [Fig.7].

[0041] It should be noted that the drawings described above are schematic and are not necessarily to scale for the sake of legibility and to simplify their understanding. The sections are made along the normal to the surface of the substrate where the interconnection structure is formed. Detailed description of the implementation methods

[0042] Identical elements or elements performing the same function shall bear the same re- references for the different modes of implementation, for the sake of simplification.

[0043] An object of the invention is a method for manufacturing an organic electroluminescent device, comprising the steps: a) use a stacking structure consisting successively of: - a substrate 1, integrating thin-film type n transistors 10, each comprising a drain D, a source S and a gate G; - an interconnection structure 2, electrically connected to the n-type transistors 10, and comprising: a common anode 20, electrically connected to the sources S of the n-type transistors 10; interconnection holes 21, each being electrically connected to a drain D of an n-type transistor 10; b) form a set of anodic layers 3 and a set of electrical contact pads 4 on the interconnection structure 2, the anodic layers 3 being spaced apart to form a network of rows and columns, each anodic layer 3 being electrically connected to the common anode 20; each electrical contact pad 4 being adjacent to an anodic layer 3 and being electrically connected to an interconnection hole 21; (c) form a set of stacks 5 of organic semiconductor layers, each stack 5 of organic semiconductor layers extending over and around an anodic layer 3, at a distance from the electrical contact pad 4 adjacent to said anodic layer 3; d) form a cathode layer 6 extending over the interconnection structure 2, over the stack of organic semiconductor layers 5 and over the electrical contact pad set 4; e) successively form an optical cover layer 7 and an encapsulation layer 8 on the cathode layer 6; f) locally etch the encapsulation layer 8, the optical coating layer 7 and the cathode layer 6 so as to electrically isolate the anodic layers 3 from each other and form a pixel matrix; each pixel comprising an anodic layer 3 and an electrical contact pad 4, adjacent to said anodic layer 3. Step a)

[0044] Step a) is illustrated in [Fig. 1].

[0045] Step a) consists of using a stack comprising successively: - a substrate 1, integrating thin-film type n transistors 10, each comprising a drain D, a source S and a gate G; - an interconnection structure 2, electrically connected to the n-type transistors 10, and comprising: a common anode 20, electrically connected to the sources S of the n-type transistors 10; interconnection holes 21, each being electrically connected to a drain D of an n-type transistor 10.

[0046] By way of non-limiting example, substrate 1 can be made of silicon.

[0047] Thin-film type n transistors (TFTs for "Thin Film Transistors" in (English language) have a channel that can be implemented in: - a transparent conductive oxide (TCO for "Transparent Conductive Oxide" in English), - a transparent semiconducting oxide (TSO for "Transparent Semiconducting Oxide" in English) such as Indium-Gallium-Zinc oxide In-Ga-Zn (IGZO).

[0048] In particular, the IGZO has shown improved current stability for driving organic light-emitting diode (OLED) devices such as organic light-emitting diode (OLED) microdisplays. "Microdisplay" refers to a display in which each pixel has an area of ​​30 pm by 30 pm or less.

[0049] The thin-film type n transistors 10 are advantageously arranged to form a 2T-1C type pixel power supply and addressing scheme, i.e. two TFT type transistors and a capacitor drive one pixel.

[0050] The common anode 20 is electrically connected to the sources S of the n-type transistors 10, preferably via additional interconnection holes 22. The common anode 20 is advantageously embedded within the interconnection structure 2. The common anode 20 may be made of a metallic material. By way of non-limiting example, the metallic material may comprise a first layer of an aluminum-copper (Al-Cu) alloy and a second layer of titanium nitride (TiN).

[0051] When the substrate 1 is made of silicon, the interconnection holes 21 and the additional interconnection holes 22 can be of the TSV type (“Through-Silicon Via” in English). Step b)

[0052] Step b) is illustrated in [Fig.2].

[0053] Step b) consists of forming a set of anodic layers 3 and a set of electrical contact pads 4 on the interconnection structure 2, the anodic layers 3 being spaced apart to form a network of rows and columns. The set of anodic layers 3 and the set of electrical contact pads 4 can be deposited simultaneously on the interconnection structure 2 (final metallization level), for example by physical vapor deposition. Then the set of anodic layers 3 and the set of electrical contact pads 4 can be formed (i.e., delineated) by photolithography, for example using a photosensitive resin which will then be removed ('stripping'). The set of anodic layers 3 and the set of electrical contact pads 4 can be made of a metallic material. By way of non-limiting example, the metallic material may comprise a first layer of an aluminum-copper (Al-Cu) alloy and a second layer of titanium nitride (TiN). Each anodic layer 3 is electrically connected to the common anode 20, preferably via the additional interconnection holes 22. Each electrical contact pad 4 is adjacent to an anodic layer 3 and is electrically connected to an interconnection hole 21. Each electrical contact pad 4 is therefore connected to a drain D of an n-type transistor 10.

[0054] Step b) is advantageously carried out so that the network of rows and columns has a step (i.e., spatial period) less than or equal to 10 pm. Step c)

[0055] Step c) is illustrated in [Fig.3].

[0056] Step c) consists of forming a set of stacks 5 of organic semiconductor layers, each stack 5 of organic semiconductor layers extending over an anodic layer 3 and around said anodic layer 3, at a distance from the electrical contact pad 4 adjacent to said anodic layer 3.

[0057] By way of non-limiting example, each stack 5 of organic semiconductor layers may successively comprise: - a HIL (Hole Injection Loyer) layer formed on the anodic layer 3; - a hole transport layer (HTL); - an EML emissive layer (“Emissive Layer” in English); - an electron transport layer ETL (Electron Transport Layer in English); - an electron injection layer EIL (Electron Injection Layer in English).

[0058] By way of alternative, each stack 5 of organic semiconductor layers may successively comprise: - a HIL hole injection layer formed on the anodic layer 3; - an HTL hole transport layer; - an EML emissive layer; - a hole blocking layer (HBL) ; - an electron transport layer (ETL).

[0059] Step c) can be performed with a shadow mask. Step c) is advantageously followed by a step consisting of removing the shadow mask in an inert atmosphere, for example based on dinitrogen N2 or argon Ar.

[0060] The stacks 5 of organic semiconductor layers can be formed by a deposition technique known to those skilled in the art, for example, physical vapor deposition (PVD). By way of non-limiting example, each stack 5 of organic semiconductor layers can have a thickness on the order of 100 nm. Step d)

[0061] Step d) is illustrated in [Fig.4].

[0062] Step d) consists of forming a cathode layer 6 extending over the interconnection structure 2, over the stack of organic semiconductor layers 5 and over the electrical contact pad set 4.

[0063] Step d) is advantageously carried out so that the cathode layer 6 is made of a metallic material, preferably silver Ag. By way of non-limiting example, the cathode layer 6 may have a thickness of the order of 15 nm.

[0064] Step d) is advantageously carried out without a shadow mask. In other words, the cathode layer 6 is formed by a full-plate type deposit. Step e)

[0065] Step e) is illustrated in [Fig.5].

[0066] Step e) consists of successively forming an optical cover layer 7 and an encapsulation layer 8 on the cathode layer 6.

[0067] Step e) is advantageously carried out so that the optical coating layer 7 is made of silicon monoxide SiO₂. By way of non-limiting example, the optical coating layer 7 can be formed on the cathode layer 6 by physical vapor deposition (PVD). The optical coating layer 7 is electrically insulating. By way of non-limiting example, the optical coating layer 7 can have a thickness on the order of 25 nm.

[0068] Step e) is advantageously carried out so that the encapsulation layer 8 is made of alumina Al₂O₃. The alumina Al₂O₃ encapsulation layer 8 is preferably formed on the optical coating layer 7 by atomic layer deposition (ALD). The encapsulation layer 8 is electrically insulating. By way of non-limiting example, the encapsulation layer 8 may have a thickness on the order of 25 nm.

[0069] Steps d) and e) are advantageously carried out so that the cathode layer 6, the optical coating layer 7 and the encapsulation layer 8 have a total thickness less than or equal to 75 nm. Step f)

[0070] Step f) is illustrated in [Fig.7].

[0071] Step f) consists of locally etching the encapsulation layer 8, the optical coating layer 7, and the cathode layer 6 so as to electrically isolate the anodic layers 3 from each other and form a pixel matrix. Each pixel comprises an anodic layer 3 and an electrical contact pad 4 adjacent to said anodic layer 3.

[0072] As illustrated in [Fig. 6], step f) is advantageously preceded by a step consisting of forming a photosensitive etching mask 9 on the encapsulation layer 8 formed in step e), the photosensitive etching mask 9 being adapted to delimit the pixel array. By way of non-limiting example, the etching mask 9 may be a photosensitive resin such as a resin called JSR (e.g., JSR 420) marketed by JSR. The photosensitive etching mask 9 is made of an electrically insulating material. The photosensitive etching mask 9 is advantageously retained after step f). By way of non-limiting example, the photosensitive etching mask 9 may have a thickness on the order of 1.5 µm.

[0073] Step f) is advantageously carried out so that the set of electrical contact pads 4 is not exposed after the etching. More specifically, the photosensitive etching mask 9 (illustrated in [Fig. 6]) is designed so that the set of electrical contact pads 4 is not exposed after the etching.

[0074] Step f) is advantageously performed by ion beam etching (IBE). The parameters of the IBE etching, in particular the ion energy, the ion directivity and the ion beam density, will be adjusted by those skilled in the art according to the thickness and nature of the materials of the cathode layer 6, the optical coating layer 7 and the encapsulation layer 8.

[0075] By way of non-limiting example, when the cathode layer 6 is made of silver Ag, the optical coating layer 7 is made of silicon monoxide SiO, the encapsulation layer 8 is made of alumina Al2O3, the total thickness of these layers 6, 7, 8 not exceeding 75 nm, it is possible to perform IBE etching with an ion directivity of -5° and an ion beam current of 200 mA. Step g)

[0076] Step g) is illustrated in [Fig.8].

[0077] Step f) is advantageously followed by a step g) consisting of filling the areas etched in step f) with an encapsulation material 80, preferably alumina Al 2O3. Step g) is advantageously carried out so as to form a Super High Barrier (SHB) type barrier. The encapsulation material 80 is electrically insulating.

[0078] The invention is not limited to the embodiments described. A person skilled in the art is able to consider their technically feasible combinations, and their substitute equivalents.

Claims

Demands

1. A method for manufacturing an organic electroluminescent device, comprising the steps: a) using a stack comprising successively: - a substrate (1), integrating thin-film n-type transistors (10), each comprising a drain (D), a source (S), and a gate (G); - an interconnection structure (2), electrically connected to the n-type transistors (10), and comprising: a common anode (20), electrically connected to the sources (S) of the n-type transistors (10); interconnection holes (21), each being electrically connected to a drain (D) of an n-type transistor (10); b) form a set of anodic layers (3) and a set of electrical contact pads (4) on the interconnection structure (2), the anodic layers (3) being spaced apart to form a network of rows and columns, each anodic layer (3) being electrically connected to the common anode (20);each electrical contact pad (4) being adjacent to an anodic layer (3) and being electrically connected to an interconnection hole (21); c) forming an assembly of stacks (5) of organic semiconductor layers, each stack (5) of organic semiconductor layers extending over and around an anodic layer (3), at a distance from the electrical contact pad (4) adjacent to said anodic layer (3); d) forming a cathodic layer (6) extending over the interconnection structure (2), over the assembly of stacks (5) of organic semiconductor layers and over the assembly of electrical contact pads (4); e) successively forming an optical coating layer (7) and an encapsulation layer (8) on the cathodic layer (6);(f) locally etch the encapsulation layer (8), the optical overlay layer (7) and the cathode layer (6) so as to electrically isolate the anodic layers (3) from each other and form a pixel matrix; each pixel comprising an anodic layer (3) and an electrical contact pad (4) adjacent to said anodic layer (3).

2. A method according to claim 1, wherein step f) is performed by ion beam etching.

3. A method according to claim 1 or 2, wherein step f) is preceded by a step consisting of forming a photosensitive etching mask (9) on the encapsulation layer (8) formed during step e), the photosensitive etching mask (9) being adapted to delimit the pixel matrix.

4. A method according to any one of claims 1 to 3, wherein step b) is carried out so that the network of rows and columns has a pitch less than or equal to 10 pm.

5. A method according to any one of claims 1 to 4, wherein step f) forms etched areas; and step f) is followed by a step g) consisting of filling the etched areas with an encapsulation material (80), preferably alumina A12O3.

6. A method according to any one of claims 1 to 5, wherein step e) is carried out so that the optical coating layer (7) is made of silicon monoxide SiO.

7. A method according to any one of claims 1 to 6, wherein step e) is carried out so that the encapsulation layer (8) is made of alumina A12O3.

8. A method according to any one of claims 1 to 7, wherein step d) is carried out so that the cathode layer (6) is made of silver Ag.

9. A method according to any one of claims 1 to 8, wherein steps d) and e) are carried out so that the cathode layer (6), the optical coating layer (7) and the encapsulation layer (8) have a total thickness less than or equal to 75 nm.

10. A method according to any one of claims 1 to 9, wherein: - step c) is performed with a shadow mask; - step d) is performed without a shadow mask.

11. A method according to claim 10, wherein step c) is followed by a step of removing the shadow mask in an inert atmosphere.

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