Reading a multi-level non-volatile memory device, in particular a phase-change memory device, and multi-level non-volatile memory device

Abstract

Method for managing the operation of a multi-level non-volatile memory cell, the memory cell (MLB) comprising N levels, N being even and greater than two, corresponding respectively to N logic data likely to be stored in the memory cell and to N corresponding read current ranges, the method comprising a reading of the data stored in the memory cell comprising successive comparisons of a read current (Iread) delivered by the memory cell with reference currents (Iref) chosen from a set of N-1 reference currents having values ​​respectively situated between two different successive ranges, using a dichotomous algorithm starting with the reference current having the median value. Figure for the abstract: Fig 1

Description

Title of the invention: Reading a multi-level non-volatile memory device, in particular a phase-change memory device, and multi-level non-volatile memory device

[0001] Implementation and embodiment modes relate to multi-level non-volatile memories, in particular phase change memories (or PCM: Phase Change Memory) or even floating gate non-volatile memories, for example FLASH memories or even memories with buried selection transistor, and more particularly the reading of such memories.

[0002] Non-volatile memories generally store binary data on two levels corresponding to the two possible logical values ​​“0” and “1” of this binary data.

[0003] However, there are multi-level memories, having more than two levels, and capable of storing logical data capable of taking more than two logical values.

[0004] This makes it possible to obtain high-density memories that save space due to their capacity to store a higher number of logical data, and which can, for example, be used advantageously in artificial intelligence applications that require artificial neural networks (“ANN: Artificial Neural Network”) and convolutional neural networks (“CNN: Convolutional Neural Network”)•

[0005] There is a need to propose a solution allowing reliable, simple and rapid reading of such multi-level memories.

[0006] According to one embodiment, it is proposed to compare the read current delivered by the memory with reference currents successively chosen using a dichotomous algorithm.

[0007] According to one aspect, a method for managing the operation of a multi-level non-volatile memory cell is provided.

[0008] The memory cell comprises N levels, N being even and greater than two, corresponding respectively to N logical data likely to be stored in the memory cell and to N corresponding read current ranges.

[0009] The method according to this aspect comprises a reading of the data stored in the memory cell comprising successive comparisons of a reading current delivered by the memory cell with reference currents chosen from a set of N1 reference currents having values ​​respectively situated between two ranges successive different ones, using a dichotomous algorithm starting with the reference current having the median value.

[0010] The reading may comprise a supply of an adjustable current source and successive adjustments of the current source to cause it to deliver the successively chosen reference currents.

[0011] However, according to an advantageous mode of implementation, the reading comprises placing next to the memory cell, a reference memory cell structurally identical to the memory cell, and successive readings of this reference memory cell to make it deliver the corresponding reference currents.

[0012] The memory cell is for example but not exclusively a phase change type memory cell.

[0013] When the reference memory cell is phase-changing, the delivery of a reference current advantageously comprises placing the reference memory cell in an initialized state and applying a chosen reference voltage to the reference memory cell to cause it to deliver the corresponding reference current.

[0014] The method may further comprise programming the memory cell to the desired level and verifying the programming using said reading of the memory cell.

[0015] When the memory cell is phase-change, the programming of the memory cell at a level lower than the maximum level advantageously comprises programming of the memory cell at the maximum level then successive deliveries of erasing pulses of the memory cell respectively followed by successive readings of the memory cell until a reading current corresponding to the desired programming level is reached.

[0016] However, other methodologies for programming the memory cell at a level lower than the maximum level are possible.

[0017] According to another aspect there is provided a multi-level non-volatile memory device, comprising (in a minimal architecture) -at least one non-volatile memory cell comprising N levels, N being even and greater than two, corresponding respectively to N logical data capable of being stored in the memory cell and to N corresponding read current ranges, means for reading the data stored in the memory cell configured to carry out successive comparisons of a read current delivered by the memory cell with reference currents chosen from a set of N1 reference currents having values ​​respectively situated between two successive ranges different, using a dichotomous algorithm starting with the reference current having the median value.

[0018] According to one embodiment, the reading means comprise a reference memory cell located next to the memory cell and structurally identical to the memory cell and a reading module configured to carry out successive readings of this reference memory cell to make it deliver the corresponding reference currents.

[0019] According to one embodiment, the reading means comprise an adjustable current source and control means configured to carry out successive adjustments of the current source to cause it to deliver the successively chosen reference currents.

[0020] According to one embodiment, the memory cell is, by way of non-limiting example, a phase change type memory cell.

[0021] According to one embodiment, the reference memory cell of the phase change type is in an initialized state and the reading module is configured to apply a chosen reference voltage to the reference memory cell to cause it to deliver the corresponding reference current.

[0022] According to one embodiment, the device further comprises processing means configured to perform programming of the memory cell at the desired level and perform verification of the programming using said reading of the memory cell.

[0023] When the memory cell is phase-change, the processing means are advantageously configured to carry out programming of the memory cell at a level lower than the maximum level by carrying out programming of the memory cell at the maximum level then carrying out successive deliveries of erasing pulses of the memory cell respectively followed by successive readings of the memory cell until reaching a reading current corresponding to the desired programming level.

[0024] That being said, the processing means can be configured to apply other programming methodologies of the memory cell at a level lower than the maximum level.

[0025] Other advantages and characteristics of the invention will appear on examining the detailed description of non-limiting modes of implementation and embodiment, and the appended drawings in which: [Fig.l], [Fig.2], [Fig.3], [Fig.4], [Fig.5], [Fig.6], [Fig.7], [Fig.8], [Fig.9], [Fig. 10], [Fig. 11],

[0026] schematically illustrate modes of implementation and embodiment of the invention.

[0027] In [Fig. 1] the reference DISP designates a multi-level non-volatile memory device, comprising at least one non-volatile memory cell MLB comprising N levels, N being even and greater than two.

[0028] N is for example but not limited to equal to 4.

[0029] These levels correspond respectively to N logical data likely to be stored in the memory cell and to N corresponding read current ranges.

[0030] For example, when N is equal to 4, the 4 corresponding logical data can be equal respectively, in hexadecimal notation, to ObOO, ObOl, OblO and Obll.

[0031] The device DISP also comprises means for reading the data stored in the memory cell, configured as will be seen in more detail below, to carry out successive comparisons of a reading current Iread delivered by the memory cell MLB with reference currents Iref chosen from a set of N1 reference currents having values ​​respectively situated between two different successive ranges, using a dichotomous algorithm starting with the reference current having the median value.

[0032] Each reference current is delivered by an adjustable reference means REF, a possible structure of which will be discussed in more detail below.

[0033] The reading means here comprise, in addition to the reference means REF, a processing unit DGC, for example a microcontroller, capable of adjusting the reference means REF, and of recovering information representative of the data D stored in the memory cell MLB.

[0034] This information is delivered by a conventional reading amplifier AMP, forming part of the reading means, and comprising a first input El connected to the memory cell MLB to receive the reading current Iread, a second input E2 connected to the reference means REF to receive the reference current Iref, and an output OUT intended to deliver the information representative of the stored data D.

[0035] Although the memory cell may be any type of non-volatile memory cell, for example a floating gate and select transistor type memory cell buried, or a memory cell of the electrically erasable and programmable read-only memory (EEPROM) type, we will now describe an implementation and embodiment in which, unless otherwise stated, the MLB memory cell is of the phase change type.

[0036] As is well known to those skilled in the art, phase change memories are non-volatile memories based on the properties of phase change materials.

[0037] A phase change material has, in fact, the capacity to switch from a weakly resistive state to a resistive state thanks to its heating.

[0038] Phase change memories take advantage of the fact that the electrical resistances of different states of phase change materials are different in order to store data.

[0039] More precisely, when the memory is intended to store a binary logic value having two logic states, the phase change material has the capacity to switch from a resistive state (HRS, High Resistive State) to a weakly resistive state (LRS, Low Resistive State) under the effect of heat and the Joule effect generated by the application of a current between electrodes.

[0040] Switching from a resistive state to a weakly resistive state corresponds to a programming or activation operation called “SET”, i.e. an operation of writing a binary data value, for example a logic value 1.

[0041] The memory is then in a state called “initialized” (SET).

[0042] The switching from a weakly resistive state to the resistive state corresponds to an erasure or deactivation operation called “RESET”, that is to say an operation of writing an opposite binary data value, for example a logic value 0.

[0043] The memory is then in a so-called “reset” state (RESET).

[0044] To perform a programming or SET operation, the phase change material is heated between its crystallization and melting temperatures and then slowly cooled to obtain a crystalline phase. The current pulse therefore exhibits a slow decay.

[0045] On the other hand, to make the phase change material amorphous (erasure or RESET operation) it is heated above its melting temperature then cooled rapidly in order to freeze in the amorphous state at room temperature. The current pulse is therefore very short and abrupt.

[0046] As will be seen in more detail below, when the memory is multi-level, that is to say capable of storing logical data which can take N different logical values, it is possible to provide for the memory cell, intermediate states between the reset state (RESET) and the initialized state (SET).

[0047] Thus when N is equal to 4, two intermediate states can be provided corresponding respectively to a “partially reset” state and a “partially initialized” state.

[0048] The different states of the memory cell will be distinguished by the value of the read current Iread delivered by the memory cell.

[0049] [Fig.2] schematically illustrates a classic and known structure of a MLB phase change memory cell.

[0050] More precisely, it comprises a memory element for example comprising germanium, antimony and tellurium which have different resistance values ​​depending on the reset / partially reset / partially initialized / initialized states of the memory.

[0051] This memory element is associated with a heating device, for example two electrodes, which when a current flows through it heats the memory element by Joule effect to vary its resistance.

[0052] The memory cell MLB is associated with a selection transistor TS which is here a PNP bipolar transistor connected in series between the memory element and a cold supply point, typically the GND ground.

[0053] The base of the bipolar transistor is connected to a word line and is intended to receive a VWL voltage turning on this transistor so as to allow current to flow in the heating device so as to heat the memory element.

[0054] Of course, the bipolar transistor TS could be replaced by a MOS transistor, for example a PMOS transistor.

[0055] A CEL memory cell in an initialized state (SET) is for example intended to deliver in reading a current Iread of the order of 12 microamperes.

[0056] A CEL memory cell in its reset state (RESET) is likely to deliver a zero or almost zero Iread current.

[0057] A CEL memory cell in its partially reset state is capable of delivering, for example, a current Iread of the order of 4 microamperes.

[0058] A CEL memory cell in its partially initialized state is capable of delivering, for example, a current Iread of the order of 8 microamperes.

[0059] These currents are obtained in the presence, for example, of a voltage applied to the memory element of between 1.5 and 1.8 volts for a bipolar TS selection transistor and of between 0.4 and 0.5 volts for a MOS type selection transistor.

[0060] [Fig.3] illustrates in particular these different reading trends.

[0061] In practice and by way of non-limiting example, the values ​​of 0, 4, 8 and 12 microamperes correspond to target values ​​of reading currents Itread0, Itread1, Itread2, Itread3.

[0062] In practice, the effective reading currents can be located in ranges of values ​​PV1, PV2 and PV3 around the target values ​​Itread1, Itread2, Itread3 and in the range of values ​​PVO starting at the target value Itread0.

[0063] The ranges of values ​​PV1-PV3 have here, for the purposes of simplification, the same amplitude PV and the range of values ​​PVO has an amplitude equal to PV / 2.

[0064] This amplitude PV depends in particular on the sensitivity of the reading amplifier AMP and / or on a tolerance during programming / erasing of the memory cell.

[0065] As a non-limiting example, the PV amplitude can be taken equal to 1 microampere.

[0066] That being said, in practice in the case of a phase change memory cell, the PV range can, under certain conditions, increase with the increase in conductance.

[0067] Thus the range of values ​​PV3 can be greater than the range of values ​​PV2 itself greater than the range of values ​​PV 1 itself greater than the range of values ​​PVO.

[0068] However, for non-volatile floating-gate memory cells, the PV amplitude remains more or less constant.

[0069] As illustrated in [Fig.3], these target values ​​and their associated range of values ​​define here for the memory cell MLB, four levels LV0, LV1, LV2 and LV3 respectively associated with the following four logical values ​​of the data D: OObO, OObOl, OOblO and OObll.

[0070] Three reference currents Irefl, Iref2, Iref3, intended to be delivered by the reference means REF, are defined having values ​​located between the ranges of values ​​PV0-PV3, for example in the middle of the intervals between these ranges of values.

[0071] Thus, here the values ​​of these reference currents Irefl, Iref2, Iref3 are equal to 2, 4 and 6 microamperes respectively.

[0072] Figures 4 and 5 illustrate an example of programming the MLB memory cell.

[0073] This programming is done under the control of processing means incorporated in the DGC microcontroller.

[0074] Firstly, a PLS programming pulse ([Fig.4]) is delivered to the memory cell so as to place it in its initialized state (SET).

[0075] The memory cell then has level LV3 ([Fig.5]) corresponding to a reading current Iread of between 11.5 and 12.5 microamperes.

[0076] If we wish to program the memory cell at level LV2, corresponding to a reading current Iread of between 7.5 and 8.5 microamperes, we deliver to the cell- memory a BST1 burst of PLRS erase pulses until the desired read current is reached.

[0077] If it is desired to program the memory cell at level LV1, corresponding to a read current Iread of between 4.5 and 3.5 microamperes, another burst BST2 of erase pulses PLRS is delivered to the memory cell until the desired read current is reached.

[0078] If it is desired to reset (RESET) the memory cell to the LVO level, corresponding to a read current Iread of between 0.5 and 0 microamperes, another burst BST3 of erase pulses PLRS is delivered to the memory cell until the desired read current is reached.

[0079] In practice, after each erase pulse, a reading of the memory cell is carried out in the manner which will be explained below, to check the read current obtained and decide whether another erase pulse is necessary.

[0080] That being said, other programming schemes are possible.

[0081] More precisely, a first cycle can be carried out comprising a programming pulse, followed by an erasing pulse followed by a reading of the memory cell. If the desired reading current is not obtained, the same cycle is repeated but with an erasing pulse of more adjusted amplitude. And these cycles are repeated until the desired reading current is obtained.

[0082] We now refer more particularly to [Fig.6] to describe a mode of implementing a reading of the MLB memory cell to determine the logical data stored there.

[0083] The DGC microcontroller adjusts the reference means so as to make it deliver the reference current Iref2 having the median value among the values ​​of the set of reference currents Irefl-Iref3 (step ST60).

[0084] Then the reading means carry out a reading of the memory cell MLB (step ST61) by applying a reading voltage to the memory cell so as to make it deliver the reading current Iread.

[0085] The sense amplifier AMP then compares (step ST62) the read current Iread with the reference current Iref2.

[0086] If the reference current Iref2 is lower than the current Iread, then the result Res delivered by the amplifier AMP corresponds to a logic “1”.

[0087] This means that the reading current Iread is located in the interval to the right of Iref2 in [Fig.3].

[0088] If the reference current Iref2 is greater than the current Iread, then the result Res delivered by the amplifier AMP corresponds to a logic “0”.

[0089] This means that the reading current Iread is located in the interval to the left of Iref2 in [Fig.3].

[0090] The microcontroller will then implement a dichotomous algorithm so as to reduce the interval considered by half and so on so as to obtain the value of the data D stored in the memory cell.

[0091] More precisely, if in step ST62, the result Res is equal to 1, the microcontroller will adjust the reference means REF so that it delivers the reference current Iref3 (step ST66).

[0092] The reading means perform a new reading of the memory cell MLB (step ST67).

[0093] The corresponding reading current Iread is compared in the reading amplifier AMP with the reference current Iref3.

[0094] If Iref3 is less than Iread, which corresponds to a result Res equal to “1”, this means that the current Iread is located in the interval to the right of Iref3 in [Fig.3],

[0095] Consequently, as there is no longer an interval to reduce by half and therefore no more uncertainty about the value of the logical data, the data D has in this case the logical value Obll.

[0096] If Iref3 is greater than Iread, which corresponds to a result Res equal to “0”, this means that the current Iread is located in the interval to the left of Iref3 in [Fig.3],

[0097] Consequently, as there is no longer an interval to reduce by half and therefore no more uncertainty about the value of the logical data, the data D has in this case the logical value OblO.

[0098] More precisely, if in step ST62, the result Res is equal to 0, the microcontroller will adjust the reference means REF so that it delivers the reference current Irefl (step ST63).

[0099] The reading means perform a new reading of the memory cell MLB (step ST64).

[0100] The corresponding reading current Iread is compared in the reading amplifier AMP with the reference current Irefl.

[0101] If Irefl is less than Iread, which corresponds to a result Res equal to “1”, this means that the current Iread is located in the interval to the right of Irefl in [Fig.3],

[0102] Consequently, as there is no longer an interval to reduce by half and therefore no more uncertainty about the value of the logical data, the data D has in this case the logical value ObOl.

[0103] If Irefl is greater than Iread, which corresponds to a result Res equal to “0”, this means that the current Iread is located in the interval to the left of Irefl in [Fig.3],

[0104] Consequently, as there is no longer an interval to reduce by half and therefore no more uncertainty about the value of the logical data, the data D has in this case the logical value ObOO.

[0105] [Fig.7] illustrates the implementation of the dichotomous algorithm in the general case for N even and greater than 3.

[0106] The algorithm uses a parameter A which is initialized to the value 2.

[0107] The microcontroller adjusts the reference means REF so that it delivers a current Iref equal to Imax / A (step ST70).

[0108] Imax denotes the maximum value among the target values ​​of the reading currents.

[0109] In the case of [Fig.6], Imax was the value of the current Itread3, i.e. 12 microamperes.

[0110] Then in step ST71, the memory cell MLB is read.

[0111] If the result Res is equal to 1, we double the value of A (step ST72) and the microcontroller adjusts in step ST73, the reference means REF so that it delivers a current Iref having the previous value increased by N.hnax / A.(N-1).

[0112] If the result Res is equal to 0, the value of A is doubled (step ST75) and the microcontroller adjusts in step ST76, the reference means REF so that it delivers a current Iref having the previous value reduced by N.Imax / A.(Nl).

[0113] If in step ST74, A is less than or equal to N, the microcontroller loops back to step ST71.

[0114] If, on the other hand, A is greater than N, this means that the entire dichotomy has been carried out and that the value of the data D has been determined.

[0115] Reference will now be made more particularly to FIGS. 8 and 9 to describe an embodiment and implementation of a reference means REF.

[0116] Such an embodiment and implementation is described in another French patent application filed in the name of the Applicant on the same day as the present patent application and entitled “Phase change type memory device and method for reading such a device”.

[0117] Those skilled in the art may refer for all useful purposes to this other patent application.

[0118] We will now recall here the characteristics of this embodiment and implementation, which provides for the reference means REF the use of a reference memory cell CELR ([Fig.8]) of the phase change type.

[0119] The MLB memory cell and the CELR reference memory cell have an identical structure and are placed side by side.

[0120] The reference memory cell is in an initialized state (SET) and a reading module is configured to apply a chosen reference voltage to the reference memory cell to cause it to deliver the corresponding reference current.

[0121] The base of the bipolar selection transistor TSR associated with the reference memory cell CELR is also intended to receive the VWL voltage.

[0122] Of course, the bipolar transistor TSR could be replaced by a MOS transistor, for example a PMOS transistor.

[0123] The memory device DISP also comprises a bit line BL associated with the memory cell MLB and a bit line BRL associated with the reference memory cell CELR.

[0124] The RC reference designates the parasitic resistances and capacities resulting from the interconnections between the different elements of the DISP device.

[0125] The reading module includes a first voltage generator GEN1 and a second voltage generator GEN2 intended to be connected respectively to the bit lines BL and BLR.

[0126] Furthermore, the bit lines BL and BLR are respectively connected to the two inputs E1 and E2 of the read amplifier AMP.

[0127] The memory cell MLB is connected to the bit line BL while the reference cell CELR is connected to the bit line BLR.

[0128] The fact that the memory cell MLB and the reference memory cell are placed side by side allows the voltages applied to the selection transistor bases TS and TSR to be substantially the same and the read paths of the memory cell MLB and the read paths of the reference memory cell CELR to be correctly balanced.

[0129] As an indication, it will be possible to advantageously choose a distance of between 10 micrometers and 20 micrometers separating the MLB memory cell and the CELR reference memory cell for 18 nanometer technology.

[0130] Of course, this distance value is only an example and those skilled in the art will know how to adjust this value, if necessary, depending in particular on the characteristics of the memory cells and the reading schemes.

[0131] The CEL cell readout is a single input readout (as opposed to a differential readout) described with reference to [Fig.9].

[0132] In a step ST31, a voltage VBL1 is first applied to the bit line BL and a voltage VBL2 to the bit line BLR.

[0133] These two voltages VBL1 and VBL2 are respectively delivered by the two current generators GEN 1 and GEN2.

[0134] The voltage VBL1 is that which makes it possible to obtain a current corresponding to the initialized state of the MLB memory cell (typically 12 microamps).

[0135] For a bipolar selection transistor, a voltage VBL1 between 1.5V and 1.8V will be chosen.

[0136] The voltage VBL2 is a voltage less than or equal to the voltage VBL1, so as to deliver the chosen reference current to the reference memory cell CELR.

[0137] As an example, to obtain the reference current Iref 3 (10 microamperes), we will take, for a bipolar selection transistor, a voltage VBL2 between 1.5V and 1.8V.

[0138] As an example, to obtain the reference current Iref 2 (6 microamperes), we will take, for a bipolar selection transistor, a voltage VBL2 between 1.35V and 1.7V.

[0139] As an example, to obtain the reference current Iref 1 (2 microamperes), we will take, for a bipolar selection transistor, a voltage VBL2 between 1.2V and 1.55V.

[0140] Once the bit lines BL and BLR have been biased with voltages VBL1 and VBL2 in step ST31, the bit lines BL and BLR are made floating (step ST32) for example by disconnecting the two generators GEN1 and GEN2 from the bit lines BL and BLR or by stopping them.

[0141] With transistors TS and TSR on, memory cell MLB draws current Iread flowing in bit line BL while reference memory cell CELR draws reference current Iref flowing in bit line BLR (step ST33).

[0142] These two currents Iref and Iread are compared (step ST34) in the reading amplifier AMP.

[0143] If the current Iref is less than the current Iread then the result Res is equal to 1.

[0144] If the current Iread is greater than the current Iref, then the result Res is equal to 0.

[0145] It is also possible, as illustrated in [Fig.10], to use an adjustable current source SC as a reference means REF, instead of a reference memory cell CELR.

[0146] The DGC microcontroller incorporates control means capable of adjusting the current source SC to make it deliver the chosen reference current.

[0147] The current source SC then draws a current Iref (chosen from the set of currents Irefl-Iref3) into the bit line BLR while the memory cell MLB draws a current Iread into the bit line BL.

[0148] The two currents are compared in the sense amplifier AMP.

[0149] However, the single-input mode readout using the CELR reference memory cell is more accurate compared to the single-input readout method using a current source because it is less sensitive to the resistance offset of the MLB memory cell and to the structural offsets observed between a memory cell and a current source.

[0150] Generally in practice, the memory device comprises a memory plane comprising a matrix of memory cells organized in rows and columns.

[0151] Thus, as illustrated in [Fig. 11] in which the memory cells are referenced with the root CEL, a row of memory cells comprises groups of several memory cells.

[0152] For the purposes of simplification, [Fig.l 1] illustrates a single group of several memory cells CELGi and CELDi respectively coupled to the first input El of the reading amplifier AMP via controllable switches SW.

[0153] A single reference memory cell CELR is associated with this group of memory cells CEL.

[0154] This offers a significant saving of space on silicon.

[0155] And this reference memory cell is connected to the second input E2 of the reading amplifier as indicated above.

[0156] Control means MCM, for example a logic circuit, are then configured to successively select said switches SW so that the reading means can successively read each memory cell CEL as explained above.

[0157] In practice, it will be possible to choose, for example, groups of Nb memory cells associated with a single reference memory cell CELR.

[0158] And, in order not to move the memory cells of this group too far from the reference memory cell, we will choose a number Nb of memory cells partitioned into two subgroups of Nb / 2 memory cells.

[0159] And, as illustrated in [Fig.l 1], the reference memory cell CELR is framed by a first subgroup of Nb / 2 memory cells CELGi-CELGNb / 2 and by a second group of Nb / 2 memory cells CELDi-CELDNb / 2.

[0160] The distance DD between each CELGi-CELDi memory cell immediately adjacent to the reference memory cell is, as indicated above, preferably of the order of 10 to 20 microns.

[0161] And, the person skilled in the art will choose the value of Nb / 2 so that the memory cells CELGNb / 2-CELDNb / 2 furthest from the reference cell are not too impacted by too great a distance from the reference memory cell CELR.

[0162] For example, groups of 8 memory cells can be chosen on each line of the memory plan.

[0163] Each group is then associated with a reference cell framed on the left and right by 4 memory cells.

[0164] And, for example, we first read the first cell on the left MLBGi then successively the other cells on the left until we read the cell MLBGNb / 2.

[0165] Then, we read the first cell on the right MLBDi then successively the other cells on the right until we read the cell MLBDNb / 2.

[0166] Of course, any other reading order is possible.

[0167] As indicated above, the invention, and in particular the reading using a dichotomous algorithm, applies to any type of multi-level non-volatile memory, for example to a memory with a floating gate and selection transistor buried in the semiconductor substrate.

[0168] However, for such a type of memory, the programming of the different levels is carried out by completely erasing the memory to obtain level LV0 and then successively programming the memory to obtain levels LV1 and following until the desired level is obtained.

[0169] This is therefore the opposite of what is done for a phase change memory where the memory is first programmed at the highest level (SET) then the memory is progressively erased to obtain the lower levels until the desired level is obtained.

Claims

Claims

1. Method for managing the operation of a multi-level non-volatile memory cell, the memory cell (MLB) being a phase-change type memory cell comprising N levels, N being even and greater than two, corresponding respectively to N logic data capable of being stored in the memory cell and to N corresponding read current ranges, the method comprising a reading of the data stored in the memory cell comprising successive comparisons of a read current (Iread) delivered by the memory cell with reference currents (Iref) chosen from a set of Nl reference currents having values ​​respectively situated between two different successive ranges, using a dichotomous algorithm starting with the reference current having the median value, in which the reading comprises a placement next to the memory cell,of a phase-change reference memory cell (CELR) structurally identical to the memory cell, and successive readings of this reference memory cell to make it deliver the corresponding reference currents, the delivery of a reference current comprising the placement of the reference memory cell in an initialized state and an application of a chosen reference voltage to the reference memory cell to make it deliver the corresponding reference current.,

2. The method of claim 1, further comprising programming the memory cell (MLB) to the desired level and verifying the programming using said reading of the memory cell.

3. Method according to claim 2, in which the programming of the memory cell to a level lower than the maximum level comprises a programming (PLS) of the memory cell to the maximum level then successive deliveries of erase pulses (PLRS) of the memory cell respectively followed by successive readings of the memory cell until reaching a reading current corresponding to the desired programming level.

4. Multi-level non-volatile memory device, comprising at least one non-volatile memory cell (MLB) of the phase-change type having N levels, N being even and greater than two, corresponding respectively to N logic data capable of being stored in the memory cell and to N corresponding read current ranges, reading means (DGC, CELR, GEN1, GEN2, AMP) of the data (D) stored in the memory cell configured to carry out successive comparisons of a read current delivered by the memory cell with reference currents chosen from a set of N1 reference currents having values ​​respectively situated between two different successive ranges, using a dichotomous algorithm starting with the reference current having the median value in which the reading means comprise a reference memory cell (CELR) of the phase-change type,located next to the memory cell and structurally identical to the memory cell, and a reading module (GEN1, GEN2) configured to carry out successive readings of this reference memory cell to make it deliver the corresponding reference currents, in which the reference memory cell (CELR) is in an initialized state and the reading module is configured to apply a chosen reference voltage to the reference memory cell to make it deliver the corresponding reference current.,

5. Device according to claim 4, further comprising processing means (DGC) configured to perform programming of the memory cell to the desired level and perform verification of the programming using said reading of the memory cell.

6. Device according to claim 5, in which the processing means are configured to carry out programming of the memory cell (MLB) at a level lower than the maximum level by carrying out programming of the memory cell at the maximum level then carrying out successive deliveries of erasing pulses of the memory cell respectively followed by successive readings of the memory cell until reaching a reading current corresponding to the desired programming level.

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