Display pixels comprising light-emitting diodes and display screens comprising such display pixels

Abstract

Display pixel comprising light-emitting diodes and display screen comprising such display pixels. This description relates to a display pixel (12i,j) comprising at least one light-emitting diode (LED), a controllable current source (CS) supplying said LED with current pulses, and an electronic circuit (40) comprising a storage circuit (48) for storing at least one digital signal (R, G, B) and a driver circuit (50) configured to control the current source (CS) to provide the current pulses by pulse-width modulation and pulse-amplitude modulation on the basis of the digital signal (R, G, B). Figure for the abstract: Fig. 4

Description

Title of the invention: Display pixels comprising light-emitting diodes and display screen comprising such display pixels technical field

[0001] This description relates to a display pixel comprising light-emitting diodes and a display screen comprising such display pixels. Prior art

[0002] A pixel of an image corresponds to the unit element of the image displayed by a display screen. For displaying color images, the display screen generally comprises, for the display of each pixel of the image, at least three components, also called display sub-pixels, each of which emits light, called the color component of the image pixel, essentially in a single color (for example, red, green, and blue). The superposition of the color components of the image pixel emitted by the three display sub-pixels provides the observer with the color sensation corresponding to the pixel of the displayed image. In this case, the set formed by the three display sub-pixels used for displaying a pixel of an image is called the display pixel of the display screen. Each display sub-pixel may include a light source, in particular a light-emitting diode.

[0003] The display pixels can be arranged in a matrix, each display pixel being located at the intersection of a row and a column of the matrix. Electrodes are provided along the rows and columns to connect each display pixel to control circuits. In general, each row of display pixels is successively selected by a signal transmitted along the row electrodes, and the display pixels of the selected row are programmed to display the desired image pixels by signals transmitted along the column electrodes.

[0004] The human eye is much more sensitive to variations in dark tones than to similar variations in light tones. A photodetector generally provides an analog electrical signal for an image pixel that exhibits a practically linear relationship with the number of photons striking the sensor. If the display system operated with a digital control method such as pulse-width modulation, a large number of bits would be required for the digital signals of the image pixels in order to describe the dark tones with sufficient accuracy. Digitization with a low number of bits results in image posterization. displayed for dark tones.

[0005] To optimize bit usage during image encoding and / or to optimize the bandwidth used to transmit an image, a nonlinear operation, generally called gamma coding or gamma compression, is applied to the image pixel signal provided by the photodetector to redistribute the native tone levels of the image sensor into levels that are more uniform in terms of perception for the human eye. Gamma coding is, for example, defined by the following power-law expression:

[0006] [Math 1] Vb = Vavc where the real non-negative input value Va is raised to the power yc to obtain the output value Vb, with, for example, Va and Vb in the range 0-1. The exponent yc is usually equal to 1 / 2.2.

[0007] To display the image pixel, the inverse nonlinear operation, called gamma decoding or gamma expansion, is applied to the image pixel signal to efficiently convert it back into light from the original scene. Gamma decoding is, for example, defined by the following power-law expression:

[0008] [Math 2] Vd = Vc'" where the real non-negative input value Vc is raised to the power yd to obtain the output value Vd, with, for example, Vc and Vd in the range 0-1. The exponent yd is usually equal to 1 / yc, i.e. for example equal to 2.2.

[0009] Figure 1 shows an example of an ideal gamma decoding function Igam corresponding to a power-law expression with an exponent of 2.2, and, by comparison, a linear function Lin. In Figure 1, the y-axis indicates the luminance in arbitrary units and the x-axis indicates the number of levels in the grayscale (Input grayscale). For tones to appear smooth and continuous in an image, it is generally sufficient to be able to encode at least 256 different levels for the luminance L, which theoretically should only require 8 bits.

[0010] However, during the use of gamma encoding and gamma decoding, posterization may still appear on the displayed image for very dark tones when the display system operates with a digital control method such as pulse width modulation.

[0011] Figure 2 shows the evolution curves of the gamma decoding functions which are enlarged for low gray levels, illustrating the need to increase the number of bits for smooth gamma decoding at low gray levels. In [Fig. 2], the y-axis indicates luminance in arbitrary units and the x-axis indicates the number of grayscale levels (Input grayscale). By In particular, [Fig. 2] shows a gamma decoding function Rgaml2 actually obtained with 12-bit encoding (mixed dashed line), a gamma decoding function Rgaml4 actually obtained with 14-bit encoding (thick solid line), a gamma decoding function Rgamlô actually obtained with 16-bit encoding (dashed line), a gamma decoding function Rgaml8 actually obtained with 18-bit encoding (dashed line), and a gamma decoding function Rgam20 actually obtained with 20-bit encoding (thin solid line). Each gamma decoding function Rgaml2, Rgaml4, Rgamlô, Rgaml8, and Rgam20 corresponds to a gamma decoding function for a 10-bit video input.

[0012] As shown in [Fig. 2], there is a stepped portion for each of the curves Rgaml2, Rgaml4, Rgamlô, and Rgaml8, and there is no stepped portion for the curve Rgam20. In [Fig. 2], the stepped portions are clearly visible for the curves Rgaml2 and Rgaml4, and stepped portions can be detected for the curves Rgamlô and Rgaml8 at very low gray levels (in particular for levels 0-8). This means, for example, for the curve Rgaml4, that an image pixel with an ideal luminance L in the range 0-8 results in the display of an image pixel having an actual luminance L equal to 0, or that an image pixel with an ideal luminance L in the range 9-13 results in the display of an image pixel with an actual luminance L having a constant value. Encoding of at least 20 bits must be used so that dark tones are displayed with high accuracy when using gamma encoding and decoding.However, increasing the bit depth of digital image pixel signals requires a higher bandwidth interface for video data, which is undesirable. Furthermore, the operation of the pulse-width modulation (PWM) display system may require the generation of pulses of varying durations. A drawback is that increasing the bit depth of digital image pixel signals may necessitate decreasing the duration of the shortest pulse, which can be difficult to generate. Summary of the invention.

[0013] An object of an embodiment is to provide a display pixel comprising light-emitting diodes and a display screen comprising such display pixels which overcome all or part of the disadvantages of existing display pixels comprising light-emitting diodes and display screens comprising such display pixels.

[0014] Another object is to reduce, or even eliminate, the posterization of an image displayed in dark tones.

[0015] Another object is the number of bits of the signals of the digital image pixels remains weak.

[0016] An embodiment provides a display pixel comprising at least one light-emitting diode, a controllable current source supplying said light-emitting diode with successive current pulses, and an electronic circuit comprising a storage circuit for storing at least one digital signal comprising several bits and a driver circuit configured to control the current source to provide the successive current pulses by pulse-width modulation by providing the successive current pulses having different durations that depend on the bits of the digital signal, and is configured to control the current source to provide the successive current pulses by pulse-amplitude modulation by providing the successive current pulses having the same intensity selected from at least the first and second intensity.This advantageously allows for a more precise gamma decoding function without increasing the number of bits in the video input.

[0017] According to one embodiment, the driver circuit is configured to control the controllable current source to supply successive current pulses by pulse-width modulation based on the digital signal at the first intensity when a first binary signal is at a first logic value, and to control the controllable current source to supply successive current pulses by pulse-width modulation based on the digital signal at the second intensity, greater than the first intensity, when the first binary signal is at a second logic value. This advantageously allows the pulse amplitude modulation to be controlled with the first binary signal.

[0018] According to one embodiment, the electronic circuit is configured to receive the first binary signal from outside the display pixel. This advantageously allows the pulse amplitude modulation to be controlled by adding a single bit, i.e., the first binary signal, to the video input.

[0019] According to one embodiment, the controllable current source comprises a first constant current source in series with a first switch and a second constant current source in series with a second switch. The driver circuit is configured, when the first binary signal is at the second logic value, to control the first and second switches by pulse-width modulation based on the digital signal and, when the first binary signal is at the first logic value, to open the first switch and to control the second switch by pulse-width modulation based on the digital signal. This advantageously allows for pulse amplitude modulation with two current intensity levels.

[0020] According to one embodiment, the pilot circuit includes a logic gate of the type The AND gate has a first input receiving the first binary signal and a second input successively receiving the bits of the digital signal. The output of the AND logic gate controls the first switch. The driver circuit is configured to control the second switch based on successive bits of the digital signal.

[0021] According to one embodiment, the light-emitting diode comprises a first set of elementary LEDs and a second set of elementary LEDs, wherein the elementary LEDs of the first set are connected to the first constant current source and the elementary LEDs of the second set are connected to the second constant current source. Consequently, the current density through each elementary LED remains constant during the pulse amplitude modulation.

[0022] According to one embodiment, the light-emitting diode is connected to the first constant current source and to the second constant current source.

[0023] According to one embodiment, the driver circuit is configured to control said LED, when a second binary signal is at a first logic value, by turning said LED on or off for first durations that differ depending on the logic states of the bits of the digital signal, or, when the second binary signal is at a second logic value, by turning said LED on or off for second durations that differ, at least partially, from the first durations, depending on the logic states of the bits of the digital signal. This advantageously allows for controlling a change in pulse-width modulation with the second binary signal. Consequently, there are advantageously more different durations for turning the LEDs on / off than the number of bits in the video input.

[0024] According to one embodiment, the electronic circuit is configured to receive the second binary signal from outside the display pixel. This advantageously allows the modification of the pulse amplitude modulation to be controlled by adding a single bit, i.e., the second binary signal, to the video input.

[0025] According to one embodiment, the digital signal comprises NB bits b, i being in the range from 1 to NB, bit bNB being the most significant bit and bit bi being the least significant bit. The first durations comprise NB first durations TA of increasing values, and the second durations comprise NB second durations TB of increasing values. The driver circuit is configured to control said electrical diode luminescent by pulse width modulation, when the second binary signal is at the first logic value, by turning said light-emitting diode on or off during the first NB durations TA;, said light-emitting diode being on during the first duration TA; when bit b; is at a first logic state and being off during the first duration TA; when bit b; is at a second logic state, different from the first logic state, and the driver circuit is configured to control said light-emitting diode by pulse width modulation, when the second binary signal is at the second logic value, by turning said light-emitting diode on or off during the second NB durations TB;, said light-emitting diode being on during the second duration TB; when bit b; is at the first logic state and being off during the second duration TB; when bit b; is at the second logic state.

[0026] According to one embodiment, the electronic circuit is configured to receive a third binary signal comprising pulses, some of these pulses being spaced out by the first durations and some of these pulses being spaced out by the second durations, said electronic circuit being configured to turn said light-emitting diode on or off during the first durations or the second durations on the basis of said pulses.

[0027] According to one embodiment, the pulses comprise first pulses, the first pulses being spaced by first durations, and further comprise second pulses, each first pulse being followed by a second pulse, the first pulses and the subsequent second pulses being spaced by second durations.

[0028] One embodiment also provides a display screen comprising: - display pixels as defined previously, arranged in rows and columns; - the first electrically conductive tracks extending along the lines and connected to the electronic circuits of the display pixels; - second electrically conductive tracks extending along the columns and connected to the electronic circuits of the display pixels; and - a control circuit connected to the first electrically conductive tracks and to the second electrically conductive tracks.

[0029] According to one embodiment, the control circuit is configured to determine the first binary signal for each digital signal and to provide the first binary signals to the display pixels.

[0030] According to one embodiment, the control circuit is configured to determine the second binary signal for each digital signal and to provide the second binary signals to the display pixels.

[0031] According to one embodiment, the control circuit is configured to place the first binary signal at the first logic value when the digital signal corresponds to a luminance below a first luminance threshold, to place the first binary signal at the second logic value when the digital signal corresponds to a luminance above the first luminance threshold, to place the second binary signal at the second logic value when the digital signal corresponds to a luminance below a second luminance threshold, above the first luminance threshold, and to place the second binary signal at the first logic value when the digital signal corresponds to a luminance above the second luminance threshold. Brief description of the drawings

[0032] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0033] Fig. 1, already described, illustrates an example of an ideal gamma decoding function;

[0034] Figure 2, already described, illustrates an enlarged view of the gamma decoding function ideal of [Fig.l] and a real gamma decoding function with 10-bit encoding;

[0035] [Fig.3] partially and schematically illustrates one embodiment of a display screen;

[0036] [Fig.4] illustrates a block diagram of an embodiment of a display pixel of the screen of [Fig.3];

[0037] [Fig.5] illustrates the timing diagrams of signals used by the display pixel of [Fig.4] to control a light-emitting diode according to a known pulse-width modulation method;

[0038] [Fig.6] illustrates a block diagram of an embodiment of a light emission circuit for the display pixel of [Fig.4];

[0039] [Fig.7] illustrates a block diagram of another embodiment of the light emission circuit of the display pixel of [Fig.4];

[0040] [Fig.8] illustrates a block diagram of another embodiment of the light emission circuit of the display pixel of [Fig.4];

[0041] [Fig.9] illustrates the timing diagrams of signals used by the display pixel of [Fig.4] to control a light-emitting diode according to an embodiment of a pulse width modulation method;

[0042] [Fig. 10] illustrates a block diagram of an embodiment of a part of the display pixel of [Fig. 4];

[0043] [Fig.1 1] illustrates a block diagram of part of the circuit of [Fig. 10];

[0044] Figure 12 illustrates the gamma decoding function actually obtained during an implementation of an embodiment of a display method and the indices used during the display method; and

[0045] [Fig. 13] illustrates an enlarged view of [Fig. 12]. Description of the implementation methods

[0046] Unless otherwise specified, when referring to two interconnected elements, this means directly connected without any intervening elements other than conductors, and when referring to two coupled elements, this means that these two elements can be connected or linked via one or more other elements. Furthermore, a signal that alternates between a first constant state, for example a low logic state, denoted "0", and a second constant state, for example a high logic state, denoted "1", is called a "binary signal". The high and low states of the different binary signals in the same electronic circuit can be different. In practice, binary signals can correspond to voltages or currents that may not be perfectly constant in the high or low state.Furthermore, in the description that follows, the source and drain of a MOS transistor are referred to as the "power terminals" of the insulated-gate field-effect transistor, or MOS transistor.

[0047] Furthermore, unless otherwise indicated, when referring to a voltage at the level of a conductive pad, the difference between the potential at said conductive pad and a reference potential, for example ground, considered to be equal to 0 V, is considered.

[0048] Unless otherwise specified, the expressions "approximately", "roughly", "about", and "in the order of" mean within 10%, preferably within 5%. Furthermore, the expression "varyingly constant" means varying by less than 10% over time from a reference value.

[0049] In the following description, embodiments are described for a color display screen comprising color display pixels, each display pixel comprising light-emitting diodes adapted to emit radiation of different colors. However, these embodiments also apply to a monochromatic display screen comprising monochromatic display pixels, each monochromatic display pixel comprising a light-emitting diode or only light-emitting diodes adapted to emit radiation of a single color.

[0050] Figure 3 partially and schematically illustrates one embodiment of a display screen 10. The display screen 10 comprises display pixels 12^, for example, arranged in M ​​rows and N columns, M being an integer ranging from 1 Let M be an integer from 1 to 16,000, i an integer from 1 to M, and j an integer from 1 to N. For example, in [Fig. 3], M and N are both 6. Each display pixel 1¾ is connected to a low reference potential source Gnd, for example, ground, via an electrode 14; and to a high reference potential source Vcc via an electrode 16j. For example, the electrodes 14 are aligned along the rows of [Fig. 3] and the electrodes 16j are aligned along the columns of [Fig. 3], although the reverse arrangement is possible. The display screen's supply voltage is the voltage between the high reference potential Vcc and the low reference potential Gnd. The supply voltage depends in particular on the arrangement of the light-emitting diodes and the technology by which the light-emitting diodes are manufactured.As an example, the supply voltage can be in the range of 4V to 5V.

[0051] For each row, the display pixels 12j of the row are connected to at least one row electrode 18j. For each column, the display pixels 1¾ of the column are connected to at least one column electrode 20j. The display screen 10 includes a synchronization circuit 22 connected to the row electrodes 18j and adapted to deliver a synchronization signal Cornj on each row electrode 18j. The display screen 10 includes a data transmission circuit 24 connected to the column electrodes 20j and adapted to transmit a data signal Dataj on each column electrode 20j. The synchronization circuit 22 and the data transmission circuit 24 are controlled by a circuit 26, comprising, for example, a microprocessor. In particular, the circuit 26 receives the video data to be displayed by the display pixels 1¾.

[0052] In general, each row of display pixels is selected successively, and the display pixels of the selected row are programmed to display the desired image pixels. In a known method of selecting display pixels, the synchronization circuit 22 is adapted to deliver synchronization signals Corn; on the row electrodes 18; in order to successively select each row of display pixels 1¾, and the data transmission circuit 24 is adapted to deliver data signals Dataj on each column electrode 20j representing the digital color data that is stored in the selected display pixels 1¾.

[0053] Figure 4 illustrates an example of a block diagram of a display pixel 1¾ of the display screen 10. For a color display screen, the display pixel 12;,j comprises a light-emitting circuit 30 including at least three light-emitting diodes (LEDs) emitting radiation of different colors, a single LED being illustrated in Figure 4. The light-emitting circuit 30 includes, for each LED, a current source com- A controllable current source (CS) is connected in series with the light-emitting diode (LED). The controllable current source (CS) includes, for example, a MOSFET in series with a current source providing a constant current. In this example, for each LED, the anode of the LED receives a high reference potential (Vcc), and the cathode of the LED is connected to one terminal of the controllable current source (CS), with the other terminal receiving a low reference potential (Gnd). In the case of a monochromatic display, each 1¾ pixel can include a light-emitting circuit comprising a single LED.Light-emitting diodes (LEDs) can be 2D LEDs, also called planar LEDs, comprising a stack of planar layers, or 3D LEDs, each comprising a three-dimensional semiconductor element of micrometer or nanometer size extending in a preferred direction, for example a microwire or nanowire, covered by an active area. In particular, a 3D LED is said to be radial when its active area extends at least onto the side walls of the three-dimensional semiconductor element.

[0054] The display pixel 12ij further includes a driver circuit 40 for driving the controllable current source CS. The driver circuit 40 may include electronic components such as MOS transistors. The driver circuit 40 includes a storage circuit 48 (color data registers) clocked by a clock signal Clk configured to store the digital color signals R, G, B based on the received digital data. The digital color signals R, G, B each comprise a number NB of bits, from the most significant bit, called MSB, to the least significant bit, called LSB, and are representative of the color components of the image pixels to be displayed. The driver circuit 40 includes a circuit 50 (LED driver) configured to control the controllable current sources CS connected to the light-emitting diodes LED with signals I_red, I_green, and I_blue, obtained from the digital color signals R, G, B, and a PWM signal.The data may correspond to the Dataj signal transmitted to the display pixel 1¾ on the column electrode 20j during a selection phase. The PWM signal may correspond to the selection and synchronization signal Com; transmitted to the display pixel 1¾ on the row electrode 18; during a display phase.

[0055] Figure 5 illustrates a timing diagram of the PWM signal and the signals I_red_1, I_red_2, I_red_3, and I_red_4 corresponding to the I_red signal provided by the circuit 50 of the display pixel 1¾ of Figure 4 for the display of four different digital color signals R. According to one embodiment, the LEDs of the display pixel 12ij are controlled by width modulation pulse. To this end, during a display phase, the PWM signal presents a succession of PA pulses in logic state "1" which regulate the operation of circuit 50 for controlling the LEDs by pulse-width modulation. The number of PA pulses in the pulse sequence during the display phase can correspond to the number NB+1.

[0056] By way of example, when the current source CS corresponds to a current source supplying a constant current in series with a MOS transistor, the MOS transistor is switched on or off depending on the logic value "0" or "1" of each bit of the digital color signal R, G, or B, from the most significant bit MSB to the least significant bit LSB, at the rate of the PWM signal pulses, the MOS transistor being held on or off until the next PWM signal pulse. Therefore, the current source CS is switched on or off for NB successive durations depending on the logic values ​​of the bits of the digital color signal R, G, or B.For example, the current source CS can be activated for a duration when the bit of the digital color signal R, G, or B associated with that time interval is at logic value "1," and can be deactivated for a duration when the bit of the digital color signal associated with that time interval is at logic value "0." The duration TA, i, being in the range from 1 to NB, between two successive PA pulses of the PWM modulation signal can be halved each time, so that the total duration for which the LED is illuminated depends on the value of the digital color signal R. In particular, the duration TANB, which is associated with the least significant bit of the digital color signal R, G, or B, can correspond to the duration of the last PA pulse in the sequence of PA pulses of the PWM signal. The sequence of PA pulses of the PWM signal can be repeated until another image pixel is displayed.In this case, the succession of PA pulses of the PWM signal forms a display cycle, and the display phase comprises more than one display cycle.

[0057] In [Fig. 5], by way of example, the number of PA pulses in one display cycle of the PWM modulation synchronization signal is 8, and only one display cycle is shown. The signal I_red_1 is obtained for displaying an image pixel color component corresponding to the digital color signal R equal to "1010101". The signal I_red_2 is obtained for displaying an image pixel color component corresponding to the digital color signal R equal to "0101010". The signal I_red_3 is obtained for displaying an image pixel color component corresponding to the digital color signal R equal to "1111111". The signal I_red_4 is obtained for displaying an image pixel color component corresponding to the digital color signal R equal to "0000000".

[0058] According to one embodiment, the first and second mechanisms are put into The mechanism works so that, with digital color signals R, G, B encoded on NB bits, the displayed image appears as if the digital color signals were encoded on a number of bits, corresponding to the image's color depth, greater than NB. Both the first and second mechanisms contribute to eliminating the stepped portions of the gamma decoding curve with a limited increase in the number of bits of the video input. In one embodiment, the first mechanism is implemented when the gray level of the image pixel is below a first threshold and is not implemented when the gray level of the displayed image is above the first threshold. In another embodiment, the second mechanism is implemented when the gray level of the displayed image is below a second threshold and is not implemented when the gray level of the image pixel is above the second threshold.When both the first and second mechanisms can be implemented, the first threshold is lower than the second threshold. Therefore, when the gray level of the displayed image is above the second threshold—that is, for a light tone where the gamma decoding curve does not exhibit a stepped portion—neither the first nor the second mechanism is implemented. When the gray level of the image pixel is above the first threshold and below the second threshold—that is, for a dark but not very dark tone where the gamma decoding curve exhibits a not-too-pronounced stepped portion—the first mechanism is not implemented, and the second mechanism is implemented.Therefore, when the grey level of the displayed image is below the first threshold, i.e. for a very dark tone, for which the gamma decoding curve has a pronounced stair-stepped portion, both the first and second mechanisms are implemented.

[0059] According to one embodiment, the first mechanism is implemented when a first index II, corresponding to a first binary signal, is at a first logical value, for example "0", and is not implemented when the first index II is at a second logical value, for example "1". According to another embodiment, the second mechanism is implemented when a second index 12, corresponding to a second binary signal, is at a first logical value, for example "0", and is not implemented when the second index 12 is at a second logical value, for example "1". Therefore, when the gray level of the displayed image is below the first threshold, i.e., for a very dark tone, both the first and second mechanisms are implemented, and index II is at "0" and index 12 is at "0". When the gray level of the image pixel is above the first threshold and below the second threshold—that is, for a dark but not very dark tone—the first mechanism is not implemented and the second mechanism is implemented, and index II is set to "1" and index 12 to "0". When the gray level of the displayed image is above the second threshold, that is to say for a clear tone, neither of the first and second mechanisms is implemented, and index II is at "1" and index 12 at "1".

[0060] According to one embodiment, where the video input must be encoded with a higher number NBMAX of bits so that the gamma decoding curve does not exhibit a stepped portion for any gray level, the video input is encoded with a number NT of bits, and 1 bit is used for index II and 1 bit is used for index 12, the number NB+2 being less than NBMAX. For example, where the video input must be encoded with 20 bits so that the gamma decoding curve does not exhibit a stepped portion for any gray level, as shown in [Fig. 2], according to one embodiment, 13 bits are used for the video input and 2 bits for indices II and 12. The number of bits NB+2 used to ensure that the gamma decoding curve does not exhibit a stepped portion is advantageously less than NBMAX.

[0061] For the first mechanism, pulse amplitude modulation is implemented for very dark tones in addition to pulse width modulation. More precisely, the current supplied to the LED is decreased for very dark tones without altering the PWM signal. This is equivalent to modifying the PWM signal without changing the current supplied to the LED, so that more than NT different LED on / off durations are available, where NT is an integer strictly greater than NB, preferably greater than NB+1, and preferably even greater than NB+2.The display method according to the embodiment implementing the first mechanism with a digital color signal comprising NB bits is equivalent to a display method in which the known modulation synchronization signal, the PWM signal, would provide NT different durations and a digital color signal would comprise NT bits.

[0062] For the second mechanism, the PWM modulation synchronization signal is modified relative to a known PWM modulation synchronization signal, so that more than NT' different durations for the on / off of the light-emitting diodes are available, where NT' is an integer strictly greater than NB, preferably greater than NB+1, and preferably even greater than NB+2. The display method according to the embodiment implementing the second mechanism with the modified PWM modulation synchronization signal providing NT' different durations and a digital color signal comprising NB bits is equivalent to a display method in which the known PWM modulation synchronization signal would provide NT' different durations and a digital color signal would comprise NT' bits.

[0063] For the first mechanism, the intensity of the current supplied by the current source CS varies between at least two values ​​with respect to the first index II, while the diode The electroluminescent LED is controlled by pulse-width modulation. In one embodiment, the current supplied by the current source CS varies between a first intensity in a first operating mode of the first mechanism and a second intensity greater than the first intensity in a second operating mode of the first mechanism, the factor K being the ratio between the first intensity and the second intensity. A decrease in the current intensity from the current source CS by a factor K without changing the pulse-width modulation durations is equivalent to a decrease by a factor K of each pulse-width modulation duration without changing the current intensity supplied by the current source CS. In one embodiment, the index II is associated with each value of the digital color signal R, G, B.

[0064] Fig. 6 illustrates a block diagram of an embodiment of a light emission circuit 30 of the display pixel 1¾ of Fig. 4.

[0065] The controllable current source CS comprises a switch SW in series with an adjustable current source VCS providing a controllable current intensity. The switch SW is controlled by the signal I_red. The adjustable current source VCS is controlled by index II. In one embodiment, index II is a binary signal, and the variable current source VCS provides the current ICS with a first intensity ICSI when index II is at a first logic value and provides the current ICS with a second intensity ICS2, different from the first intensity ICSI, when index II is at a second logic value.

[0066] Fig. 7 illustrates a block diagram of another embodiment of the light emission circuit 30 of the display pixel 1¾ of Fig. 4.

[0067] The light-emitting circuit 30 comprises two light-emitting diodes LED1 and LED2 emitting radiation at substantially the same wavelength. Each LED1 and LED2 may comprise one or more elementary LEDs. Each elementary LED may be a 3D LED. In [Fig. 7], the LEDs LED1 and LED2 are shown connected to a common anode. However, it may be desirable to arrange the LEDs LED1 and LED2 in a different configuration. For example, the LEDs LED1 and LED2 may be connected to a common cathode.

[0068] The controllable current source CS comprises a first switch SW1 in series with a first constant current source CS1, and a second switch SW2 in series with a second constant current source CS2. The first switch SW1 in series with the first constant current source CS1 is connected between the cathode of the first light-emitting diode LED1 and the source of the The second switch SW2, in series with the second constant current source CS2, is connected between the cathode of the second LED2 and the low reference potential source Gnd. Both the first constant current source CS1 and the second constant current source CS2 are controlled by a bias signal.

[0069] In one embodiment, the first constant current source CS1 and the second constant current source CS2 are both MOS transistors, for example NMOS transistors, and the bias signal Bias is applied to the gate of each of these transistors. The first constant current source CS1 is sized to provide a constant current ICSI. The second constant current source CS2 is sized to provide a constant current ICS2. In one embodiment, the constant current ICS1 is equal to N1 times a constant reference current Iref, and the constant current ICS2 is equal to N2 times a constant reference current Iref.

[0070] The second switch SW2 is controlled by the signal I_red. The controllable current source CS also includes an AND1 logic gate of the AND type, the first input of which receives the index II and the second input of which receives the binary control signal I_red (or I_green or I_blue). The output of the AND1 logic gate controls the first switch SW1. In one embodiment, the first switch SW1 and the second switch SW2 are both MOS transistors, for example NMOS transistors, and the output of the AND1 logic gate is applied to the gate of transistor SW1 and the signal I_red is applied to the gate of transistor SW2.

[0071] According to one embodiment, index II is in logic state "1" for an image pixel that does not have a very dark tone, and index II is in logic state "0" for an image pixel with a very dark tone. More specifically, in a first operating mode of the first mechanism, to display an image pixel that does not have a very dark tone (index II in logic state "1"), the output logic gate AND1 corresponds to the signal I_red so that the first and second switches SW1 and SW2 are both controlled by the signal I_red, and, in a second operating mode of the first mechanism, to display an image pixel with a very dark tone (index II in logic state "0"), the output logic gate AND1 is set to logic value "0" so that the first switch remains open and only the second switch SW2 is controlled by the signal I_red.

[0072] According to one embodiment, the constant current ICSI is equal to NI times the constant reference current Iref and the constant current ICS2 is equal to N2 times the constant reference current Iref and the light-emitting diode LED1 comprises NI elementary light-emitting diodes and the light-emitting diode LED2 comprises N2 Elementary light-emitting diodes (LEDs), all having the same structure and emitting radiation at approximately the same wavelength, thus the current density through each elementary LED remains constant regardless of the operating mode of the first mechanism. This is advantageous when it is important to achieve a reduced dispersion of the central wavelength of the radiation emitted by the operating LEDs. Indeed, the central wavelength of the radiation emitted by the LED generally varies according to the current density through the LED, this variation being significant for three-dimensional radial LEDs.In the present embodiment, since the current density through each elementary light-emitting diode remains constant regardless of the operating mode of the first mechanism, the central wavelength of the radiation emitted by the elementary light-emitting diodes does not vary during operation.

[0073] Figure 8 illustrates a block diagram of another embodiment of the light-emitting circuit 30 for the display pixel 12ij of Figure 4. The light-emitting circuit 30 of Figure 8 comprises all the elements of the light-emitting circuit 30 of Figure 7, except that the LEDs LED1 and LED2 are replaced by LEDs, the first switch SW1 in series with the first constant current source CS1 being arranged in parallel with the second switch SW2 in series with the second constant current source CS2 between the cathode of the LED and the source of a low reference potential Gnd. In this embodiment, the current density through the LED varies between the first and second operating modes of the first mechanism.

[0074] This embodiment can be implemented when a variation in the operating wavelength of the radiation emitted by the LED can be tolerated. This can be the case when the LED is covered with a photoluminescent block comprising phosphors which are adapted, when excited by the light emitted by the LEDs, to emit light at a wavelength different from that of the light emitted by the LED. Indeed, the phosphors can emit radiation having a substantially constant central wavelength even if there is a variation in the central wavelength of the radiation emitted by the LED.

[0075] According to one embodiment, the index II is determined by the circuit 26 for each initial digital color signal determined by the circuit 26 and corresponding to an image pixel to be displayed by the display pixel 1¾ and is then sent to the display pixel 1¾. The index II received by the display pixel 1¾ can be stored in a memory of the display pixel 12^. According to one embodiment, the index II can be determined by the circuit 26 on the basis of one or more bits among the bits biti to bitNB of the initial digital color signal R, G or B determined by the circuit 26, for example at least one among the most significant bit bitNB, the second most significant bit bitNB_i, and the third most significant bit bitNB2 of the initial digital color signal R, G or B determined by the circuit 26. The index II can be determined by the circuit 26 using logic gates.According to one embodiment, index II can be set to logic state "0" if all the bits bNB to bNB nibiOu of the initial digital color signal R, G, or B, NIB1 being an integer, for example equal to 0, 1, or 2, determined by circuit 26, are in logic state "0", and index II can be set to logic state "1" if at least one of the bits bNB to bNB N1Bidu of the initial digital color signal R, G, or B is in logic state "1". According to one embodiment, index II is in logic state "0" only for an image pixel having a difference of less than or equal to 5 or 6 gray levels from the black level.

[0076] According to one embodiment, depending on the index II determined based on an initial digital color signal R, G, or B, the circuit 26 can calculate a new digital color signal R, G, or B, and the data signals Dataj sent to pixel 1¾ then correspond to the new digital color signal R, G, or B. According to one embodiment, a new digital color signal R, G, or B is determined for the first mechanism when the index II corresponds to an image pixel with a very dark tone, and no new digital color signal R, G, or B is determined for the first mechanism when the index II corresponds to an image pixel with a light tone. When no new digital color signal R, G, or B is determined for the first mechanism, the data signals Dataj sent to pixel 1¾ then correspond to the initial digital color signal R, G, or B when only the first mechanism is implemented.According to one embodiment, a new digital color signal R, G, or B is determined for the first mechanism when index II corresponds to an image pixel with a very dark tone, based on the initial digital color signal R, G, or B. For example, when index II corresponds to an image pixel with a very dark tone, a new digital color signal R, G, or B is determined by circuit 26 so that the information content of the image pixel is encoded on all NB bits of the digital color signal R, G, or B.

[0077] According to one embodiment, the first mechanism can be implemented separately from the second mechanism, which is described below. However, it may be advantageous to implement both the first and second mechanisms.

[0078] Figure 9 illustrates a timing diagram of the PWM signals, PWM2, I_red_W, and I_red_B, according to an embodiment of a method for driving the LEDs of display pixel 12ij in Figure 4, wherein the LEDs are controlled by pulse-width modulation implementing the second mechanism described previously. The signals I_red_W and I_red_B correspond to the I_red signal provided by circuit 50 of display pixel 1¾ in Figure 4 for displaying two different digital color signals R. The PWM2 signal is a signal generated by circuit 40 of display pixel 1¾ in Figure 4. In Figure 9, the digital color signal R comprises 5 bits, from bit 1 to bit 5, with bit 5 being the most significant bit and bit 1 being the least significant bit.

[0079] According to one embodiment, the PWM modulation synchronization signal comprises, for one display cycle, an alternation of first and second pulses, each first PA pulse being followed by a second PB pulse. The first PA pulses correspond to the PA pulses of the modulation synchronization signal described previously in relation to [Fig. 5], i.e., the duration TA, i being in the range from NB to 1, between two successive first PA pulses of the PWM modulation synchronization signal in one display cycle is halved each time. The duration TBj, j being in the range from NB to 1, between a first PA pulse and the successive second PB pulse of the PWM modulation synchronization signal is halved compared to the duration between the preceding successive first PA pulse and second PB pulse.The PWM2 signal includes a rising edge on each first PA pulse and a falling edge on each second PB pulse. Therefore, the pulses of the PWM2 signal have durations between TBnb and TBb.

[0080] According to one embodiment, a cycle comprises NB+1 first pulses PA and NB+1 second pulses PB. Consequently, there are NB decreasing durations TA;, i being in the range from NB to 1, between the pairs of successive first pulses PA and NB decreasing durations TB;, i being in the range from NB to 1, between the pairs of successive first and second pulses PA, PB.

[0081] More generally, the PWM time signal comprises pulses, some of these pulses being spaced by the first durations TA, i being in the range from 1 to NB, and some of these pulses being spaced by the second durations TB, i being in the range from 1 to NB. For example, the pulses used to determine the first durations TA may precede or follow the pulses used to determine the second durations TB. However, the embodiment described above in which the first and second pulses PA, PB are alternated advantageously avoids increasing the display cycle time compared to the case where only the first durations TA are used.

[0082] According to one embodiment, in a display cycle, one or more, but not all, of the durations TBi to TBnb last as long as at least one of the durations TAnb to TA. According to one embodiment, the duration TBnb between the first PA pulse and the second successive PB pulse at the very beginning of the display cycle lasts as long as the duration TANB to TAi between two successive PA pulses towards the end of the display cycle, for example, the duration between the penultimate first pulse and the last first pulse of the display cycle, or the duration between the third penultimate first pulse and the penultimate first pulse of the display cycle. There exist durations NT' of different values ​​in the group comprising all the durations TANB to TAi and TBnb to TBh, with NT' strictly greater than NB and strictly less than 2*NB.

[0083] In [Fig. 9], the PWM time-modulation signal comprises six initial PA pulses alternating with six second PB pulses. The duration TBnb between the first succession of first and second PA and PB pulses from the start of the display cycle is as long as the duration TA2 between the penultimate first pulse and the penultimate first pulse of the display cycle, and the duration TBnb i between the second succession of first and second PA and PB pulses from the start of the display cycle is as long as the duration TAi between the penultimate first pulse and the last first pulse of the display cycle. The last second PB pulse, illustrated in [Fig. 9], which follows the last first PA pulse, is not used, so it could be omitted, although, in practice, it may be easier to generate a second PB pulse after each first PA pulse to simplify the generation of the PWM2 signal.

[0084] According to one embodiment, the second index 12 is associated with each value of the digital color signal R, G, B. Index 12 can be a binary value. During a display operation, depending on the logic state of index 12, the durations TANB to TAi or the durations TBnb to TBi are used to drive the light-emitting diode LED.

[0085] According to one embodiment, the index 12 is determined by the circuit 26 for each initial digital color signal determined by the circuit 26 corresponding to an image pixel to be displayed by the display pixel 1¾ and is then sent to the display pixel 12ij. The index 12 received by the display pixel 1¾ can be stored in a memory of the display pixel 1¾. According to one embodiment, the index 12 can be determined by the circuit 26 on the basis of one or more bits among the bits biti to bitNB of the initial digital color signal R, G, or B determined by the circuit 26, for example, at least one among the most significant bit bitNB, the second most significant bit bitNB-i, and the third most significant bit bitNB2 of the initial digital color signal R, G, or B determined by the circuit 26. The index 12 can be determined by the circuit 26 using logic gates. According to one embodiment, index 12 is in a first logical state, For example, logic state "1" for an image pixel with a light tone, and index 12 is in a second logic state, for example, logic state "0" for an image pixel with a dark tone. According to one embodiment, index 12 can be set to logic state "0" if all bits bNB to bXH XIH2 of the initial digital color signal R, G, or B, where NIB2 is an integer, for example, 0, 1, or 2, determined by circuit 26, are in logic state "0," and index 12 can be set to logic state "1" if at least one of the bits bNB to bNB N1B2 of the initial digital color signal R, G, or B is in logic state "1." The switching conditions for index 12 and index II are determined such that index 12 switches for tones lighter than index II. According to one embodiment, the integer NIB2 is greater than the integer NIB1.

[0086] According to one embodiment, depending on the index 12 determined based on an initial digital color signal R, G, or B, the circuit 26 can calculate a new digital color signal R, G, or B, and the Dataj data signals sent to pixel 1¾ then correspond to the new digital color signal R, G, or B. According to one embodiment, a new digital color signal R, G, or B is determined for the second mechanism when the index 12 corresponds to an image pixel with a dark tone, and no new digital color signal R, G, or B is determined when the index 12 corresponds to an image pixel with a light tone. When no new digital color signal R, G, or B is determined for the second mechanism, the Dataj data signals sent to pixel 1¾ then correspond to the initial digital color signal R, G, or B.According to one embodiment, a new digital color signal R, G or B is determined for the second mechanism when the index 12 corresponds to an image pixel having a dark tone, based on the initial digital color signal R, G or B. For example, when the index 12 corresponds to an image pixel having a dark tone, a new digital color signal R, G or B is determined by the circuit 26 so that the informational content of the image pixel is coded on all the NB bits of the digital color signal R, G or B.

[0087] According to one embodiment, index 12 is in logic state "1" for an image pixel with a light tone and index 12 is in logic state "0" for an image pixel with a dark tone. More specifically, in a first operating mode of the second mechanism, to display an image pixel with a light tone (index 12 in logic state "1"), the durations TANB to TAi are used to power the LED. The current source CS powering the LED is switched on or off during successive durations TANB to TAi depending on the logic value "0" or "1" of each bit bNB to bi of the R, G, or B color digital signal, starting from the most significant bit bNB of the R, G, or B color digital signal. In a second operating mode of the second mechanism, to For the display of an image pixel with a dark tone (index 12 in logic state "0"), the durations TBnb to TBi are used to power the LED. The current source CS powering the LED is switched on or off during successive durations TBnb to TBi depending on the logic value "0" or "1" of each bit bNB to bi of the digital color signal R, G, or B, starting from the most significant bit bNB of the digital color signal R, and is switched off between two successive durations TBnb to TBb. For example, in [Fig. 9], the signal I_red_W is obtained using durations TANB to TAi, and the signal I_red_B is obtained using durations TBnb to TBh.

[0088] Alternatively, when the current source CS corresponds to a MOS transistor, this transistor can be turned on or off, for durations TA; or TBj, depending on the logic value "0" or "1" of each bit of the R, G or B color signal from the least significant bit to the most significant bit of the R, G or B color signal. In this case, the duration TA;, i being in the range from NB to 1, between two successive first PA pulses of the PWM modulation synchronization signal in a display cycle is multiplied by two each time, and the duration TBj, j being in the range from NB to 1, between a first PA pulse and the second successive PB pulse of the PWM modulation synchronization signal is multiplied by two with respect to the duration between the first PA pulse and the second successive PB pulse that precede it.

[0089] The display method according to the present embodiment, with the PWM modulation synchronization signal comprising the first and second pulses PA and PB and a digital color signal comprising NB bits, is equivalent to a display method in which the PWM modulation synchronization signal comprises only the first pulses and a digital color signal comprising NT' bits bj', j being in the range from 1 to NT'. Consequently, a color depth of NT' bits is advantageously obtained with a digital color image encoded on NB bits. Figure 9 shows the correspondence between bit bj', i being in the range from 1 to 5, and bit bj', j being in the range from 1 to 8.

[0090] Fig. 10 illustrates a block diagram of an embodiment of part of the circuit 40 of Fig. 4.

[0091] Circuit 40 includes - a circuit 60 configured to receive the PWM modulation synchronization signal and to provide the PWM2 signal; - a storage circuit 48 comprising a shift register clocked by the PWM2 signal, in which the digital color signal R, G or B is stored and providing a binary signal / bj at its output QB; - a 62-bit circuit configured to provide a 12-bit binary index; and - a logic circuit 64 configured to receive the signals / b;, 12 and PWM2 and to provide a binary control signal I_red, I_green or I_blue.

[0092] The binary signal / b; is the logical complement of the binary bit b; of the digital color signal R, G, or B. When clocked by the PWM2 signal, the shift register 48 successively provides its output QB with the bit / b;, which is the logical complement of the bit b;, i being in the range from NB to 1, starting with the complement of the most significant bit bNB. The circuit 60 must provide a PWM2 signal comprising a rising edge on each first PA pulse and a falling edge on each second PB pulse.

[0093] In one embodiment, the circuit 62 includes a memory in which the index 12 is stored when received by the display pixel 1¾. In another embodiment, the index 12 is stored in the shift register 48 and is used to drive the LED by pulse-width modulation with the shorter of the durations TAi or TBi such that it has no substantial impact on the total illumination time of the LED. For example, when the index 12 is equal to the logic state "1" for the light tones and is stored in the shift register 48, the pulse-width modulation control of the LED with the shorter duration TAi associated with the index 12 being equal to "1" would have virtually no impact on the total duration for which the LED is illuminated.The shortest TAi duration is advantageously placed at as low a level as possible.

[0094] Figure 11 illustrates a block diagram of one embodiment of the logic circuit 64 of Figure 10. The logic circuit 64 comprises: - a first NOR1 logic gate of the N / A type having a first input receiving the binary signal PWM2 and having a second input receiving the binary index 12; and - a second NOR2 logic gate of the NOT-OR type having a first input receiving the binary signal / b; and having a second input receiving the binary signal supplied at the output of the first NOR1 logic gate and supplying the binary control signal I_red (or I_green or I_blue).

[0095] In the present embodiment, in the first operating mode of the second mechanism, for bright tones, the binary index 12 is set to the logic value "1". Consequently, the output of the first NOR1 logic gate remains at the logic value "0" throughout the display cycle and the output I_red (or I_green or I_blue) of the second NOR2 logic gate is equal to the binary logic complement of the binary signal / b;, that is, equal to the bit b;.

[0096] Since the shift register 48 is clocked by the PWM2 signal, the logic circuit 64 successively provides the NB bits of the R color digital signal clocked by the The PWM2 signal is preferably applied to each rising edge of the PWM2 signal. The rising edges of the PWM2 signal are simultaneous with the rising edges of the first PA pulses of the PWM modulation synchronization signal. This results in pulse-width modulation in the first operating mode of the second mechanism with durations TANB to TA.

[0097] In the present embodiment, in the second operating mode of the second mechanism, for dark tones, the binary index 12 is set to the logic value "0". Consequently, the output of the first NOR1 logic gate is equal to the logic complement of the PWM2 binary signal. When the PWM2 signal is at logic state "0", the output of the first NOR1 logic gate is equal to logic state "1" and the I_red output of the second NOR2 logic gate is equal to logic state "0". The LED is then off. When the PWM2 signal is at logic state "1", that is, between each first PA pulse and the subsequent second PB pulse, the output of the first NOR1 logic gate is set to logic value "0" and the I_red output of the second NOR2 logic gate is equal to the logic complement of the / b; binary signal, that is, equal to bit b; of the digital color signal R stored in the shift register 48.We then obtain a pulse width modulation with the second operating mode of the second mechanism with durations TBnb to TBi.

[0098] According to one embodiment, the second mechanism is implemented for dark tones, and the first and second mechanisms are implemented for very dark tones. Therefore, there are three modes of operation for displaying an image pixel for the display pixel 1¾.

[0099] In the first operating mode of the display method, for very dark tones, index 12 is set to logic value "0" and index II is set to logic value "0". Consequently, the second durations TBnb to TBi are used, and the current intensity through the light-emitting diode is at its lowest. In the second operating mode of the display method, for tones between very dark and dark tones, index 12 is set to logic value "0" and index II is set to logic value "1". Consequently, the second durations TBnb to TBi are used, and the current intensity through the light-emitting diode is at its highest. In the third operating mode of the display method, for bright tones, index 12 is set to logic value "1" and index II is set to logic value "1".Therefore, the first TANB to TAi durations are used and the current intensity through the light-emitting diode is the highest.

[0100] According to one embodiment, the indices II and 12 are sent to the display pixel 1¾ using the Dataj data signal in addition to the bits of the initial or new digital color signal R, G, B. For example, when the digital color signal R, G, B is encoded on NB bits and each index II and index 12 is encoded on one bit, the Dataj data signal is used to send NB+2 bits to the display pixel 1¾ for each digital color signal R, G, B. In another embodiment, each of the indices II and 12 is sent to the display pixel 1¾ using both the Dataj data signal and the Com synchronization signal, for example, by providing specific simultaneous patterns for the Dataj data signal and the Com synchronization signal. In another embodiment, each of the indices II and 12 is sent to the display pixel 1¾ using the Dataj data signal by specifically determining one or more bits of the digital color signal R, G, B, according to a determined logic, for example, a bit from among the least significant bit bB, the second least significant bit b2, or the third least significant bit b3 of the digital color signal R, G, B.The display pixel 1¾ is then adapted to extract each of the indices II and 12 from the stored digital color signal R, G, B.

[0101] By way of example, Table 1 below includes: - in the first column entitled "Gray Scale (10-bit)", the 1023 grey scale values ​​in decimal notation can be coded with 10 bits; - in the second column entitled "Ideal Linear (13 bits)", the corresponding ideal values ​​obtained in decimal notation after a linear conversion which can be coded with 13 bits; - in the third column entitled "Ideal 2.2", the corresponding ideal values ​​in decimal notation after a gamma conversion with yd equal to 2.2; - in the fourth column entitled "Real (13 bits) without indexes", the corresponding real values ​​in decimal notation after a gamma conversion with yd equal to 2.2 which can be coded on 13 bits without using the indices II and 12; - in the fifth column entitled "II", the value of index II; - in the sixth column entitled "12", the value of the index 12; - in the seventh column entitled "Real (13 bits) with index", the corresponding real values ​​in decimal notation after a gamma conversion with yd equal to 2.2 which can be coded with 13 bits using the indices II and 12; - in the eighth column entitled "Ideal* 128 or 16", the corresponding ideal values ​​in decimal notation; - in the ninth column entitled "Round-up", the rounded value from the eighth column; and - in the ninth column entitled "Note", M1 is indicated for the first operating mode of the display process, M2 is indicated for the second operating mode of the display process and M3 is indicated for the third operating mode of the display process.

[0102] [Tables 1] Grayscale (10 bits) Ideal Linear (13 bits) Ideal 2.2 Real (13_bit) II 12 Real (13 bits) without index Ideal*128 or 16 Horizontal rotation Note 0 0 0.00 0 0 0.00 0 0 Ml 1 15 0.01 0 0 0 0.01 0.9967963 26 1 Ml 2 23 0.02 0 0 0 0.02 2.5527418 47 3 Ml 3 31 0.04 0 0 0 0.04 4.9226775 03 5 Ml 4 39 0.06 0 0 0 0.06 8.1573255 33 8 Ml 5 47 0.10 0 0 0 0.09 12.297616 51 12 Ml 6 55 0.14 0 1 0 0.13 2.1722689 2 2 M2 7 63 0.18 0 1 0 0.19 2.9286325 19 3 M2 8 71 0.24 0 1 0 0.25 3.8096408 83 4 M2 9 79 0.30 0 1 0 0.31 4.8183159 27 5 M2 10 87 0.37 0 1 0 0.38 5.9574173 69 6 M2 11 95 0.45 0 1 0 0.44 7.2294890 32 7 M2 12 103 0.54 1 1 0 0.56 8.6368935 29 9 M2 • 110 887 61.58 62 1 0 61.56 985.25270 34 985 M2 111,895 62.81 63 1 0 62.81 1004.9081 06 1005 M2 112,903 64.05 64 1 0 64.06 1024.7754 72 1025 M2 113,911 65.30 65 1 0 65.31 1044.8551 82 1045 M2 114,919 66.57 67 1 0 66.56 1065.1476 08 1065 M2 115,927 67.85 68 1 1 68 M3 116,935 69.15 69 1 1 69 M3 117 943 70.46 70 1 1 70 M3 • 1019 8159 8120.76 8121 1 1 8121 M3 1020 8167 8138.29 8138 1 1 8138 M3 1021 8175 8155.84 8156 1 1 8156 M3 1022 8183 8173.41 8173 1 1 8173 M3 1023 8191 8191.00 8191 1 1 8191 M3

[0103] Fig. 12 illustrates the gamma decoding function Rgaml3+2 actually obtained during the implementation of the display method described above and the values ​​of index II and index 12.

[0104] Figure 13 illustrates an enlarged view of Figure 12. The curve Rgaml3+2 closely follows the ideal gamma decoding function Igam shown in Figure 1, with substantially the same accuracy as that obtained with the gamma decoding function Rgam20 obtained with 20-bit encoding. Consequently, the same accuracy can be achieved using only 15 bits, with 13 bits for the digital color signals R, G, B and 2 bits for the indices II and 12. This advantageously leads to a reduction in data rate and circuit size of approximately 25%.

[0105] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and Several variations could be combined, and other variations will emerge for the person skilled in the art. In particular, the PWM modulation can be generated internally in the driver circuit 40 of the display pixel 1¾ to avoid using the Com signal to generate it. Other embodiments may also use other electro-optical components such as organic light-emitting diodes (LEDs). Furthermore, the first mechanism described above can be implemented with a pulse-width modulation (PWM) control different from the one described previously. For example, the PWM control may consist of controlling the current source to power the LED with a single current window during each display cycle, the ratio between the duration of the current window and the duration of the display cycle depending on the associated digital color data.

[0106] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Claims

1. A display pixel (1¾) comprising at least one light-emitting diode (LED), a controllable current source (CS) supplying said light-emitting diode (LED) with successive current pulses, and an electronic circuit (40) comprising a storage circuit (48) for storing at least one digital signal (R, G, B) comprising several bits and a driver circuit (50) configured to control the current source (CS) to provide the successive current pulses by pulse width modulation by providing the successive current pulses having different durations which depend on the bits of the digital signal (R, G, B), and is configured to control the current source (CS) to provide the successive current pulses by pulse amplitude modulation by providing the successive current pulses having the same intensity selected from at least first and second intensities.

2. The display pixel of claim 1, wherein the driver circuit (50) is configured to control the controllable current source (CS) to provide the successive current pulses by pulse width modulation based on the digital signal (R, G, B) at the first intensity when a first binary signal (II) is at a first logic value, and to control the controllable current source (CS) to provide the successive current pulses by pulse width modulation based on the digital signal (R, G, B) at the second intensity, higher than the first intensity, when the first binary signal (II) is at a second logic value.

3. The display pixel of claim 2, wherein the electronic circuit (40) is configured to receive the first binary signal (II) from outside the display pixel.

4. A display pixel according to claim 2 or 3, wherein the controllable current source (CS) comprises a first constant current source (CS1) in series with a first switch (SW1) and a second constant current source (CS2) in series with a second switch (SW2), wherein the driver circuit (50) is configured, when the first binary signal (II) is at the second logic value, to control the first switch (SW1) and the second switch (SW2) by pulse width modulation based on the digital signal (R, G, B), to control the first switch (SW 1) and the second switch (SW2) by pulse width modulation according to the digital signal (R, G, B) and, when the first binary signal (II) is at the first logic value, to open the first switch (SW1) and to control the second switch (SW2) by pulse width modulation according to the digital signal (R, G, B).

5. Display pixel according to claim 4, wherein the driver circuit (50) comprises a logic gate (AND1) of the AND type having a first input receiving the first binary signal (II) and having a second input successively receiving the bits of the digital signal (R, G, B), the output of the logic gate (AND1) of the AND type controlling the first switch (SW1), and wherein the driver circuit (50) is configured to control the second switch (SW2) from the successive bits of the digital signal (R, G, B).

6. A display pixel according to claim 4 or 5, wherein the light-emitting diode (LED) comprises a first set (LED1) of elementary light-emitting diodes and a second set (LED2) of elementary light-emitting diodes, wherein the elementary light-emitting diodes of the first set (LED1) of elementary light-emitting diodes are connected to the first constant current source (CS1) and the elementary light-emitting diodes of the second set (LED2) of elementary light-emitting diodes are connected to the second constant current source (CS2).

7. A display pixel according to claim 4 or 5, wherein the light-emitting diode (LED) is connected to the first constant current source (CS1) and the second constant current source (CS2).

8. A display pixel according to any one of claims 1 to 7, wherein the driver circuit (50) is configured to control said light-emitting diode (LED), when a second binary signal (12) is at a first logic value, by switching on or off said light-emitting diode for different first durations (TA5, TA4, TA3, TA2, TAi) depending on the logic states of the bits of the digital signal (R, G, B) or, when the second binary signal (12) is at a second logic value, by switching on or off said light-emitting diode for different second durations (TB5, TB4, TB3, TB2, TBi), at least partially different from the first durations, depending on the logical states of the bits of the digital signal (R, G, B).

9. The display pixel of claim 8, wherein the electronic circuit (40) is configured to receive the second binary signal (12) from outside the display pixel.

10. A display pixel according to claim 8 or 9, wherein the digital signal (R, G, B) comprises NB bits b,, i being in the range from 1 to NB, bit bNB being the most significant bit and bit bi being the least significant bit, wherein the first durations comprise NB first durations TA; (TA5, TA4, TA3, TA2, TAJ of increasing values, wherein the second durations comprise NB second durations TB; (TB5, TB4, TB3, TB2, TBi) of increasing values, wherein the driver circuit (50) is configured to control said light-emitting diode (LED) by pulse width modulation, when the second binary signal (12) is at the first logic value, by switching on or off said light-emitting diode during the NB first durations TA; (TA5, TA4, TA3, TA2, TAi), said light-emitting diode being switched on during the first duration TA; when bit b;is in a first logic state and being off during the first duration TA; when the bit b; is in a second logic state, different from the first logic state, and in which the driver circuit (50) is configured to control said light-emitting diode by pulse width modulation, when the second binary signal (12) is at the second logic value, by switching on or off said light-emitting diode during the NB second durations TB; (TB5, TB4, TB3, TB2, TBi), said light-emitting diode being on during the second duration TB; when the bit b; is in the first logic state and being off during the second duration TB; when the bit b; is in the second logic state.;

11. A display pixel according to any one of claims 8 to 10, wherein the electronic circuit (40) is configured to receive a third binary signal (Com;) comprising pulses (PA, PB), some of these pulses being spaced apart by first durations (TA5, TA4, TA3, TA2, TAi) and some of these pulses being spaced apart by second durations (TB5, TB4, TB, TB, TB32[), said electronic circuit being configured to turn on or off said light-emitting diode (LED) for the first durations or the second durations as a function of said pulses.

12. The display pixel of claim 11, wherein the pulses comprise first pulses (PA), the first pulses being spaced apart by first durations (TA5, TA4, TA3, TA2, TAJ, and further comprise second pulses (PB), each first pulse (PA) being followed by a second pulse (PB), the first pulses and subsequent second pulses being spaced apart by second durations (TB5, TB4, TB3, TB2, TBi).

13. Display screen (10) comprising: - display pixels (1¾) according to any one of claims 1 to 12, arranged in rows and columns; - first electrically conductive tracks (18;) extending along the rows and connected to the electronic circuits (40) of the display pixels; - second electrically conductive tracks (20i) extending along the columns and connected to the electronic circuits (40) of the display pixels; and - a control circuit (22, 24, 26) connected to the first electrically conductive tracks (180) and to the second electrically conductive tracks (20i).

14. A display screen according to claim 13, wherein the control circuit (22, 24, 26) is configured to determine the first binary signal (II) for each digital signal (R, G, B) and to provide the first binary signals to the display pixels (1¾).

15. A display screen according to claim 14, wherein the display pixels (1¾) are in accordance with claim 8, and wherein the control circuit (22, 24, 26) is configured to determine the second binary signal (12) for each digital signal (R, G, B) and to provide the second binary signals to the display pixels (1¾

16. )■ Display screen according to claim 15, in which the control circuit (22, 24, 26) is configured to place the first binary signal (II) at the first logic value when the digital signal (R, G, B) corresponds to a luminance lower than a first luminance threshold, to place the first binary signal (II) at the second logic value when the digital signal (R, G, B) corresponds to a luminance higher than the first luminance threshold, to place the second binary signal (12) at the second logic value when the digital signal (R, G, B) corresponds to a luminance lower than a second luminance threshold, higher than the first luminance threshold, and to place the second binary signal (12) at the first logic value when the digital signal (R, G, B) corresponds to a luminance higher than the second luminance threshold.

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