Display pixels comprising light-emitting diodes and display screen comprising such display pixels

Abstract

Display pixel comprising light-emitting diodes and display screen comprising such display pixels The present description relates to a display pixel (12i,j) comprising at least one light-emitting diode (LED), a controllable current source (CS) supplying said light-emitting diode (LED) with current pulses, and an electronic circuit (40) comprising a storage circuit (48) for storing at least one digital signal (R, G, B) and a driver circuit (50) configured to control the current source (CS) in order to provide the current pulses by pulse width modulation and by pulse amplitude modulation on the basis of the digital signal (R, G, B). Figure for abstract: Fig. 4

Description

Title of the invention: Display pixels comprising light-emitting diodes and display screen comprising such display pixels Technical field

[0001] The present disclosure relates to a display pixel comprising light-emitting diodes and a display screen comprising such display pixels. Prior art

[0002] A pixel of an image corresponds to the unit element of the image displayed by a display screen. For the display of color images, the display screen generally comprises, for the display of each pixel of the image, at least three components, also called display sub-pixels, which each emit light radiation, called the color component of the image pixel, essentially in a single color (for example, red, green and blue). The superposition of the color components of the image pixel emitted by the three display sub-pixels provides the observer with the colored sensation corresponding to the pixel of the displayed image. In this case, the assembly formed by the three display sub-pixels used for the display of a pixel of an image is called a display pixel of the display screen. Each display sub-pixel may comprise a light source, in particular a light-emitting diode.

[0003] The display pixels may be distributed in a matrix, with each display pixel located at the intersection of a row (also called a line) and a column of the matrix. Electrodes are provided along the rows and columns to connect each display pixel to control circuits. In general, each row of display pixels is successively selected by a signal transmitted along the row electrodes, and the display pixels in the selected row are programmed to display the desired image pixels by signals transmitted along the column electrodes.

[0004] The human eye is much more sensitive to variations in dark tones than to similar variations in light tones. A photodetector typically provides an analog electrical image pixel signal that has a substantially linear relationship to the number of photons striking the sensor. If the display system operated with a digital control method such as pulse width modulation, a large number of bits would have to be used for the digital image pixel signals in order to describe the dark tones with sufficient accuracy. Scanning with a low bit depth results in posterization of the displayed image for dark tones.

[0005] To optimize bit utilization during image coding and / or to optimize the bandwidth used to transport an image, a non-linear operation, generally referred to as gamma coding or gamma compression, is applied to the image pixel signal provided by the photodetector to redistribute the native tone levels of the image sensor into levels that are more perceptually uniform for the human eye. Gamma coding is, for example, defined by the following power law expression:

[0006] [Math 1] Vb = Va7C where the non-negative real input value Va is raised to the power yc to obtain the output value Vb, with, for example, Va and Vb in the range 0-1. The exponent yc is usually equal to 1 / 2.2.

[0007] To display the image pixel, the inverse nonlinear operation, called gamma decoding or gamma expansion, is applied to the image pixel signal to efficiently convert it back to the original scene light. Gamma decoding is for example defined by the following power law expression:

[0008] [Math 2] Vd = Vc7d where the non-negative real input value Vc is raised to the power yd to obtain the output value Vd, with, for example, Vc and Vd in the range 0-1. The exponent yd is usually equal to 1 / yc, i.e., for example, equal to 2.2.

[0009] [Fig. 1] shows an example of an ideal gamma decoding function Igam corresponding to a power law expression with an exponent equal to 2.2, and, for comparison, a linear function Lin. In [Fig.l], the y-axis indicates the luminance in arbitrary units and the x-axis indicates the number of grayscale levels (Input grayscale). For tones to appear smooth and continuous in an image, it is generally sufficient to be able to code at least 256 different levels for the luminance L, which should theoretically only require 8 bits.

[0010] However, when using gamma encoding and gamma decoding, posterization may still appear on the displayed image for very dark tones when the display system is operating with a digital control method such as pulse width modulation.

[0011] [Fig.2] shows the evolution curves of the gamma decoding functions which are enlarged for low gray levels and which illustrates the need to increase the number of bits for smooth gamma decoding on low gray levels. In In [Fig.2], the y-axis indicates the luminance in arbitrary units and the x-axis indicates the number of grayscale levels (Input grayscale). In particular, [Fig.2] shows an Rgaml2 gamma decoding function actually obtained with 12-bit coding (mixed dashed line), an Rgaml4 gamma decoding function actually obtained with 14-bit coding (thick solid line), an Rgaml6 gamma decoding function actually obtained with 16-bit coding (dotted line), an Rgaml8 gamma decoding function actually obtained with 18-bit coding (dotted line), and an Rgam20 gamma decoding function actually obtained with 20-bit coding (thin solid line). Each Rgaml2, Rgaml4, Rgaml6, Rgaml8, and Rgam20 gamma decoding function corresponds to a gamma decoding function for a 10-bit video input.

[0012] As shown in [Fig. 2], there is a stepped portion for each of the curves Rgaml2, Rgaml4, Rgaml6 and Rgaml8, and there is no stepped portion for the curve Rgam20. In [Fig. 2], the stepped portions are clearly visible for the curves Rgaml2 and Rgaml4 2 and stepped portions can be detected for the curves Rgaml6 and Rgaml8 for very low gray levels (especially for levels 0-8). This means, for example for the curve Rgaml4, that an image pixel with an ideal luminance L in the range 0-8 results in the display of an image pixel having an actual luminance L equal to 0, or that an image pixel with an ideal luminance L in the range 9-13 results in the display of an image pixel with an actual luminance L having a constant value. At least 20-bit encoding should be used to ensure that dark tones are displayed with high accuracy when using gamma encoding and decoding.However, increasing the number of bits in digital image pixel signals requires a higher bandwidth interface for the video data, which is undesirable. In addition, operation of the display system by pulse width modulation may require the generation of pulses of different durations. A disadvantage is that increasing the number of bits in digital image pixel signals may require decreasing the duration of the pulse with the shortest duration, which may be difficult to generate. Summary of the invention

[0013] An object of an embodiment is to provide a display pixel comprising light emitting diodes and a display screen comprising such display pixels which overcome some or all of the disadvantages of existing display pixels comprising light emitting diodes and display screens comprising such display pixels.

[0014] Another object is to reduce, or even eliminate, the posterization of an image displayed in dark tones.

[0015] Another object is that the number of bits of the signals of the digital image pixels remains low.

[0016] One embodiment provides a display pixel comprising at least one light-emitting diode, a controllable current source supplying said light-emitting diode with successive current pulses, and an electronic circuit comprising a storage circuit for storing at least one digital signal comprising several bits and a driver circuit configured to control the current source to provide the successive current pulses by pulse width modulation by providing the successive current pulses having different durations which depend on the bits of the digital signal, and is configured to control the current source to provide the successive current pulses by pulse amplitude modulation by providing the successive current pulses having the same intensity selected from at least the first and the second intensity.This advantageously allows for a more accurate gamma decoding function without increasing the number of bits of the video input.

[0017] According to one embodiment, the driver circuit is configured to control the controllable current source to provide the successive current pulses by pulse width modulation based on the digital signal at the first intensity when a first binary signal is at a first logic value, and to control the controllable current source to provide the successive current pulses by pulse width modulation based on the digital signal at the second intensity, greater than the first intensity, when the first binary signal is at a second logic value. This advantageously makes it possible to control the pulse amplitude modulation with the first binary signal.

[0018] According to one embodiment, the electronic circuit is configured to receive the first binary signal from outside the display pixel. This advantageously makes it possible to control the pulse amplitude modulation by adding a single bit, i.e. the first binary signal, to the video input.

[0019] According to one embodiment, the controllable current source comprises a first constant current source in series with a first switch and a second constant current source in series with a second switch. The driver circuit is configured, when the first binary signal is at the second logic value, to control the first switch and the second switch by pulse width modulation based on the digital signal and, when the first binary signal is at the first logic value, to open the first switch and to control the second switch by pulse width modulation pulse based on the digital signal. This advantageously allows pulse amplitude modulation with two current intensity levels.

[0020] According to one embodiment, the driver circuit comprises an AND type logic gate having a first input receiving the first binary signal and having a second input successively receiving the bits of the digital signal, the output of the AND type logic gate controlling the first switch. The driver circuit is configured to control the second switch from the successive bits of the digital signal.

[0021] According to one embodiment, the light-emitting diode comprises a first set of elementary light-emitting diodes and a second set of elementary light-emitting diodes, in which the elementary light-emitting diodes of the first set of elementary light-emitting diodes are connected to the first constant current source and the elementary light-emitting diodes of the second set of elementary light-emitting diodes are connected to the second constant current source. Consequently, the current density passing through each elementary light-emitting diode remains constant during the pulse amplitude modulation.

[0022] According to one embodiment, the light-emitting diode is connected to the first constant current source and to the second constant current source.

[0023] According to one embodiment, the driver circuit is configured to control said light-emitting diode, when a second binary signal is at a first logic value, by switching on or off said light-emitting diode for different first durations depending on the logic states of the bits of the digital signal or, when the second binary signal is at a second logic value, by switching on or off said light-emitting diode for different second durations, at least partly different from the first durations, depending on the logic states of the bits of the digital signal. This advantageously makes it possible to control a modification of the pulse width modulation with the second binary signal. Consequently, there are advantageously more different durations for switching on / off the light-emitting diodes than the number of bits of the video input.

[0024] According to one embodiment, the electronic circuit is configured to receive the second binary signal from outside the display pixel. This advantageously makes it possible to control the modification of the pulse amplitude modulation by adding a single bit, i.e. the second binary signal, to the video input.

[0025] According to one embodiment, the digital signal comprises NB bits b,, i being in the range from 1 to NB, the bit bNB being the most significant bit and the bit bi being the least significant bit. The first durations comprise NB first durations TA; of increasing values, and the second durations comprise NB second durations TB; of increasing values. The driver circuit is configured to control said light-emitting diode by pulse width modulation, when the second binary signal is at the first logic value, by switching on or off said light-emitting diode during the NB first durations TA;, said light-emitting diode being switched on during the first duration TA; when bit b; is at a first logic state and being switched off during the first duration TA; when bit b;is in a second logic state, different from the first logic state, and the driver circuit is configured to control said light-emitting diode by pulse width modulation, when the second binary signal is at the second logic value, by switching on or off said light-emitting diode during the NB second durations TB;, said light-emitting diode being switched on during the second duration TB; when the bit b; is in the first logic state and being switched off during the second duration TB; when the bit b; is in the second logic state. ;

[0026] According to one embodiment, the electronic circuit is configured to receive a third binary signal comprising pulses, some of these pulses being spaced apart by first durations and some of these pulses being spaced apart by second durations, said electronic circuit being configured to turn on or off said light-emitting diode during the first durations or the second durations on the basis of said pulses.

[0027] According to one embodiment, the pulses comprise first pulses, the first pulses being spaced apart by first durations, and further comprise second pulses, each first pulse being followed by a second pulse, the first pulses and subsequent second pulses being spaced apart by second durations.

[0028] An embodiment also provides a display screen comprising: - display pixels as defined previously, arranged in rows and columns; - first electrically conductive tracks extending along the lines and connected to the electronic circuits of the display pixels; - second electrically conductive tracks extending along the columns and connected to the electronic circuits of the display pixels; and - a control circuit connected to the first electrically conductive tracks and to the second electrically conductive tracks.

[0029] According to one embodiment, the control circuit is configured to determine the first binary signal for each digital signal and to provide the first binary signals to the display pixels.

[0030] According to one embodiment, the control circuit is configured to determine the second binary signal for each digital signal and to provide the second binary signals to the display pixels.

[0031] According to one embodiment, the control circuit is configured to place the first binary signal at the first logic value when the digital signal corresponds to a luminance lower than a first luminance threshold, to place the first binary signal at the second logic value when the digital signal corresponds to a luminance higher than the first luminance threshold, to place the second binary signal at the second logic value when the digital signal corresponds to a luminance lower than a second luminance threshold, higher than the first luminance threshold, and to place the second binary signal at the first logic value when the digital signal corresponds to a luminance higher than the second luminance threshold. Brief description of the drawings

[0032] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0033] [Fig.l], already described, illustrates an example of an ideal gamma decoding function;

[0034] [Fig.2], already described, illustrates an enlarged view of the gamma decoding function ideal of [Fig.l] and an actual gamma decoding function with 10-bit coding;

[0035] [Fig.3] partially and schematically illustrates an embodiment of a display screen;

[0036] [Fig.4] illustrates a block diagram of an embodiment of a display pixel of the screen of [Fig.3];

[0037] [Fig.5] illustrates the timing diagrams of signals used by the display pixel of [Fig.4] to control a light-emitting diode according to a known method of pulse width modulation;

[0038] [Fig.6] illustrates a block diagram of an embodiment of the light emitting circuit of the display pixel of [Fig.4];

[0039] [Fig.7] illustrates a block diagram of another embodiment of the light emitting circuit of the display pixel of [Fig.4];

[0040] [Fig.8] illustrates a block diagram of another embodiment of the light emitting circuit of the display pixel of [Fig.4];

[0041] [Fig.9] illustrates the timing diagrams of signals used by the display pixel of [Fig.4] to control a light-emitting diode according to one embodiment of a pulse width modulation method;

[0042] [Fig. 10] illustrates a block diagram of one embodiment of a portion of the display pixel of [Fig.4];

[0043] [Fig. 11] illustrates a block diagram of part of the circuit of [Fig. 10];

[0044] [Fig. 12] illustrates the gamma decoding function actually obtained during an implementation of an embodiment of a display method and the indexes used during the display method; and

[0045] [Fig. 13] illustrates an enlarged view of [Fig. 12]. Description of the embodiments

[0046] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be linked by means of one or more other elements. In addition, a signal which alternates between a first constant state, for example a low logic state, noted "0", and a second constant state, for example a high logic state, noted "1", is called a "binary signal". The high and low states of the different binary signals of the same electronic circuit can be different. In practice, binary signals can correspond to voltages or currents which may not be perfectly constant in the high or low state.Further, in the following description, the source and drain of a MOS transistor are referred to as the "power terminals" of the insulated gate field effect transistor, or MOS transistor.

[0047] Furthermore, unless otherwise indicated, when referring to a voltage at a conductive pad, the difference between the potential at said conductive pad and a reference potential, for example ground, is considered to be equal to 0 V.

[0048] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean within 10%, preferably within 5%. In addition, the expression "substantially constant" means that it varies by less than 10% over time compared to a reference value.

[0049] In the following description, embodiments are described for a color display screen comprising color display pixels, each display pixel comprising light-emitting diodes adapted to emit radiation of different colors. However, these embodiments also apply to a monochromatic display screen comprising display pixels monochromatic, each monochromatic display pixel comprising a light-emitting diode or only light-emitting diodes adapted to emit radiation of a single color.

[0050] [Fig. 3] partially and schematically illustrates an embodiment of a display screen 10. The display screen 10 comprises display pixels 12^, for example, arranged in M ​​rows and N columns, M being an integer varying from 1 to 8,000 and N being an integer varying from 1 to 16,000, i being an integer varying from 1 to M, and j being an integer varying from 1 to N. For example, in [Fig. 3], M and N are equal to 6. Each display pixel 1¾ is connected to a source of low reference potential Gnd, for example ground, via an electrode 14; and to a source of high reference potential Vcc via an electrode 16j. For example, the electrodes 14; are aligned along the lines of [Fig.3] and the electrodes 16j are aligned along the columns of [Fig.3], the reverse arrangement being possible.The supply voltage of the display screen corresponds to the voltage between the high reference potential Vcc and the low reference potential Gnd. The supply voltage depends in particular on the arrangement of the light-emitting diodes and the technology by which the light-emitting diodes are manufactured. For example, the supply voltage can be in the order of 4 V to 5 V.

[0051] For each row, the display pixels 1¾ of the row are connected to at least one row electrode 18;. For each column, the display pixels 12;j of the column are connected to at least one column electrode 20j. The display screen 10 comprises a synchronization circuit 22 connected to the row electrodes 18; and adapted to deliver a synchronization signal Corn; on each row electrode 18;. The display screen 10 comprises a data transmission circuit 24 connected to the column electrodes 20j and adapted to transmit a data signal Data, on each column electrode 20j. The synchronization circuit 22 and the data transmission circuit 24 are controlled by a circuit 26, comprising for example a microprocessor. In particular, the circuit 26 receives the video data to be displayed by the display pixels 1¾.

[0052] In general, each row of display pixels is selected successively and the display pixels of the selected row are programmed to display the desired image pixels. In a known method of selecting the display pixels, the synchronization circuit 22 is adapted to deliver synchronization signals Corn; on the row electrodes 18; in order to successively select each row of display pixels 1¾ and the data transmission circuit 24 is adapted to deliver Dataj data signals on each column electrode 20j representing the digital color data that is stored in the selected display pixels 1¾.

[0053] [Fig. 4] illustrates an example of a block diagram of a display pixel 1¾ of the display screen 10. For a color display screen, the display pixel 1¾ comprises a light-emitting circuit 30 comprising at least three LEDs emitting radiation of different colors, a single LED being illustrated in [Fig. 4]. The light-emitting circuit 30 comprises, for each LED, a controllable current source CS which is connected in series with the LED. The controllable current source CS comprises, for example, a MOS transistor in series with a current source providing a constant current.In the present example, for each light-emitting diode LED, the anode of the light-emitting diode LED receives a high reference potential Vcc and the cathode of the light-emitting diode LED is for example connected to one terminal of the controllable current source CS, the other terminal of the controllable current source CS receiving a low reference potential Gnd. In the case of a monochromatic display screen, each display pixel 1¾ may comprise a light-emitting circuit comprising a single light-emitting diode LED.The LED light-emitting diodes may be 2D light-emitting diodes, also called planar light-emitting diodes, comprising a stack of planar layers, or 3D light-emitting diodes, each comprising a three-dimensional semiconductor element of micrometric or nanometric size extending in a preferred direction, for example a micro-wire or a nanowire, covered with an active zone. In particular, a 3D light-emitting diode is said to be of the radial type when its active zone extends at least on the side walls of the three-dimensional semiconductor element.

[0054] The display pixel 1¾ further comprises a driver circuit 40 for driving the controllable current source CS. The driver circuit 40 may in particular comprise electronic components such as MOS transistors. The driver circuit 40 comprises a storage circuit 48 (color data registers) clocked by a clock signal Clk configured to store the digital color signals R, G, B on the basis of the received digital data. The digital color signals R, G, B each comprise a number NB of bits, from the most significant bit, called MSB, to the least significant bit, called LSB, and are representative of the color components of the image pixels to be displayed. The driver circuit 40 comprises a circuit 50 (LED driver) configured to control the controllable current sources CS connected to the light-emitting diodes LED with signals I_red, I_green and I_blue, obtained from the digital color signals R, G, B, and a PWM signal. The data may correspond to the signal Dataj transmitted to the display pixel 1¾ on the column electrode 20j during a selection phase. The PWM signal may correspond to the selection and synchronization signal Com; transmitted to the display pixel 1¾ on the row electrode 18; during a display phase.

[0055] [Fig. 5] illustrates a timing diagram of the PWM signal and the signals I_red_l, I_red_2, I_red_3 and I_red_4 corresponding to the signal I_red supplied by the circuit 50 of the display pixel 1¾ of [Fig. 4] for the display of four different digital color signals R. According to one embodiment, the light-emitting diodes LED of the display pixel 12;j are controlled by pulse width modulation. To this end, during a display phase, the PWM signal has a succession of pulses PA in the logic state "1" which sets the pace for the operation of the circuit 50 for controlling the light-emitting diodes LED by pulse width modulation. The number of pulses PA in the succession of pulses in the display phase may correspond to the number NB+1.

[0056] For example, when the current source CS corresponds to a current source providing a constant current in series with a MOS transistor, the MOS transistor is activated or deactivated as a function of the logic value "0" or "1" of each bit of the digital color signal R, G or B, from the most significant bit MSB to the least significant bit LSB, at the rate of the pulses of the PWM signal, the MOS transistor being kept activated or deactivated until the next pulse of the PWM signal. Consequently, the current source CS is activated or deactivated for NB successive durations as a function of the logic values ​​of the bits of the digital color signal R, G or B.For example, the current source CS may be activated for a duration where the bit of the digital color signal R, G or B associated with this time interval is at the logic value "1" and may be deactivated for a duration where the bit of the digital color signal associated with this time interval is at the logic value "0". The duration TA;, i being in the range from 1 to NB, between two successive PA pulses of the PWM modulation signal may be divided each time by two, so that the total duration during which the light-emitting diode is lit depends on the value of the digital color signal R. In particular, the duration TANB which is associated with the least significant bit of the digital color signal R, G or B may correspond to the duration of the last PA pulse of the succession of PA pulses of the PWM signal. The succession of PA pulses of the PWM signal may be repeated until another image pixel is displayed.In this case, the succession of PA pulses of the PWM signal forms a display cycle and the display phase comprises more than one display cycle.

[0057] In [Fig.5], as an example, the number of PA pulses in one display cycle of the PWM modulation synchronization signal is equal to 8 and only one display cycle is shown. The signal I_red_l is obtained for displaying an image pixel color component corresponding to the digital color signal R equal to "1010101". The signal I_red_2 is obtained for displaying an image pixel color component corresponding to the digital color signal R equal to "0101010". The signal I_red_3 is obtained for displaying an image pixel color component corresponding to the digital color signal R equal to "1111111". The signal I_red_4 is obtained for displaying an image pixel color component corresponding to the digital color signal R equal to "0000000".

[0058] According to one embodiment, the first and second mechanisms are implemented so that, with digital color signals R, G, B encoded on NB bits, the displayed image appears as if the digital color signals were encoded on a number of bits, which corresponds to the color depth of the image, greater than NB. Both the first and second mechanisms participate in the elimination of the stepped parts of the gamma decoding curve with a limited increase in the number of bits of the video input. According to one embodiment, the first mechanism is implemented when the gray level of the image pixel is less than a first threshold and is not implemented when the gray level of the displayed image is greater than the first threshold.According to one embodiment, the second mechanism is implemented when the gray level of the displayed image is lower than a second threshold and is not implemented when the gray level of the image pixel is higher than the second threshold. When both the first and second mechanisms can be implemented, the first threshold is lower than the second threshold. Therefore, when the gray level of the displayed image is higher than the second threshold, i.e. for a light tone, for which the gamma decoding curve does not have a stepped portion, neither of the first and second mechanisms is implemented. When the gray level of the image pixel is higher than the first threshold and lower than the second threshold, i.e. for a dark but not very dark tone, for which the gamma decoding curve has a not too pronounced stepped portion, the first mechanism is not implemented and the second mechanism is implemented.Therefore, when the gray level of the displayed image is below the first threshold, i.e. for a very dark tone, for which the gamma decoding curve has a pronounced stepped part, both the first and second mechanisms are implemented.

[0059] According to one embodiment, the first mechanism is implemented when a first index II, corresponding to a first binary signal, is at a first logical value, for example "0", and is not implemented when the first index II is to a second logical value, for example "1". According to one embodiment, the second mechanism is implemented when a second index 12, corresponding to a second binary signal, is at a first logical value, for example "0", and is not implemented when the second index 12 is at a second logical value, for example "1". Therefore, when the gray level of the displayed image is lower than the first threshold, i.e. for a very dark tone, the first and second mechanisms are both implemented, and the index II is at "0" and the index 12 is at "0". When the gray level of the image pixel is higher than the first threshold and lower than the second threshold, i.e. for a dark but not very dark tone, the first mechanism is not implemented and the second mechanism is implemented, and the index II is at "1" and the index 12 is at "0".When the gray level of the displayed image is higher than the second threshold, i.e. for a light tone, neither of the first nor second mechanisms is implemented, and index II is at "1" and index 12 at "1".

[0060] According to one embodiment, in the case where the video input must be coded on a higher number NBMAX of bits so that the gamma decoding curve does not have a stepped part for any gray level, the video input is coded on a number NT of bits and 1 bit is used for index II and 1 bit is used for index 12, the number NB+2 being less than NBMAX. For example, in the case where the video input must be coded on 20 bits so that the gamma decoding curve does not have a stepped part for any gray level, as shown in [Fig. 2], according to one embodiment, 13 bits are used for the video input and 2 bits for indexes II and 12. The number of bits NB+2 used so that the gamma decoding curve does not have a stepped part is advantageously less than NBMAX.

[0061] For the first mechanism, pulse amplitude modulation is implemented for very dark tones in addition to pulse width modulation. More specifically, the current supplied to the LED is decreased for very dark tones without modifying the PWM signal. This is equivalent to modifying the PWM signal without modifying the current supplied to the LED, so that more than NT different on / off durations of the LEDs are available, where NT is an integer strictly greater than NB, preferably greater than NB+1, and more preferably greater than NB+2.The display method according to the embodiment implementing the first mechanism with a digital color signal comprising NB bits is equivalent to a display method in which the known modulation synchronization signal, the PWM signal, would provide NT different durations and a digital color signal would comprise NT bits.

[0062] For the second mechanism, the PWM modulation synchronization signal is modified relative to a known PWM modulation synchronization signal, so that more than NT' different durations for activation / deactivation of the light-emitting diodes are available, where NT' is an integer strictly greater than NB, preferably greater than NB+1, and more preferably greater than NB+2. The display method according to the embodiment implementing the second mechanism with the modified PWM modulation synchronization signal providing NT' different durations and a digital color signal comprising NB bits is equivalent to a display method in which the known PWM modulation synchronization signal would provide NT' different durations and a digital color signal would comprise NT' bits.

[0063] For the first mechanism, the intensity of the current supplied by the current source CS varies between at least two values ​​with respect to the first index II, while the light-emitting diode LED is controlled by pulse width modulation. According to one embodiment, the intensity of the current supplied by the current source CS varies between a first intensity in a first operating mode of the first mechanism and a second intensity greater than the first intensity in a second operating mode of the first mechanism, the factor K being the ratio between the first intensity and the second intensity. A decrease in the intensity of the current by the current source CS by a factor K without modifying the durations used for the pulse width modulation is equivalent to a decrease by a factor K of each duration used for the pulse width modulation without modifying the intensity of the current supplied by the current source CS.According to one embodiment, the index II is associated with each value of the digital color signal R, G, B.

[0064] [Fig.6] illustrates a block diagram of an embodiment of light emitting circuit 30 of the display pixel 1¾ of [Fig.4].

[0065] The controllable current source CS comprises a switch SW in series with an adjustable current source VCS providing a current of controllable intensity. The switch SW is controlled by the signal I_red. The adjustable current source VCS is controlled by the index II. According to one embodiment, the index II is a binary signal and the variable current source VCS provides the current ICS with a first intensity ICSI when the index II is at a first logic value and provides the current ICS with a second intensity ICS2, different from the first intensity ICSI, when the index II is at a second logic value.

[0066] [Fig.7] illustrates a block diagram of another embodiment of light emitting circuit 30 of the display pixel 12ij of [Fig.4].

[0067] The light emitting circuit 30 comprises two light emitting diodes LED1 and LED2 emitting radiation at substantially the same wavelength. Each light emitting diode LED1 and LED2 may comprise one or more elementary light-emitting diodes. Each elementary light-emitting diode can be a 3D light-emitting diode. In [Fig.7], light-emitting diodes LED1 and LED2 are shown connected to a common anode. However, it may be desirable to arrange light-emitting diodes LED1 and LED2 in another configuration. For example, light-emitting diodes LED1 and LED2 can be connected to a common cathode.

[0068] The controllable current source CS comprises a first switch SW 1 in series with a first constant current source CS1, and a second switch SW2 in series with a second constant current source CS2. The first switch SW1 in series with the first constant current source CS1 is connected between the cathode of the first light-emitting diode LED1 and the source of the low reference potential Gnd. The second switch SW2 in series with the second constant current source CS2 is connected between the cathode of the second light-emitting diode LED2 and the source of the low reference potential Gnd. The first constant current source CS 1 and the second constant current source CS2 are both controlled by a bias signal Bias.

[0069] According to one embodiment, the first constant current source CS1 and the second constant current source CS2 are both MOS transistors, for example NMOS transistors, and the bias signal is applied to the gate of each of these transistors. The first constant current source CS1 is sized to provide a constant current ICSI. The second constant current source CS2 is sized to provide a constant current ICS2. According to one embodiment, the constant current ICS1 is equal to N1 times a constant reference current Iref and the constant current ICS2 is equal to N2 times a constant reference current Iref.

[0070] The second switch SW2 is controlled by the signal I_red. The controllable current source CS also comprises a logic gate AND1 of the AND type whose first input receives the index II and whose second input receives the binary control signal I_red (or I_green or I_blue). The output of the logic gate AND1 controls the first switch SW1. According to one embodiment, the first switch SW1 and the second switch SW2 are both MOS transistors, for example NMOS transistors, and the output of the logic gate AND1 is applied to the gate of the transistor SW1 and the signal I_red is applied to the gate of the transistor SW2.

[0071] According to one embodiment, the index II is in the logic state "1" for an image pixel which does not have a very dark tone and the index II is in the logic state "0" for an image pixel having a very dark tone. More precisely, in a first mode of operation of the first mechanism, to display an image pixel which does not have a very dark tone (index II in logic state "1"), the output logic gate AND1 corresponds to the signal I_red so that the first and second switches SW 1 and SW2 are both controlled by the signal I_red, and, in a second mode of operation of the first mechanism, for the display of an image pixel having a very dark tone (index II in logic state "0"), the output logic gate AND1 is set to the logic value "0" so that the first switch remains open and only the second switch SW2 is controlled by the signal I_red.

[0072] According to one embodiment, the constant current ICSI is equal to NI times the constant reference current Iref and the constant current ICS2 is equal to N2 times the constant reference current Iref and the light-emitting diode LED1 comprises N1 elementary light-emitting diodes and the light-emitting diode LED2 comprises N2 elementary light-emitting diodes, all the elementary light-emitting diodes having the same structure and emitting radiation at substantially the same wavelength. Thus, the current density passing through each elementary light-emitting diode remains constant regardless of the operating mode of the first mechanism. This is advantageous when it is important to obtain a reduced dispersion of the central wavelength of the radiation emitted by the light-emitting diodes in operation.Indeed, the central wavelength of the radiation emitted by the light-emitting diode generally varies as a function of the current density passing through the light-emitting diode, this variation being significant for three-dimensional light-emitting diodes of the radial type. In the present embodiment, since the current density passing through each elementary light-emitting diode remains constant regardless of the operating mode of the first mechanism, the central wavelength of the radiation emitted by the elementary light-emitting diodes does not vary during operation.

[0073] [Fig. 8] illustrates a block diagram of another embodiment of light-emitting circuit 30 of the display pixel 1¾ of [Fig. 4]. The light-emitting circuit 30 of [Fig. 8] comprises all the elements of the light-emitting circuit 30 of [Fig. 7], except that the light-emitting diodes LED1 and LED2 are replaced by light-emitting diodes LED, the first switch SW1 in series with the first constant current source CS1 being arranged in parallel with the second switch SW2 in series with the second constant current source CS2 between the cathode of the light-emitting diode LED and the source of a low reference potential Gnd. In the present embodiment, the current density through the light-emitting diode LED varies between the first and second operating modes of the first mechanism.

[0074] This embodiment can be implemented when an operating variation of the central wavelength of the radiation emitted by the light-emitting diode LED can be tolerated. This can be the case when the light-emitting diode LED is covered with a photoluminescent block comprising phosphors which are adapted, when excited by the light emitted by the light-emitting diodes, to emit light at a wavelength different from the wavelength of the light emitted by the light-emitting diode LED. Indeed, the phosphors can emit radiation having a substantially constant central wavelength even if there is a variation in the central wavelength of the radiation emitted by the light-emitting diode LED.

[0075] According to one embodiment, the index II is determined by the circuit 26 for each initial digital color signal determined by the circuit 26 and corresponding to an image pixel to be displayed by the display pixel 1¾ and is then sent to the display pixel 12ij. The index II received by the display pixel 1¾ may be stored in a memory of the display pixel 1¾. According to one embodiment, the index II may be determined by the circuit 26 based on one or more bits from among the bits biti to bitNB of the initial digital color signal R, G or B determined by the circuit 26, for example at least one from among the most significant bit bitNB, the second most significant bit bitNB-i, and the third most significant bit bitNB 2 of the initial digital color signal R, G or B determined by the circuit 26. The index II may be determined by the circuit 26 using logic gates.According to one embodiment, the index II can be set to the logic state "0" if all the bits bNB to bNB NiBi of the initial digital color signal R, G or B, NIB1 being an integer, for example equal to 0, 1 or 2, determined by the circuit 26 are in the logic state "0" and the index II can be set to the logic state "1" if at least one of the bits bNB to bNB.N1Bi of the initial digital color signal R, G or B is in the logic state "1". According to one embodiment, the index II is in the logic state "0" only for an image pixel having a difference less than or equal to 5 or 6 gray levels with respect to the black level.

[0076] According to one embodiment, depending on the index II determined on the basis of an initial digital color signal R, G, or B, the circuit 26 can calculate a new digital color signal R, G, or B and the data signals Dataj sent to the pixel 1¾ then correspond to the new digital color signal R, G, or B. According to one embodiment, a new digital color signal R, G, or B is determined for the first mechanism when the index II corresponds to an image pixel having a very dark tone and no new digital color signal R, G, or B is determined for the first mechanism when the index II corresponds to an image pixel having a light tone. When no new digital color signal R, G, or B is not determined for the first mechanism, the data signals Dataj sent to the pixel 1¾ then correspond to the initial digital color signal R, G or B when only the first mechanism is implemented. According to one embodiment, a new digital color signal R, G or B is determined for the first mechanism when the index II corresponds to an image pixel having a very dark tone, based on the initial digital color signal R, G or B. For example, when the index II corresponds to an image pixel having a very dark tone, a new digital color signal R, G or B is determined by the circuit 26 so that the information content of the image pixel is encoded on all NB bits of the digital color signal R, G or B.

[0077] According to one embodiment, the first mechanism may be implemented separately from the second mechanism, which is described below. However, it may be advantageous to implement both the first mechanism and the second mechanism.

[0078] [Fig.9] illustrates a timing diagram of the signals PWM, PWM2,1_red_W and I_red_B according to an embodiment of a method for driving the light-emitting diodes LED of the display pixel 12ij of [Fig.4], for which the light-emitting diodes LED are controlled by pulse width modulation implementing the second mechanism described previously. The signals I_red_W and I_red_B correspond to the signal I_red provided by the circuit 50 of the display pixel 1¾ of [Fig.4] for the display of two different digital color signals R. The signal PWM2 is a signal generated by the circuit 40 of the display pixel 1¾ of [Fig.4]. In [Fig.9], the digital color signal R comprises 5 bits, from biti to bit5, bit5 being the most significant bit and biti being the least significant bit.

[0079] According to one embodiment, the PWM modulation synchronization signal comprises, for a display cycle, an alternation of first and second pulses, each first PA pulse being followed by a second PB pulse. The first PA pulses correspond to the PA pulses of the modulation synchronization signal described previously in relation to [Fig. 5], that is to say that the duration TA;, i being in the range from NB to 1, between two successive first PA pulses of the PWM modulation synchronization signal in a display cycle is divided by two each time. The duration TBj, j being in the range from NB to 1, between a first PA pulse and the second successive PB pulse of the PWM modulation synchronization signal is divided by two compared to the duration between the first PA pulse and the second successive PB pulse preceding.The PWM2 signal includes a rising edge at every first PA pulse and a falling edge at every second PB pulse. By . Therefore, the pulses of the PWM2 signal have durations between TBnb and TBb

[0080] According to one embodiment, a cycle comprises NB+1 first PA pulses and NB+1 second PB pulses. Consequently, there are NB decreasing durations TA;, i being in the range from NB to 1, between the pairs of successive first PA pulses and NB decreasing durations TB;, i being in the range from NB to 1, between the pairs of successive first and second PA, PB pulses.

[0081] More generally, the PWM time signal comprises pulses, some of these pulses being spaced apart by the first durations TA;, i being in the range from 1 to NB, and some of these pulses being spaced apart by the second durations TB;, i being in the range from 1 to NB. For example, the pulses used to determine the first durations TA; may precede or follow the pulses used to determine the second durations TB;. However, the embodiment described above in which the first and second pulses PA, PB are alternated advantageously makes it possible not to increase the duration of the display cycle compared to the case where only the first durations TA; would be used.

[0082] According to one embodiment, in a display cycle, one or more, but not all, of the durations TBi to TBnb last as long as at least one of the durations TAnb to TAp. According to one embodiment, the duration TBnb between the first pulse PA and the second successive pulse PB at the very beginning of the display cycle lasts as long as the duration TANB to TAi between two first successive pulses PA towards the end of the display cycle, for example the duration between the penultimate first pulse and the last first pulse of the display cycle, or the duration between the third penultimate first pulse and the penultimate first pulse of the display cycle. There are durations NT' of different values ​​in the group comprising all the durations TANB to TAi and TBnb to TBh with NT' strictly greater than NB and strictly less than 2*NB.

[0083] In [Fig.9], the PWM modulation time signal comprises 6 first PA pulses which are alternated with 6 second PB pulses. The duration TBnb between the first succession of first and second PA and PB pulses from the beginning of the display cycle is as long as the duration TA2 between the penultimate first pulse and the penultimate first pulse of the display cycle, and the duration TBnb i between the second succession of first and second PA and PB pulses from the beginning of the display cycle is as long as the duration TAi between the penultimate first pulse and the last first pulse of the display cycle. The last second PB pulse, illustrated in [Fig.9], which follows the last first PA pulse is not used, so that it could be absent, even if, in In practice, it may be easier to generate a second PB pulse after each first PA pulse to simplify the generation of the PWM2 signal.

[0084] According to one embodiment, the second index 12 is associated with each value of the digital color signal R, G, B. The index 12 may be a binary value. During a display operation, depending on the logic state of the index 12, the durations TANB to TAi or the durations TBnb to TBi are used to drive the light-emitting diode LED.

[0085] According to one embodiment, the index 12 is determined by the circuit 26 for each initial digital color signal determined by the circuit 26 corresponding to an image pixel to be displayed by the display pixel 1¾ and is then sent to the display pixel 12ij. The index 12 received by the display pixel 1¾ can be stored in a memory of the display pixel 1¾. According to one embodiment, the index 12 may be determined by the circuit 26 based on one or more bits from bits biti to bitNB of the initial digital color signal R, G, or B determined by the circuit 26, for example at least one from the most significant bit bitNB, the second most significant bit bitNB-i, and the third most significant bit bitNB 2 of the initial digital color signal R, G, or B determined by the circuit 26. The index 12 may be determined by the circuit 26 using logic gates.According to one embodiment, the index 12 is in a first logic state, for example the logic state "1", for an image pixel having a light tone and the index 12 is in a second logic state, for example the logic state "0", for an image pixel having a dark tone. According to one embodiment, the index 12 can be set to the logic state "0" if all the bits bNB to bNB N1B2 of the initial digital color signal R, G or B, NIB2 being an integer, for example equal to 0, 1 or 2, determined by the circuit 26 are in the logic state "0" and the index 12 can be set to the logic state "1" if at least one of the bits bNB to bNB N1B2 of the initial digital color signal R, G or B is in the logic state "1". The switching conditions of index 12 and index II are determined so that index 12 switches for lighter tones than index II. According to one embodiment, the integer NIB2 is greater than the integer NIB1.

[0086] According to one embodiment, depending on the index 12 determined on the basis of an initial digital color signal R, G, or B, the circuit 26 can calculate a new digital color signal R, G, or B and the data signals Dataj sent to the pixel 1¾ then correspond to the new digital color signal R, G, or B. According to one embodiment, a new digital color signal R, G, or B is determined for the second mechanism when the index 12 corresponds to an image pixel having a dark tone and no new digital color signal R, G, or B is determined when the index 12 corresponds to an image pixel having a light tone. When no new digital color signal R, G, or B is determined for the second mechanism, the data signals Dataj sent to the pixel 1¾ then correspond to the initial digital color signal R, G or B. According to one embodiment, a new digital color signal R, G or B is determined for the second mechanism when the index 12 corresponds to an image pixel having a dark tone, based on the initial digital color signal R, G or B. For example, when the index 12 corresponds to an image pixel having a dark tone, a new digital color signal R, G or B is determined by the circuit 26 so that the information content of the image pixel is encoded on all NB bits of the digital color signal R, G or B.

[0087] According to one embodiment, the index 12 is in the logic state "1" for an image pixel having a light tone and the index 12 is in the logic state "0" for an image pixel having a dark tone. More specifically, in a first operating mode of the second mechanism, to display an image pixel having a light tone (index 12 in logic state "1"), the durations TANB to TAi are used to power the light-emitting diode LED, the current source CS powering the light-emitting diode LED is activated or deactivated during the successive durations TAnb to TAi depending on the logic value "0" or "1" of each bit bNB to bi of the digital color signal R, G or B starting from the most significant bit bNB of the digital color signal R, G or B and, in a second operating mode of the second mechanism, to display an image pixel having a dark tone (index 12 in logic state "0"),the durations TBnb to TBi are used to power the light-emitting diode LED, the current source CS powering the light-emitting diode LED being switched on or off during the successive durations TBnb to TBi depending on the logic value "0" or "1" of each bit bNB to bi of the digital color signal R, G or B starting from the most significant bit bNB of the digital color signal R, and being switched off between two successive durations TBnb to TBb For example, in [Fig.9], the signal I_red_W is obtained using the durations TANB to TAi and the signal I_red_B is obtained using the durations TBnb to TBb ,

[0088] Alternatively, when the current source CS corresponds to a MOS transistor, this transistor can be activated or deactivated, during the durations TA; or TBj, depending on the logic value "0" or "1" of each bit of the color signal R, G or B from the least significant bit to the most significant bit of the color signal R, G or B. In this case, the duration TA;, i being in the range from NB to 1, between two first successive pulses PA of the PWM modulation synchronization signal in a display cycle is multiplied by two each time, and the duration TBj, j being in the range from NB to 1, between a first pulse PA and the second successive pulse PB of the PWM modulation synchronization signal is multiplied by two relative to the duration between the first PA pulse and the second successive PB pulse which precedes it.

[0089] The display method according to the present embodiment with the PWM modulation synchronization signal comprising the first and second pulses PA and PB and a digital color signal comprising NB bits is equivalent to a display method in which the PWM modulation synchronization signal comprises only the first pulses and a digital color signal comprising NT' bits b / , j being in the range from 1 to NT'. Therefore, a color depth of NT' bits is advantageously obtained with a digital color image encoded on NB bits. [Fig.9] indicates the correspondence between the bit b;, i being in the range from 1 to 5, and the bit b / , j being in the range from 1 to 8.

[0090] [Fig. 10] illustrates a block diagram of one embodiment of a portion of the circuit 40 of [Fig. 4].

[0091] Circuit 40 comprises - a circuit 60 configured to receive the PWM modulation synchronization signal and to provide the PWM2 signal; - a storage circuit 48 comprising a shift register clocked by the PWM2 signal, in which the digital color signal R, G or B is stored and providing a binary signal / bj at its output QB; - a circuit 62 configured to provide a binary index 12; and - a logic circuit 64 configured to receive the signals / b;, 12 and PWM2 and to provide a binary control signal I_red, I_green or I_blue.

[0092] The binary signal / b; is the logical complement of the binary bit b; of the digital color signal R, G or B. When it is clocked by the signal PWM2, the shift register 48 successively provides at its output QB bit / b;, which is the logical complement of the bit b;, i being in the range from NB to 1, starting with the complement of the most significant bit bNB. The circuit 60 must provide a signal PWM2 comprising a rising edge at each first pulse PA and a falling edge at each second pulse PB.

[0093] According to one embodiment, the circuit 62 includes a memory in which the index 12 is stored when it is received by the display pixel 1¾. According to one embodiment, the index 12 is stored in the shift register 48 and is used to drive the light-emitting diode LED by pulse width modulation with the shorter of the durations TAi or TBi so that it has substantially no impact on the total lighting duration of the light-emitting diode LED. For example, when the index 12 is equal to the logic state "1" for the light tones and it is stored in shift register 48, controlling the LED by pulse width modulation with the shortest duration TAi associated with index 12 equal to "1" would have practically no impact on the total time the LED is on. The shortest duration TAi is advantageously placed as low as possible.

[0094] [Fig. 11] illustrates a block diagram of one embodiment of the logic circuit 64 of [Fig. 10]. The logic circuit 64 comprises: - a first logic gate NOR1 of NOR type having a first input receiving the binary signal PWM2 and having a second input receiving the binary index 12; and - a second NOR2 logic gate of NOR type having a first input receiving the binary signal / b; and having a second input receiving the binary signal supplied to the output of the first NOR1 logic gate and supplying the binary control signal I_red (or I_green or I_blue).

[0095] In the present embodiment, in the first mode of operation of the second mechanism, for light tones, the binary index 12 is set to the logic value "1". Consequently, the output of the first logic gate NOR1 remains at the logic value "0" throughout the display cycle and the output I_red (or I_green or I_blue) of the second logic gate NOR2 is equal to the binary logic complement of the binary signal / b;, i.e. equal to bit b;.

[0096] As the shift register 48 is clocked by the signal PWM2, the logic circuit 64 successively provides the bits NB of the digital color signal R clocked by the signal PWM2, preferably at each rising edge of the signal PWM2. The rising edges of the signal PWM2 are simultaneous with the rising edges of the first pulses PA of the PWM modulation synchronization signal. A pulse width modulation is then obtained in the first operating mode of the second mechanism with durations TANB to TA,.

[0097] In the present embodiment, in the second operating mode of the second mechanism, for dark tones, the binary index 12 is set to the logic value "0". Consequently, the output of the first logic gate NOR1 is equal to the logic complement of the binary signal PWM2. When the signal PWM2 is in the logic state "0", the output of the first logic gate NOR1 is equal to the logic state "1" and the output I_red of the second logic gate NOR2 is equal to the logic state "0". The light-emitting diode LED is then off. When the signal PWM2 is in the logic state "1", that is to say between each first pulse PA and the second successive pulse PB, the output of the first logic gate NOR1 is set to the logic value "0" and the output I_red of the second logic gate NOR2 is equal to the complement logic of the binary signal / b;, i.e. equal to bit b; of the digital color signal R stored in the shift register 48. We then obtain a pulse width modulation with the second operating mode of the second mechanism with durations TBnb to TBb

[0098] According to one embodiment, the second mechanism is implemented for dark tones and the first and second mechanisms are implemented for very dark tones. Therefore, there are three modes of operation for displaying an image pixel for the 1¾ display pixel.

[0099] In the first mode of operation of the display method, for very dark tones, index 12 is set to the logic value "0" and index II is set to the logic value "0". Therefore, the second durations TBnb to TBi are used and the intensity of the current passing through the light-emitting diode is the lowest. In the second mode of operation of the display method, for tones between very dark tones and dark tones, index 12 is set to the logic value "0" and index II is set to the logic value "1". Therefore, the second durations TBnb to TBi are used and the intensity of the current passing through the light-emitting diode is the highest. In the third mode of operation of the display method, for bright tones, index 12 is set to the logic value "1" and index II is set to the logic value "1".Therefore, the first durations TANB to TAi are used and the current intensity through the light-emitting diode is the highest.

[0100] According to one embodiment, the indices II and 12 are sent to the display pixel 1¾ using the data signal Dataj in addition to the bits of the initial or new R, G, B digital color signal. For example, when the R, G, B digital color signal is encoded on NB bits and each index II and index 12 is encoded on one bit, the data signal Dataj is used to send NB+2 bits to the display pixel 1¾ for each R, G, B digital color signal. According to another embodiment, each of the indices II and 12 is sent to the display pixel 1¾ using both the data signal Dataj and the synchronization signal Com;, for example by providing simultaneous specific patterns for the data signal Dataj and the synchronization signal Com;.According to another embodiment, each of the indices II and 12 is sent to the display pixel 1¾ using the data signal Dataj by specifically determining one or more bits of the digital color signal R, G, B, according to a determined logic, for example one bit among the least significant bit bb the second least significant bit b2, or the third least significant bit b3 of the digital color signal R, G, B. The display pixel 12ij is then adapted to extract each of the indices II and 12 from the stored digital color signal R, G, B. .

[0101] As an example, Table 1 below includes: - in the first column titled "Gray Scale (10-bit)", the 1023 gray scale values ​​in decimal notation that can be encoded with 10 bits; - in the second column titled "Linear Ideal (13 bits)", the corresponding ideal values ​​obtained in decimal notation after a linear conversion which can be coded with 13 bits; - in the third column titled "Ideal 2.2", the corresponding ideal values ​​in decimal notation after a gamma conversion with yd equal to 2.2; - in the fourth column titled "Real (13 bits) without indexes", the corresponding real values ​​in decimal notation after a gamma conversion with yd equal to 2.2 which can be coded on 13 bits without using indexes II and 12; - in the fifth column entitled "II", the value of index II; - in the sixth column titled "12", the value of index 12; - in the seventh column titled "Real (13 bits) with index", the corresponding real values ​​in decimal notation after a gamma conversion with yd equal to 2.2 which can be coded with 13 bits with the use of indices II and 12; - in the eighth column entitled "Ideal* 128 or 16", the corresponding ideal values ​​in decimal notation; - in the ninth column entitled "Round-up", the rounded value of the eighth column; and - in the ninth column entitled "Note", M1 is indicated for the first mode of operation of the display method, M2 is indicated for the second mode of operation of the display method and M3 is indicated for the third mode of operation of the display method.

[0102] [Tables 1] Color screen (10 bits) Liner image (1 3 bits) Image 2.2 Display (1 3_bit) II 12 Display (13 bits) sans index Image*128 or 16 Tour d'horizon Note 0 0 0,00 0 0 0 0,00 0 0 Ml 1 15 0.01 0 0 0 0.01 0.9967963 26 1 Ml 2 23 0.02 0 0 0 0.02 2.5527418 47 3 Ml 3 31 0.04 0 0 0 0.04 4.9226775 03 5 Ml 4 39 0.06 0 0 0 0.06 8.1573255 33 8 Ml 5 47 0.10 0 0 0 0.09 12.297616 51 12 Ml 6 55 0.14 0 1 0 0.13 2.1722689 2 2 M2 7 63 0.18 0 1 0 0.19 2.9286325 19 3 M2 8 71 0.24 0 1 0 0.25 3.8096408 83 4 M2 9 79 0.30 0 1 0 0.31 4.8183159 27 5 M2 10 87 0.37 0 1 0 0.38 5.9574173 69 6 M2 11 95 0.45 0 1 0 0.44 7.2294890 32 7 M2 12 103 0.54 1 1 0 0.56 8.6368935 29 9 M2 • 110 887 61.58 62 1 0 61.56 985.25270 34 985 M2 111 895 62.81 63 1 0 62.81 1004.9081 06 1005 M2 112 903 64.05 64 1 0 64.06 1024.7754 72 1025 M2 113 911 65.30 65 1 0 65.31 1044.8551 82 1045 M2 114 919 66.57 67 1 0 66.56 1065.1476 08 1065 M2 115 927 67.85 68 1 1 68 M3 116 935 69.15 69 1 1 69 M3 117 943 70.46 70 1 1 70 M3 • 1019 8159 8120.76 8121 1 1 8121 M3 1020 8167 8138.29 8138 1 1 8138 M3 1021 8175 8155.84 8156 1 1 8156 M3 1022 8183 8173.41 8173 1 1 8173 M3 1023 8191 8191.00 8191 1 1 8191 M3

[0103] [Fig. 12] illustrates the gamma decoding function Rgaml3+2 actually obtained when implementing the display method described above and the values ​​of index II and index 12.

[0104] [Fig.13] illustrates an enlarged view of [Fig.12]. The Rgaml3+2 curve closely follows the ideal gamma decoding function Igam illustrated in [Fig.l] with substantially the same accuracy as that obtained with the gamma decoding function Rgam20 obtained with 20-bit coding. Therefore, the same accuracy can be obtained using only 15 bits, with 13 bits for the digital color signals R, G, B and 2 bits for the indices II and 12. This advantageously leads to a reduction in data rate and circuit size of approximately 25%.

[0105] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. In particular, the PWM modulation may be generated internally in the driver circuit 40 of the display pixel 1¾ to avoid using the Com signal; to generate it. Other embodiments may also use other electro-optical components such as organic light-emitting diodes. Furthermore, the first mechanism described above may be implemented with a pulse width modulation control different from the pulse width modulation control described above.For example, the pulse width modulation control may include controlling the current source to supply the light emitting diode with a single current window during each display cycle, with the ratio of the duration of the current window to the duration of the display cycle depending on the associated digital color data.

[0106] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

1. Claims A display pixel (1¾) comprising at least one light-emitting diode (LED), a controllable current source (CS) supplying said light-emitting diode (LED) with successive current pulses, and an electronic circuit (40) comprising a storage circuit (48) for storing at least one digital signal (R, G, B) comprising several bits and a driver circuit (50) configured to control the current source (CS) to provide the successive current pulses by pulse width modulation by providing the successive current pulses having different durations which depend on the bits of the digital signal (R, G, B), and is configured to control the current source (CS) to provide the successive current pulses by pulse amplitude modulation by providing the successive current pulses having the same intensity selected from at least first and second intensities,wherein the driver circuit (50) is configured to control the controllable current source (CS) to provide the successive current pulses by pulse width modulation based on the digital signal (R, G, B) at the first intensity when a first binary signal (II) is at a first logic value, and to control the controllable current source (CS) to provide the successive current pulses by pulse width modulation based on the digital signal (R, G, B) at the second intensity, higher than the first intensity, when the first binary signal (II) is at a second logic value, wherein the controllable current source (CS) comprises a first constant current source (CS1) in series with a first switch (SW1) and a second constant current source (CS2) in series with a second switch (SW2), wherein the driver circuit (50) is configured,when the first binary signal (II) is at the second logic value, to control the first switch (SW1) and the second switch (SW2) by pulse width modulation based on the digital signal (R, G, B), to control the first switch (SW 1) and the second switch (SW2) by pulse width modulation based on the digital signal (R, G, B) and, when the first, binary signal (II) is at the first logic value, to open the first switch (SW1) and to control the second switch (SW2) by pulse width modulation according to the digital signal (R, G, B), and wherein the light-emitting diode (LED) comprises a first set (LED1) of elementary light-emitting diodes and a second set (LED2) of elementary light-emitting diodes, wherein the elementary light-emitting diodes of the first set (LED1) of elementary light-emitting diodes are connected to the first constant current source (CS1) and the elementary light-emitting diodes of the second set (LED2) of elementary light-emitting diodes are connected to the second constant current source (CS2).

2. The display pixel of claim 1, wherein the electronic circuit (40) is configured to receive the first binary signal (II) from outside the display pixel.

3. Display pixel according to claim 1 or 2, wherein the driver circuit (50) comprises a logic gate (AND1) of the AND type having a first input receiving the first binary signal (II) and having a second input successively receiving the bits of the digital signal (R, G, B), the output of the logic gate (AND1) of the AND type controlling the first switch (SW1), and wherein the driver circuit (50) is configured to control the second switch (SW2) from the successive bits of the digital signal (R, G, B).

4. A display pixel according to any one of claims 1 to 3, wherein the light-emitting diode (LED) is connected to the first constant current source (CS1) and the second constant current source (CS2).

5. A display pixel according to any one of claims 1 to 4, wherein the driver circuit (50) is configured to control said light-emitting diode (LED), when a second binary signal (12) is at a first logic value, by switching on or off said light-emitting diode for different first durations (TA5, TA4, TA3, TA2, TAJ depending on the logic states of the bits of the digital signal (R, G, B) or, when the second binary signal (12) is at a second logic value, by switching on or off said light-emitting diode for different second ... different durations (TB5, TB4, TB3, TB2, TBj, at least partially different from the first durations, depending on the logical states of the bits of the digital signal (R, G, B).

6. The display pixel of claim 5, wherein the electronic circuit (40) is configured to receive the second binary signal (12) from outside the display pixel.

7. A display pixel according to claim 5 or 6, wherein the digital signal (R, G, B) comprises NB bits b;, i being in the range from 1 to NB, the bit bNB being the most significant bit and the bit bi being the least significant bit, wherein the first durations comprise NB first durations TA; (TA5, TA4, TA3, TA2, TAi) of increasing values, wherein the second durations comprise NB second durations TB; (TB5, TB4, TB3, TB2, TBi) of increasing values, wherein the driver circuit (50) is configured to control said light-emitting diode (LED) by pulse width modulation, when the second binary signal (12) is at the first logic value, by turning on or off said light-emitting diode during the NB first durations TA; (TA5, TA4, TA3, TA2, TAi), said light-emitting diode being lit during the first duration TA; when bit b;is in a first logic state and being off during the first duration TA; when the bit b; is in a second logic state, different from the first logic state, and in which the driver circuit (50) is configured to control said light-emitting diode by pulse width modulation, when the second binary signal (12) is at the second logic value, by switching on or off said light-emitting diode during the NB second durations TB; (TB5, TB4, TB3, TB2, TBi), said light-emitting diode being on during the second duration TB; when the bit b; is in the first logic state and being off during the second duration TB; when the bit b; is in the second logic state.;

8. A display pixel according to any one of claims 5 to 7, wherein the electronic circuit (40) is configured to receive a third binary signal (Com;) comprising pulses (PA, PB), some of these pulses being spaced apart by first durations (TA5, TA4, TA3, TA2, TAi) and some of these pulses being spaced apart by second durations (TB5, TB4, TB, TB, TB32[), said electronic circuit being configured to turn on or off said light-emitting diode (LED) for the first durations or the second durations depending on said pulses.

9. The display pixel of claim 8, wherein the pulses comprise first pulses (PA), the first pulses being spaced apart by first durations (TA5, TA4, TA3, TA2, TAi), and further comprise second pulses (PB), each first pulse (PA) being followed by a second pulse (PB), the first pulses and subsequent second pulses being spaced apart by second durations (TB5, TB4, TB3, TB2, TB;).

10. Display screen (10) comprising: - display pixels (1¾) according to any one of claims 1 to 9, arranged in rows and columns; - first electrically conductive tracks (18;) extending along the rows and connected to the electronic circuits (40) of the display pixels; - second electrically conductive tracks (20;) extending along the columns and connected to the electronic circuits (40) of the display pixels; and - a control circuit (22, 24, 26) connected to the first electrically conductive tracks (18;) and to the second electrically conductive tracks (20;).

11. A display screen according to claim 10, wherein the control circuit (22, 24, 26) is configured to determine the first binary signal (II) for each digital signal (R, G, B) and to provide the first binary signals to the display pixels (1¾).

12. A display screen according to claim 11, wherein the display pixels (1¾) are according to claim 8, and wherein the control circuit (22, 24, 26) is configured to determine the second binary signal (12) for each digital signal (R, G, B) and to provide the second binary signals to the display pixels (1¾).

13. A display screen according to claim 12, wherein the control circuit (22, 24, 26) is configured to set the first binary signal (II) to the first logic value when the digital signal (R, G, B) corresponds to a luminance less than a first luminance threshold, for placing the first binary signal (II) at the second logic value when the digital signal (R, G, B) corresponds to a luminance greater than the first luminance threshold, for placing the second binary signal (12) at the second logic value when the digital signal (R, G, B) corresponds to a luminance lower than a second luminance threshold, greater than the first luminance threshold, and for placing the second binary signal (12) at the first logic value when the digital signal (R, G, B) corresponds to a luminance greater than the second luminance threshold.

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