Display pixels comprising light emitting devices and display screen comprising such display pixels

Abstract

Display pixel comprising light emitting devices and display screen comprising such display pixels The present description relates to a display pixel (12i,j) comprising a light emitting device (LED), a controllable current source (CS) supplying the light emitting device (LED) and a driver circuit (50) receiving a digital color signal (R, G, B). The digital color signal comprises a number NB of bits each having a rank ranging from the least significant bit to the most significant bit.The driver circuit receives at least some of said NB bits in a first order then in a second order, different from the first order, and, for each bit received, activates the controllable current source when said bit is at a first logic value for a duration which depends on the rank of said bit or deactivates the controllable current source for said duration when said bit is at a second logic value, said durations increasing from the least significant bit to the most significant bit. Figure for the abstract: Fig. 2.

Description

Title of the invention: Display pixels comprising light emitting devices and display screen comprising such display pixels Technical field

[0001] The present description relates to a display pixel comprising light emitting devices, for example light emitting diodes, and a display screen comprising such display pixels. Prior art

[0002] A pixel of an image corresponds to the unit element of the image displayed by a display screen. For the display of color images, the display screen generally comprises, for the display of each image pixel, at least three components, also called display sub-pixels, which each emit light radiation, called the color component of the image pixel, essentially in a single color (for example, red, green and blue). The superposition of the color components of the image pixel emitted by the three display sub-pixels provides the observer with the colored sensation corresponding to the displayed image pixel. In this case, the assembly formed by the three display sub-pixels used for the display of a pixel of an image is called a display pixel of the display screen. Each display sub-pixel may comprise a light source, in particular a light-emitting diode.

[0003] The display pixels may be distributed in a matrix, with each display pixel located at the intersection of a row (also referred to as a line) and a column of the matrix. Electrodes are provided along the rows and columns to connect each display pixel to control circuits. In general, each row of display pixels is successively selected by a signal transmitted along the row electrodes, and the display pixels in the selected row are programmed to display the desired image pixels by signals transmitted along the column electrodes.

[0004] It is known to control a light-emitting diode by pulse width modulation, also called PWM (English acronym for "Pulse Width Modulation"). This type of control consists of circulating successive current pulses of constant intensity in the light-emitting diode, the pulses being repeated cyclically, the duty cycle determining the light intensity emitted by the light-emitting diode. Such control advantageously makes it possible to operate the light-emitting diode at its operating point. optimal operation where the efficiency of the light-emitting diode, equal to the ratio between the luminous power emitted by the light-emitting diode and the electrical power consumed by the light-emitting diode, is maximum. In addition, a pulse width modulation control allows the current density passing through the light-emitting diode to be kept constant. This is advantageous because, for some types of light-emitting diodes, the central wavelength of the radiation emitted by the light-emitting diode can vary with the current density passing through the light-emitting diode.

[0005] The light-emitting diode may be powered by a controllable current source. The controllable current source may comprise a current source in series with a switch. The switch is controlled to achieve the pulse width modulation while the current source delivers the constant current. The current source may comprise a MOS transistor, the current flowing through the MOS transistor depending on the gate voltage of the MOS transistor. The gate voltage of the MOS transistor may correspond to a voltage stored in a capacitor. However, certain leakage currents may cause the voltage stored in a capacitor to vary, which causes the current supplied by the current source to vary over time. It may be necessary to provide a refresh circuit which may be complex in order to frequently refresh the voltage across the capacitor. Summary of the invention

[0006] An object of an embodiment is to provide a display pixel comprising light emitting diodes and a display screen comprising such display pixels which overcome some or all of the disadvantages of existing display pixels comprising light emitting diodes and display screens comprising such display pixels.

[0007] An embodiment provides a display pixel comprising at least one light-emitting device, a controllable current source supplying said light-emitting device with current, and a driver circuit configured to activate or deactivate the controllable current source, and to receive bits of a digital color signal, said digital color signal comprising a number NB of bits each having a rank ranging from the least significant bit of the digital color signal to the most significant bit of the digital color signal, each bit of the digital color signal having a first logic value or a second logic value, said driver circuit being configured to receive at least some of said NB bits in a first order and then in a second order, different from the first order, said driver circuit being configured, for each bit received, to light the controllable current source when said bit is at the first logic value for a duration which depends on the rank of said bit or to switch off the controllable current source for said duration when said bit is at the second logic value, said durations increasing from the least significant bit to the most significant bit. This advantageously makes it possible to reduce the differential non-linearity of the display pixel. In addition, there may advantageously not be any sudden variations in the evolution of the current relative to the value of the digital color signal.

[0008] According to one embodiment, said pilot circuit is configured to receive at least some of said NB bits in the first order according to the decreasing ranks of the bits and in the second order according to the increasing ranks of the bits, or vice versa. This advantageously makes it possible to reduce the risk of the occurrence of the phenomenon of false dynamic contours.

[0009] According to one embodiment, said pilot circuit is configured to receive at least some of these NB bits in the first order comprising successive first, second and third bits, the rank of the second bit being higher than the rank of the first bit and the rank of the third bit, or the rank of the second bit being lower than the rank of the first bit and the rank of the third bit.

[0010] According to one embodiment, said pilot circuit is configured, after receiving said bits in the second order, to then receive said bits in a third order, then in a fourth order, different from the third order. This advantageously makes it possible to reduce the phenomena of false dynamic contours.

[0011] According to one embodiment, the third order is identical to the first order and the fourth order is identical to the second order, or the third order is identical to the second order and the fourth order is identical to the first order.

[0012] According to one embodiment, the controllable current source comprises a switch in series with a constant current source, the driver circuit being configured, for each bit received, to activate said switch for said duration when said bit is at the first logic value or to deactivate said switch for said duration when said bit is at the second logic value.

[0013] According to one embodiment, the constant current source comprises a MOS transistor and a capacitor, said MOS transistor having its drain or its source connected to said switch and said capacitor having an electrode connected to the gate of said MOS transistor.

[0014] According to one embodiment, the display pixel further comprises a storage circuit configured to store said digital color signal and to provide the driver circuit with at least some of said NB bits in the first order, then in the second order. Advantageously, it is not necessary to have a complex refresh circuit to refresh the storage circuit.

[0015] According to one embodiment, the storage circuit comprises NB memory cells DFFi, i varying from 0 to NB-1, for storing the bits of the digital color signal, where each memory cell DFF; is a flip-flop clocked by a synchronization signal. The structure of the storage circuit is advantageously simplified.

[0016] According to one embodiment, the storage circuit comprises NB first multiplexers MUXi, i being in the range from 0 to NB-1, each being controlled by a control signal, each first multiplexer MUX;, i being in the range from 1 to NB-2, comprising a first input connected to the output of the memory cell DFF, h a second input connected to the output of the memory cell DFF i+i and an output connected to the input of the memory cell DFF;, in which each first multiplexer MUX;, i being between 1 and NB-2, is configured to send to its output the signal provided by the memory cell DFFi4 when the control signal is at a first logic value, and to send to its output the signal provided by the memory cell DFFi+i when the control signal is at a second logic value, in which the first multiplexer MUXNB.i comprises a first input connected to the output of the memory cell DFFNB 2, a second input connected to the output of the memory cell DFF0 and an output connected to the input of the memory cell DFFNB i, in which the first multiplexer MUXxh । is configured to send to its output the signal provided by the memory cell DFFNB 2 when the control signal is at the first logic value, and to send to its output the signal provided by the memory cell DFF0 when the control signal is at the second logic value, in which the first multiplexer MUX0 comprises a first input connected to the output of the memory cell DFFNB.i, a second input connected to the output of the memory cell DFFi and in which the first multiplexer MUX0 is configured to send to its output the signal provided by the memory cell DFFNB1 when the control signal is at the first logic value, and to send to its output the signal provided by the memory cell DFFi when the control signal is at the second logic value.

[0017] According to one embodiment, the storage circuit comprises a second multiplexer, controlled by the control signal and comprising a first input connected to the output of the memory cell DFFXH H, a second input connected to the output of the memory cell, and an output providing said bits to the driver circuit, the second multiplexer being configured to send to its output the signal provided by the memory cell DFFNB i when the control signal is at the first logic value, and to send to its output the signal provided by the memory cell DFF0 when the control signal is at the second logic value.

[0018] According to one embodiment, said storage circuit is configured to provide the driver circuit with all the bits of the digital color signal in the first order, then in the second order, except that the least significant bit of the digital color signal is provided only once. It may be advantageous for the least significant bit displayed for the shortest duration to be displayed only once, when it may be difficult to generate successive pulses to provide the two successive shortest durations, for example due to latencies in the operation of the display screen.

[0019] Another embodiment provides a display screen comprising: display pixels as defined above; first electrodes connected to the display pixels; a first circuit for outputting a selection signal to each first electrode for selecting the display pixels connected to the first electrode; second electrodes connected to the display pixels; and a second circuit for delivering data signals to the second electrodes.

[0020] Another embodiment provides a method for controlling a display pixel comprising at least one light-emitting device, a controllable current source supplying said light-emitting device with a current, a driver circuit configured to activate or deactivate the controllable current source, and to receive bits of a digital color signal, said digital color signal comprising a number NB of bits each having a rank ranging from the least significant bit of the digital color signal to the most significant bit of the digital color signal, each bit of the digital color signal having a first logic value or a second logic value, the method comprising the steps of providing the driver circuit with at least some of these NB bits in a first order, then in a second order, different from the first order, and causing said driver circuit, for each bit received,to activate the controllable current source when said bit is at the first logical value for a duration which depends on the rank of said bit or to deactivate the controllable current source for said duration when said bit is at the second logical value, said durations increasing from the least significant bit to the most significant bit.

[0021] According to one embodiment, the display pixel further comprises a storage circuit configured to store said digital color signal, the method comprising the step of causing said storage circuit to provide the driver circuit with at least some of said NB bits in the first order, then in the second order.

[0022] According to one embodiment, the controllable current source comprises a switch in series with a constant current source and the constant current source comprises a MOS transistor and a capacitor. Refreshing the voltage at capacitor terminals is prevented while the storage circuit provides the driver circuit with at least some of said NB bits in the first order and then in the second order. Since the refreshing of the voltage across the capacitor does not have to be done frequently, especially during the display phase, the structure of a refresh circuit that refreshes the voltage across the capacitor can advantageously be simple. Brief description of the drawings

[0023] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0024] [Fig.l] partially and schematically illustrates an embodiment of a display screen;

[0025] [Fig.2] shows an example of a block diagram of a display pixel of the display screen of [Fig.l];

[0026] [Fig.3] shows examples of timing diagrams of a signal used by the display pixel of [Fig.2] to control a light-emitting diode by pulse width modulation and the current supplied to the light-emitting diode;

[0027] [Fig.4] shows an example of a controllable current source of the display pixel of [Fig.2];

[0028] [Fig.5] shows the evolution of the current supplied by the controllable current source of [Fig.4] with a first configuration of leakage currents;

[0029] [Fig.6] shows the evolution of the differential non-linearity of the display pixel with the evolution of the current illustrated in [Fig.5] as a function of the color signal to be displayed;

[0030] [Fig.7] shows the evolution of the brightness of the display pixel with the evolution of the current illustrated in [Fig.5] as a function of the color signal to be displayed;

[0031] [Fig.8] shows the evolution of the current supplied by a controllable current source of [Fig.4] with a second configuration of leakage currents;

[0032] [Fig.9] shows the evolution of the differential non-linearity of the display pixel with the evolution of the current illustrated in [Fig.8] as a function of the color signal to be displayed;

[0033] [Fig. 10] shows the evolution of the brightness of the display pixel with the evolution of the current illustrated in [Fig.8] as a function of the color signal to be displayed;

[0034] [Fig.l 1] illustrates the successive display of two image pixels corresponding to successive gray levels;

[0035] [Fig. 12] shows the evolution of the lighting period over time for the display of the image pixels illustrated in [Fig.l 1];

[0036] [Fig. 13] illustrates a method of determining the ignition period during a frame in time;

[0037] [Fig. 14] shows a block diagram of an exemplary storage circuit of the display pixel of [Fig.2];

[0038] [Fig. 15] shows a block diagram of an exemplary refresh circuit for the display pixel of [Fig.2];

[0039] [Fig. 16] shows the evolution of the current supplied by the controllable current source of [Fig.4] with the first configuration of the leakage currents according to an embodiment of operation of the display pixel;

[0040] [Fig. 17] shows the evolution of the differential non-linearity of the display pixel with the evolution of the current illustrated in [Fig. 16] as a function of the color signal to be displayed;

[0041] [Fig. 18] shows the evolution of the brightness of the display pixel with the evolution of the current illustrated in [Fig. 16] as a function of the color signal to be displayed;

[0042] [Fig. 19] shows the evolution of the current supplied by the controllable current source of [Fig. 4] with the second leakage current configuration according to an embodiment of operation of the display pixel;

[0043] [Fig.20] shows the evolution of the differential non-linearity of the display pixel with the evolution of the current illustrated in [Fig. 19] as a function of the color signal to be displayed;

[0044] [Fig.21] shows the evolution of the brightness of the display pixel with the evolution of the current illustrated in [Fig. 19] as a function of the color signal to be displayed;

[0045] [Fig.22] illustrates an embodiment of operation of the display pixel for the successive display of two image pixels corresponding to successive gray levels;

[0046] [Fig.23] shows the evolution of the lighting period over time for the display of the image pixels represented in [Fig.22];

[0047] [Fig.24] illustrates another embodiment of operation of the display pixel for the successive display of two image pixels corresponding to successive gray levels;

[0048] [Fig.25] shows the evolution of the lighting period over time for the display of the image pixels illustrated in [Fig.24];

[0049] [Fig.26] illustrates modes of operation of the display pixel for displaying an image pixel;

[0050] [Fig.27] illustrates other embodiments of operation of the display pixel for displaying an image pixel; and

[0051] [Fig.28] shows a block diagram of an exemplary embodiment of the storage circuit of the display pixel of [Fig.2]. Description of the embodiments

[0052] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0053] Furthermore, a signal that alternates between a first constant state, for example a low logic state, denoted "0", and a second constant state, for example a high logic state, denoted "1", is called a "binary signal". The high and low states of the different binary signals of the same electronic circuit may be different. In practice, the binary signals may correspond to voltages or currents that may not be perfectly constant in the high or low state.

[0054] Furthermore, unless otherwise indicated, when a voltage is mentioned at a conductive pad, the difference between the potential at said conductive pad and a reference potential, for example ground, is considered to be equal to 0 V.

[0055] Furthermore, the "power terminals" of a metal-oxide-semiconductor field-effect transistor, also called a MOS transistor, refer to the source and drain of the MOS transistor.

[0056] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean within 10%, preferably within 5%. In addition, the expression "substantially constant" means that it varies by less than 10% over time compared to a reference value.

[0057] A light-emitting diode is said to be three-dimensional when it comprises a three-dimensional semiconductor element of micrometric or nanometric size extending in a preferred direction, for example a microwire or a nanowire, covered with an active zone. In particular, a three-dimensional light-emitting diode is said to be of the radial type when its active zone extends at least over the side walls of the three-dimensional semiconductor element.

[0058] [Fig. 1] partially and schematically illustrates an embodiment of a display screen 10. The display screen 10 comprises display pixels 12^, for example, arranged in M ​​rows and N columns, M being an integer varying from 1 to 8,000 and N being an integer varying from 1 to 16,000, i being an integer varying from 1 to M, and j being an integer varying from 1 to N. For example, in [Fig.l], M and N are equal to 6. Each display pixel l^ is connected to a source of low reference potential Gnd, for example ground, via an electrode 14; and to a source of high reference potential Vcc via of an electrode 16j. For example, the electrodes 14; are shown as being aligned along the rows of [Fig.l] and the electrodes 16j are shown as being aligned along the columns of [Fig.l], the reverse arrangement being possible. The supply voltage of the display screen corresponds to the voltage between the high reference potential Vcc and the low reference potential Gnd, and is denoted Vcc as the high reference potential. The supply voltage Vcc depends in particular on the arrangement of the light-emitting diodes and the technology by which the light-emitting diodes are manufactured. For example, the supply voltage Vcc can be of the order of 3.5 V to 5.5 V.

[0059] For each row, the display pixels 1¾ of the row are connected to a row electrode 18;. For each column, the display pixels 1¾ of the column are connected to a column electrode 20j. The display screen 10 comprises a selection circuit 22 connected to the row electrodes 18; and adapted to deliver a selection signal Com; on each row electrode 18;. The display screen 10 comprises a data transmission circuit 24 connected to the column electrodes 20j and adapted to transmit a data signal Dataj on each column electrode 20j. The selection circuit 22 and the control circuit 24 are controlled by a circuit 26, comprising for example a microprocessor.

[0060] [Fig. 2] shows an example of a block diagram of a display pixel 12;,j of the display screen 10. For a color display screen, the display pixel 12;,j comprises at least three light-emitting circuits emitting radiation of different colors. Each light-emitting circuit comprises at least one light-emitting diode LED connected in series to a controllable current source CS, only one light-emitting circuit being illustrated in [Fig. 2]. Each light-emitting diode LED is connected in series to a controllable current source CS, comprising for example a MOS transistor in series with a current source providing a constant current.In the present example, for each light-emitting diode LED, the anode of the light-emitting diode LED receives a high reference potential Vcc and the cathode of the light-emitting diode LED is for example connected to one terminal of the controllable current source CS, the other terminal of the controllable current source CS receiving a low reference potential Gnd. In the case of a monochromatic display screen, each display pixel 1¾ may comprise a light-emitting circuit comprising a single light-emitting diode LED.

[0061] The display pixel 12;j further comprises a driver circuit 40 for driving the controllable current source CS. The driver circuit 40 may in particular comprise electronic components such as MOS transistors. The driver circuit 40 comprises a storage circuit 48 (Color Data registers) clocked by a clock signal Clk configured to store digital color signals R, G, B based on the received digital signal Data. The digital color signals R, G, B each comprise a number NB of bits, ranging from the most significant bit, called MSB, to the least significant bit, called LSB, and are representative of the color components of the image pixels to be displayed. The driver circuit 40 comprises a circuit 50 (LED driver) configured to control the controllable current sources CS connected to the light-emitting diodes LED with signals I_red, I_green and I_blue, obtained from the digital color signals R, G, B, and a PWM signal. The signal Data may correspond to the signal Dataj transmitted to the display pixel 1¾ on the column electrode 20j during a writing phase. The PWM signal may correspond to the selection and synchronization signal Com; transmitted to the display pixel 1¾ on the row electrode 18; during a display phase.

[0062] [Fig. 3] shows timing diagrams of the PWM signal and the signals I_red_l, I_red_2, I_red_3 and I_red_4 corresponding to the signal I_red supplied by the circuit 50 of the display pixel 1¾ of [Fig. 2] for the display of four different digital color signals R. According to one embodiment, the light-emitting diodes LED of the display pixel 12ij are controlled by pulse width modulation. For this purpose, during a display cycle, the PWM signal has a succession of pulses P in the logic state "1" which sets the rhythm for the operation of the circuit 50 for controlling the light-emitting diodes LED by pulse width modulation. The number of pulses P in the succession of pulses can correspond to the number NB+1. Each pair of successive pulses P delimits a duration Di, i being in the range from NB-1 to 0.

[0063] For example, when the current source CS corresponds to a current source providing a constant current in series with a switch, the switch is closed or open depending on the logic value "0" or "1" of each bit of the digital color signal R, G or B, from the most significant bit MSB to the least significant bit LSB, at the rate of the pulses P of the PWM signal, the switch being kept open or closed until the next pulse P of the PWM signal. Consequently, the controllable current source CS is activated or deactivated for NB successive durations Di depending on the logic values ​​of the bits of the digital color signal R, G or B.For example, the current source CS can be activated for a duration Di when the bit of the digital color data R, G or B associated with this time interval is at the logic value "1" and can be deactivated for a duration Di when the bit of the digital color data R, G or B associated with this time interval is at the logic value "0".

[0064] In a display cycle, the duration Di, i being in the range from NB-1 to 0, between two successive pulses P of the PWM signal is divided each time by two, so that the total time the LED is lit depends on the value of the digital color signal R, G or B. The display phase of an image pixel may comprise two or more display cycles. That is, the succession of pulses P of the PWM signal illustrated in [Fig.3] may be repeated until another image pixel is displayed.

[0065] In [Fig.3], as an example, the number NB is equal to 7 and only one display cycle is shown. The signal I_red_l is obtained for displaying an image pixel color component corresponding to the color signal R equal to "1010101". The signal I_red_2 is obtained for displaying an image pixel color component corresponding to the color signal R equal to "0101010". The signal I_red_3 is obtained for displaying an image pixel color component corresponding to the color signal R equal to "1111111". The signal I_red_4 is obtained for displaying an image pixel color component corresponding to the color signal R equal to "0000000".

[0066] [Fig.4] shows a block diagram of an example of a controllable current source CS of the display pixel 1¾ of [Fig.2]. In the present example, for each light-emitting diode LED, the anode of the light-emitting diode LED receives a high reference potential Vcc, and the cathode of the light-emitting diode LED is for example connected to one terminal of the controllable current source CS, the other terminal of the controllable current source CS receiving a low reference potential Gnd. In a variant, the cathode of the light-emitting diode LED receives a low reference potential Gnd and the anode of the light-emitting diode LED is connected to one terminal of the controllable current source CS, the other terminal of the controllable current source CS receiving a high reference potential Vcc.As an example, the controllable current source CS comprises a switch SW 1 which is connected in series to a transistor TL. The display pixel 1¾ further comprises a capacitor C for adjusting the voltage at the gate of the transistor TL. The capacitor C has a first electrode connected, preferably connected, to the gate of the transistor Tl, and a second electrode receiving a low reference potential Gnd. The voltage at the gate of the transistor Tl may correspond to the voltage across the capacitor C. The switch SW1 is controlled by the signals I_red (or I_green or I_blue). The current ICs flowing through the light-emitting diode LED corresponds to the current at the drain of the transistor TL.

[0067] In operation, there may be current leaks at the capacitor C. In [Fig.4], the possible current leaks are represented by a first constant current source L1 and a second constant current source L2. The first constant current source Lia has a first terminal receiving the high reference potential Vcc and a second terminal connected to the first electrode of the capacitor C. The first constant current source L1 supplies a current L1 to the first electrode of capacitor C. The second constant current source L2 has a first terminal connected to the first electrode of capacitor C and a second terminal connected to the second electrode of capacitor C. The second constant current source L2 draws a current L2 from the first electrode of capacitor C.

[0068] [Fig.5] shows the evolution of the current ICs over time during a display phase DP in a first configuration of the leakage currents and the durations D5 to DO of the successive values ​​of the signal I_red, a single display cycle being represented. The duration D5 is associated with the MSB of the digital color data R to be displayed and the duration DO is associated with the LSB of the digital color data R to be displayed. In the first configuration, the intensity of the leakage current L1 is lower than the intensity of the leakage current L2, so that the voltage across the capacitor C decreases with time. For example, the current ICs decreases from 30 pA to 20 pA during the display phase. For example, the number NB is equal to 6. The digital color signal R can take 64 different values.

[0069] [Fig.6] shows the evolution of the differential non-linearity DNL of the display pixel 1¾ with the evolution of the current ICs illustrated in [Fig.5] as a function of the value of the digital color signal R indicated in decimals. The differential non-linearity DNL describes the deviation between the two values ​​of the average current supplied to the light-emitting diode during a display phase corresponding to adjacent digital input values ​​of the digital color signal R. In the first configuration of the leakage currents, the DNL is greater than 1 bit at certain transitions between two adjacent digital input values, in particular when a high number of bits switches between the two adjacent digital input values, for example at the time of the transition between the adjacent digital input values ​​"011111" and "100000".

[0070] [Fig.7] shows the evolution of the brightness BR of the display pixel 1¾ with the evolution of the ICs current illustrated in [Fig.5] as a function of the value of the digital color signal R indicated in decimals. Ideally, the brightness BR should be proportional to the digital color signal R. However, [Fig.5] shows that the evolution of the brightness BR includes sudden and abrupt increases.

[0071] [Fig.8] shows the evolution of the current ICs over time during a display phase DP in a second configuration of the leakage currents and the durations D5 to D0 of the successive values ​​of the signal I_red, a single display cycle being represented. In the second configuration, the intensity of the leakage current L1 is greater than the intensity of the leakage current L2, so that the voltage across the capacitor C increases with time. For example, the current ICs increases from 20 pA to 30 pA during the display phase. In addition, [Fig.8] shows the signal I_red which is the same than that of [Fig.5].

[0072] [Fig.9] shows the evolution of the differential nonlinearity DNL of the display pixel 1¾ with the evolution of the current ICs shown in [Fig.8] as a function of the digital color signal R indicated in decimals. In the second configuration of the leakage currents, the DNL is less than -1 bit at certain transitions between two adjacent digital input values, in particular when a high number of bits switches between the two adjacent digital input values, for example at the time of the transition between the adjacent digital input values ​​"011111" and "100000".

[0073] [Fig. 10] shows the evolution of the brightness BR of the display pixel 1¾ with the evolution of the current ICs shown in [Fig.8] as a function of the digital color signal R indicated in decimals. The brightness evolution curve is not monotonous.

[0074] Digital driving displays can pose problems in rendering dynamic images. When displaying animated images, the human eye may perceive gray levels that do not actually exist at the edge of the gray levels. This type of defect in gray levels is called dynamic false edge (DFC) phenomenon. The dynamic false edge phenomenon is a kind of false visual perception that forms on the retina when observing animated images on digital driving displays. This does not exist on the image source itself.

[0075] [Fig. 11] shows a timing diagram of the signal I_red for two successive frames F1 and F2 during which two successive image pixels are displayed by the display pixel 1¾. Each frame F1, F2 successively comprises a writing phase WRT during which the data of the signal Data, are sent to the display pixel 12jj, a display phase DP during which the image pixel is displayed by the display pixel 12^, and a waiting extinction phase, until the end of the frame F1, F2, during which no image pixel is displayed by the display pixel 1¾. For example, the number NB of bits of the digital color signal R is equal to 6. The first color component of the image pixel corresponds to the digital color signal R equal to "10000" (gray level equal to "16") and the second color component of the image pixel corresponds to the digital color signal R equal to "01111" (gray level equal to "15").Each duration D4 to D0 represented in gray for each frame Fl and F2 corresponds to the closing of switch SW1 of the controllable current source CS and each duration D4 to D0 represented in white corresponds to the opening of switch SW 1 of the controllable current source CS.

[0076] The risk of occurrence of the dynamic false contour phenomenon is estimated using a criterion called the ignition period during a time period of a frame, as explained below. The risk of occurrence of the dynamic false contour phenomenon is reduced when the variations in the ignition period during of a time period of a frame are reduced.

[0077] [Fig. 12] shows the evolution of the TUP ignition period during a time period of one frame for displaying the image pixels illustrated in [Fig. 11]. The abscissa axis x corresponds to the position P of the sliding window, as explained below. A strong variation of the TUP ignition period can be measured.

[0078] [Fig. 13] illustrates a method for determining the TUP ignition period during a frame over time. First and second successive frames are considered. The first frame FRAME1 corresponds to the display of the first color component of the image pixel corresponding to the digital color signal R equal to "10000" (gray level equal to "16") and the second frame FRAME2 corresponds to the display of the second color component of the image pixel corresponding to the digital color signal R equal to "01111" (gray level equal to "15"). Each frame is divided into a number NF of steps, one step corresponding to a duration D0. In the example of [Fig. 13], NF is equal to 43. A sliding window is moved from the first frame to the second frame, one step at a time.For each position P of the sliding window, the lighting period TUP is determined equal to the number of steps in the sliding window for which the light-emitting diode LED is lit for the first and second frames.

[0079] [Fig. 14] shows a block diagram of an embodiment of the storage circuit 48 of the display pixel 1¾ of [Fig. 2] which makes it possible to obtain the display phase illustrated in figures 3, 5, 8 or 11.

[0080] The storage circuit 48 comprises memory cells DFF0 to DFFnb_i. Each memory cell DFF;, i being in the range from 0 to NB-1, is configured to store one bit of the digital color signal R, G or B. According to one embodiment, each memory cell DFF; corresponds to a flip-flop, for example a D flip-flop having a D input and a Q output, clocked by a Clk or PWM signal depending on the operating phase of the display pixel. For each memory cell DFF;, i being in the range from 0 to NB-2, the Q output of the memory cell DFF; is connected to the D input of the memory cell DFFi+i. The Q output of the memory cell DFFNB i provides the signal I_red. The storage circuit 48 further comprises a multiplexer MUX controlled by a Mode signal. The MUX multiplexer includes a first input "0" receiving the Data signal, a second input "1" connected to the Q output of the DFFnb memory cell.i, and an output connected to the D input of the DFF0 memory cell. When the Mode signal is at a first logic value, for example "0", the MUX multiplexer sends the Data signal to its output. When the Mode signal is at a second logic value, for example "1", the MUX multiplexer sends the signal provided by the DFF.NB i memory cell to its output.

[0081] During a write phase, the Mode signal is at the logic value "0" and the cells of memory cells DFF;, i being in the range from 0 to NB-1, are clocked by the signal Clk. The signal Data corresponds to the bits of the digital color signal R which are successively supplied, from the most significant bit to the least significant bit, to the multiplexer MUX, and which progress in the succession of memory cells DFFi, i being in the range from 0 to NB-1, so that, at the end of the writing phase, the most significant bit is stored in the memory cell DFFNB i and the least significant bit is stored in the memory cell DFF0.

[0082] During a display phase, the Mode signal is set to the logic value "1" and the memory cells DFF;, i being in the range from 0 to NB-1, are clocked by the PWM signal. The multiplexer MUX provides at its output the signal provided by the memory cell DFFNB b. Consequently, the signal I_red is successively equal to each bit of the digital color signal R, from the most significant bit to the least significant bit.

[0083] It would be desirable to overcome the disadvantages of existing display pixels explained previously with respect to DNL and DFC, while retaining a display pixel provided with a storage circuit comprising memory cells corresponding to flip-flops.

[0084] In order to prevent the voltage across capacitor C from varying, it may be necessary to provide a refresh circuit which refreshes the voltage across capacitor C.

[0085] [Fig. 15] shows a block diagram of an embodiment of a refresh circuit 60 of the display pixel 1¾ of [Fig. 2], configured to refresh the voltage across the capacitor C. The refresh circuit 60 comprises a resistor R in series with a switch SW2 controlled by a binary signal Rsh. The signal Rsh is provided by a refresh control circuit 62. The refresh circuit 60 further comprises a current mirror comprising MOS transistors T2 and T3, for example PMOS transistors. The sources of the transistors T2 and T3 receive a high reference voltage Vcc. The drain of the transistor T2 is connected, preferably connected, to one terminal of the resistor R. The other terminal of the resistor R is connected, preferably connected, to a terminal of the switch SW2. The other terminal of the switch SW2 receives the low voltage reference Gnd.The gate of transistor T2 is connected, preferably connected, to the gate of transistor T3 and to the drain of transistor T2. The refresh circuit 60 further comprises a MOS transistor T4, for example an NMOS transistor. The drain of transistor T4 is connected, preferably connected, to the drain of transistor T3. The source of transistor T4 receives the low voltage reference Gnd. The gate of transistor T4 is connected to the drain of transistor T4. The refresh circuit 60 further comprises a switch SW3 controlled by the signal Rsh. A terminal of the switch . SW3 is connected, preferably connected, to the gate of transistor T4. The other terminal of switch SW3 is connected, preferably connected, to the first electrode of capacitor C. The size ratio between transistor T2 and transistor T3 is 1:n. The size ratio between transistor T1 and transistor T4 is 1:m.

[0086] The refresh control circuit 62 can be complex when a refresh of the voltage across the capacitor C must be carried out frequently, in particular during the display phase.

[0087] According to one embodiment, the display phase of an image pixel comprises at least a first display cycle and a second display cycle and the order of the bits of the digital color signal R, G or B which are displayed in the first display cycle is different from the order of the bits of the digital color signal R, G or B which are displayed in the second display cycle. This means that for a digital color signal R, G or B comprising NB bits, each bit of rank i being associated with a duration Di, i being in the range from NB-1 to 0, the order of the successive durations Di during which the controllable current source CS is activated or deactivated in the first display cycle is different from the order of the successive durations Di during which the controllable current source CS is activated or deactivated in the second display cycle.

[0088] According to an embodiment illustrated by [Fig. 16] described below, the order of the durations Di in the first display cycle is reversed with respect to the order of the durations Di in the second display cycle, with the possible exception of the duration at the end of the first display cycle which may not be repeated at the beginning of the second display cycle. This means that the first duration of the first display cycle is the last duration of the second display cycle, the second duration of the first display cycle is the penultimate duration of the second display cycle, and so on. The last duration of the first display cycle may be the first duration of the second display cycle, or the last duration of the first display cycle is not present in the second display cycle and the first duration of the second display cycle is the penultimate duration of the first display cycle.

[0089] [Fig. 16] shows the evolution of the current ICs over time in the first leakage current configuration (leakage current L1 greater than leakage current L2) and the durations of the successive values ​​of the signal I_red with a display phase DP of an image pixel comprising successive first and second display cycles C1 and C2, the order of the bits of the digital color signal R displayed in the first display cycle C1 being the inverse of the order of the bits of the digital color signal R displayed in the second display cycle C2. According to one embodiment, in the first display cycle C1, the switch SW 1 of the controllable current source CS is controlled by the bits of the digital color signal R successfully- sively from the most significant bit to the least significant bit and, in the second display cycle C2, the switch SW 1 of the controllable current source CS is controlled by the bits of the digital color signal R successively from the least significant bit to the most significant bit. In the present embodiment, the least significant bit LSB is displayed once at the end of the first display cycle and once at the beginning of the second display cycle. Alternatively, the least significant bit may be displayed only once at the end of the first display cycle, the second display cycle starting with the bit following the least significant bit (LSB+1).

[0090] [Fig. 17] shows the evolution of the differential nonlinearity DNL of the pixel display 1¾ with the evolution of the current ICs illustrated in [Fig. 16] as a function of the value of the digital color signal R indicated in decimals. The differential non-linearity DNL is equal to zero for each value of the digital color signal R.

[0091] [Fig. 18] shows the evolution of the brightness BR of the display pixel 1¾ with the evolution of the ICs current illustrated in [Fig. 16] as a function of the value of the R, G or B color signal indicated in decimals. The BR brightness is proportional to the value of the R, G or B color signal. There are no sudden variations.

[0092] [Fig. 19] shows the evolution of the ICs current over time during a phase display in the second configuration (leakage current L1 lower than leakage current L2) and the durations of the successive values ​​of the I_red signal with a display phase identical to that of [Fig. 16].

[0093] [Fig.20] shows the evolution of the differential nonlinearity DNL of the pixel display 1¾ with the evolution of the current ICs illustrated in [Fig. 18] as a function of the value of the digital color signal R indicated in decimals. The differential non-linearity DNL is equal to zero for each value of the digital color signal R.

[0094] [Fig.21] shows the evolution of the brightness BR of the display pixel 1¾ with the evolution of the ICs current illustrated in [Fig. 19] as a function of the value of the R, G or B color signal indicated in decimals. The brightness BR is proportional to the value of the R, G or B color signal. There are no sudden variations.

[0095] The DNL is maintained at zero regardless of the type of leakage of capacitor C. There is no need to use a complex refresh circuit to update the voltage across capacitor C.

[0096] [Fig.22] is a figure similar to [Fig. 11] except that, for each frame Fl and F2, the display phase DP comprises two display cycles Cl and C2 according to the embodiment of figures 16 and 19, and except that the least significant bit displayed during the duration D0 is not displayed twice but only once. In particular, in the first display cycle Cl, the switch SW 1 of the controllable current source CS is controlled by the bits of the digital color signal R success- sively from the most significant bit during the duration D4 to the least significant bit during the duration DO and, in the second display cycle C2, the switch SW 1 of the controllable current source CS is controlled by the bits of the digital color signal R successively from the bit after the least significant bit during the duration DI to the most significant bit during the duration D4. It may be advantageous for the least significant bit displayed during the duration DO to be displayed only once, when it may be difficult to generate successive pulses to provide the two successive durations DO, for example due to latencies in the operation of the display screen.

[0097] [Fig.23] shows the evolution of the TUP ignition period over time for the display of the image pixels illustrated in [Fig.22]. The units of the time axis are arbitrary. The extrema of the TUP ignition period illustrated in [Fig.23] are reduced compared to the TUP ignition period illustrated in [Fig. 12]. The risk of the occurrence of the dynamic false contour phenomenon is therefore advantageously reduced.

[0098] [Fig. 24] is a figure similar to [Fig. 22] except that, for each frame F1 and F2, the display phase DP comprises four display cycles C1, C2, C3 and C4. According to one embodiment, in the first display cycle C1, the switch SW 1 of the controllable current source CS is controlled by the bits of the digital color signal R successively from the most significant bit during the duration D4 to the bit following the least significant bit during the duration DI. In the second display cycle C2, the switch SW 1 of the controllable current source CS is controlled by the bits of the digital color signal R successively from the second bit after the least significant bit during the duration D2 to the most significant bit during the duration D4, then by the least significant bit during DO.The third display cycle C3 is identical to the first display cycle Cl and the fourth display cycle C4 is identical to the second display cycle C2.

[0099] [Fig.25] shows the curve of the evolution of the TUP ignition period over time for the display of the image pixels illustrated in [Fig.24]. The extrema of the TUP ignition period illustrated in [Fig.25] are reduced compared to the TUP ignition period illustrated in [Fig.25]. The risk of the occurrence of the false dynamic contour phenomenon is therefore advantageously reduced.

[0100] [Fig.26] shows the durations of the successive values ​​of the signal I_red with a display phase of an image pixel comprising the first and second successive display cycles Cl and C2 according to three embodiments.

[0101] In the upper timing diagram, in the first display cycle Cl, the switch SW 1 of the controllable current source CS is controlled by the bits of the digital color signal R successively from the least significant bit during the duration D0 to the most significant bit during the duration D4 and, in the second display cycle C2, the switch SW 1 of the controllable current source CS is controlled by the bits of the digital color signal R successively from the most significant bit during the duration D4 to the least significant bit during the duration DO. The display phase is followed by a waiting extinction phase.

[0102] In the embodiments described above, the standby extinction phase follows the display phase. However, when the display phase comprises at least two display cycles, a standby extinction phase may be provided after each display cycle of the display phase.

[0103] In the central timing diagram, in the first display cycle C1, the switch SW 1 of the controllable current source CS is controlled by the bits of the digital color signal R successively from the least significant bit during the duration DO to the most significant bit during the duration D4, the first display cycle C1 being followed by a waiting extinction phase, and, in the second display cycle C2, the switch SW 1 of the controllable current source CS is controlled by the bits of the digital color signal R successively from the most significant bit during the duration D4 to the least significant bit followed during the duration DO, the second display cycle C2 being followed by a waiting extinction phase.

[0104] In the lower timing diagram, in the first display cycle C1, the switch SW 1 of the controllable current source CS is controlled by the bits of the digital color signal R successively from the most significant bit during the duration D4 to the least significant bit during the duration D0, the first display cycle C1 being followed by a waiting extinction phase and, in the second display cycle C2, the switch SW 1 of the controllable current source CS is controlled by the bits of the digital color signal R successively from the least significant bit during the duration D0 to the most significant bit during the duration D4, the second display cycle C2 being followed by a waiting extinction phase.

[0105] [Fig.27] shows four examples of timing diagrams of the I_red signal of a phase display comprising the first, second, third and fourth display cycles C1, C2, C3 and C4 according to four embodiments.

[0106] In the uppermost timing diagram, in the first display cycle C1, the switch SW 1 of the controllable current source CS is controlled by the bits of the digital color signal R successively from the most significant bit during the duration D4 to the least significant bit during the duration D0, in the second display cycle C2, the switch SW 1 of the controllable current source CS is controlled by the bits of the digital color signal R successively from the least significant bit during the duration D0 to the most significant bit significant during the duration D4, the third display cycle C3 being identical to the first display cycle Cl, and the fourth display cycle C4 being identical to the second display cycle C2.

[0107] In the upper middle timing diagram, in the first display cycle C1, the switch SW 1 of the controllable current source CS is controlled by the bits of the digital color signal R successively from the least significant bit during the duration DO to the most significant bit during the duration D4, in the second display cycle C2, the switch SW 1 of the controllable current source CS is controlled by the bits of the digital color signal R successively from the most significant bit during the duration D4 to the least significant bit during the duration DO, the third display cycle C3 being identical to the first display cycle C1, and the fourth display cycle C4 being identical to the second display cycle C2.

[0108] In the lower middle timing diagram, in the first display cycle C1, the switch SW 1 of the controllable current source CS is controlled by the bits of the digital color signal R successively from the most significant bit during the duration D4 to the least significant bit during the duration DO, in the second display cycle C2, the switch SW 1 of the controllable current source CS is controlled by the bits of the digital color signal R successively from the least significant bit during the duration DO to the most significant bit during the duration D4, the third display cycle C3 being identical to the second display cycle C2, and the fourth display cycle C4 being identical to the first display cycle C1.

[0109] In the lowest timing diagram, in the first display cycle C1, the switch SW 1 of the controllable current source CS is controlled by the bits of the digital color signal R successively from the least significant bit during the duration DO to the most significant bit during the duration D4, in the second display cycle C2, the switch SW 1 of the controllable current source CS is controlled by the bits of the digital color signal R successively from the most significant bit during the duration D4 to the least significant bit during the duration DO, the third display cycle C3 being identical to the second display cycle C2, and the fourth display cycle C4 being identical to the first display cycle C1.

[0110] [Fig.28] shows a block diagram of an embodiment of the storage circuit 48 of the display pixel 1¾ of [Fig.2] which makes it possible to obtain the display phase illustrated in [Fig. 16].

[0111] The storage circuit 48 comprises memory cells DFF0 to DFFNB b. Each memory cell DFF;, i being in the range from 0 to NB-1, is configured to store one bit of the digital color signal R, G or B. According to one embodiment, each memory cell DFF; corresponds to a flip-flop, for example a D flip-flop having a D input and a Q output, clocked by a Clk or PWM signal depending on the operating phase of the display pixel. The storage circuit 48 further comprises multiplexers MUX0 to MUXNB i controlled by a signal Dir. Each multiplexer MUX;, i being in the range from 1 to NB-2, comprises a first input "0" connected to the Q output of the memory cell DFF, H a second input "1" connected to the Q output of the memory cell DFFi+i and an output connected to the D input of the memory cell DFF;. When the signal Dir is at a first logic value, for example "0", the multiplexer MUX;, i being in the range from 1 to NB-2, sends to its output the signal provided by the memory cell DFFi4.When the signal Dir is at a second logic value, for example "1", the multiplexer MUX;, i being in the range from 1 to NB-2, sends to its output the signal provided by the memory cell DFFi+i. The multiplexer MUXNB.i comprises a first input "0" connected to the output Q of the memory cell DFFNB 2, a second input "1" connected to the output Q of the memory cell DFF0 and an output connected to the input D of the memory cell DFFNB.i. When the signal Dir is at the first logic value, for example "0", the multiplexer MUXxh । sends to its output the signal provided by the memory cell DFFNB 2. When the signal Dir is at the second logic value, for example "1", the multiplexer MUXxh । sends to its output the signal provided by the memory cell DFF0. The multiplexer MUX0 comprises a first input "0" connected to the output Q of the memory cell DFFNB i, a second input "1" connected to the output Q of the memory cell DFFi.When the signal Dir is at the first logic value, for example "0", the multiplexer MUX0 sends to its output the signal provided by the memory cell DFFNB b When the signal Dir is at the second logic value, for example "1", the multiplexer MUX0 sends to its output the signal provided by the memory cell DFFi. .

[0112] The storage circuit 48 further comprises a multiplexer MUXI controlled by a Mode signal. The multiplexer MUXI comprises a first input "0" receiving the Data signal, a second input "1" connected to the Q output of the multiplexer MUX0 and an output connected to the D input of the memory cell DFF0. When the Mode signal is at a first logic value, for example "0", the multiplexer MUXI sends the Data signal to its output. When the Mode signal is at a second logic value, for example "1", the multiplexer MUXI sends the signal supplied by the multiplexer MUX0 to its output. The storage circuit 48 further comprises a multiplexer MUXO controlled by the Dir signal. The multiplexer MUXO comprises a first input "0" connected to the Q output of the memory cell DFFNB i, a second input "1" connected to the Q output of the memory cell DFF0, and an output supplying the signal I_red. When the Dir signal is at the first logic value, for example "0", the MUXO multiplexer sends to its output the signal provided by the DFFnb_i memory cell. When the Dir signal is at the second logic value, for example "1", the MUXO multiplexer sends to its output the signal provided by the DFF.O memory cell

[0113] During a write phase, the signal Mode is at the logic value "0", the signal Dir is at the logic value "0", and the memory cells DFF;, i being in the range from 0 to NB-1, are clocked by the signal Clk. The signal Data corresponds to the bits of the digital color signal R which are successively supplied, from the most significant bit to the least significant bit, to the multiplexer MUXI. The bits supplied by the multiplexer MUXI move in the succession of memory cells DFF;, i being in the range from 0 to NB-1, so that, at the end of the write phase, the most significant bit is stored in the memory cell DFFNB i and the least significant bit is stored in the memory cell DFF0.

[0114] During a display phase, the signal Mode is set to the logic value "1" and the memory cells DFF;, i being in the range from 0 to NB-1, are clocked by the PWM signal. The multiplexer MUXI provides at its output the signal provided by the multiplexer MUXp In the first display cycle, the signal Dir is at the logic value "0", so that the multiplexer MUXO provides at its output the signal provided by the memory cell DFFNB b In addition, each multiplexer MUX;, i being in the range from 0 to NB-1, sends at its output the signal provided by the memory cell DFFm. Consequently, the signal I_red is successively equal to each bit of the digital color signal R, from the most significant bit to the least significant bit. In the second display cycle, the Dir signal is at logic value "1", so that the MUXO multiplexer provides at its output the signal provided by the DFF0 memory cell.Furthermore, each multiplexer MUX;, i being in the range from 0 to NB-2, sends to its output the signal provided by the memory cell DFFi+i. Therefore, the signal I_red is successively equal to each bit of the digital color signal R, from the least significant bit to the most significant bit.

[0115] The Mode and Dir signals can be generated by the driver circuit 40 on the basis of the synchronization signal Com; and the data signal Dataj. The storage circuit 48 illustrated in [Fig.28] advantageously has a structure comprising flip-flop memory cells DFF0 to DFFNB4, as for the storage circuit 48 illustrated in [Fig.14],

[0116] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0117] Finally, the practical implementation of the described embodiments and variants is at the scope of the person skilled in the art from the functional indications given above.

Claims

Demands

1. A display pixel (1¾) comprising at least one light-emitting device (LED), a controllable current source (CS) supplying said light-emitting device (LED) with current, and a driver circuit (50) configured to turn the controllable current source (CS) on or off, and to receive bits of a digital color signal (R, G, B), said digital color signal (R, G, B) comprising NB bits, each having a rank from the least significant bit of the digital color signal to the most significant bit of the digital color signal, each bit of the digital color signal having a first logic value or a second logic value, said driver circuit (50) being configured to receive at least some of said NB bits in a first order and then in a second order, different from the first order, said driver circuit (50) being configured, for each bit received,to activate the controllable current source (CS) when said bit is at the first logic value for a duration that depends on the position of said bit, or to deactivate the controllable current source (CS) for said duration when said bit is at the second logic value, said durations increasing from the least significant bit to the most significant bit.

2. Display pixel according to claim 1, wherein said driver circuit (50) is configured to receive at least some of said NB bits in the first order according to the descending rank of the bits and in the second order according to the ascending rank of the bits, or vice versa.

3. Display pixel according to claim 1 or 2, wherein said driver circuit (50) is configured to receive at least some of said NB bits in the first order comprising successive first, second and third bits, the rank of the second bit being greater than the rank of the first bit and the rank of the third bit, or the rank of the second bit being less than the rank of the first bit and the rank of the third bit.

4. Display pixel according to any one of claims 1 to 3, wherein said driver circuit (50) is configured, after receiving said bits in the second order, to then receive said bits in a third order, and then in a fourth order, different from the third order.

5. Display pixel according to claim 4, wherein the third order is identical to the first order and the fourth order is identical to the second order, or wherein the third order is identical to the second order and the fourth order is identical to the first order.

6. Display pixel according to any one of claims 1 to 5, wherein the controllable current source (CS) comprises a switch (SW1) in series with a constant current source (T1), the driver circuit (50) being configured, for each received bit, to conduct said switch (SW1) for said duration when said bit is at the first logic value or to open said switch (SW1) for said duration when said bit is at the second logic value.

7. Display pixel according to claim 6, wherein the constant current source (Tl) comprises a MOS transistor (Tl) and a capacitor (Cl), said MOS transistor (Tl) having its drain or source connected to said switch (SW1) and said capacitor (Cl) having an electrode connected to the gate of said MOS transistor (Tl).

8. Display pixel according to any one of claims 1 to 7, further comprising a storage circuit (48) configured to store said digital color signal (R, G, B) and to provide the driver circuit (50) at least some of said NB bits in the first order and then in the second order.

9. Display pixel according to claim 8, wherein the storage circuit (48) comprises NB memory cells DFF;, i varying from 0 to NB-1, for storing the bits of the digital color signal (R, G, B), wherein each memory cell DFF; is a flip-flop clocked by a synchronization signal (CLK, PWM).

10. Display pixel according to claim 9, wherein the storage circuit (48) comprises NB first multiplexers MUX;, i in the range from 0 to NB-1, each being controlled by a control signal (Dir), each first multiplexer MUXi, i being in the range from 1 to NB-2, comprising a first input connected to the output of the memory cell DFF, H a second input connected to the output of the memory cell DFFi+i and an output connected to the input of the memory cell DFF;, wherein each first multiplexer MUX i, i being in the range from 1 to NB-2, is configured to send to its output the signal provided by the memory cell DFF, when the control signal (Dir) is at a first logic value, and to send to its output the signal provided by the memory cell DFFi+i when the control signal (Dir) is at a second logic value, wherein the first multiplexer MUXNB i includes a first input connected to the output of the memory cell DFFNB 2, a second input; connected to the output of memory cell DFF0 and an output connected to the input of memory cell DFFNB i, in which the first multiplexer MUXNB-i is configured to send to its output the signal provided by memory cell DFFNB 2 when the control signal (Dir) is at the first logic value, and to send to its output the signal provided by memory cell DFF0 when the control signal (Dir) is at the second logic value, in which the first multiplexer MUX0 includes a first input connected to the output of memory cell DFFNB.i, a second input connected to the output of memory cell DFFi and in which the first multiplexer MUX0 is configured to send to its output the signal provided by memory cell DFFNB i when the control signal (Dir) is at the first logic value, and to send to its output the signal provided by memory cell DFFi when the control signal (Dir) is at the second logic value.

11. Display pixel according to claim 10, wherein the storage circuit (48) comprises a second multiplexer (MUXO), controlled by the control signal (Dir) and comprising a first input connected to the output of the memory cell DFFNB i, a second input connected to the output of the memory cell, and an output providing said bits to the driver circuit (50), the second multiplexer (MUXO) being configured to send to its output the signal provided by the memory cell DFFNB i when the control signal (Dir) is at the first logic value, and to send to its output the signal provided by the memory cell DFF0 when the control signal (Dir) is at the second logic value.

12. Display pixel according to any one of claims 1 to 11, wherein said storage circuit (48) is configured to provide the driver circuit (50) with all the bits of the digital color signal in the first order and then in the second order, except for the least significant bit of the digital color signal which is provided only once.

13. Display screen (10) comprising: display pixels (1¾) according to any one of claims 1 to 10; first electrodes (180) connected to the display pixels (1¾); a first circuit (22) for delivering a selection signal (Com;) on each first electrode for selecting the display pixels (1¾) connected to the first electrode; second electrodes (20j) connected to the display pixels (1¾); and a second circuit (24) to deliver data signals (Dataj) on the second electrodes.

14. A method for controlling a display pixel (1¾) comprising at least one light-emitting device (LED), a controllable current source (CS) supplying said light-emitting device (LED) with current, a driver circuit (50) configured to turn the controllable current source (CS) on or off and to receive bits of a digital color signal (R, G, B), said digital color signal (R, G, B) comprising a number NB of bits, each having a rank from the least significant bit of the digital color signal to the most significant bit of the digital color signal, each bit of the digital color signal having a first logic value or a second logic value, the method comprising the steps of supplying the driver circuit (50) with at least some of said NB bits in a first order, and then in a second order, different from the first order, and of bringing said driver circuit (50), for each bit received,to activate the controllable current source (CS) when said bit is at the first logic value for a duration that depends on the position of said bit, or to deactivate the controllable current source (CS) for said duration when said bit is at the second logic value, said durations increasing from the least significant bit to the most significant bit.

15. A method according to claim 14, wherein the display pixel (1¾) further comprises a storage circuit (48) configured to store said digital color signal (R, G, B), the method comprising the step of causing said storage circuit (48) to supply the driver circuit (50) with at least some of said NB bits in the first order, and then in the second order.

16. A method according to claim 14 or 15, wherein the controllable current source (CS) comprises a switch (SW1) in series with a constant current source (Tl), wherein the constant current source (Tl) comprises a MOS transistor (Tl) and a capacitor (Cl), wherein the refresh of the voltage across the capacitor (Cl) is prevented while the storage circuit (48) supplies the driver circuit (50) with at least some of said NB bits in the first order and then in the second order.