WIRELESS CHARGING TRANSMITTER DEVICE

Abstract

According to one aspect, a wireless charge transmitter device is proposed comprising: - a generation circuit including at least one square wave processing circuit (ECRCT1, ECRT2) comprising: - a first switching circuit (PCOM) with PMOS-type transistors comprising a group of PMOS-type performance transistors (PMOSP) and at least one PMOS-type function transistor (PMOSF), - a second switching circuit (NCOM) with NMOS-type transistors comprising a group of connected NMOS-type performance transistors (NMOSP) and at least one NMOS-type function transistor (NMOSF). Figure for the abstract: Figure 3

Description

Title of the invention: WIRELESS CHARGING TRANSMITTER DEVICE

[0001] Embodiments relate to wireless charging circuits, including wireless charging using NFC (Near Field Communication) technology.

[0002] Wireless charging allows electronic devices to be charged without using a physical connection but from a magnetic field.

[0003] Wireless charging using NFC technology has the advantage of being undemanding in terms of space occupation and allows the use of antennas on printed circuit boards.

[0004] Wireless charging using NFC technology makes it possible to charge an electronic device wirelessly over a short distance, for example around 10 cm.

[0005] NFC technology is an open technology platform standardized in ISO / IEC 18092 and ISO / IEC 21481 but incorporates many already existing standards such as the type A and type B protocols defined in ISO-14443 which can be communication protocols usable in NFC technology. Wireless charging using NFC technology is defined by version 2.0 of the NFC WLC (“Wireless Charging”) specification published in October 2021 by the NFC Forum.

[0006] NFC wireless charging is particularly useful for charging relatively small electronic devices, such as wireless headphones and smart watches, fitness trackers, or other Internet of Things electronic devices. For example, electronic devices can be charged by NFC wireless charging from a smartphone or from a dedicated charging station.

[0007] More particularly, NFC wireless charging relies on a charging transmitter device (also referred to as a “poller”) and a power receiver device (also referred to as a “listener”). The charging transmitter device is used to charge the power receiver device. As previously indicated, the charging transmitter device may be a smartphone or a dedicated charging station, for example.

[0008] The speed of wireless charging (especially NFC) depends on the power of the charging signal generated by the charging transmitter device. The higher the power of the charging signal generated by the charging transmitter device, the faster the charging of the power receiving device. It is particularly preferable to generate a charging signal with a relatively high power between 1 Watt and 3 Watts.

[0009] In order to recharge the charging receiver device, the charging signal is generated over a relatively long period during the lifetime of the charging transmitter, in particular greater than 20,000 hours (i.e. 6 hours per day for 10 years). As a result, the charging signal can be generated over a period of several years during the lifetime of the charging transmitter, whereas NFC communication is of the order of a few hundred hours.

[0010] However, generating a charging signal having a high power over a long period of time may degrade the components of said charging signal generating circuit of the charging transmitter device. The degradation of these components may degrade the performance of wireless charging.

[0011] The power of the charging signal is defined by the current and voltage supplied to the antenna of the charging transmitter. The current is defined according to the impedance of the antenna and therefore cannot be increased. Furthermore, increasing the current involves increasing the temperature generated by the charging signal generator circuit. Thus, in order to increase the power of the charging signal, it is better to increase the voltage supplied to the antenna of the charging transmitter.

[0012] It is therefore appropriate to use components that can withstand high voltages to increase the power of the charging signal. However, as seen previously, the performance of these components can deteriorate over time.

[0013] In particular, the circuit for generating the charging signal comprises a circuit for generating a square signal in differential at a given frequency, in particular at 13.56 MHz in the context of NFC charging. The square signal reshaped by the electromagnetic interference filter (in English "electromagnetic interference (EMI) filters") then corresponds to the charging signal. This circuit for generating a square signal comprises transistors of the "MOSFET" type (acronym for "metal-oxide-semiconductor field-effect transistor"). These "MOSFET" type transistors are controlled so as to generate said square signal.

[0014] These “MOSFET” type transistors are generally designed to obtain a relatively low impedance at the output of the recharge signal generation circuit. However, such transistors are not configured to withstand high drain-source voltages, which can reduce their lifetime.

[0015] In order to reduce the loss of performance of a transistor over time, it is possible to increase the channel length of this transistor. However, this solution involves increasing the size of the recharge signal generation circuit.

[0016] There is therefore a need to propose a solution making it possible to provide a signal of recharge having a relatively high power while reducing the performance drop over time of the circuit generating such a recharge signal.

[0017] According to one aspect, there is provided a wireless charging transmitter device comprising: - a generation circuit configured to generate a charging signal at a given frequency, - an antenna configured to transmit said charging signal, the generation circuit comprising at least one circuit for producing a square signal comprising: • a first PMOS type transistor switching circuit comprising a group of PMOS type performance transistors and at least one PMOS type functionality transistor, said at least one PMOS type functionality transistor having an output impedance greater than an output impedance of the PMOS type performance transistors, • a second NMOS type transistor switching circuit comprising a group of NMOS type performance transistors and at least one NMOS type functionality transistor, said at least one NMOS type functionality transistor having an output impedance greater than an output impedance of the NMOS type performance transistors.

[0018] PMOS and NMOS type functionality transistors are used to ensure transitions between a high state and a low state of the recharge signal. These functionality transistors are configured to withstand relatively high drain-source voltages, for example of the order of 7.5 Volts.

[0019] PMOS and NMOS type performance transistors are used to ensure a relatively low output impedance of the generation circuit.

[0020] In an advantageous embodiment, the PMOS-type performance transistors have a source configured to receive a supply voltage, a drain connected to a drain of the NMOS-type performance transistors, and a gate configured to receive a first control signal. In addition, the NMOS-type performance transistors also have a source connected to a cold point and a gate configured to receive a second control signal.

[0021] Advantageously, said at least one PMOS type functionality transistor has a source configured to receive a supply voltage, a drain connected to a drain of said at least one NMOS type functionality transistor, and a gate configured to receive a third control signal. In addition, said at least one NMOS type functionality transistor also has a source connected to a cold point and a gate configured to receive said third control signal.

[0022] In an advantageous embodiment, the performance transistors of type PMOS and the NMOS type performance transistors are controlled offset relative to said at least one PMOS type functionality transistor and said at least one NMOS type functionality transistor so as to avoid simultaneously applying a drain-source voltage and a gate-source voltage greater than a defined voltage threshold on the PMOS type performance transistors and on the NMOS type performance transistors.

[0023] The fact of controlling the PMOS type performance transistors and those of the NMOS type in an offset manner, relative to said at least one PMOS type functionality transistor and said at least one NMOS type functionality transistor, makes it possible to protect these performance transistors from high voltages. It is then possible to increase the drain-source voltage of said at least one PMOS type functionality transistor and said at least one NMOS type functionality transistor. In particular, this drain-source voltage can be increased over a long period without too much impact on the lifetime of these functionality transistors. The functionality transistors thus have greater lengths compared to those of the performance transistors. This allows them to be more robust to aging and thus to maintain good performance over time. This therefore makes it possible to increase the lifetime of these functionality transistors.Performance transistors, on the other hand, have shorter lengths in order to minimize their occupied surface area. Functionality transistors occupy only a small area compared to the entire generation circuit. Thus, although the lengths of functionality transistors are greater than those of performance transistors, this does not result in a significant increase in the surface area of ​​the generation circuit.

[0024] Advantageously, the voltage threshold is between 0.4 Volt and 1 Volt.

[0025] Preferably, the wireless charging transmitter device further comprises a control circuit configured to generate the first control signal, the second control signal and the third control signal.

[0026] Advantageously, the wireless charging transmitter device further comprises a circuit generating an initial clock signal. In addition, the control circuit comprises: - a first delay circuit configured to receive as input said initial clock signal and to generate as output a first intermediate clock signal time-shifted relative to the initial clock signal, said first intermediate clock signal corresponding to the third control signal - a second delay circuit configured to receive as input said first intermediate clock signal and to generate as output a second intermediate clock signal time-shifted relative to the first intermediate clock signal, - a first edge selection circuit configured to generate the first control signal from an alternating selection of the initial clock signal and the second intermediate clock signal, - a second edge selection circuit configured to generate the second control signal from an alternating selection of the initial clock signal and the second intermediate clock signal, this selection being inverted with respect to that of the first edge selection circuit.

[0027] Preferably, the NMOS type performance transistors have an output impedance of between 0.5 ohm and 1 ohm.

[0028] Advantageously, the NMOS type performance transistors have a channel length greater than or equal to 0.72 micrometers.

[0029] Preferably, the PMOS type performance transistors have an output impedance of between 0.5 ohm and 1 ohm.

[0030] Advantageously, the PMOS type performance transistors have a channel length greater than or equal to 0.72 micrometers.

[0031] Preferably, said at least one NMOS type functionality transistor has an output impedance of between 5 ohms and 10 ohms.

[0032] Advantageously, said at least one NMOS type functionality transistor has a channel length greater than or equal to 1.44 micrometers, in particular two to three times longer than the channel length of NMOS type performance transistors.

[0033] Preferably, said at least one PMOS type functionality transistor has an output impedance of between 5 ohms and 10 ohms.

[0034] Advantageously, said at least one PMOS type functionality transistor has a channel length greater than or equal to 1.44 micrometers, in particular two to three times longer than the channel length of PMOS type performance transistors.

[0035] Other advantages and characteristics of the invention will appear on examining the detailed description of embodiments, which are in no way limiting, and the appended drawings in which:

[0036] [Fig.l]

[0037] [Fig.2]

[0038] [Fig.3]

[0039] [Fig.4]

[0040] [Fig.5] illustrate embodiments and implementations of the invention.

[0041] [Fig.l] illustrates an embodiment of a wireless charging transmitter device WLCD.

[0042] The WLCD charge transmitter device comprises a power source (not shown), a CGSR circuit for generating a recharge signal, an FLT electromagnetic interference filter, an IMTCH impedance matching circuit, and an ANT antenna.

[0043] The power source may be a battery for example.

[0044] The recharge signal generation circuit CSGR is configured to generate a recharge signal from the power source. The recharge signal is composed of two square signals in phase opposition. These square signals are transmitted to the antenna ANT via the electromagnetic interference filter FLT and then the impedance matching circuit IMTCH.

[0045] The electromagnetic interference filter FLT is a circuit configured to attenuate, or even eliminate, electromagnetic interference in the square signals generated by the CSGR circuit for generating the recharge signal.

[0046] The impedance matching circuit IMTCH is configured to match the impedance seen by the antenna ANT.

[0047] The antenna ANT is configured to transmit the recharging signal generated by the CSGR circuit for generating the recharging signal.

[0048] Such a charging signal may be received by a charging receiver LST device so as to be able to wirelessly recharge a battery of the charging receiver LST device.

[0049] [Fig.2] illustrates an embodiment of a CSGR circuit for generating a recharge signal as described previously. The CSGR generation circuit comprises two circuits ECRCT1, ECRCT2 for generating a square signal operating in phase opposition. The circuits ECRT1 and ECRCT2 are configured to generate the square signals RFO1 and RFO2 respectively in phase opposition. These square signals RFO1 and RFO2 form the recharge signal which is then emitted by the antenna ANT in a sinusoidal form after filtering.

[0050] Each circuit ECRCT1, ECRCT2 corresponds to a circuit of an inverter chain. Thus, each circuit ECRCT1, ECRCT2 for producing a square signal comprises a PMOS type transistor switching circuit PCOM and an NMOS type transistor switching circuit NCOM. PMOS type transistors are P-type insulated gate field effect transistors (also referred to by the acronym “MOSFET” from the English “metal-oxide-semiconductor field-effect transistor”). NMOS type transistors are N-type insulated gate field effect transistors.

[0051] [Fig.3] illustrates an embodiment of the last stage of these circuits ECRCT1 and ECRCT2.

[0052] In particular, the PMOS type transistor switching circuit PCOM comprises a first group of PMOS type transistors, called performance PMOSP transistors, and a PMOS type transistor, called functionality PMOSF transistor.

[0053] In particular, the functionality PMOSF transistor is used to ensure the transition between a low state and a high state of the recharge signal. The functionality PMOSF transistor has a relatively high output impedance. For example, the functionality PMOSF transistor has an output impedance of between 5 ohms and 10 ohms, for example of the order of 8 ohms. In order to obtain such an output impedance, the functionality PMOSF transistor has a channel length greater than or equal to 1.44 micrometers.

[0054] The performance PMOSP transistors are configured to improve the performance of the switching circuit. The performance PMOS transistors have a relatively low output impedance. For example, the performance PMOSP transistors have an output impedance of between 0.5 ohm and 1 ohm, for example of the order of 0.5 ohm. In order to obtain such an output impedance, each performance PMOSP transistor has a channel length greater than or equal to 0.72 micrometers, in particular two to three times smaller than the channel length of the functionality PMOSF transistors.

[0055] The NMOS type transistor switching circuit comprises a first group of NMOS type transistors, called performance NMOSP transistors, and at least one other NMOS type transistor, called functionality NMOSF transistor.

[0056] In particular, a functionality NMOSF transistor is also used to provide a transition between a high state and a low state of the recharge signal. The functionality NMOSF transistor has a relatively high output impedance. For example, the functionality NMOSF transistor has an output impedance of between 5 ohms and 10 ohms, for example of the order of 8 ohms. In order to obtain such an output impedance, the functionality NMOSF transistor has a channel length greater than or equal to 1.44 micrometers.

[0057] The performance NMOSP transistors are configured to improve the performance of the switching circuit. The performance NMOSP transistors have a relatively low output impedance. For example, the performance NMOSP transistors have an output impedance of between 0.5 ohm and 1 ohm, for example of the order of 0.5 ohm. In order to obtain such an output impedance, each performance NMOSP transistor has a channel length of greater than or equal to 0.72 micrometers, in particular two to three times smaller than the channel length of the functionality PMOSF transistors.

[0058] The functionality PMOSF transistor and the functionality NMOSF transistor are configured to be switched offset relative to the performance PMOSP transistors and the performance NMOSP transistors. In this way, the functionality PMOSF transistor and the functionality NMOSF transistor can simultaneously experience high drain-source voltages and high gate-source voltages. However, both the PMOSF functionality transistor and the NMOSF functionality transistor are configured to withstand such high voltages. This is because the PMOSF functionality transistor and the NMOSF functionality transistor have a larger gate size to withstand aging.

[0059] The functionality PMOSF transistor has a source, a drain and a gate. The source of this functionality PMOSF transistor is connected to a power source VDD. The gate of this functionality PMOSF transistor is configured to receive a signal DCLK1.

[0060] The functionality NMOSF transistor has a source, a drain and a gate. The drain of the functionality NMOSF transistor is connected to the drain of a functionality PMOSF transistor. The drain of each functionality NMOSF transistor is connected to the drain of this functionality PMOSF transistor. The source of this functionality NMOSF transistor is connected to a cold point, in particular to a ground GND. The gate of this functionality NMOSF transistor is configured to receive the signal DCLK1.

[0061] The performance PMOSP transistors and the performance NMOSP transistors are configured to be switched offset from the functionality PMOSF transistor and the functionality NMOSF transistor. In this way, the performance PMOSP transistors and the performance NMOSP transistors do not simultaneously experience high drain-source voltages and high gate-source voltages. This avoids operating conditions that may result in hot carrier injection that may degrade the performance PMOSP transistors and the performance NMOSP transistors.

[0062] The performance PMOSP transistor has a source, a drain and a gate. The source of this performance PMOSP transistor is connected to the power source VDD. The gate of this performance PMOS transistor is configured to receive a signal DCLK0.

[0063] The performance NMOSP transistor has a source, a drain and a gate. The drain of each performance NMOSP transistor is connected to the drain of a performance PMOSP transistor. The source of this performance NMOSP transistor is connected to a cold point, in particular to the GND ground. The gate of this performance NMOSP transistor is configured to receive a DCLK2 signal.

[0064] The recharge signal generation circuit also comprises a COMC control circuit. This COMC control circuit is configured to control the PMOSP, PMOSF and NMOSP, NMOSF transistors of the PCOM, NCOM switching circuits.

[0065] [Fig.4] illustrates an embodiment of such a COMC control circuit. The COMC control circuit is configured to receive a clock signal CLK_RF01. This CLK_RF01 clock signal may be provided by a radio frequency oscillator of the WLCD wireless charging transmitter device. The radio frequency oscillator may include a phase-locked loop.

[0066] The control circuit COMC comprises a first delay circuit DLYL This first delay circuit DLY1 is configured to receive the clock signal CLK_RFO1 and to generate a signal DCLK1 offset by a duration tl relative to the clock signal CLK_RFO1. The duration tl can be adjusted via a first digital control signal PDLYL The duration tl can be between 0.5 nanoseconds and 10 nanoseconds.

[0067] The control circuit comprises a second delay circuit DLY2. The second delay circuit DLY2 is configured to receive the signal DCLK1 and to generate a signal TCLK2 offset by a duration t2 relative to the signal DCLK1, and by the sum of the durations t1 and t2 relative to the clock signal CLK_RFO1. The duration t2 can be adjusted via a digital control signal PDLY2. The duration t2 can be between 0.5 nanoseconds and 10 nanoseconds.

[0068] As described below, the duration t1 makes it possible to avoid cross-conductance between the performance PMOSP, NMOSP transistors and the functionality PMOSF, NMOSF transistors of each ECRCT circuit for producing a square wave signal. The duration t2 makes it possible to improve the lifetime of the performance PMOSP, NMOSP transistors and the functionality PMOSF, NMOSF transistors of each circuit for producing a square wave signal by avoiding simultaneously providing a drain-source voltage and a relatively high gate-source voltage.

[0069] The control circuit also comprises a first edge selection circuit EDGS1. The first edge selection circuit is configured to receive the clock signal CLK_RFO1 and the signal TCLK2. The first edge selection circuit EDGS1 is configured to output a signal DCLK0 corresponding either to the clock signal CLK_RFO1 or to the signal TCLK2. In particular, the first edge selection circuit EDGS1 comprises a set of logic gates for generating the signal DCLK0.

[0070] The control circuit also comprises a second edge selection circuit EDGS2. The second edge selection circuit EDGS2 is configured to receive the clock signal CLK_RFO1 and the signal TCLK2. The second edge selection circuit EDGS2 is configured to output a signal DCLK2 corresponding either to the clock signal CLK_RFO1 or to the signal TCLK2. In particular, the second edge selection circuit EDGS2 comprises a set of logic gates for generating the signal DCLK2.

[0071] The control circuit comprises a first buffer circuit BUF0. The first buffer circuit is configured to receive the unbuffered signal DCLK0 and to deliver this buffered DCLKO signal to the gate of the performance PMOS transistors.

[0072] The control circuit comprises a second buffer circuit BUF1. The second buffer circuit is configured to receive the unbuffered DCLK1 signal and to deliver this buffered DCLK1 signal to the gate of the functionality PMOSF transistor and to the gate of the functionality NMOSF transistor.

[0073] The control circuit comprises a third buffer circuit BUF2. The third buffer circuit is configured to receive the unbuffered DCLK2 signal and to deliver this buffered DCLK2 signal to the gate of the performance NMOSP transistors.

[0074] The control circuit therefore generates three control signals DCLKO, DCLK1 and DCLK2. The DCLKO signal is used to control the performance PMOSP transistors. The DCLK1 signal is used to control the functionality PMOSF transistor and to control the functionality NMOSF transistor. The DCLK2 signal is used to control the performance NMOSP transistors.

[0075] [Fig.5] shows the signals DCLKO, DCLK1 and DCLK2 as well as a square wave signal generated by a square wave processing circuit during one clock cycle.

[0076] As illustrated in this [Fig.5], on each clock cycle CLK_RFO1, the control circuit is configured to generate a DCLKO signal having: - a falling edge FE0 delayed by said duration t2 relative to a falling edge FE1 of the signal DCLK1 and delayed by the sum of the durations t1 and t2 relative to a falling edge FE2 of the signal DCLK2 (the signal DCLKO then being generated by selecting the falling edge of the signal TCLK2, and the signal DCLK2 then being generated by selecting the falling edge FCLK0 of the signal CLK_RFO1), - a rising edge RE0 advanced by said duration tl relative to a rising edge RE1 of the signal DLCK1 and advanced by the sum of the durations tl and t2 relative to a rising edge RE2 of the signal DCLK2 (the signal DCLKO then being generated by selecting the rising edge RCLK0 of the signal CLK_RFO1, and the signal DCLK2 then being generated by selecting the rising edge of the signal TCLK2).

[0077] Thus, before the falling edge FE2 of the signal DCLK2, the output impedance IMP of the square signal generation circuit corresponds to the output impedance of the performance transistors and is therefore a relatively low impedance LIMP. Between the falling edge FE2 of the signal DCLK2 and the falling edge FE0 of the signal DCLKO, the output impedance IMP of the square signal generation circuit corresponds to an intermediate impedance MIMP between the output impedance of the functionality transistors and the output impedance of the performance transistors. Between the falling edge FE0 of the signal DCLKO and the rising edge RE0 of the signal DCLKO, the output impedance IMP of the square signal generation circuit corresponds to the output impedance of the performance transistors and is therefore a relatively low impedance LIMP. Between the rising edge REO of the DCLKO signal and the rising edge RE2 of the DCLK2 signal, the output impedance IMP of the square wave processing circuit corresponds to an intermediate impedance MIMP between the output impedance of the functionality transistors and the output impedance of the performance transistors. After the rising edge RE2 of the DCLK2 signal, the output impedance IMP of the square wave processing circuit corresponds to the output impedance of the performance transistors and is therefore a relatively low impedance LIMP.

[0078] In this way, the functionality PMOSF transistor and the functionality NMOSF transistor are configured to simultaneously receive a drain-source voltage and a relatively high gate-source voltage. Thus, the functionality PMOSF transistor and the functionality NMOSF transistor can operate under conditions that may result in hot carrier injection. Nevertheless, the functionality PMOSF transistor and the functionality NMOSF transistor are configured to withstand these operating conditions. Indeed, these NMOSF and functionality PMOSF transistors have a gate size that is sufficiently large to withstand these operating conditions.

[0079] The performance PMOSP transistors and the performance NMOSP transistors are configured to avoid simultaneously receiving a drain-source voltage and a relatively high gate-source voltage. Thus, the performance PMOSP transistors and the performance NMOSP transistors avoid operating under conditions that may result in hot carrier injection. It is therefore possible to use performance transistors having a relatively low output impedance. This makes it possible to use NMOSP, performance PMOSP transistors of reduced lengths compared to the NMOSF, functionality PMOSF transistors.

[0080] In this way, it is possible to increase the voltage of the recharge signal generated by the CSGR circuit. Thus, it is possible to emit a recharge signal having a relatively high power, for example between 1 Watt and 3 Watts. Such power can therefore be obtained with a charging signal generation circuit having transistors having on average relatively small channel lengths. Indeed, in such a generation circuit, only the functionality NMOSF, PMOSF transistors have a channel length large enough to simultaneously support a relatively high gate-source voltage and a drain-source voltage, the performance NMOSP, PMOSP transistors having a shorter channel length.

Claims

Claims

1. Wireless charging transmitter device comprising: - a generation circuit (CSGR) configured to generate a charging signal at a given frequency, - an antenna configured to emit said charging signal, the generation circuit (CSGR) comprising at least one circuit (ECRCT1, ECRT2) for generating a square signal comprising: • a first switching circuit (PCOM) with PMOS type transistors comprising a group of transistors (PMOSP) of PMOS type performance and at least one transistor (PMOSF) of PMOS type functionality, said at least one transistor (PMOSF) of PMOS type functionality having an output impedance greater than an output impedance of the transistors (PMOSP) of PMOS type performance, • a second switching circuit (NCOM) with NMOS type transistors comprising a group of transistors (NMOSP) of NMOS type performance and at least one transistor (NMOSF) of NMOS type functionality,said at least one transistor (NMOSF) of NMOS type functionality having an output impedance greater than an output impedance of the transistors (NMOSP) of NMOS type performance.,

2. The device of claim 1, wherein the PMOS-type performance transistors have a source configured to receive a supply voltage, a drain connected to a drain of the NMOS-type performance transistors, and a gate configured to receive a first control signal (DCLKO), and the NMOS-type performance transistors also have a source connected to a cold point and a gate configured to receive a second control signal (DCLK2).

3. Device according to claim 2, wherein said at least one PMOS type functionality transistor has a source configured to receive a supply voltage, a drain connected to a drain of said at least one NMOS type functionality transistor, and a gate configured to receive a third control signal (DCLK1), and said at least one NMOS type functionality transistor also has a source connected to a cold point and a gate configured to receive said third control signal (DCLK1).

4. Device according to claim 3, in which the PMOS-type performance transistors (PMOSP) and the NMOS-type performance transistors (NMOSP) are controlled offset relative to said at least one PMOS-type functionality transistor (PMOSF) and said at least one NMOS-type functionality transistor (NMOSF) so as to avoid simultaneously applying a drain-source voltage and a gate-source voltage greater than at least one defined voltage threshold on the PMOS-type performance transistors (PMOSP) and on the NMOS-type performance transistors (NMOSP).

5. Device according to claim 4 in which the voltage threshold is between 0.4 Volt and 1 Volt.

6. Device according to one of claims 3 to 5, further comprising a control circuit (COMC) configured to generate the first control signal (DCLKO), the second control signal (DCLK2) and the third control signal (DCLK1).

7. Device according to claim 6, further comprising a circuit generating an initial clock signal (CLK_RFO1), and wherein the control circuit comprises: - a first delay circuit (DLY1) configured to receive as input said initial clock signal and to generate as output a first intermediate clock signal time-shifted relative to the initial clock signal (CLK_RFO1), said first intermediate clock signal corresponding to the third control signal (DCLK1) - a second delay circuit (DLY2) configured to receive as input said first intermediate clock signal and to generate as output a second intermediate clock signal (TCLK2) time-shifted relative to the first intermediate clock signal,- a first edge selection circuit (EDGS1) configured to generate the first control signal (DCLKO) from an alternating selection of the initial clock signal (CLK_RFO1) and the second intermediate clock signal (TCLK2), - a second edge selection circuit (EDG2) configured to generate the second control signal (DCLK2) from an alternating selection of the initial clock signal (CLK_RFO1) and the second intermediate clock signal (TCLK2), this selection being inverted with respect to that of the first edge selection circuit.,

8. Device according to one of claims 1 to 7, in which the NMOS type performance transistors (NMOSP) have an output impedance between 0.5 ohm and 1 ohm.

9. Device according to claim 8, in which the NMOS type performance transistors (NMOSP) have a channel length greater than or equal to 0.72 micrometers.

10. Device according to one of claims 1 to 9, in which the transistors (PMOSP) of PMOS type performance have an output impedance of between 0.5 ohm and 1 ohm.

11. Device according to claim 10, in which the PMOS type performance transistors (PMOSP) have a channel length greater than or equal to 0.72 micrometers.

12. Device according to one of claims 1 to 11, in which said at least one transistor (NMOSF) of NMOS type functionality has an output impedance of between 5 ohms and 10 ohms.

13. Device according to claim 12, wherein said at least one transistor (NMOSF) of NMOS type functionality has a channel length greater than or equal to 1.44 micrometers.

14. Device according to one of claims 1 to 13, in which said at least one transistor (PMOSF) of PMOS type functionality has an output impedance of between 5 ohms and 10 ohms.

15. Device according to claim 14, wherein said at least one transistor (PMOSF) of PMOS type functionality has a channel length greater than or equal to 1.44 micrometers.

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