Multilayer integration process for electronic circuits

Abstract

Multilayer integration process for electronic circuits The process of integrating electronic components and conductive tracks on a support comprising a substrate (2') equipped with a conductive track (4') and electronic components (5') makes it possible to design electronic circuits in three dimensions and thus increase the integration potential of equipment.It comprises the following successive steps: step 1: deposition of an insulating material (6) onto the support so as to cover the entire support, including the substrate and the electronic circuit, with an outer layer of insulating material; step 2: selective removal of a portion of the insulating material so as to form at least one hole (7) opening through the outer layer of insulating material; step 3: integration of an electronic circuit (3) onto the outer layer of insulating material and into at least one hole, said electronic circuit comprising at least one electronic component (5) and / or a conductive trace (4). Figure to be published with the abbreviation: Figure 5.

Description

Title of the invention: Method for multilayer integration of electronic circuits. TECHNICAL FIELD OF THE INVENTION

[0001] The technical field of the invention is that of electronic circuits.

[0002] The present invention relates to a multilayer integration method of electronic components and conductive tracks on a support comprising an electronic circuit. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0003] Plastronics, also known by the English term Molded Interconnect Device, is a process combining plastics engineering and electronics which allows electronic circuits to be integrated directly onto thermoplastic parts, even when the surfaces on which the electronic circuits are integrated are not flat surfaces.

[0004] This technology makes it possible to increase the potential for integrating equipment, but it usually remains limited to single-layer electronic circuits, that is to say, to electronic circuits in which the routing and arrangement of electronic components are two-dimensional.

[0005] In order to add even more electronics to existing substrates, there is a need for a technology that allows, in particular, the superposition of several electronic components and the generation of routing based on the superposition of several conductive traces that may have different electrical potentials. This technology must also be adapted to cases where the surfaces on which the electronic circuits are integrated are not flat surfaces. Summary of the invention

[0006] The invention offers a solution to the problems mentioned above, by proposing a technology allowing the integration of electronic circuits in a three-dimensional way, in particular allowing the superposition of several successive layers of electronic components and conductive tracks for said electronic components.

[0007] One aspect of the invention relates to a method for integrating electronic components and conductive tracks onto a support, said support comprising a substrate equipped with an electronic circuit, which method comprises the following successive steps: • Step 1: Deposition of an insulating material onto the support so as to cover the entire support, including the substrate and the electronic circuit, with an external layer of insulating material, • Step 2: Selective removal of a portion of the insulating material to create at least one through-hole through the outer layer of insulating material, • Step 3: Integration of an electronic circuit on the outer layer of insulating material and / or in at least one hole.

[0008] This process advantageously allows the superposition of electronic components and / or conductive tracks on an electronic circuit, which in particular allows the superposition of several electronic components and several conductive tracks, for example with different electrical potentials.

[0009] According to one aspect of the invention, the deposition of the insulating material in step 1 is carried out by a vapor phase deposition process, which advantageously makes it possible to create a conforming and very thin insulating layer, which can be deposited on the entire external surface of the support, even in the most inaccessible corners and on surfaces that are not flat.

[0010] According to another aspect of the invention, the deposition process is a vapor phase deposition process without crosslinking of the insulating material.

[0011] Crosslinking is a chemical or physical process that consists of forming covalent or chemical bonds between the molecular chains of a deposited organic material. This can be achieved by heating, exposure to radiation, the addition of chemical reagents, etc. Crosslinking is a specific case of polymerization that involves the formation of bonds between polymer chains, thus creating a three-dimensional network. Polymerization is a more general term that refers to the formation of a polymer from monomers, whether or not crosslinking occurs. The deposition of parylene is therefore not a crosslinking process.

[0012] Chemical Vapor Deposition (CVD) is a coating technique that involves vaporizing a material in gaseous form and then condensing it onto the target surface to form a thin film. CVD allows for conformal and uniform coatings on complex substrates. The deposited film is generally very thin, making it ideal for applications requiring electrical insulation.

[0013] Vapor deposition has the following advantages: • The conformity with the surface allows for the production of thin (between 100 nm and 20 pm) and very homogeneous protections which can be easily laser or plasma engraved to create a multitude of openings for electrical contacts on an industrial scale. • The absence of solvent, catalyst and pollutants such as bromine, NaCl, etc. allows direct deposition onto a silicon chip for example, which is more difficult with a crosslinking material that contains this type of material. • Excellent electrical insulation in the thicknesses mentioned, which notably allows use in the field of power.

[0014] Furthermore, the CVD process is carried out at room temperature, thus preserving heat-sensitive materials, which is not the case with crosslinking and limits its use in the field specifically targeted by this invention.

[0015] According to a further aspect of the invention, the insulating material is parylene, namely a material selected from polymers derived from paraxylene, because it is advantageously an excellent electrical insulator, suitable for vapor phase deposition and selective removal by various technologies.

[0016] According to one aspect of the invention, the insulating material layer obtained in step 1 has a thickness of between 0.1 µm and 200 µm, preferably between 0.5 µm and 75 µm and more preferably between 5 µm and 15 µm. These thicknesses are advantageously compatible with multilayer structures in both the field of electronics and in the field of microelectronics.

[0017] According to another aspect of the invention, the selective removal in step 2 is carried out using one of the following technologies or a combination thereof: • Excimer laser engraving, • femtosecond laser engraving, • Oxygen plasma etching, • nitrogen plasma etching, • rare gas plasma etching.

[0018] These various techniques advantageously allow for the selective and localized removal of insulating material in order to create holes through which elements located beneath the insulating layer become accessible, for example, to connect them electrically to elements that will be integrated onto said insulating layer, these elements being, for example, electronic components or conductive traces. They are also suitable when the surfaces on which the electronic circuits are integrated are not flat surfaces.

[0019] According to a further aspect of the invention, at least one through hole obtained in step 2 has a round, square, or rectangular cross-section. These shapes are merely examples of cross-sectional shapes that are advantageously easy to produce and are suitable for connecting elements located under the insulating layer to those located on top of it.

[0020] According to one aspect of the invention, the electronic circuit integrated in step 3 comprises at least one electronic component and / or a conductive track.

[0021] According to one aspect of the invention, step 3 comprises a selective metallization step of at least a portion of the outer layer of insulating material and / or at least one hole so as to deposit a conductive track therein. This step advantageously makes it possible to create conductive tracks, not necessarily connected to each other, on the layer of insulating material and to deposit a conductive material in the holes in order to electrically connect the elements located under the layer of insulating material to those located on it.

[0022] According to another aspect of the invention, the conductive track deposited in step 3 is a layer comprising mainly gold, palladium, copper, silver, carbon, or a mixture thereof. These compositions are merely examples of compositions that are advantageously excellent conductors and are easily deposited by the selective metallization techniques envisaged for the process of the invention.

[0023] According to a further aspect of the invention, the deposition of the conductive track during step 3 is carried out using one of the following technologies or a combination thereof: • Aerosol printing (AJP), • inkjet printing, • chemically activated laser structuring (LSCA).

[0024] These various techniques advantageously allow the creation of very thin conductive tracks with very high precision in terms of thickness and other dimensions. They are also suitable when the surfaces on which the electronic circuits are integrated are not flat. Since the most precise techniques are generally more expensive, they are preferentially reserved for cases where the process of the invention is applied to microelectronics.

[0025] According to one aspect of the invention, step 3 comprises a step of mounting at least one electronic component onto the outer layer of insulating material and into at least one hole. This step advantageously allows electronic components to be connected either with other elements of an electronic circuit located beneath said layer of insulating material, or with other elements of an electronic circuit located on the same layer as said electronic components, or with other elements that will be integrated into another upper layer of the electronic circuit, located above the layer in which the electronic components are integrated. In this last case, the upper layer will be at least partially insulated from the electronic components integrated during step 3, this upper layer being obtained by repeating steps 1 to 3 of the process.

[0026] According to another aspect of the invention, at least one electronic component has electrical contacts and at least one electrical contact is mounted in a hole. This advantageously allows an electronic component to be electrically connected to an element of an electronic circuit located below said hole. As a reminder, such an element is, for example, an electronic component or a conductive trace.

[0027] According to a further aspect of the invention, the process includes a surface treatment step of the outer layer of insulating material, provided for before step 3, in order to improve its adhesion to the conductive track. This treatment is particularly advantageous when the insulating material exhibits a certain degree of incompatibility with the techniques used to perform the metallization of the insulating material.

[0028] According to one aspect of the invention, the surface treatment is carried out using one of the following technologies or a combination thereof: • Plasma surface treatment, • flame surface treatment, • High-frequency electrical discharge surface treatment, • UV surface treatment.

[0029] These different techniques advantageously promote the metallization of the insulating material, particularly when its surface is not flat.

[0030] According to another aspect of the invention, at least one removable protective cover is placed on the support before step 1. This advantageously allows areas of the support to be left uncovered with insulating material. Indeed, during step 1, each protective cover is covered with insulating material, thus protecting the support below. It is then simply a matter of removing each cover to reveal areas of the support that are not covered with insulating material.

[0031] According to a further aspect of the invention, steps 1, 2 and 3 are repeated in order, at least once. This advantageously allows for the creation of several successive layers of electronic circuit, each comprising electronic components and / or conductive tracks, these successive layers being at least partially insulated from each other by a layer of insulating material.

[0032] According to one aspect of the invention, the electronic circuit obtained in steps 1, 2, and 3 is electrically connected with at least one other electronic circuit of a lower layer. This advantageously allows several successive layers of electronic circuits to be electrically connected.

[0033] The term "lower layer" here refers to the layer immediately below the layer comprising the insulating material and the electronic circuit obtained in steps 1, 2, and 3, or another layer located even below it. This lower layer may be a layer obtained in steps 1, 2, and 3. It may also be of the support on which at least one layer obtained during steps 1, 2 and 3 is deposited.

[0034] The invention and its various applications will be better understood by reading the following description and examining the accompanying figures. BRIEF DESCRIPTION OF THE FIGURES

[0035] The figures are presented for illustrative purposes only and are not intended to limit the invention. For clarity, the thicknesses of some layers are considerably exaggerated.

[0036] [Fig.1] is a schematic cross-sectional view of a support comprising a substrate equipped with an electronic circuit comprising five electronic components integrated on a conductive track.

[0037] [Fig.2] is a schematic cross-sectional view of the support of [Fig.1] on which is deposited a layer of insulating material according to step 1 of the process of the invention.

[0038] [Fig.3] is a schematic cross-sectional view of the support of [Fig.2] where holes are formed in the insulating material layer (step 2 of the process).

[0039] [Fig.4] is a schematic cross-sectional view of the support of [Fig.3] on which two electronic components and a conductive track are integrated on the outer layer of insulating material, the conductive track also being integrated into two holes (step 3 of the process).

[0040] [Fig.5] is a schematic cross-sectional view of the support of [Fig.4] on which another a layer comprising insulating material and an electronic circuit is superimposed by repeating steps 1 to 3 of the process of the invention once.

[0041] [Fig.6] is a table giving several variants of parylene. DETAILED DESCRIPTION

[0042] Unless otherwise specified, the same element appearing on different figures presents a unique reference.

[0043] By convention, in the present application, the terms "conductor" mean "electrical conductor, whose function is to allow an electric current to pass through", while the terms "insulator" mean "electrical insulator, whose function is to prevent the passage of any electric current, for example between two conductive parts subjected to a difference in electrical potential".

[0044] The invention relates to a multilayer integration method for electronic components 5 and conductive tracks 4 on a support 1 comprising a substrate 2' equipped with an electronic circuit 3' having at least one conductive track 4' and / or an electronic component 5', even when the surfaces of said support 1 on which the electronic components 5 and the conductive tracks 4 are integrated The sandstones are not flat surfaces. The electronic circuit 3' can be an electronic circuit 3 obtained by the process of the invention or another pre-existing electronic circuit 3'.

[0045] Thus, the method of the invention can be used indifferently to integrate additional electronics on existing substrates 2' already equipped with one or more electronic circuits 3' or to integrate multilayer electronics on a substrate 2' initially devoid of electronic circuits, the first layer of electronic circuit 3' then being able to be integrated in a conventional way.

[0046] The method of the invention comprises three main successive steps, which may be repeated individually or sequentially, these steps together enabling the integration of at least one electronic component 5 and / or at least one conductive track 4 onto an electronic circuit 3' so as to form an additional layer of electronic circuit 3, preferably connected at least partially to the layer of electronic circuit 3' located below. An electronic circuit 3 is understood to mean an assembly comprising at least one electronic component 5 and / or at least one conductive track 4.

[0047] By way of example, [Fig. 1] shows a support 1 comprising an electronic circuit 3' having a conductive track 4' on which five electronic components 5' are integrated. The steps of the invention will be described with reference to [Fig. 2]-[Fig. 4] which illustrate the multilayer integration of electronic circuits 3 having conductive tracks 4 and electronic components 5 on this support 1.

[0048] The support 1 can be any part comprising a substrate 2' equipped with an electronic circuit 3'. The support 1 is, for example, a ceramic, a plastic support, an electronic board comprising a printed circuit board, a plastronic substrate, a substrate obtained by selective metallization, or any other support 1 integrating electronic components 5' and conductive tracks 4'. The electronic circuit 3' may also have been obtained by the process according to the invention.

[0049] The deposition of track 4' onto a plastic substrate can notably be carried out by the following processes: • Aerosol printing (AJP), • inkjet printing, • conductive paste extrusion • Laser direct structuring (LDS), • print and metallize (print-then-plate in English), • bi-injection (two-shot molding in English), • laser-induced forward transfer (FIP).

[0050] In the case where the substrate is a ceramic, the deposition of track 4' can in particular be done by high temperature firing technology of ceramic components (HTCC for High Temperature Cofired Ce ramie), by simultaneous low temperature firing of ceramics (LTCC for Low Temperature Cofired Ce ramie) or by a process already used on inertial sensors for example, in particular ink-based thick film deposition (ceramic thick film in English).

[0051] In a first step, the entire support 1 is covered with a layer of insulating material 6 (see [Fig.2]), that is to say, all external surfaces of the support 1 are covered, as well as all elements mounted on it, in particular the substrate 2' and the electronic circuit 3'. In the case where electronic components 5' are mounted on the support 1 at a distance from the conductive track 4', for example by being mounted by fixing or power supply tabs, the insulating material 6 also covers the external face of said tabs, the underside of said electronic components 5' and the surface of the conductive track 4' which is hidden under these electronic components 5'.

[0052] This deposit of a layer of insulating material 6 is preferably conformal.

[0053] By insulating layer we mean here a film of sealing and protective material against corrosion, while a conformal layer refers to a thin, regular, and uniform film of material. A conformal insulating layer also implies a notion of near-hermeticity, with moisture penetration that is, for example, one hundred times lower than epoxy.

[0054] The deposition of an insulating material 6 is preferably carried out by a vapor phase deposition (VPD) technique, which allows the insulating material 6 to penetrate everywhere, to cover all external surfaces of the support 1, regardless of the shape of the latter, and to form a very thin conforming layer of insulating material 6 whose thickness can be controlled, for example with a deposition tolerance of about 0.1 pm.

[0055] The deposition is preferably carried out without crosslinking of the insulating material 6.

[0056] The insulating material layer 6 deposited during this first step preferably has a thickness between 0.1 pm and 200 pm, more preferably between 0.5 pm and 75 pm and even more preferably between 5 pm and 15 pm.

[0057] The insulating material 6 used is preferably parylene, which is the name of a range of polymers derived from paraxylene, also known as polyparaxylylene, poly(p-xylylene), paraxylene, para-xylylene, p-xylylene or p-quinodimethane, and which are very well suited to the needs of the invention

[0058] In the basic parylene motif, the substitution of aromatic hydrogens by elements or groups modifies its properties. Thus, there are numerous variants of parylene within the range of polymers derived from paraxylene. In its basic form, consisting solely of hydrogen and carbon atoms, it is called parylene N.

[0059] The table in [Fig.6] gives several variants of parylene.

[0060] Among these variants, parylene F and HT exhibit satisfactory temperature resistance, while parylene N shows degraded adhesion at 70°C. However, plasma or laser etching of parylene F and HT results in a lower etching rate than for parylene N and C. Therefore, in applications, the parylene used is chosen according to the operating temperatures and the desired etching speed.

[0061] It should be noted that parylene is a semi-crystalline, non-crosslinked polymer with a crystallinity level of approximately 50%, which can be increased by heat treatment. It is thus distinguished from epoxy, which is a three-dimensional, crosslinked polymer.

[0062] Thus, although parylene is preferred, the insulating material 6 is preferably based on any type of solid semi-crystalline molecule exhibiting electrical insulation properties.

[0063] According to a preferred embodiment, parylene deposition is a chemical vapor deposition (CVD) coating process that uses a solid precursor called a p-xylylene dimer or p-cyclophane. According to a preferred embodiment, this dimer is sublimated at high temperature in an evaporation chamber, then thermally cracked in a pyrolysis chamber to form gaseous p-xylylene monomers. These monomers then condense onto the surface to be coated in a deposition chamber at low pressure and ambient temperature, thus forming a parylene polymer film. One can therefore speak of polymerization in the sense that a polymer is formed from monomers, but it is a very particular polymerization that occurs without a catalyst, without a solvent, and without the elimination of by-products, therefore very different from what occurs, for example, with an epoxy, a silicone, or any other organic material of this type.To date, the exact polymerization mechanism of p-xylylene does not yet appear to be fully elucidated, but it would involve the formation of free radicals or diradicals that add together to form linear chains.

[0064] In the event that it is desired to avoid a part of the support 1 being covered with insulating material 6, it is possible to position a removable protective cover on the support 1 before the first step, which cover is then removed before proceeding with the following steps of the process.

[0065] In a second step, through holes 7 are made through the outer layer of insulating material 6 (see [Fig.3]). These holes 7, or vias, are obtained by selectively removing a portion of the insulating material 6.

[0066] By through-hole, we mean that where a hole 7 is made, all the insulating material 6 is removed, allowing access to what is below in order to connect them electrically to conductive tracks 4 and / or to electronic components 5 deposited subsequently.

[0067] By selective removal of insulating material 6, we mean that during this step, only the insulating material 6 is removed, without degrading the other materials or the elements located below it, for example without damaging the support 1 or the electronic circuit 3'3' located under the insulating material 6.

[0068] In the case where there is a pre-existing layer of insulating material 6 under the layer of insulating material 6 in which holes are to be made, two scenarios are possible: • If there is no contact on this lower layer and an engraving has already been started on the surface layer, it is possible to continue the engraving through this layer. • If there is contact on this lower layer, the engraving stops due to the difference in sensitivity on the contact.

[0069] The holes 7 made during this second step are known as "via" by those skilled in the art. They have, for example, a round, square or rectangular cross-section.

[0070] These holes 7 are for example formed above conductive tracks 4' or electrical connector of an electronic component 5' of the lower layer in order to create areas of electrical contact with the elements of said lower layer.

[0071] Several technologies can be used to carry out the selective removal of insulating material 6. The technologies preferred are laser etching and plasma etching.

[0072] Laser engraving, for example by excimer laser or femtosecond laser, makes it possible in particular to remove the insulating material 6 selectively by adjusting the wavelength and the duration of excitation of said laser, with a very precise cutting path, which can be programmed, and it does not require the use of a mask or other technique aimed at protecting the surface in which holes 7 are formed.

[0073] Excimer laser etching removes material by combustion. It is an inexpensive technology, but it tends to deform the etched edges due to heating. Argon fluoride excimer lasers are preferred.

[0074] Femtosecond laser etching removes material by vaporization. This technology is even more precise than the excimer laser and does not distort the etched edges, but it is more expensive. The femtosecond laser has the advantage of a very short pulse time and no degradation of the material.

[0075] Plasma etching, for example with oxygen plasma, nitrogen plasma, or rare gas plasma, makes it possible to remove the insulating material 6 quickly and inexpensively. Generally, however, this etching must be carried out through a mask designed to protect the insulating material 6, in which no holes 7 are desired. Such a mask, for example made of metal, is preferably a plate of material that is more resistant to the plasma used than the insulating material 6, and which has cutouts through which the plasma is projected, corresponding to the areas where holes 7 are to be made.

[0076] Oxygen plasma etching allows for the removal of material by chemical attack when the insulating material 6 is a material containing a significant amount of carbon, such as parylene. It does not attack metals, which notably prevents attack on the conductive tracks 4' and other metallic elements of the electronic circuit 3, 3' located beneath the insulating material 6.

[0077] Nitrogen plasma etching (or nitride plasma etching) is a technique used to selectively modify or remove materials in the presence of activated nitrogen gas in a low-pressure environment. It is primarily used for dry etching, reactive etching, or surface cleaning applications. However, nitrogen plasma etching is generally not recommended for modifying or etching parylene, unlike oxygen (O2) plasma etching, which is more commonly used. This is because parylene is a highly inert polymer and resistant to chemicals; consequently, it is less reactive to the active nitrogen in the nitrogen plasma than more reactive materials such as other polymers.Furthermore, parylene has high erosion resistance, meaning it is difficult to remove using conventional etching methods, and nitrogen plasma may not be powerful enough to effectively remove parylene. Finally, nitrogen plasma etching is likely to damage underlying electronic components or other materials present in the parylene in addition to the parylene itself.

[0078] Rare gas plasma etching, for example argon plasma etching, allows material to be removed by mechanical attack. This technique, although less expensive, is also less selective than oxygen plasma etching.

[0079] It is possible to combine different plasmas. For example, oxygen and argon plasma etching is very advantageous in that it improves cleaning efficiency and surface quality when creating holes 7.

[0080] In a third step, an electronic circuit 3 is integrated onto the assembly resulting from the previous steps (see [Fig. 4]). Thus, one or more conductive tracks 4 and one or more electronic components 5 are integrated onto the outer layer of insulating material 6 and / or into a hole 7.

[0081] The integration of a conductive track 4 is achieved by selective metallization of one or more parts of the outer layer of insulating material 6 and of one or more holes 7. Several conductive tracks 4 can thus be deposited, without them necessarily being electrically connected to each other at the time of their deposition. They can be connected subsequently.

[0082] The conductive tracks 4 are preferably predominantly based on gold, palladium, copper, silver, carbon or a mixture thereof. They can be deposited in the form of a liquid conductive ink or in aerosol form.

[0083] Several technologies can be used for depositing a conductive track 4. Among the preferred technologies, we can mention aerosol jet printing (AJP), inkjet printing (jetting), and laser structuring chemically activated (LSCA).

[0084] The LSCA process, which is not widely known, combines laser engraving and non-electrolytic (electroless) metal deposition.

[0085] Sintering, for example laser sintering, also makes it possible to improve the electrical and thermal conductivity of the conductive tracks 4.

[0086] Similarly, a surface treatment of the outer layer of insulating material 6 may be provided before the third step in order to improve the adhesion of this layer with the conductive track 4. This treatment is preferably carried out by plasma, by flame treatment (also known as flame treatment), by high-frequency electrical discharge (also known as Corona treatment) and / or by UV treatment.

[0087] The integration of an electronic component 5 onto the outer layer of material The insulating contact 6 and the connection in at least one hole 7 are made in a conventional manner. The electronic components 5 are preferably surface-mounted by soldering.

[0088] In the case where the electronic component 5 has electrical contacts, at least one electrical contact may be mounted in a hole 7 or on a conductive track 4. For the sake of simplicity in the figures, these electrical contacts are not shown.

[0089] The three steps of the process make it possible to integrate a layer of conductive tracks 4 and electronic components 5 on a support 1, and to connect all or part of these conductive tracks 4 and electronic components 5 with pre-existing conductive tracks 4' and electronic components 5' on the support 1.

[0090] These steps can be repeated individually, for example in order to deposit the insulating material 6, to form holes 7 and / or to integrate electronic components 5 and conductive tracks 4 several times, respectively during the first, second and third steps of the process.

[0091] The three steps of the process can also be repeated in order in order to integrate other similar layers by superimposing them, thus offering many possibilities for routing and arrangement of electronic components 5, including the possibility of providing several conductive tracks 4 each at a different electrical potential.

[0092] A support 1 thus comprising two superimposed layers according to the process of the invention is represented on [Fig.5], illustrating one example among the many possibilities of three-dimensional integration of the invention.

[0093] Indeed, the method of the invention makes it possible to design electronic circuits not only in two dimensions, but also in three dimensions, which notably allows for a considerable increase in the integration potential of equipment. The method of the invention makes it possible to design electronic circuits whose routing and arrangement of electronic components can be three-dimensional.

[0094] It should also be noted that the invention, depending on the technologies used for each step, can be used both in the field of electronics and in the field of microelectronics.

[0095] Although described through a number of examples, variants and embodiments, the process according to the invention includes various variants, modifications and improvements which will be obvious to a person skilled in the art, it being understood that these variants, modifications and improvements are part of the scope of the invention.

Claims

Demands

1. A method for integrating electronic components (5) and conductive tracks (4) onto a support (1), said support (1) comprising a substrate (2') equipped with an electronic circuit (3'), characterized in that it comprises the following successive steps: - step 1: deposition of an insulating material (6) onto the support (1) so as to cover the entire support (1), including the substrate (2') and the electronic circuit (3'), with an outer layer of insulating material (6), - step 2: selective removal of a portion of the insulating material (6) so as to form at least one hole (7) opening through the outer layer of insulating material (6), - step 3: integration of an electronic circuit (3), comprising at least one electronic component (5) and at least one conductive track (4), onto the outer layer of insulating material (6) and / or into at least one hole (7);and in that - the support (1) is a ceramic, a plastic support, an electronic board comprising a printed circuit, a plastronic substrate, a substrate obtained by selective metallization.;

2. A method according to claim 1, characterized in that the deposition of the insulating material (6) in step 1 is carried out by a vapor phase deposition process.

3. A method according to any one of the preceding claims, characterized in that the insulating material (6) is parylene, namely a material selected from polymers derived from paraxylene.

4. A method according to any one of the preceding claims, characterized in that the insulating material layer (6) obtained in step 1 has a thickness between 0.1 qm and 200 qm, preferably between 0.5 qm and 75 qm and more preferably between 5 qm and 15 qm.

5. A method according to any one of the preceding claims, characterized in that the selective removal of step 2 is carried out using one of the following technologies or a combination thereof: - excimer laser etching, - femtosecond laser etching, - oxygen plasma etching, - nitrogen plasma etching, - rare gas plasma etching.

6. Method according to the preceding claim, characterized in that step 3 comprises a step of selective metallization of at least a part of the outer layer of insulating material (6) and / or of at least one hole (7) so as to deposit a conductive track (4).

7. A method according to the preceding claim, characterized in that the deposition of the conductive track (4) during step 3 is carried out using one of the following technologies or a combination thereof: - aerosol printing (AJP), - inkjet printing, - chemically activated laser structuring (LSCA).

8. A method according to any one of the preceding claims, characterized in that steps 1, 2 and 3 are repeated in order, at least once.

9. A method according to any one of the preceding claims, characterized in that the electronic circuit (3) obtained during steps 1, 2 and 3 is electrically connected with at least one other electronic circuit (3, 3') of a lower layer.

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