Device for driving a video interface for a display circuit matrix

Abstract

The present invention proposes a device for controlling a digital video stream to be transmitted to a pixel matrix integrated on the front face of a box, the box grouping together on the rear face a set of control and command signals. The control device comprises: - a matrix arrangement unit configured to define the pixel matrix by a plurality of pixel sub-matrices, and group the sub-matrices into a plurality of rows of sub-matrices and a plurality of columns of sub-matrices;and - a flow sequencing unit, configured to: - share synchronization and clock signals between all the sub-matrix lines, such that each synchronization and clock signal drives the plurality of sub-matrix lines, - assign a selection signal to each sub-matrix line, such that activating a selection signal for a line makes it possible to address all the sub-matrices belonging to said line, - assign a data distribution bus respectively to each of the sub-matrix columns, such that activating a data transmission signal for said buses makes it possible to send digital data in parallel on said buses to all the sub-matrices of each sub-matrix column. Figure for the abstract: Fig. 3;

Description

Title of the invention: Device for controlling a video interface for a matrix of display circuits Field of invention

[0001] The invention relates to the technical field of integrated circuits performing a display function with emissive pixel matrices, and relates to a device for controlling a digital video stream to be displayed by such a matrix.

[0002] The invention is advantageously applicable to the production of a display function for small screens. State of the art

[0003] The ever-increasing demand for small-sized display devices with an emissive pixel matrix but having a high definition, such as smartphones (i.e. microscreens, miniscreens), has led to the development of integrated circuits performing a display function, which must be integrated with all the command and control logic in small-sized boxes having a limited number of input / output (I / O) signals.

[0004] Such integration constraints are today at the heart of the problem of increasing the resolution of such small display devices.

[0005] This problem does not exist for assemblies of juxtaposed large screens, such as LCD panels for example, which do not have the same levels of integration.

[0006] Indeed, to achieve higher definitions, with a given pixel size on a single-chip system, it is necessary to increase the surface area of ​​the circuit. The manufacturing yields of large-surface monolithic circuits then become too low.

[0007] An alternative consists of assembling several smaller surface circuits into a matrix, which allows a gain in efficiency while accumulating the pixels of each circuit.

[0008] The question then arises of managing the video stream destined for several circuits, knowing that the assembly must be integrated into the same box to form only one display screen from a system point of view.

[0009] Two alternatives are known. A first approach is a parallel and independent management of the different circuits, which leads to multiplying the number of video interface signals to address each circuit. A second approach is a serial and shared management of the different circuits which requires increasing the transmission rates by a factor equal to the number of circuits to be addressed.

[0010] The packaging of such a system comprising several assembled circuits for small displays makes these two approaches unsatisfactory. Indeed, parallel management multiplies the number of inputs / outputs and complicates the routing in the package. Serial management increases the transmission rates beyond the frequencies acceptable for routing simple signals (“single-ended” in English).

[0011] There is then a need for a solution making it possible to manage the sequencing of a digital video stream to be displayed by a display device with an emissive pixel matrix, which is integrated into a small-sized box.

[0012] The present invention meets this need. Summary of the invention

[0013] The present invention relates to a device and a method for controlling a digital video stream to be transmitted to a matrix of emissive pixels for display on a small-sized display device.

[0014] The present invention proposes a device for controlling a digital video stream to be transmitted to a pixel matrix integrated on the front face of a box, the box grouping together on the rear face a set of control and command signals.

[0015] The control device comprises: - a matrix arrangement unit configured to define the pixel matrix by a plurality of pixel sub-matrices, and group the sub-matrices into a plurality of sub-matrix rows and a plurality of sub-matrix columns; - a flow sequencing unit, configured to: - sharing synchronization and clock signals between all the sub-matrix lines, such that each synchronization and clock signal drives the plurality of sub-matrix lines, - assign a selection signal to each row of sub-matrices, such that activating a selection signal for a row makes it possible to address all the sub-matrices belonging to said row, - assigning a data distribution bus respectively to each of the columns of sub-matrices, such that the activation of a data transmission signal for said buses makes it possible to send in parallel on said buses, digital data to all the sub-matrices of each column of sub-matrices.

[0016] In one embodiment, the matrix arrangement unit is configured to define a number of sub-matrices according to an image resolution to be displayed by the pixel matrix.

[0017] In one embodiment, the stream sequencing unit comprises a row selection module configured to select at least one row of sub-matrices, such that activating a selection signal for a row makes it possible to address all the sub-matrices belonging to said row of sub-matrices.

[0018] In one embodiment, the stream sequencing unit comprises a column selection module configured to select at least one column of sub-matrices, such that activation of the transmission signal makes it possible to send digital data in parallel to all the sub-matrices of the selected columns.

[0019] In one embodiment, the box is connected to an electronic card, said card comprising an adaptation circuit for converting into digital data, a video stream provided by an external video source.

[0020] In one embodiment, each circuit of the pixel matrix further comprises shift registers for storing digital data.

[0021] In one embodiment, each circuit of the pixel array further comprises a ramp digital-to-analog conversion unit for converting digital data into analog voltages to be applied to the emissive pixel circuits of the array.

[0022] In one embodiment, the device further comprises a 'global shutter' type processing unit for managing the offset between a synchronization signal and an actual display of an image.

[0023] Another object of the invention relates to a display system which comprises a device for controlling a digital video stream according to the invention.

[0024] In one embodiment, the pixel matrix is ​​a 1050 x 1050 pixel matrix, the matrix arrangement unit makes it possible to define an arrangement of 25 pixel sub-matrices of 210 x 210 pixels each, organized into 5 rows of sub-matrices and 5 columns of sub-matrices. Brief description of the figures

[0025] Other characteristics, details and advantages of the invention will emerge on reading the description given with reference to the appended drawings given by way of example.

[0026] [Fig.l] is a schematic representation of the device for controlling a digital video stream of the invention, according to one embodiment.

[0027] [Fig.2] represents a matrix of pixels organized into groups of sub-matrices, according to one embodiment of the invention.

[0028] [Fig.3] represents a distribution of control and command signals on sub-matrix lines, according to an embodiment of the invention.

[0029] [Fig.4] illustrates the successive sending on different distribution buses of digital data depending on the selection of different sub-matrix lines, according to an embodiment of the invention.

[0030] Figures 5a and 5b illustrate a sequencing of a transmission of image lines to different sub-matrix lines, according to an embodiment of the invention.

[0031] [Fig.6] schematically represents an electronic card integrating a device for controlling a digital video stream, according to one embodiment of the invention.

[0032] [Fig.7] schematically represents an implementation of a circuit for a display sub-matrix, according to an embodiment of the invention.

[0033] [Fig.8] schematically illustrates a display with reduced image resolution.

[0034] [Fig.9] schematically illustrates the management of a display in “global shutter” mode, according to one embodiment of the invention. Detailed description of the invention

[0035] [Fig.l] is a schematic representation of the device 100 for controlling a digital video stream according to the invention, making it possible to display a digital video stream on a display system 130, such a system being in a ratio where the display surface is equal or almost equal to the surface of the control and control circuits. The display systems concerned by the present invention are displays whose surface is of the order of 5 cm x 5 cm or more generally in a range of 1 to 10 cm on each side for definitions of 512x512 to 2048x2048 pixels.

[0036] The invention is implemented for display systems which are organized into a plurality of abutted circuits forming a circuit matrix (we speak of multi-circuit or multi-chip display). The display system 130 is constituted by a matrix of emissive pixels 120, independently of the nature of the emitted light, visible or infrared.

[0037] Emissive pixel matrix display systems are also referred to as “Read-In Integrated circuit” according to the recognized Anglicism.

[0038] In one embodiment, the emissive pixels are produced in the form of heating micro-resistors on a silicon substrate which integrates a pixel control circuit, i.e. the circuit individually controls the voltages of each micro-resistor.

[0039] Some principles relating to the display of an image on a single-chip matrix of pixels are recalled, considering a digital transmission of the value of the pixels coded on N bits. An image to be displayed is composed of XxY pixels, the system displays F images per second. The rate of the digital video stream is then NxXxYxF bits per second.

[0040] In the case of transmitting pixel values ​​in a digital format, it is necessary to have a digital / analog conversion phase in order to voltage-drive the pixel display device. The sequencing of the video stream must be organized according to the time Tconv to be devoted to the conversion phases. The conversion for all the pixels of an image can be carried out in parallel with the transmission of the next image. This allows for continuous transmission of images and avoids throughput peaks between two conversion phases. The disadvantage of parallel conversion lies in the need to be able to store a complete image. In addition, there is a latency before an image is displayed, which can be problematic.

[0041] Another approach to managing the sequencing of the video stream consists of line-by-line sequencing, where the image lines are converted on the fly. The transfer time of a line is noted TUgne. The transmission is no longer continuous since it is interrupted by the conversion phases, on the other hand the storage of digital data is limited to that of a single line and no longer to a complete image.

[0042] In a more general approach, called sequencing by group of lines, it is possible to group the lines of the image (groups of K image lines) at the time of transmission. This makes it possible to reduce the number of conversion phases per image, while limiting the storage of digital data to K lines. Different parameters can be adjusted so as to ensure that there is no overflow on the time of the following image, respecting the equation: YxTiigne+(Y / K)xTconv< P, (P = 1 / F). In the case where the number of lines K does not divide the number Y of pixels (Y= pxK+r), the sequencing works with a number of pixels Y'= (p+l)xK, (p and r being integers). There is then an interruption in the data flow corresponding to the 'K-r' lines not physically present.This scheme is all the more interesting as the conversion time is long (for example with a ramp DAC) compared to the transfer time of K lines (K "Y) and not dependent on the number of lines converted.

[0043] With the previously mentioned problem of the ever-increasing difficulty of integrating pixels on a single-chip system, and the transition to multi-chip systems considered by the subject of the present invention, it appears that the sequencing of the digital video stream can no longer be managed according to the classic approaches of parallel or serial sequencing or by group of image lines.

[0044] Thus, the digital video stream control device 100 of the invention comprises a matrix arrangement unit (102) configured to define the pixel matrix by a plurality of sub-matrices and create groups of sub-matrices, and comprises a digital video stream sequencing unit (104).

[0045] The matrix arrangement unit (102) makes it possible to define circuit sub-matrices. Each sub-matrix is ​​a circuit and the set of circuit sub-matrices forms the complete matrix.

[0046] Starting from an initial matrix composed of lines and columns of circuits, the arrangement unit makes it possible to create, by grouping circuits, lines of sub- matrices and columns of sub-matrices.

[0047] In one embodiment, the arrangement unit makes it possible to group the sub-matrices into a number G of groups of sub-matrices.

[0048] In a preferred embodiment, a group of sub-matrices groups the sub-matrices of a row of sub-matrices.

[0049] In one embodiment, the matrix arrangement unit is configured to define a number of sub-matrices and a number of sub-matrix groups based on an image resolution to be displayed by the pixel matrix.

[0050] In a particular implementation, the substrate is a 6 cm x 6 cm package, and the desired total definition is 1050 x 1050 pixels. The total definition of such a device is the sum of the definitions of each individual circuit. The arrangement unit makes it possible to divide the screen (i.e. the initial matrix) into 25 sub-matrices of 210 x 210 pixels each. The initial matrix is ​​thus organized into 5 rows of sub-matrices and 5 columns of sub-matrices.

[0051] The flow sequencing unit (104) is configured to manage the different control and command signals of the pixel circuits, based on the configuration of the matrix into groups of sub-matrices.

[0052] The sequencing of the flow is further adjustable by different parameters which are the conversion time Tconv, the transfer time per line Tiigne, the number G of groups of sub-matrices and the number K of lines of the image.

[0053] Using the previous notations, the sequencing of the data is managed at the level of the sequencing unit according to the following equation:

[0054] Tconv=(Gl)xKxTline.

[0055] [Fig.2] represents a matrix of pixels organized into sub-matrices, according to a embodiment of the invention.

[0056] For reasons of simplification of the description, an example is taken for a matrix of pixels divided into 9 sub-matrices. The sub-matrices are grouped into G=3 groups of 3 sub-matrices forming 3 lines of sub-matrices. In this example, the sequencing of a digital video stream will be controlled for three groups of matrices, a first group grouping the sub-matrices (1, 2, 3) of the first line of sub-matrix, a second group grouping the sub-matrices (4, 5, 6) of the second line of sub-matrix, and a third group grouping the sub-matrices (7, 8, 9) of the third line of sub-matrix.

[0057] For simplicity of description, a group of sub-matrices is referred to as a "row of sub-matrices".

[0058] Those skilled in the art understand that the principles of the invention as described remain applicable to any other arrangement of groups of sub-matrices.

[0059] [Fig.3] represents a distribution of the control and command signals on rows of sub-matrices, according to the example of a pixel matrix arranged in 3 rows of sub-matrices, and 3 columns of sub-matrices.

[0060] The flow sequencing unit (104) integrated into the control device of the invention (which can also be designated more generally as a video interface), makes it possible to manage the sequencing (a) of global synchronization signals 302 (vertical synchronization VSYNC; horizontal synchronization HSYNC) and clock (PCLK) and (b) of control signals (circuit selection signals CS[0] CS[i]) and signals for transmitting the digital values ​​of the pixels PIXEL_IN to sub-matrices).

[0061] Thus, in general, the flow sequencing unit is configured to:

[0062] - share synchronization and clock signals between all the lines of sub-matrices, such that each synchronization and clock signal drives the plurality of sub-matrix lines; - assigning a selection signal for each row of sub-matrices, such that activating a selection signal of a row of sub-matrices makes it possible to address all the sub-matrices belonging to said row; - assign a data distribution bus respectively to each of the sub-matrix columns, such that the activation of a data transmission signal makes it possible to send digital data in parallel on said buses to all the sub-matrices.

[0063] [Fig.3] thus illustrates the specific cross-interconnection according to the invention of the different signals, in a view called "box" on which the circuits are positioned. From the outside, the box has on the front face (or first face) the pixel matrix comprising all the emissive pixel circuits, and on the rear face (or face opposite the first face) the different signals coming from the video interface and which are distributed to the different circuits according to the cross interconnection scheme of the invention. It is thus possible to pool the signals at the box level.

[0064] Advantageously, the global synchronization signals 302 are shared, i.e. shared between all the sub-matrices, and each synchronization signal is connected to all the circuits of the matrix. Thus, the flow sequencing unit allows the vertical and horizontal synchronization signals and the clock signal to be shared between all the sub-matrix lines, such that each of the synchronization and clock signals each drives the plurality of sub-matrix lines.

[0065] The sub-matrix grouping sequencing mode makes it possible to generate and assign a selection signal (CS) for each row of sub-matrices. Thus, the flow sequencing unit makes it possible to assign a pixel circuit selection signal to each row of sub-matrices, such that activating a selection signal for a row makes it possible to address all the sub-matrices belonging to said row of sub-matrices.

[0066] In an “orthogonal” manner, the signals enabling the transmission of digital data to the matrix circuits are shared between the different lines of sub-matrices. The video interface enables data to be transmitted in parallel on several PIXEL_IN transmission buses. Thus, the flow sequencing unit enables a data transmission signal to be assigned to each PIXEL_IN data distribution bus, respectively for each of the L columns of sub-matrices (PIXEL_IN[1] [N] with 1 = 1 to L, and N = the number of bits per pixel). Activating a data transmission signal enables digital data to be sent in parallel on the buses to all the sub-matrices.

[0067] [Fig.4] illustrates the parallel sending of digital data on three distribution buses (PIXEL_IN[1], PIXEL_IN[2], PIXEL_IN[3]), depending on the selection by the selection signal (CS[0], CS[1], CS[2]) of different lines of sub-matrices, for the example of a pixel matrix arranged in 3 lines of sub-matrices and 3 columns of sub-matrices.

[0068] Thus, when the selection signal CS[0] is active (i.e. the signal serving the first row of sub-matrices), the digital data are sent in parallel via the transmission buses PIXEL_IN[1], PIXEL_IN[2], PIXEL_IN[3], to the three sub-matrices (1, 2, 3) of the first row. Similarly, when the selection signal CS[1] is in turn active (i.e. the signal serving the second row of sub-matrices), the digital data are sent in parallel via the transmission buses PIXEL_IN[1], PIXEL_IN[2], PIXEL_IN[3], to the three sub-matrices (4, 5, 6) of the second row. When the selection signal CS[2] is in turn active (i.e. the signal serving the third row of sub-matrices), the digital data is sent in parallel via the transmission buses PIXEL_IN[1], PIXEL_IN[2], PIXEL_IN[3], to the three sub-matrices (7, 8, 9) of the third row.

[0069] Advantageously, the arrangement of the matrix in lines of sub-matrices makes it possible to share the same video interface to successively transmit the lines of images to the different lines of sub-matrices, as illustrated in Figures 5a and 5b.

[0070] [Fig.5a] illustrates for the duration P of an image N, the sequencing produced by the device of the invention for a matrix arranged in three lines of sub-matrices, and [Fig.5b] illustrates the interlacing of the transmission of the image lines between the different lines of sub-matrices, from a video interface point of view.

[0071] The device of the invention thus makes it possible to share the signals at the box level. In addition, with the adjustment of the various parameters (number G of sub-matrix groups, number K of image lines, conversion time, transfer time of line), it is possible to have a continuous transmission of pixels while hiding the conversion time. Advantageously, this allows the frequency to be reduced compared to a serial transmission.

[0072] Furthermore, it should be noted that for a sub-matrix, the line transfer and conversion (Conv) phases do not overlap, which allows better decoupling between the digital pixel acquisition circuits and the digital / analog conversion chain. This also makes it possible to avoid using a double storage buffer.

[0073] [Fig.6] schematically represents an example of implementation of a device 604 for controlling a digital video stream according to the invention, on an electronic card 606.

[0074] The electronic card also integrates an adaptation circuit 603 which performs a function of converting a video stream, received from a video source 602 from a standard interface (for example from a computer with a graphics card via an HDMI cable), to the video stream control device 604.

[0075] The video stream control device 604 produces an arrangement 610 of 9 sub-matrices (sub-matrix 1 sub-matrix 9) for a pixel matrix integrated on a housing 608.

[0076] The video stream control device 604 also generates the sequencing of the various control and command signals (612, 614, 616) of the sub-matrices. The various control and command signals (612, 614, 616) are distributed at the level of the box according to the described configuration of a pooling of the synchronization signals (VSYNC, HSYNC) and PCLK clock signals between all the sub-matrix lines, and of an orthogonal distribution of the pixel circuit selection signals CS for the sub-matrix lines and of the digital data distribution signals PIXEL_in for the sub-matrix columns.

[0077] [Fig.7] schematically represents an implementation of circuits allowing a display on a set of 702 pixels.

[0078] In this embodiment, the digital data PIXEL_IN distributed via the transmission buses are received serially and stored in shift registers 708 during the transmission phase.

[0079] During the digital / analog conversion phase, a ramp DAC converter 710 scans through all the voltage values, and a comparator and sampling logic 712 makes it possible to distribute the target voltages at each pixel 702.

[0080] No further details are given of the arrangements for data storage, ramp DAC conversion and pixel level control, which are operations whose implementation, according to different implementations, is within the reach of the person skilled in the art.

[0081] [Fig.8] schematically illustrates a display produced with a reduced image resolution. The sequencing of the video stream carried out by the control device of the invention addresses a reduced number of sub-matrices.

[0082] In one embodiment, the flow sequencing unit comprises a row selection module configured to select one or more sub-matrix rows to activate all circuits belonging to said sub-matrix row.

[0083] In one embodiment, the stream sequencing unit comprises a column selection module configured to select one or more columns of sub-matrices to send digital data to all sub-matrices connected to each bus of the selected columns.

[0084] In the illustrated example of a matrix divided into three rows of sub-matrices, it can be defined to drive the circuit selection signal CS on the first two rows of sub-matrices, and to drive the distribution of the pixel values ​​only on the last two columns of sub-matrices. This makes it possible to select the sub-matrices (2, 3) of the first row of sub-matrices and the sub-matrices (5, 6) of the second row of sub-matrices, and to display only the pixels of the circuits of the sub-matrices (2, 3, 5, 6). This makes it possible to reduce the definition of the image by a third horizontally and vertically.

[0085] The flow control device of the invention allows operation in “rolling shutter” mode or in “global shutter” mode. [Fig.9] schematically illustrates the management of a display in “global shutter” mode, according to one embodiment of the invention.

[0086] The flow sequencing operated by the control device of the invention introduces a time shift between the different groups of pixel sub-matrices. However, the simultaneous display of an image (i.e. the “global shutter” mode) remains possible without shifting the frame synchronization signals (VSYNC and HSYNC) between the sub-matrices.

[0087] For this, the control device comprises a 'global shutter' type processing unit which makes it possible to manage the offset between a synchronization signal and an actual display of an image.

[0088] In one embodiment, the 'global shutter' unit comprises a counter in each sub-matrix counting the same number of clock cycles. An adjustment of the various parameters (number of sub-matrices, number G of groups of sub-matrices, number K of image lines) makes it possible to synchronize the display of the image at a time when all the pixels of an image N have been converted while the conversion phase of the image N+1 is not yet finished (which would otherwise have the undesirable effect of replacing the values ​​of the pixels N by those of the pixels N+1).

Claims

Claims

1. Device (100) for controlling a digital video stream to be transmitted to a pixel matrix (120) integrated on the front face of a housing (130), the housing grouping on the rear face a set of control and command signals, the control device comprising: - a matrix arrangement unit (102) configured to define the pixel matrix by a plurality of pixel sub-matrices, and group the sub-matrices into a plurality of rows of sub-matrices and a plurality of columns of sub-matrices;- a flow sequencing unit (104), configured to: - share synchronization and clock signals between all the sub-matrix lines, such that each synchronization and clock signal controls the plurality of sub-matrix lines, - assign a selection signal to each sub-matrix line, such that the activation of a selection signal for a line makes it possible to address all the sub-matrices belonging to said line, - assign a data distribution bus respectively to each of the sub-matrix columns, such that the activation of a data transmission signal for said buses makes it possible to send digital data in parallel on said buses to all the sub-matrices of each sub-matrix column.;

2. The device according to claim 1 wherein the matrix arrangement unit is configured to define a number of sub-matrices according to an image resolution to be displayed by the pixel matrix.

3. The device according to claim 1 or claim 2 wherein the stream sequencing unit comprises a row selection module configured to select at least one row of sub-matrices, such that the activation of a selection signal for a row makes it possible to address all the sub-matrices belonging to said row of sub-matrices.

4. The device according to any one of claims 1 to 3 wherein the flow sequencing unit comprises a column selection module configured to select at least one column of sub-matrices, such that activation of the transmission signal makes it possible to send digital data in parallel to all the sub-matrices of the selected columns.

5. The device according to any one of claims 1 to 4 in in which the box is connected to an electronic card, said card comprising an adaptation circuit for converting into digital data, a video stream provided by an external video source.

6. The device according to any one of claims 1 to 5 wherein each circuit of the pixel matrix further comprises shift registers for storing digital data.

7. The device according to any one of claims 1 to 6 wherein each circuit of the pixel array further comprises a ramp digital-to-analog conversion unit for converting digital data into analog voltages to be applied to the emissive pixel circuits of the array.

8. The device according to any one of claims 1 to 7 further comprising a 'global shutter' type processing unit making it possible to manage the offset between a synchronization signal and an actual display of an image.

9. A display system comprising a device for controlling a digital video stream according to any one of claims 1 to 8.

10. The display system according to claim 9 wherein the pixel matrix is ​​a 1050 x 1050 pixel matrix, the matrix arrangement unit makes it possible to define an arrangement of 25 pixel sub-matrices in 5 groups of sub-matrices of 210 x 210 pixels each, organized in 5 rows of sub-matrices and 5 columns of sub-matrices.

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