Zero current detector

Abstract

Zero current detector The present description relates to a zero current detection circuit (101) comprising: - a first comparator (101-Comp) configured to compare a first voltage (Vsw100), representative of a first current (IL101), to a first threshold voltage (Vos101); - a calibration circuit (101-CAL) configured to modify the value of the first threshold voltage (Vos101) given variations in process, voltage and / or temperature. Figure for abstract: Fig. 1

Description

Title of the invention: Zero current detector Technical field

[0001] The present description relates generally to electronic devices and circuits. More particularly, the present description relates to a zero current detection circuit. Prior art

[0002] Zero current detection circuits are circuits that can sense a current in order to detect when said current is equal to zero. They are commonly used in voltage converter circuits, such as DC-DC converters.

[0003] It would be desirable to at least partially improve certain aspects of known zero current detection circuits. Summary of the invention

[0004] There is a need for a zero current detection circuit having relatively high accuracy.

[0005] One embodiment overcomes all or part of the drawbacks of known zero current detection circuits.

[0006] One embodiment provides a zero current detection circuit comprising: - a first comparator configured to compare a first voltage, representative of a first current, to a first threshold voltage; - a calibration circuit configured to modify the value of the first threshold voltage given variations in process, voltage and / or temperature.

[0007] According to one embodiment, said first threshold voltage is an offset voltage of said first comparator.

[0008] According to one embodiment, said calibration circuit comprises a second comparator circuit.

[0009] According to one embodiment, said second comparator circuit is more precise than the first comparator.

[0010] According to one embodiment, the circuit comprises a logic circuit configured to be the main control circuit of the zero current detection circuit.

[0011] Another embodiment provides a DC-DC converter comprising a zero current detection circuit described previously.

[0012] According to one embodiment, the converter comprises two switches connected in series and a coil, one of the terminals of which is connected to the middle node between said two switches.

[0013] According to one embodiment, said zero current detection circuit is configured to detect when the current in said coil is equal to zero. Brief description of the drawings

[0014] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0015] [Fig.l] represents an example of application of an embodiment of a zero current detection circuit;

[0016] [Fig.2] is a timing diagram illustrating an example of operation of a zero current detection circuit;

[0017] [Fig.3] is a block diagram representing a zero current detector according to a mode of realization;

[0018] [Fig.4] shows in more detail a circuit of the embodiment of [Fig.3];

[0019] [Fig.5] shows in more detail another circuit of the embodiment of the [Fig.3] ;

[0020] [Fig.6] shows in more detail another circuit of the embodiment of the [Fig.3] ;

[0021] [Fig.7] represents, in more detail and partly in block form, another circuit of the embodiment of [Fig.3];

[0022] [Fig.8] shows in more detail a part of the circuit of [Fig.7];

[0023] [Fig.9] shows in more detail a part of the circuit of [Fig.7];

[0024] [Fig. 10] shows in more detail a part of the circuit of [Fig.7];

[0025] [Fig.l 1] shows in more detail a part of the circuit of [Fig.7]; and

[0026] [Fig. 12] shows in more detail another circuit of the embodiment of the [Fig.3], Description of the embodiments

[0027] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0028] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.

[0029] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0030] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0031] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0032] [Fig.l] represents, very schematically and partly in block form, a DC-DC converter circuit 100 comprising an embodiment of a zero current detection circuit (ZCD) 101.

[0033] The DC-DC converter circuit 100 comprises two switches S101 and S102 connected in series between a first node receiving an input voltage Vin100 and a second node receiving a first reference voltage PWRGND100, for example, ground.

[0034] According to an example, switches S101 and S102 are both metal-oxide-semiconductor field-effect transistors, also called MOSFET transistors or MOS transistors. More particularly, switch S101 is a P-type MOS transistor, also called a P-channel MOS transistor or PMOS transistor, and switch S102 is an N-type MOS transistor, also called an N-channel MOS transistor or NMOS transistor. The source terminal of switch S101 is connected, preferably connected, to the first node that receives the input voltage Vin100, and the drain terminal of switch S101 is connected, preferably connected, to the drain terminal of switch S102. The source terminal of switch S102 is connected, preferably connected, to the second node that receives the reference voltage PWRGND100. The gate terminals of the switches receive control voltages from a control circuit 102 (Logic Driving).More particularly, switch S101 receives a control voltage PdrvlOO from control circuit 102 at its gate terminal, and switch S102 receives a control voltage NdrvlOO from control circuit 102 at its gate terminal.

[0035] According to another example, switches S101 and S102 are both NMOS transistors.

[0036] According to another example, the switches S101 and S102 can be implemented by another type of transistor, for example by bipolar transistors.

[0037] The control circuit 102 is a circuit which can provide the control voltages PdrvlOO and NdrvlOO after receiving two pulse signals PonlOO and Non 100 from a pulse modulator circuit 103 (Puise Mod) and a control voltage VZCD100 from the embodiment of the detection circuit of zero current 101. According to one example, the signals Pon100 and Non 100 are non-overlapping signals. The person skilled in the art will understand how such a circuit can be implemented. According to one example, the pulse modulator circuit 103 is supplied by a supply voltage AVD100 and a second reference voltage GND100 different from the first reference voltage PWRGND100.

[0038] The pulse modulator circuit 103 is a circuit that can provide the two pulse signals Pon100 and No 100 based on a reference voltage Vrefl00. The reference voltage Vref 100 is different from the reference voltage GND100. The person skilled in the art will understand how to implement such a circuit.

[0039] The DC-DC converter circuit 100 further comprises a coil L101 connected between the middle node between the switches S101 and S102, referenced A101, and corresponding to the drain terminals of the switches S101 and S102, and an output node BIOL. The zero current detection circuit 101 is configured to monitor the input current IL101 of the coil L101. The voltage between the node A101 and the reference voltage GND100 is designated Vswl00. The output voltage Vout100 of the DC-DC converter 100 is provided between the node B101 and the node which receives the reference voltage GND100.

[0040] The DC-DC converter circuit 100 further comprises a capacitor C101 connected between the node B101 and the node which receives the second reference voltage GND100.

[0041] The DC-DC converter circuit 100 further comprises a current source 1101 connected between the node B101 and the node which receives the second reference voltage GND100.

[0042] According to one embodiment, the zero current detection circuit 101 comprises a comparator 101-Comp which can compare the voltage Vswl00 to a threshold voltage Vosl01. The voltage Vswl00 is representative of the input current IL101 of the coil L101. The threshold voltage Vosl01 is used to compensate for an internal offset and delay of the comparator 101-Comp due, for example, to process, voltage and temperature (PVT) variations.

[0043] The zero current detection circuit 101, also referred to herein as the zero current detector 101, further comprises a voltage source 101-Vos that provides the threshold voltage Vos101, and an automatic calibration circuit 101-CAL. According to one embodiment, the automatic calibration circuit 101-CAL is used to configure the voltage source 101-Vos to account for environmental variations, such as temperature variations, and / or manufacturing variations such as process variations and / or voltage variations. In other words, the automatic calibration circuit 101-CAL is used to account for what are frequently referred to as PVT variations of the comparator 101-Comp, where PVT denotes process, voltage, and temperature.

[0044] The operation of the zero current detection circuit 101 is described in more detail in connection with [Fig.2].

[0045] The voltage VswlOO is generated by the switching actions of the DC-DC converter via the power switches S101 and S102. More particularly,

[0046] The basic DC-DC operation is as follows.

[0047] When switch S101 is on, switch S102 is off (controlled via voltages Pdrv and Ndrv), the node that supplies voltage VswlOO receives voltage VinlOO via switch S101, output voltage VoutlOO, capacitor C101 and inductor L101 are charged (so that the current in inductor IL101 increases according to a ramp).

[0048] When switch S101 is blocked, switch S102 is on (controlled via signals Pdrv and Ndrv), the node which supplies voltage VswlOO receives voltage PWRGND100 via switch S102, output voltage VoutlOO, capacitor C101 and inductor L101 are discharged (so that the current in inductor IL101 decreases according to a ramp).

[0049] The operation of the zero current detector is as follows.

[0050] The voltage VxwlOO is used to detect the state of the inductor current during the ramp-down of the inductor L101 in the phase during which the switch S101 is blocked and the switch S102 is conducting.In particular: - if switch S102 is blocked before the current in the inductor reaches zero amperes, the current in the inductor will switch the body diode of switch S102, and therefore the voltage VswlOO is equal to a voltage -VD corresponding to the opposite of a voltage VD of the body diode of switch S102, which means that the main comparator of the ZCD detects a zero current state too early, and - if switch S102 is blocked after the current in the inductor reaches zero amperes, the current in the inductor continues to flow into switch S102, and therefore the voltage VswlOO is equal to a voltage equal to the product of the value of the current in the inductor and the on-resistance of the N-type power switch S102, which means that the main comparator of the ZCD detects a zero current state too late.

[0051] Too early or too late detections are then corrected by the ZCD loop which will be described in more detail later. This ZCD loop block also has a comparator which compares the voltage Vswl00 to the voltage PWRGND100 and governs a correction voltage which will be described later. This correction voltage Vcorr300 then modifies the offset voltage of the main comparator via the currents described later.

[0052] [Fig. 2] is a timing diagram illustrating an example of operation of the DC-DC converter circuit 100 described in relation to [Fig. 1] and, more particularly, illustrating the operation of the zero current detection circuit 101.

[0053] [Fig.2] includes: - a curve 201 representing the temporal evolution of the pulse voltage PonlOO; - a curve 202 representing the temporal evolution of the NonlOO pulse voltage; - a curve 203 representing the temporal evolution of the control voltage PdrvlOO; - a curve 204 representing the temporal evolution of the control voltage NdrvlOO; - a curve 205 representing the temporal evolution of the input current IL101 of the coil L101; - a curve 206 representing the time evolution of the voltage VswlOO; and - a curve 207 representing the time evolution of the control voltage VZCD100.

[0054] Each rising edge of the pulse voltage PonlOO triggers a rising edge of the control voltage PdrvlOO. This causes the input voltage VinlOO to be transferred into the coil L101. Thus, the current IL101 increases. Similarly, each falling edge of the pulse voltage PonlOO triggers a falling edge of the control voltage PdrvlOO, which stops the growth of the current IL101.

[0055] Each rising edge of the pulse voltage NonlOO causes a rising edge of the control voltage NdrvlOO. This causes the reference voltage GND100 to be transferred into the coil L101. Thus, the current IL 101 decreases.

[0056] However, a falling edge of the pulse signal Non100 does not cause a falling edge of the control voltage Nrdv100. A falling edge of the pulse signal Non100 is controlled by the control circuit 102 based on an internal delay configured by the circuit 102 and based on the control circuit VZCD100 provided by the zero current detection circuit 101. More particularly, a falling edge of the control voltage Ndrv100 will appear when the current IL 101 reaches zero amperes.

[0057] The threshold voltage Vos 101 is assumed to be sized to compensate for an internal offset voltage of the comparator 101-Comp and to take into account a delay TdrvlOO of the control circuit 102. The delay TdrvlOO corresponds to the duration between an instant at which the control circuit detects a rising edge of the control voltage VZCD100 and an instant at which the control circuit causes a falling edge of the control voltage NdrvlOO. However, due to PVT variations, the threshold voltage VoslOl must generally be adjusted in real time, to ensure high accuracy of the DC-DC converter circuit 100.

[0058] [Fig. 3] is a block diagram showing one embodiment of a zero current detection circuit 300 of a type similar to the zero current detection circuit 101 described in connection with [Fig. 1].

[0059] The zero current detection circuit 300, also referred to hereinafter as the zero current detector 300 or ZCD circuit 300, comprises: - a logic circuit 301 (LOGIC Control); - a comparator 302 (Comparator); - a circuit 303 (Right Push); And - a 304 circuit (ZCD Turn).

[0060] The logic circuit 301 is the main control circuit of the ZCD circuit 300. The logic circuit 301 provides an external control voltage Non-ZCD300 similar to the control voltage VZCD100 described in connection with [Fig. 1]. According to an example, the logic circuit 301 further provides internal currents and voltages, such as voltages ACT300, ACTB300, Poni300, Noni300, AfterN300 and NdrviB300 which will be described in more detail in connection with FIGS. 4 to 12. An example of the logic circuit 301 will be described in more detail in connection with [Fig. 12].

[0061] According to one example, the logic circuit 301 receives an internal reset voltage RSTN300, which will be described in more detail in relation to FIGS. 4 to 12, and external voltages such as: - an activation voltage EN300 which will be described in more detail in relation to figures 4 to 12; - a voltage Pon300 of a type similar to the voltage Pon100 described in relation to [Fig.l], and which will be described in more detail in relation to figures 4 to 12; and - a voltage Ndrv300 of a type similar to the voltage NdrvlOO described in relation to [Fig.l], and which will be described in more detail in relation to figures 4 to 12.

[0062] Comparator 302 is the main comparator of the zero current detection circuit 300. Comparator 302 is of a type similar to comparator 101-Comp described in connection with [Fig.l]. According to one example, comparator 302 receives the following currents and voltages: voltages ACTB300, Ndrvi300, PWRGND100, VswlOO, VPP300 and VPN300, which will be described in more detail in connection with FIGS. 4 to 12 and currents Icorr300 and IcorrAVS300, which will be described in more detail in connection with FIGS. 4 to 12.

[0063] According to one example, the comparator 302 is configured to generate the reset voltage RSTN300 and a voltage VBP300 which will be described in more detail in relation to figures 4 to 12. According to an example, the voltage VBP300 is a bias voltage.

[0064] The combination of circuits 303 and 304 constitutes an automatic calibration circuit of a type similar to that of the automatic calibration circuit 101-CAL described in connection with [Fig. 1].

[0065] Circuit 303 is a circuit that can detect when the internal offset voltage of comparator 302 causes false detection of the monitored current. More particularly, circuit 303 can generate a push signal whenever the comparator detects that the monitored current is positive due to the value of the offset voltage. The operation of circuit 303 will be described in connection with [Fig.6].

[0066] According to one example, the circuit 303 receives a voltage VBP300, a correction voltage Vcorr300 and a voltage SWON300 which will be described in more detail in relation to FIGS. 4 to 12.

[0067] According to one example, the circuit 303 is configured to generate a voltage ACT300 and a current IPR300. According to one example, the current IPR300 is supplied to the comparator 302.

[0068] As previously indicated, circuit 304 is part of the automatic calibration circuit and is used to correct the offset voltage of comparator 302. Circuit 304 receives, for example, voltage Poni300, voltage Noni300, voltage AfterN300, voltage ACT300, voltage VswlOO and reference voltage PWRGND100.

[0069] The circuit 304 is, for example, configured to generate the following voltages and currents: - the correction voltage Vcorr300; - SWON300 voltage; - the current Icorr300; and - the IcorrAVS300 current.

[0070] [Fig.4] shows in more detail an example of a logic circuit 400 intended to implement the logic circuit 301 of the zero current detection circuit 300 described in relation to [Fig.3].

[0071] As previously described, the logic circuit 400 receives the voltages Pon300, EN300 and Ndrv300.

[0072] The logic circuit 400 comprises, for example, three inverters INV401, INV402 and INV403 and a NOR gate NOR401. The inverter INV401 receives the voltage Pon300 and the inverter INV402 receives the voltage EN300. A first input of the NOR gate NOR401 is connected, preferably connected, to the output of the inverter INV401 and a second input of the NOR gate NOR401 is connected, preferably connected to the output of the inverter INV402 which provides an ENiB400 voltage. An input of the inverter INV403 is connected, preferably connected, to the output of the inverter INV402.

[0073] The logic circuit 400 further comprises a flip-flop FF401, an inverter INV404 and three NOR gates NOR402, NOR403 and NOR404.

[0074] The FF401 flip-flop is a D-type bistable flip-flop, comprising three inputs R, CLK and D and two outputs Q and Q. The D input of the FF401 flip-flop receives a supply voltage AVD100, and the CLK input of the FF401 flip-flop is connected, preferably connected, to an output of the inverter INV404 and receives a voltage PoniB400. An input of the inverter INV404 is connected, preferably connected, to an output of the NOR gate NOR401 which provides the voltage Poni300.

[0075] A first input of the NOR402 NOR gate is connected, preferably connected, to the Q output of the FF401 flip-flop, a second input of the NOR402 NOR gate is connected, preferably connected, to an output of the NOR403 NOR gate. An output of the NOR402 NOR gate is connected, preferably connected, to a first input of the NOR403 NOR gate.

[0076] A second input of the NOR403 NOR gate is connected, preferably connected, to the output of the NOR401 NOR gate. A third input of the NOR403 NOR gate receives the reset voltage RST300 and a fourth input of the NOR403 NOR gate receives the voltage ENiB300.

[0077] A first input of the NOR404 NOR gate provides the voltage Noni300 and is connected, preferably connected, to the output of the NOR403 NOR gate and a second input of the NOR404 NOR gate receives the voltage EniB400. An output of the NOR404 NOR gate is connected, preferably connected, to the reset input R of the FF40L flip-flop

[0078] The logic circuit 400 further comprises two inverters INV405 and INV406. An input of the inverter INV405 is connected, preferably connected, to the output of the NOR gate NOR403 and an output of the inverter INV405 is connected, preferably connected, to an input of the inverter INV406. An output of the inverter INV406 provides the voltage NON-ZCD300.

[0079] The logic circuit 400 further comprises a second flip-flop FF402, two inverters INV407 and INV408, a level shift circuit LS401 (LS), another NOR gate NOR405 and a delay element D401.

[0080] The FF402 flip-flop is a D-type bistable flip-flop, comprising three inputs R, CLK and D and two outputs Q and Q. The D input of the FF402 flip-flop receives the voltage Poni300. The CLK input of the FF402 flip-flop receives the voltage NdrviB300 and is connected, preferably connected, to an output of the inverter INV407 and to an input of the inverter INV408. An input of the inverter INV407 is connected, preferably connected, to an output of the level shifter LS401 and an output of the inverter INV408 provides a voltage Ndrvi300. According to an example, an input of the level shifter LS401 receives the voltage Ndrv300. The output Q of the flip-flop FF402 provides the voltage AfterN300, and is connected, preferably connected, to an input of the delay element D401.

[0081] An output of the delay element D401 provides the voltage AfterNRST400, and is connected, preferably connected, to a first input of the NOR gate NOR405. A second input of the NOR gate NOR405 receives the voltage ENiB400. An output of the NOR gate NOR405 is connected, preferably connected, to the reset input R of the flip-flop FF402.

[0082] The logic circuit 400 further comprises two NOR gates NOR406 and NOR407 and two inverters INV409 and INV410. A first input of the NOR gate NOR406 receives the voltage Poni300 and a second input of the NOR gate NOR406 is connected, preferably connected, to an output of the NOR gate NOR407. An output of the NOR gate NOR406 is connected, preferably connected, to an input of the inverter INV409 and to a first input of the NOR gate NOR407. An output of the inverter INV409 provides the voltage ACT300 and is connected, preferably connected, to an input of the inverter INV410 and an output of the inverter INV410 provides the voltage ACTB300.

[0083] A second input of the NOR407 NOR gate receives the voltage EniB400. A third input of the NOR407 NOR gate receives the voltage AfterNRST400.

[0084] [Fig.5] shows in more detail an example of a comparator 500 intended to implement the main comparator 101-COMP of the zero current detection circuit 100 described in relation to [Fig.1] or the main comparator 302 of the zero current detection circuit 300 described in relation to [Fig.3].

[0085] As previously described, the comparator 500 receives the voltages ACTB300, NdrvIB300, PWRGND100, VswlOO, VPP300, VPN300 and the currents Icorr300, IcorrAVS300 and IPR300.

[0086] The comparator 500 comprises, for example, a PMOS transistor T501 which receives on its gate terminal the voltage ACT300. A source terminal of the transistor T501 is connected, preferably connected, to a node which provides the supply voltage AVD100. A drain terminal of the transistor T501 is connected, preferably connected, to a gate terminal of a first differential pair. The transistor T501 is, for example, controlled by a circuit similar to the circuit 301 described in relation to [Fig. 3] or to the circuit 400 described in relation to [Fig. 4]. The transistor T501 is used to deactivate the comparator 400 if necessary.

[0087] The first differential pair comprises two PMOS transistors T502 and T503. A source terminal of transistor T502 and a source terminal of transistor T503 are connected, preferably connected, to each other and to the source terminal of transistor T501 and to the node that provides the supply voltage AVD100. A gate terminal of transistor T502 and a gate terminal of transistor T503 are connected, preferably connected, to each other and to the drain terminal of transistor T501.

[0088] The comparator 500 further comprises a PMOS transistor T504, an NMOS transistor T513 and a current source C501. A source terminal of the transistor T504 is connected, preferably connected, to the node that provides the supply voltage AVD100. A drain terminal of the transistor T504 receives the bias voltage VBP300. A gate terminal of the transistor T504 is connected, preferably connected, to the gate terminals of the transistors T502 and T503 and receives the bias voltages VBP300. A source terminal of the transistor T513 receives a current generated by the current source C501. A drain terminal of the transistor T513 is connected, preferably connected, to the drain terminal of the transistor T504. A gate terminal of the transistor T513 receives the voltage ACT300. The current source C501 receives the reference voltage GND100. Transistors T504 and T513 and current source C501 are used for biasing.

[0089] The comparator 500 further comprises two PMOS transistors T514 and T515, two NMOS transistors T516 and T517 and a resistor R503. A source terminal of the transistor T514 is connected, preferably connected, to the node which provides the supply voltage AVD100. A drain terminal of the transistor T514 is connected, preferably connected, to the gate terminal of the transistor T515 and to the drain terminal of the transistor T516. A gate terminal of the transistor T514 receives the bias voltage VBP300. A source terminal of the transistor T515 receives the bias voltage VBP300. A drain terminal of the transistor T514 is connected, preferably connected, to a first terminal of the resistor R503. A source terminal of the transistor T516 is connected, preferably connected, to a source terminal of the transistor T517. One gate terminal of transistor T516 receives voltage ACTB300. One gate terminal of transistor T517 receives voltage ACT300.These transistors T514 to T517 are used to quickly lower the VBP300 bias voltage when the ACT300 voltage is equal to a high level.

[0090] The comparator 500 further comprises, for example, a second differential pair comprising two PMOS transistors T505 and T506. A source terminal of the transistor T505 is connected, preferably connected, to the drain terminal of the transistor T502. A source terminal of the transistor T506 is connected, preferably connected, to the drain terminal of the transistor T503. Gate terminals of the transistors T505 and T506 are connected, preferably wired, to each other and to a node that receives the VPP300 voltage.

[0091] The comparator 500 further comprises, for example, a level shift circuit LS501 (LS-RST) and an inverter INV501. An input of the level shift circuit LS501 is connected, preferably connected, to the drain terminal of the transistor T506. An output of the level shift circuit LS501 is connected, preferably connected, to an input of the inverter INV501. An output of the inverter INV501 provides the reset voltage RSTN300.

[0092] The comparator 500 further comprises, for example, a current mirror comprising two NMOS transistors T507 and T508. A drain terminal of the transistor T507 is connected, preferably connected, to the drain terminal of the transistor T505 and to the gate terminals of the transistors T507 and T508. A drain terminal of the transistor T508 is connected, preferably connected, to the drain terminal of the transistor T506.

[0093] The comparator 500 further comprises, for example, a third differential pair comprising two NMOS transistors T509 and T510. A source terminal of the transistor T509 is connected, preferably connected, to the source terminal of the transistor T507. A source terminal of the transistor T510 is connected, preferably connected, to the source terminal of the transistor T508. A gate terminal of the transistor T509 and a gate terminal of the transistor T510 are connected, preferably connected, to each other and to a node which receives the voltage VPN300.

[0094] According to one example, the current Icorr300 may be supplied to the comparator 500 at the source terminals of the transistors T508 and T510.

[0095] The comparator 500 further comprises, for example, a PMOS transistor T518. A source terminal of the transistor T518 receives the current IcorrAVS300 and the current IRP300. A drain terminal of the transistor T518 is connected, preferably connected, to the drain terminal of the transistor T509. A gate terminal of the transistor T518 is connected, preferably connected, to the node which receives the voltage VPP300.

[0096] The comparator 500 further comprises two resistors R501 and R502. A first terminal of the resistor R501 is connected, preferably connected, to a drain terminal of the transistor T509 and a second terminal of the resistor R501 is connected, preferably connected, to a node which receives the reference voltage PWRGND100. A first terminal of the resistor R502 is connected, preferably connected, to a drain terminal of the transistor T510 and a second terminal of the resistor R502 is connected, preferably connected, to a node which receives the voltage VswlOO.

[0097] Transistors T502, T503, T507 and T508 and resistors R501 and R502 constitute, for example, comparator 500. Transistors T505, T506, T509 and T510 are, for example, protection devices.

[0098] The comparator 500 further comprises, for example, a level shift circuit LS502 (LS) and an NMOS transistor T511. An input of the level shift circuit LS502 receives the voltage NdrviB300. An output of the level shift circuit LS502 is connected, preferably connected, to a gate terminal of the transistor T511. A drain terminal of the transistor T511 is connected, preferably connected, to the drain terminals of the transistors T506 and T508. A source terminal of the transistor T511 receives the reference voltage PWRGND100.

[0099] The comparator 500 further comprises, for example, a level shift circuit LS503 (LS) and an NMOS transistor T512. An input of the level shift circuit LS503 receives the voltage ACTB300. An output of the level shift circuit LS503 is connected, preferably connected, to a gate terminal of the transistor T512. A drain terminal of the transistor T512 is connected, preferably connected, to the drain terminals of the transistors T505 and T507. A source terminal of the transistor T512 receives the reference voltage PWRGND100.

[0100] According to one example, the comparator 500 does not use the same ground domain as the other circuits of the zero current detection circuit. In such a case, the level shift circuits LS501, LS502 and LS503 are used, for example, to switch the ground domains within the comparator 500.

[0101] [Fig.6] shows in more detail an example of a circuit 600 for implementing the circuit 303 of the zero current detection circuit 300 described in relation to [Fig.3].

[0102] As previously described, the circuit 600 receives the voltages VACT300, VBP300, SWON300 and Vcorr300 and the current IPR300.

[0103] The circuit 600 comprises, for example, a PMOS transistor T601 which receives at its gate terminal the voltage ACT300. A source terminal of a transistor T601 is connected, preferably connected, to a node which provides the supply voltage AVD100. A drain terminal of the transistor T601 is connected, preferably connected, to a gate terminal of a first differential pair. The transistor T601 is controlled by a circuit of a type similar to the circuit 301 described in relation to [Fig. 3] or to the circuit 400 described in relation to [Fig. 4]. The transistor T601 is used to deactivate the circuit 600 if necessary.

[0104] The first differential pair comprises, for example, two PMOS transistors T602 and T603. A source terminal of the transistor T602 and a source terminal of the transistor T603 are connected, preferably connected, to each other and to the source terminal of the transistor T601 and to the node that provides the supply voltage AVD100. A gate terminal of the transistor T602 and a gate terminal of the transistor T603 are connected, preferably connected, to each other and to the drain terminal of the transistor T601.

[0105] The circuit 600 further comprises, for example, a current source C601 and an NMOS transistor T615. A source terminal of the transistor T615 receives a current from the current source C601. A drain terminal of the transistor T615 is connected, preferably connected, to the drain terminal of the transistor T602. The gate terminal of the transistor T615 receives the voltage ACT300.

[0106] The comparator 600 further comprises, for example, two PMOS transistors T616 and T617, two NMOS transistors T618 and T619 and a resistor R601. A source terminal of the transistor T616 is connected, preferably connected, to the node that provides the supply voltage AVD100. A drain terminal of the transistor T616 is connected, preferably connected, to the gate terminal of the transistor T617 and to the drain terminal of the transistor T619. A gate terminal of the transistor T616 receives the bias voltage VBP300. A source terminal of the transistor T617 receives the bias voltage VBP300. A drain terminal of the transistor T617 is connected, preferably connected, to a first terminal of the resistor R601. A second terminal of the resistor R601 is connected, preferably connected, to a drain terminal of the transistor T618. A source terminal of transistor T618 is connected, preferably connected, to a source terminal of transistor T619.One gate terminal of transistor T619 receives voltage ACTB300. One gate terminal of transistor T618 receives voltage ACT300. These transistors T616 to T619 are used to quickly lower bias voltage VBP300 when voltage AZCT300 is equal to a high level.

[0107] The circuit 600 further comprises, for example, three transistors T604, T605 and T606. A source terminal of the transistor T604 is connected, preferably connected, to a drain terminal of the transistor T603. A drain terminal of the transistor T604 is connected, preferably connected, to the drain terminals of the transistors T605 and T606. Gate terminals of the transistors T604 and T605 are connected, preferably connected, to each other. A gate terminal of the transistor T606 is connected, preferably connected, to a node that receives a correction voltage VCorrôOO. Source terminals of the transistors T605 and T606 are, for example, referenced to ground.

[0108] The circuit 600 further comprises, for example, two inverters INV601 and INV602, a flip-flop FF601 and a NAND gate NAND601. The flip-flop FF601 is, for example, a D-type bistable flip-flop, comprising three inputs R, CLK and D and two outputs Q and Q.

[0109] An input of the inverter INV601 is connected, preferably connected, to the drain terminals of the transistors T604, T605 and T606. An output of the inverter INV601 is connected, preferably connected, to an input of the inverter INV602. An output of the inverter INV602 is connected, preferably connected, to the CLK input of the flip-flop FF601. The D input of the flip-flop FF601 receives, for example, the supply voltage AVD100. The Q output of flip-flop FF601 is connected, preferably connected, to a first input of NAND gate NAND601. A second input of NAND gate NAND601 receives a voltage 16Cy600. A third input of NAND gate NAND601 receives a voltage 2Cy600. A fourth input of NAND gate NAND601 receives a voltage ACT300. An output of NAND gate NAND601 is connected, preferably connected, to the gate terminals of transistors T604 and T605.

[0110] The circuit 600 further comprises, for example, four transistors 607, T608, T609 and T610. A source terminal of the transistor T607 is connected, preferably connected, to the node that provides the supply voltage AVD100. A drain terminal of the transistor T607 is connected, preferably connected, to a source terminal of the transistor T608. A gate terminal of the transistor T607 is connected, preferably connected, to the gate terminals of the transistors T602 and T603.

[0111] A drain terminal of transistor T608 is connected, preferably connected, to the drain terminals of transistors T609 and T610. Gate terminals of transistors T608 and T609 are connected, preferably connected, to each other. A gate terminal of transistor T610 is connected, preferably connected, to a node that receives the correction voltage VCorrôOO. Source terminals of transistors T609 and T610 are referenced to ground.

[0112] The circuit 600 further comprises, for example, two inverters INV603 and INV604, a flip-flop FF602 and a NAND gate NAND602. The flip-flop FF602 is a D-type bistable flip-flop, comprising three inputs R, CLK and D and two outputs Q and Q

[0113] An input of the inverter INV603 is connected, preferably connected, to the drain terminals of the transistors T608, T609 and T610. An output of the inverter INV603 is connected, preferably connected, to an input of the inverter INV604. An output of the inverter INV604 is connected, preferably connected, to the input CLK of the flip-flop FF602. The input D of the flip-flop FF602 receives the supply voltage AVD100. The output Q of the flip-flop FF602 is connected, preferably connected, to a first input of the NAND gate NAND602. A second input of the NAND gate NAND602 receives the voltage 16Cy600. A third input of the NAND gate NAND602 receives a voltage 8Cy600. A fourth input of the NAND gate NAND602 receives a voltage ACT300. An output of the NAND gate NAND602 is connected, preferably connected, to the gate terminals of transistors T608 and T609.

[0114] The circuit 600 further comprises, for example, a second differential pair comprising two PMOS transistors T611 and T612. Source terminals of the transistors T611 and T612 are connected, preferably connected, to the node that provides the voltage AVD100 power supply. Gate terminals of transistors T611 and T612 are connected, preferably connected, to each other and to a node that receives the VBP300 voltage.

[0115] The circuit 600 further comprises, for example, two PMOS transistors T613 and T614. A source terminal of the transistor T613 is connected, preferably connected, to the drain terminal of the transistor T611. A source terminal of the transistor T614 is connected, preferably connected, to the drain terminal of the transistor T612. Drain terminals of the transistors T613 and T614 receive the current IPR300.

[0116] The circuit 600 further comprises, for example, a circuit 610 which provides the voltages 2Cy600, 8Cy600 and 16Cy600.

[0117] The circuit 610 comprises, for example, a NOR gate NOR601 which receives, at a first input, the voltage 16Cy600 and, at a second input, the voltage SWON300.

[0118] The circuit 610 further comprises, for example, five flip-flops FF603, FF6064, FF605, FF606 and FF607. The flip-flops FF603 to FF607 are D-type bistable flip-flops, each comprising three inputs R, CLK and D and two outputs Q and Q. The output of the NOR gate NOR601 is connected, preferably connected, to the CLK terminal of the flip-flop FF603. The Q output of the flip-flop FF603 is connected, preferably connected, to the D input of the flip-flop FF603 and to the CLK terminal of the flip-flop FF604. The Q output of the flip-flop FF604 is connected, preferably connected, to the D input of the flip-flop FF604 and to the CLK terminal of the flip-flop FF605. The Q output of the flip-flop FF604 provides the voltage 2Cy600. The Q output of the FF605 flip-flop is connected, preferably connected, to the D input of the FF605 flip-flop and to the CLK terminal of the FF606 flip-flop. The Q output of the FF606 flip-flop is connected, preferably connected, to the D input of the FF606 flip-flop and to the CLK terminal of the FF607 flip-flop.The Q output of the FF606 flip-flop provides the voltage 8Cy600. The Q output of the FF607 flip-flop provides the voltage 16Cy600.

[0119] Circuit 600 is used to verify the detection of the current in the inductor and ensures that the current in the inductor is negative, i.e., less than zero, to allow the zero current detection circuit to operate properly. There are two phases of operation. During the first phase, after the first two cycles of the SWON signal, if the current in the inductor is positive, transistor T613 is turned on to provide more offset current to the main current comparator by injecting more current into the main current comparator. During the second phase, after the first eight cycles of the SWON signal, if the current in the inductor is still positive, T614 is turned on to provide more offset current to the main current comparator by injecting more current into the main current comparator.

[0120] [Fig.7] shows, in more detail, an example of a circuit 700 intended to implement the circuit 304 of the zero current detection circuit 300 described in relation to [Fig.3].

[0121] As previously described, circuit 700 receives voltages Poni300, Noni300, AfterN300, and ACT300.

[0122] The circuit 700 comprises, for example, a PMOS transistor T701 which receives on its gate terminal the voltage ACT300. A source terminal of the transistor T701 is connected, preferably connected, to a node which provides the supply voltage AVD100. A drain terminal of the transistor T701 is connected, preferably connected, to a gate terminal of a first differential pair. The transistor T701 is for example controlled by a circuit similar to the circuit 301 described in relation to [Fig.3] or to the circuit 400 described in relation to [Fig.4]. The transistor T701 is used to deactivate the circuit 700 if necessary.

[0123] The first differential pair comprises, for example, two PMOS transistors T702 and T703. A source terminal of the transistor T702 and a source terminal of the transistor T703 are connected, preferably connected, to each other and to the source terminal of the transistor T701 and to the node that provides the supply voltage AVD100. A gate terminal of the transistor T702 and a gate terminal of the transistor T703 are connected, preferably connected, to each other and to the drain terminal of the transistor T701.

[0124] The circuit 700 further comprises, for example, two PMOS transistors T704 and T705 and a current source CS701. The source terminal of the transistor T704 is connected, preferably connected, to the node that provides the supply voltage AVD100. The drain terminal of the transistor T704 is connected, preferably connected, to the drain terminal of the transistor T705. The source terminal of T705 is connected, preferably connected, to an input of the current source CS701. A gate terminal of the transistor T704 is connected, preferably connected, to the gate terminals of the transistors T702 and T703. The gate terminal of the transistor T705 receives the voltage ACT300.

[0125] The circuit 700 further comprises, for example, two PMOS transistors T731 and T732, two NMOS transistors T733 and T734 and a resistor T704. A source terminal of the transistor T731 is connected, preferably connected, to the node which receives the voltage AVD100. A drain terminal of the transistor T731 is connected, preferably connected, to a drain terminal of the transistor T734 and to a gate terminal of the transistor T732. A drain terminal of the transistor T731 is connected, preferably connected, to a source terminal of the transistor T732 and to a gate terminal of the transistor T704. A drain terminal of the transistor T732 is connected, preferably connected, to a first terminal of the resistor R704. A second terminal of the resistor R704 is connected, preferably connected, to the drain terminal of the transistor T733. A source terminal of the Transistor T733 is connected, preferably connected, to a source terminal of transistor T734. A gate terminal of transistor T733 receives voltage ACT300. A gate terminal of transistor T734 receives voltage ACTB300. These four transistors constitute a start-up circuit that allows voltage VBPT700 to be quickly lowered when voltage ACT300 reaches a high level.

[0126] The circuit 700 further comprises, for example, a PMOS transistor T706 and an NMOS transistor T707. A source terminal of the transistor T706 is connected, preferably connected, to a drain terminal of the transistor T703. A drain terminal of the transistor T706 is connected, preferably connected, to a drain terminal of the transistor T707. A gate terminal of the transistor T706 receives an AfterNiB700 voltage. A gate terminal of the transistor T707 receives an AfterNiNor700 voltage.

[0127] The circuit 700 further comprises, for example, a level clamping circuit CL701 (CLAMP) described in more detail in relation to [Fig. 8]. An output of the level clamping circuit CL701 is connected, preferably connected, to the source terminal of the transistor T707.

[0128] The circuit 700 further comprises, for example, a current mirror comprising two NMOS transistors T708 and T709. A drain terminal of the transistor T708 is connected, preferably connected, to the gate terminals of the transistors T708 and T709 and to a drain terminal of the transistor T702. A drain terminal of the transistor T709 is connected, preferably connected, to a drain terminal of the transistor T707.

[0129] The circuit 700 further comprises, for example, a differential pair comprising two NMOS transistors T710 and T711. A source terminal of the transistor T710 is connected, preferably connected, to a source terminal of the transistor T708. A source terminal of the transistor T711 is connected, preferably connected, to a source terminal of the transistor T709. Gate terminals of the transistors T710 and T711 are connected, preferably connected, to each other and to a node that receives the voltage VPNT700.

[0130] The circuit 700 further comprises, for example, two resistors R701 and R702. A first terminal of the resistor R701 is connected, preferably connected, to a drain terminal of the transistor T710 and a second terminal of the resistor R701 is connected, preferably connected, to a node which receives the voltage PWRGND100. A first terminal of the resistor R702 is connected, preferably connected, to a drain terminal of the transistor T711 and a second terminal of the resistor R702 is connected, preferably connected, to a node which receives the voltage VswlOO.

[0131] The circuit 700 further comprises, for example, a level shift circuit LS701 and an NMOS transistor T711-2. An input of the level shift circuit LS701 receives the voltage ACTB300. An output of the level shift circuit LS701 is connected, preferably connected, to a gate terminal of the transistor T711-2. A drain terminal of the transistor T711-2 is connected, preferably connected, to the terminal drain terminal of transistor T708. A source terminal of transistor T711-2 is connected, preferably connected, to the second terminal of resistor R701 and to the node that receives the reference voltage PWRGND100.

[0132] The circuit 700 further comprises, for example, a circuit 701 (PROBE) which can exchange voltages with the control circuit 301 of the zero current detection circuit. More particularly, the circuit 701 provides a voltage END700 to, and receives the voltages Noni300 and NoniB300 from, the control circuit 301. In addition, an input of the circuit 701 is connected, preferably connected, to the drain terminal of the transistor T711. An example of a circuit 701 will be described in more detail in relation to [Fig.II],

[0133] The circuit 700 further comprises, for example, four transistors T712, T713, T714 and T714-2. A source terminal of the transistor T712 receives the supply voltage AVD100. A drain terminal of the transistor T712 is connected, preferably connected, to the drain terminal and the gate terminal of the transistor T714-2. The drain terminal of the transistor T712 provides a voltage VBNT700. A gate terminal of the transistor T712 is connected, preferably connected, to the gate terminals of the transistors T703 and T713. A source terminal of the transistor T713 is connected, preferably connected, to the node that provides the supply voltage AVD100. A drain terminal of the transistor T713 is connected, preferably connected, to the source terminal of the transistor T714. A drain terminal of transistor T714 is connected, preferably connected, to the drain terminals of transistors T706 and T707. A source terminal of transistor T714-2 receives the reference voltage GND100.

[0134] The circuit 700 further comprises, for example, a circuit 702 (RESCUE) described in more detail in relation to [Fig. 10]. An output of the circuit 702 is connected, preferably connected, to the gate terminal of the transistor T714. The circuit 702 receives several voltages described in relation to [Fig. 10].

[0135] The circuit 700 further comprises, for example, two initialization circuits 703 (NLOOK BOOSTING) and 704 (NLOOKINIT) described in more detail in relation to [Fig. 9]. An output of the circuit 702 is connected, preferably connected, to the drain terminal of the transistor T714. The circuits 703 and 704 receive several voltages described in relation to [Fig. 10].

[0136] The circuit 700 further comprises, for example, three PMOS transistors T715, T717 and T718, an NMOS transistor T716, a NOR gate NOR701, a flip-flop FF701 and an inverter IINV701.

[0137] A first input of the NOR gate NOR701 receives the voltage AfterNi700. A second input of the NOR gate NOR701 is connected, preferably connected, to an output of the circuit 702 which provides a voltage RESCUE700. A third input of the NOR gate NOR701 receives the voltage INIT700 coming from of an output Q of the flip-flop FF701. An output of the NOR gate NOR701 is connected, preferably connected, to an input of the inverter INV701 and to a gate terminal of the transistor T715. An output of the inverter INV701 is connected, preferably connected, to a gate terminal of the transistor T717.

[0138] Regarding the FF701 flip-flop: - a D input of the FF701 flip-flop receives the AVD100 voltage; - a CLK clock input of the FF701 flip-flop receives the NoniB300 voltage; - an inverted reset input of the FF701 flip-flop receives the voltage EN300; and - a Q output of the FF701 flip-flop provides an InitB700 voltage.

[0139] Drain terminals of transistors T715 and T716 are connected, preferably connected, to the drain terminal of transistor T706 and to a drain terminal of transistor T717 and to a source terminal of transistor T718. Source terminals of transistors T715 and T716 are connected, preferably connected, to each other. A drain terminal of transistor T717 is connected, preferably connected, to a drain terminal of transistor T718.

[0140] The circuit 700 further comprises, for example, a comparator COMP701, two NMOS transistors T719 and T735, a current source CS702 and a capacitor C701. A first input (+) of the comparator COMP701 is connected, preferably connected, to the drain terminal of the transistor T717 and to the drain terminal of the transistor T718. A second input (-) of the comparator COMP701 is connected, preferably connected, to an output of the comparator COMP701 and to the source terminals of the transistors T715 and T716. A power supply terminal of the comparator COMP701 is connected, preferably connected, to a drain terminal of the transistor T735. A source terminal of the transistor T735 is connected, preferably connected, to an output terminal of the current source CS702. The current source CS702 receives the reference voltage GND100. A drain terminal of transistor T719 is connected, preferably connected, to the power supply terminal of comparator COMP701.A source terminal of transistor T719 is connected, preferably connected, to the node that receives the reference voltage GND300. According to one embodiment, comparator COMP701 is more accurate than comparator 500 described in relation to [Fig.5].

[0141] The circuit 700 further comprises, for example, a capacitor C701 arranged between the drain terminal of the transistor T718 and the node that receives the reference voltage GND300. In addition, the capacitor C701 receives the voltage VCorr300 which is controlled by the voltage AfterN300. The voltage AfterN300 is used by the circuit 700 to trigger the charging and discharging of the capacitor C701 and, consequently, the charging and discharging of the voltage Vcorr300. More particularly, such charging is triggered by a high level of the voltage AfterN300.

[0142] The circuit 700 further comprises two PMOS transistors T720 and T721. The gate terminals of the transistors T720 and T721 receive the voltage ACT300. Source terminals of the transistors T720 and T721 receive the supply voltage AVD100.

[0143] The circuit 700 further comprises, for example, a current mirror comprising two PMOS transistors T722 and T723. Source terminals of the transistors T722 and T723 are connected, preferably connected, to each other and receive the supply voltage AVD100. Gate terminals of the transistors T722 and T723 are connected, preferably connected, to each other, the drain terminal of the transistor T720 and the drain terminal of the transistor T722. The drain terminal of the transistor T723 provides the correction current ICorr300.

[0144] The circuit 700 further comprises, for example, a PMOS transistor T724. A source terminal of the transistor T724 receives the supply voltage AVD100. A gate terminal of the transistor T724 is connected, preferably connected, to the gate terminals of the transistors T722 and T723.

[0145] The circuit 700 further comprises, for example, a current mirror comprising two PMOS transistors T725 and T726. Source terminals of the transistors T725 and T726 are connected, preferably connected, to each other and receive the supply voltage AVD100. Gate terminals of the transistors T725 and T726 are connected, preferably connected, to each other, the drain terminal of the transistor T725, the drain terminal of the transistor T721 and the drain terminal of the transistor T724. A drain terminal of the transistor T726 provides the correction current ICorrAVS300.

[0146] The circuit 700 further comprises, for example, two NMOS transistors T727 and T728 and a resistor R703. A drain terminal of the transistor T727 is connected, preferably connected, to the drain terminal of the transistor T722. A source terminal of the transistor T727 is connected, preferably connected, to a first terminal of the resistor R703. A second terminal of the resistor R703 is connected, preferably connected, to a drain terminal of the transistor T728. A source terminal of the transistor T728 is connected, preferably connected, to the node that provides the reference voltage GND300. A gate terminal of the transistor T727 is connected, preferably connected, to the source terminal of the transistor T728. A gate terminal of the transistor T728 receives the voltage ACTB300.

[0147] The circuit 700 further comprises, for example, two NMOS transistors T729 and T730. A drain terminal of the transistor T729 is connected, preferably connected, to the drain terminals of the transistors T724 and T725. A source terminal of the transistor T729 is connected, preferably connected, to the node that provides the reference voltage GND300. A gate terminal of the transistor T729 is connected, preferably connected, to the gate terminals of the transistors T714-2 and T719. A drain terminal of the transistor T730 is connected, preferably connected, to the gate terminal of the transistor T729. A source terminal of transistor T730 is connected, preferably connected, to the node that provides the reference voltage GND300. A gate terminal of transistor T730 receives the voltage ACT300.

[0148] Circuit 700 operates as follows. When voltage ACT300 reaches a high level, corresponding to a logic 1, the zero current detection circuit begins to operate. During the period in which voltage AfterN300 is at a logic 1, comparator COMP701 of circuit 700 compares voltages PWRGND100 and VswlOO. Sampling transistors T715 to T718 are turned on and the voltage on sample and hold capacitor C701 is changed. Correction voltage Vcorr300 changes currents Icorr and IcorrAVS which are applied to the main comparator of circuit 500.

[0149] When the voltage ACT300 reaches a low level, corresponding to a logic 0, the other current comparator subcircuits of the zero current detection circuit are disabled to save power and the sampling transistors T715 to T718 are also turned off. However, the voltage on the capacitor C701 is maintained even after a long time by using the buffer COMP701 which clamps the voltage between the sources and drains of the transistors T717 and T718 to reduce leakage.

[0150] [Fig.8] shows, in more detail, an example of a level setting circuit 800 intended to implement the circuit 701 of the circuit 700 described in relation to [Fig.7],

[0151] The circuit 800 comprises, for example, a flip-flop FF801. The flip-flop 801 is a D-type bistable flip-flop, comprising three inputs R, CLK and D and two outputs Q and Q. The D input receives the supply voltage AVD100. The R input receives the voltage ACT300. The CLK input receives the voltage NoniB300.

[0152] The circuit 800 further comprises, for example, a PMOS transistor T801 and an NMOS transistor T802. A source terminal of the transistor T801 receives the supply voltage AVD100. A drain terminal of the transistor T801 is connected, preferably connected, to a drain terminal of the transistor T802. A source terminal of the transistor T802 provides a voltage to an output node OUT800 of the circuit 800.

[0153] According to one example, this output node OUT800 is connected, preferably connected, to the source terminal of transistor T707 of circuit 700. Circuit 800 is used to prevent rapid discharge which may occur in the source terminal of transistor T707 of circuit 700.

[0154] [Fig.9] shows, in more detail, an example of a booster circuit 900 intended to implement the circuit 703 of the circuit 700 described in relation to [Fig.7].

[0155] The circuit 900 comprises, for example, a resistor R901, a PMOS transistor T901 and two NMOS transistors T902 and T903. A first terminal of the resistor R901 is connected, preferably connected, to a node that provides the supply voltage AVD100. A second terminal of resistor R901 is connected, preferably connected, to a drain terminal of transistor T902. A source terminal of transistor T901 is connected, preferably connected, to the node that provides the supply voltage AVD100. A drain terminal of transistor T901 is connected, preferably connected, to a gate terminal of transistor T902. A gate terminal of transistor T901 receives the voltage VBPT300. A source terminal of transistor T902 is connected, preferably connected, to a drain terminal of transistor T903. A source terminal of transistor T903 is connected, preferably connected, to an output node OUT900 of circuit 900.

[0156] The circuit 900 further comprises, for example, an NMOS transistor T904 and a resistor R902. A drain terminal of the transistor T904 is connected, preferably connected, to the gate terminal of the transistor T902 and to the drain terminal of the transistor T901. A source terminal of the transistor T904 is connected, preferably connected, to a first terminal of the resistor R902. A second terminal of the resistor R902 is connected, preferably connected, to a node which receives the reference voltage GND300.

[0157] The circuit 900 further comprises, for example, three NMOS transistors T905, T906 and T907. A drain terminal of the transistor T905 is connected, preferably connected, to its gate terminal and to the drain terminal of the transistor T904. A drain terminal of the transistor T906 is connected, preferably connected, to its gate terminal and to the source terminal of the transistor T907. A drain terminal of the transistor T907 is connected, preferably connected, to its gate terminal and to the node which receives the reference voltage GND300.

[0158] The circuit 900 further comprises, for example, an NMOS transistor T908. A drain terminal of the transistor T908 is connected, preferably connected, to the drain terminal of the transistor T904. A source terminal of the transistor T908 is connected, preferably connected, to the node that receives the reference voltage GND300. A gate terminal of the transistor T908 receives the voltage ENiB400.

[0159] According to one example, this output node OUT900 is connected, preferably connected, to the source terminal of transistor T707 of circuit 700. Circuit 900 is used to raise the voltage at the source terminal of transistor T707 of circuit 700.

[0160] With some modifications, circuit 900 may also provide an exemplary implementation of circuit 704 of circuit 700. In this case, circuit 900 is used to assist in initializing the voltage at the source terminal of transistor T707 of circuit 700. More particularly, to obtain an exemplary circuit 704, voltage SWON300 is replaced, for example, by voltage INIT300 and voltage ENiB400 is replaced by voltage INITB300.

[0161] [Fig. 10] shows in more detail an example of a level clamping circuit 1000 intended to implement the circuit 702 of the circuit 700 described in relation to [Fig.7].

[0162] The circuit 1000 comprises, for example, a flip-flop FF1001 and two delay elements D1001 and D1002. The flip-flop FF1001 is a D-type bistable flip-flop, comprising three inputs R, CLK and D and two outputs Q and Q. The D input of the flip-flop FF1001 is connected, preferably connected, to an output of the delay element D1001. An input of the delay element D1001 receives the voltage Noni300. The CLK input of the flip-flop FF 1001 receives the voltage Poni300. The R input of the flip-flop FF 1001 is connected, preferably connected, to an output of the delay element D1002. An input of the delay element D1002 receives a reset voltage RST1000.

[0163] The circuit 1000 further comprises, for example, a PMOS transistor T1001 and an NMOS transistor T1002. A source terminal of the transistor T1001 is connected, preferably connected, to a node that provides the supply voltage AVD100. A gate terminal of the transistor T1001 is connected, preferably connected, to the Q output of the flip-flop FF1001. A source terminal of the transistor T1002 is connected, preferably connected, to a node that provides the voltage GND300. A gate terminal of the transistor T1002 is connected, preferably connected, to the Q output of the flip-flop FF1002.

[0164] The circuit 1000 further comprises, for example, an NMOS transistor T1003, two PMOS transistors T1004 and T1005 and a resistor R1001. A source terminal of the transistor T1003 receives the supply voltage AVD100. A drain terminal of the transistor T1003 is connected, preferably connected, to the drain terminal of the transistor T1001 and to the drain terminal of the transistor T1004. A gate terminal of the transistor T1003 receives the voltage VBPT700. A source terminal of the transistor T1004 is connected, preferably connected, to a drain terminal of the transistor T1005. A gate terminal of the transistor T1004 receives a voltage CCM1000. A source terminal of the transistor T1005 is connected, preferably connected, to a first terminal of the resistor R1001. A second terminal of resistor R1001 is connected, preferably connected, to a node that provides the reference voltage GND300.

[0165] The circuit 1000 further comprises, for example, two PMOS transistors T1006 and T1007. Source terminals of the transistors T1006 and T1007 are connected, preferably connected, to the node that provides the supply voltage AVD100. Gate terminals of the transistors T1006 and T1007 are connected, preferably connected, to each other, to the drain terminal of the transistor T1007 and to the drain terminal of the transistor T1003. A drain terminal of the transistor T1006 is connected, preferably connected, to the drain terminal of the transistor T1002 and to the gate terminal of the transistor T1002.

[0166] The circuit 1000 further comprises, for example, an NMOS transistor T1008. A source terminal of the transistor T1008 is connected, preferably connected, to the node that receives the reference voltage GND300. A drain terminal of the transistor T1008 is connected, preferably connected, to the gate terminal of the transistor T1005 and to the drain terminal of the transistor T1003. A gate terminal of the transistor T1008 receives a voltage VBNT700.

[0167] The circuit 1000 further comprises, for example, two NMOS transistors T1009 and T1010 and a resistor R1002. A drain terminal of the transistor T1009 is connected, preferably connected, to the drain terminal of the transistor T1003. A source terminal of the transistor T1009 is connected, preferably connected, to the source terminal of the transistor T1010. A drain terminal of the transistor T1010 is connected, preferably connected, to a first terminal of the resistor R1002. A gate terminal of the transistor T1010 receives a voltage VNT700. A second terminal of the resistor R1002 receives the voltage VswlOO.

[0168] The circuit 1000 further comprises a flip-flop FF1002 and a delay element D1003, a NOR gate1001, a NAND gate NAND1001 and an inverter INV1001. The flip-flop FF1002 is a D-type bistable flip-flop comprising three inputs R, CLK and D and two outputs Q and Q. The D input of the flip-flop FF1002 is connected, preferably connected, to an output of the delay element D1003. An input of the delay element D1003 receives the voltage Noni300. The CLK input of the flip-flop FF1002 receives the voltage Poni300. The R input of the flip-flop FF1002 is connected, preferably connected, to an output of the NOR gate NOR1001. A first input of the NOR gate NOR1001 is connected, preferably connected, to the drain terminal of the transistor T1003. A second input of the NOR gate NOR1001 receives the voltage AfterNi700. The output Q of the flip-flop FF 1002 is connected, preferably connected, to a first input of the NAND gate NAND1001.A second input of the NAND gate NAND1001 receives the voltage Noni300. An output of the NAND gate NAND1001 is connected, preferably connected, to an input of the inverter INV1001 and provides a voltage RESCUEB1000. An output of the inverter INV1001 provides a voltage RESCUE1000.

[0169] According to one example, the voltage RESCUEB1000 is used to control the transistor T714 of the circuit 700 and the voltage RESCUE100 is supplied to an input of the NOR gate NOR701. The circuit 1000 is used to raise the voltage at the source terminal of the transistor T707 of the circuit 700.

[0170] According to one example, and with respect to [Fig.l], the circuit 1000 can be used to maintain the offset of the comparator 101-Comp at the same level when the current in the diode L101 is non-zero.

[0171] [Fig. 11] shows in more detail an example of a level setting circuit 1100 intended to implement the circuit 701 of the circuit 700 described in relation to [Fig.7].

[0172] The circuit 1100 comprises, for example, a PMOS transistor Tl 101. A source terminal of the transistor Tl 101 is connected, preferably connected, to a node which provides the supply voltage AVD100. A gate terminal of the transistor Tl 101 receives the voltage NoniB300.

[0173] The circuit 1100 further comprises, for example, two resistors RI 101 and RI 102. A first terminal of the resistor RI 101 is connected, preferably connected, to a first terminal of the resistor RI 101 and to the node which provides the supply voltage AVD100.

[0174] The circuit 1100 further comprises, for example, three PMOS transistors Tl 102, Tl 103 and Tl 104 and two NMOS transistors Tl 105 and Tl 106. A source terminal of the transistor Tl 102 is connected, preferably connected, to a second terminal of the resistor RI 101. A drain terminal of the transistor Tl 102 is connected, preferably connected, to a source terminal of the transistor Tl 103. A drain terminal of the transistor Tl 103 is connected, preferably connected, to a source terminal of the transistor Tl 104. A drain terminal of the transistor Tl 104 is connected, preferably connected, to a drain terminal of the transistor Tl 105. A source terminal of the transistor Tl 105 is connected, preferably connected, to a drain terminal of the transistor Tl 106. A source terminal of the transistor Tl 105 is connected, preferably connected, to a node which provides the reference voltage GND300. Gate terminals of transistors Tl 104 and Tl 106 receive a voltage Ns21100.A gate terminal of transistor Tl 105 receives the voltage NoniB300. .

[0175] The circuit 1100 further comprises, for example, five PMOS transistors Tl 107, Tl 108, Tl 109, Tl 110 and Tl 111. A drain terminal of the transistor Tl 107 is connected, preferably connected, to the drain terminal of the transistor Tl 106. A source terminal of the transistor Tl 107 is connected, preferably connected, to the node that provides the reference voltage GND300. Gate terminals of the transistors Tl 107 and Tl 108 are connected, preferably connected, to each other and to the gate terminal of the transistor Tl 103. The two conduction terminals of the transistor Tl 108 are connected, preferably connected, to each other and to the node that provides the reference voltage GND300. A drain terminal of transistor Tl 109 is connected, preferably connected, to the gate terminals of transistors Tl 108 and Tl 109. A source terminal of transistor Tl 108 receives the reference voltage GND300.A drain terminal of transistor Tl 110 is connected, preferably connected, to the drain terminals of transistors Tl 106 and Tl 107. A source terminal of transistor Tl 110 receives the reference voltage GND300. Both terminals . conduction terminals of transistor Tl 111 are connected, preferably connected, to each other and to the node which provides the reference voltage GND300.

[0176] The circuit 1100 further comprises, for example, a PMOS transistor T1 112. A source terminal of transistor Tl 112 is connected, preferably connected, to a second terminal of resistor RI 102. A drain terminal of transistor Tl 112 is connected, preferably connected, to the gate terminal of transistor Tl 103 and to the gate terminals of transistors Tl 107 and Tl 108. A gate terminal of transistor Tl 112 is connected, preferably connected, to the gate terminal of transistor Tl 109 and receives voltage Noni300.

[0177] The circuit 1100 further comprises, for example, an inverter INV1101. An input of the inverter INV 1101 is connected, preferably connected, to the drain terminals of the transistors Tl 101, Tl 104 and Tl 105 and to the gate terminal of the transistor Tl 111. An output of the inverter INV101 provides the voltage END700 to the gate terminals of the transistors Tl 102 and Tl 110. This output of the inverter INV 1101 also constitutes the output node of the circuit 1100.

[0178] According to one example, circuit 1100 is used to enable and disable a comparator offset voltage adjustment operation.

[0179] [Fig. 12] shows in more detail an example of a logic circuit 1200 intended to implement the logic circuit 301 of the circuit 300 described in relation to [Fig. 3].

[0180] The logic circuit 1200 comprises two inverters INV 1201 and INV 1202 connected in series. An input of the inverter INV1201 receives the voltage Pon300 and an output of the inverter INV1201 provides the voltage PoniB300. An input of the inverter INV1202 receives the voltage PoniB300 and an output of the inverter INV1202 provides the voltage Poni300.

[0181] The logic circuit 1200 further comprises two inverters INV 1203 and INV 1204 connected in series. An input of the inverter INV1203 receives the voltage Non300 and an output of the inverter INV1203 provides the voltage NoniB300. An input of the inverter INV1204 receives the voltage NoniB300 and an output of the inverter INV1204 provides the voltage Noni300.

[0182] The logic circuit 1200 further comprises two inverters INV 1205 and INV 1206 connected in series. An input of the inverter INV1205 receives the voltage EN300, and an output of the inverter INV1205 provides the voltage ENiB300. An input of the inverter INV1206 receives the voltage ENiB300 and an output of the inverter INV1206 provides the voltage ENi300.

[0183] The logic circuit 1200 further comprises two inverters INV 1207 and INV 1208 connected in series. An input of the inverter INV1207 receives the voltage ACT300 and an output of the inverter INV1207 provides the voltage ACTiB300. An input of the inverter INV1208 receives the ACTB300 voltage and one output of the INV1208 inverter provides the ACTi300 voltage.

[0184] The logic circuit 1200 further comprises two NAND logic gates Nandl201 and Nandl202. The gate Nandl201 provides the voltage AfterNiB300 and receives: - the voltage AfterN300; - the Eni300 voltage; and - an exit from the Nandl202 gate.

[0185] Gate Nandl202 receives voltages END700 and Poni300.

[0186] The logic circuit 1200 further comprises an inverter INV1209, a flip-flop FF1201, a NOR logic gate NOR1201 and a NOR logic gate NOR1202. An input of the inverter INV 1209 receives the voltages AfterNiB300 and an output of the inverter INV 1209 is connected, preferably connected, to a clock input CLK of the flip-flop FF 1201. An input D of the flip-flop FF 1201 receives the voltage AVD100. A reset voltage of the flip-flop FF1201 is connected, preferably connected, to an output of the NOR logic gate NOR1201. A Q output of the flip-flop FF1201 provides AfterNiN1200. A Q output of the flip-flop FF1201 provides AfterNiNB1200. The NOR gate NOR1201 receives the voltages ENi300 and END700. The NOR gate NOR1202 receives the voltages AfterNiB300 and AfterNiNB1200 and provides voltages AfterNNOR1200.

[0187] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0188] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. Zero current detection circuit (101; 300) comprising: - a first comparator (101-Comp; 302; 500) configured to compare a first voltage (VswlOO), representative of a first current (IL101), to a first threshold voltage (Vos 101); - a calibration circuit (101-CAL; 303, 304; 700) configured to modify the value of the first threshold voltage (VoslOl) given variations in process, voltage and / or temperature.

2. The circuit of claim 1, wherein said first threshold voltage (VoslOl) is an offset voltage of said first comparator (101-Comp; 302; 500).

3. A circuit according to claim 1 or 2, wherein said calibration circuit (700) comprises a second comparator circuit (COMP701).

4. The circuit of claim 3, wherein said second comparator circuit (COMP701) is more accurate than the first comparator (101-Comp; 302; 500).

5. A circuit according to any one of claims 1 to 4, comprising a logic circuit (301; 400) configured to be the main control circuit of the zero current detection circuit (101; 300).

6. A DC-DC converter comprising a zero current detection circuit according to any one of claims 1 to 12.

7. a J. Converter according to claim 6, comprising two switches (S 101, S102) connected in series and a coil (L101) one of the terminals of which is connected to the middle node between said two switches (S 101, S102).

8. The converter of claim 7, wherein said zero current detection circuit is configured to detect when the current in said coil is equal to zero.

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