Multipath amplifier circuit

Abstract

Multi-path amplifier circuit The present description relates to a multi-path amplifier circuit (300) comprising: first and second amplification paths (201, 202) of an input voltage, connected in parallel, the first path comprising a first amplifier stage (216, 218, 220), a second amplifier stage (226) and a band-stop filter (NOTCH FILTER) between a first node (NOMF, NVOPF) connected to the second amplifier stage (226) and a second node (NVOMI, NVOPI) connected to an output of the first amplifier stage (216, 218, 220); and a control unit (321) configured to, following detection of a change in common mode of the input voltage and for a first duration, open said first path (201) and connect the first node (NVOMF, NVOPF) to the second node (NVOMI, NVOPI) with a unity gain amplifier (320). Figure for abstract: Fig. 2

Description

Title of the invention: Multipath amplifier circuit Technical field

[0001] The present description relates generally to multipath amplifier circuits and methods of operation thereof. Prior art

[0002] The measurement of low voltages, for example in the context of motor supply current measurements, can be disturbed when the common mode of this voltage varies suddenly. Summary of the invention

[0003] There is a need to reduce the disturbance time during a sudden change in the common mode of a voltage.

[0004] One embodiment overcomes all or part of the drawbacks of known multipath amplifier circuits.

[0005] One embodiment provides a multipath amplifier circuit comprising: first and second input voltage amplification paths, connected in parallel, the first path comprising a first amplifier stage, a second amplifier stage and a band-stop filter between a first node connected to the second amplifier stage and a second node connected to an output of the first amplifier stage; and a control unit configured to, following detection of a change in common mode of the input voltage and for a first duration, open said first path and connect the first node to the second node with a unity gain amplifier.

[0006] An embodiment provides a method of operating a multi-path amplifier circuit comprising first and second paths for amplifying an input voltage, connected in parallel, the first path comprising a first amplifier stage, a second amplifier stage and a band-stop filter between a first node connected to the second amplifier stage and a second node connected to an output of the first amplifier stage; the method comprising, following detection of a change in common mode of the input voltage and for a first duration, implementing a circuit control unit to: - open the first path, and - connect the first node to the second node with a unity gain amplifier.

[0007] In one embodiment, the second path is taken when frequencies of the input voltage are higher than a first frequency and wherein the first path is taken when frequencies of the input voltage are lower than this first frequency.

[0008] In one embodiment, the first amplifier stage is configured to compensate for an offset voltage present at its input.

[0009] In one embodiment, the first amplifier stage comprises a first connecting amplifier, a first shaping circuit configured to modulate an input voltage of the first amplifier, and a second shaping circuit, configured to demodulate an output voltage of the first amplifier.

[0010] In one embodiment, the unity gain amplifier is configured to implement offset compensation of its input voltage.

[0011] In one embodiment, the unity gain amplifier is configured to copy the input voltage offset of the second amplifier stage to the second node with an offset less than or equal to 50pV during the first duration.

[0012] In one embodiment, the unity gain amplifier comprises: an amplifier stage having an output configured to be connected to the second node, a first and a second differential amplifier circuit configured to, each in turn, measure and compensate for their respective voltage offset.

[0013] In one embodiment, the first and second differential amplifier circuits each have: respective first inputs connected to the second node, respective second inputs connected to the first node, and respective outputs connected to an input node of the amplifier stage.

[0014] In one embodiment, the detection of a change in the common mode of the input voltage is implemented by a rising and / or falling edge detector of the common mode of the input voltage.

[0015] In one embodiment, the amplifier circuit comprises: a fourth amplifier connecting an output node of the amplifier circuit and an output of the second amplifier stage; and a first capacitive element connecting said output node and said output of the second amplifier stage.

[0016] In one embodiment, a second capacitive element connects the second node and the output node of the amplifier circuit.

[0017] In one embodiment, the second node is connected to a third capacitive element.

[0018] One embodiment provides an electronic current determination device comprising a measuring resistor and an amplifier circuit as described above, in which the input voltage of the amplifier circuit is taken between two terminals of said resistor.

[0019] One embodiment provides a system for controlling a motor comprising a motor and a device as described above implemented on at least one power supply phase of the motor. Brief description of the drawings

[0020] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0021] [Fig.l] schematically represents an example of a motor system to which the embodiments apply;

[0022] [Fig.2] schematically represents circuits of the system of [Fig.l] according to an example;

[0023] [Fig.3] schematically represents circuits of the system of [Fig.l] according to one embodiment;

[0024] [Fig.4] schematically represents circuits of [Fig.3];

[0025] [Fig.5] represents a timing diagram of the operation of the circuits of [Fig.4];

[0026] [Fig.6] represents a circuit of [Fig.3] according to one embodiment;

[0027] [Fig.7] represents a circuit of [Fig.3] according to one embodiment;

[0028] [Fig.8] represents a circuit of [Fig.3] according to one embodiment;

[0029] [Fig.9] represents a circuit of [Fig.3] according to one embodiment;

[0030] [Fig. 10] represents a circuit of [Fig.9] according to one embodiment;

[0031] [Fig.l 1] represents a circuit of [Fig.9] according to one embodiment;

[0032] [Fig. 12] represents a timing diagram of the operation of a circuit of [Fig.l] when a circuit of [Fig.3] is used; and

[0033] [Fig. 13] schematically represents a motor system according to one embodiment. Description of the embodiments

[0034] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0035] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.

[0036] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0037] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0038] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0039] [Fig.l] schematically represents an example of a motor system to which the embodiments apply.

[0040] In the example shown, a motor 108 (M) is powered by at least one phase 104 which passes through a resistor 106 (RSHUNT) whose value is very low. By measuring the voltage INP-INM present at the terminals of this resistor 106, it is possible to deduce therefrom the value of the current passing through the motor 108.

[0041] In the example shown, an amplifier circuit 109 is connected, preferably connected to the terminals of the resistor 106 to amplify the voltage INP-INM for example with a gain greater than 10 at the level of outputs OM-OP.

[0042] The amplifier circuit 109 comprises a resistor 105 of value R connecting a node IP to the terminal of the resistor 106 which is connected to the motor 108. The amplifier circuit 109 further comprises a resistor 107 of value R connecting a node IM to the terminal of the resistor 106 which receives the phase intended for the motor 108. A resistor 111 and another resistor 103, both having a value G*R where G is the gain, respectively connect the node IP to the output OM and the node IM to the output OP.

[0043] In the example shown, an amplifier circuit 102 has an input (denoted “-”) connected, preferably connected, to the IP node to receive a VIP potential, and another input (denoted “+”) connected, preferably connected, to the IM node to receive a VIM potential. The amplifier circuit 102 receives clock signals Clkl, Clk2 and a voltage VNEG from an operating unit 113 (REF). An output of the circuit 102 (denoted “+”) is connected to the OM output and another output of the circuit 102 (denoted “-”) is connected to the OP output.

[0044] [Fig. 2] schematically represents circuits of the system of [Fig. 1] according to an example. More particularly [Fig. 2] represents circuits 113 and 102 of [Fig. 1].

[0045] In the example shown, the circuit 113 comprises a voltage rail receiving a voltage VCC. This voltage rail is connected, preferably connected, to: - a low dropout regulator circuit 223 (LDO) (Low dropout, in English) which generates a regulated voltage VREG distributed to an oscillator 225 (OSC), a clock signal generator 227 (Clk Generator) and a negative charge pump circuit 229 (Negative Charge Pump in English) which generates the voltage VNEG; and - a voltage generator circuit 231 (Bias & Reference).

[0046] In the example shown, the oscillator 225 provides a signal Fclk to the circuit 227 so that it generates the signals Clkl and Clk2. The signal Clk2 has, for example, a frequency divided by two compared to Clkl.

[0047] The circuit 102 comprises for example a positive voltage generation block 217 (Positive supply) connected, preferably connected, at the input to the terminals INP, INM of the resistor 106 as well as to the voltage rail VCC and delivering a voltage VCMP at the output.

[0048] The circuit 102 comprises a first and a second path 201, 202 for amplifying the voltage between the IP and IM nodes. Each of the paths comprises a path dedicated to processing the VIP potential received on the IP node and another path dedicated to processing the VIM potential received on the IM node.

[0049] For the sake of clarity, in the remainder of the text, a single node will designate a node placed at the same level on both tracks of the same path.

[0050] In the example shown, the two paths are connected in parallel between the node IP,IM and a node N4M,N4P. The first path 201 comprises a first amplifier 216 (gml) which connects a first shaping circuit 218 (Chopper Modulator in English) and a second shaping circuit 220 (Chopper Demodulator) referenced to ground. The voltage present between the two channels of the first path at the output of the amplifier 216 is VOM-VOP. These two shaping circuits receive the clock signal Clkl and are configured to cancel the voltage offset present at the input of the amplifier 216. The first shaping circuit 218 has an input connected, preferably connected, to the node IP,IM and the second shaping circuit 220 has an output connected, preferably connected, to a node NVOMI,NVOPI. In one example, the first amplifier 216 receives the voltage VCMP, the voltage VCC, the voltage VNEG and is also connected, preferably connected, to ground..

[0051] In one example, the node NVOMI,NVOPI is a capacitive node, i.e. a capacitance C3 connects the two paths of the first path at the node NVOMI,NVOPI.

[0052] In the example shown, a band-stop filter 212 (NOTCH FILTER) connects a node NVOMF,NVOPF, which is connected to an amplifier 226 (gm2), and the node NVOMI,NVOPI. The band-stop filter 212 receives, for example, the signal Clk2. The frequency of the signal Clkl is, for example, several hundred kHz or even a few MHz.

[0053] The shaping circuits are configured to perform chopping, or chopping, which is a continuous time modulation technique that does not cause noise aliasing. The input voltage VIP,VIM of the shaping circuit 218 first passes through the shaping circuit 218 driven by the signal Clkl. Then, the modulated signal at the output of the circuit 218 is amplified with its own input offset. The drift (ripple in English) due to the voltage offset at the input of the amplifier circuit 216 is filtered by the bandstop filter 212 so that a constant voltage between the two NVOMF-NVOPF paths is obtained.

[0054] The amplifier 226 receives for example the voltage VCC and is also connected, preferably connected, to ground. The amplifier is connected, preferably connected, at the output to the node N4M,N4P.

[0055] In the example shown, a feedback circuit 224 (CM Feedback), referenced to ground, connects the amplifier 216 to the node NVOMI,NVOPI. The feedback circuit 224 is configured to allow the regulation of the output common mode of the amplifier 216 around a given fixed voltage.

[0056] The second path 202 comprises an amplifier 230 (gm4) which connects the node IP,IM and the node N4M,N4P. The amplifier 230 receives the voltages VCMP,VCC,VNEG and is also connected, preferably connected, to ground. The set of circuits 218,220 and 212 makes it possible to obtain precise amplification but limits the frequency of the input signal. Thus, the second path 202 is mainly used when the frequency of the input signal is greater than 100kHz and, conversely, for a frequency of the input signal less than 100kHz, the first path is mainly used.

[0057] In one example, the amplifier circuit 102 comprises a fourth amplifier 228 (gm3) connecting an output node OM,OP of the circuit 102 and an output of the amplifier 226 which is the node N4M,N4P. The amplifier 228 receives for example the voltage VCC and is also connected, preferably connected, to ground.

[0058] The circuit 102 further comprises a capacitive element of value C2 connecting, for each channel respectively, the node OM,OP and the node N4M,N4P.

[0059] The circuit 102 further comprises a capacitive element of value Cl connecting, for each channel respectively, the node NVOMI,NVOPI and the node OM,OP.

[0060] The common mode of the voltage present on phase 104 can vary greatly in the case of a motor, for example between 0 and 120V, and with a variation of up to approximately 50V in ten nanoseconds. This common mode variation is also found on IP-IM, i.e. on the VIP-VIM voltage. However, during the sudden variation of common mode, the OM-OP output of the circuit of [Fig.2] varies before returning to a more stable value. The time to return to a voltage value within a range of ±0.5% of the value before the sudden change of common mode is greater than 5 ps. This recovery time is relatively long due to the limitation of the speed due to the sampling implemented by the circuit 212.

[0061] It is necessary to reduce this return time, for example, to approach a time of the order of ps.

[0062] To do this, the described embodiments provide that the amplifier circuit comprises a control unit configured to, following detection of a change in common mode of the input voltage, open the first path 201 for a first duration.

[0063] This allows the signal, upon detection of a change in the common mode, to pass entirely through the second path during the opening time of the first path, this second path being faster than the first path. The return time is thus reduced.

[0064] In one embodiment, the voltage offset at the input of the amplifier 226 is stored during the opening of the first path. This makes it possible to further improve the speed of the return time.

[0065] [Fig. 3] schematically represents circuits of the system of [Fig. 1] according to one embodiment. More particularly, [Fig. 3] represents an example of the circuit 113 and another amplifier circuit 300.

[0066] In the example shown, circuit 113 is similar to that of [Fig.2] except that a signal having the frequency FOSC of oscillator 225 is made available to circuit 113.

[0067] In the example shown, the circuit 300 is similar to circuit 102 of [Fig.2] except that the circuit 300 comprises a control unit 321 (LOGIC), a detector 310 of variation of rising and / or falling edge of the common mode of the voltage INP-INM, and a unity gain amplifier 320 (AZ BUF). The detector 310 is connected, preferably connected, to an input of the control unit 321. The control unit 321 is connected, preferably connected, to the unity gain amplifier 320, to the filter 212 and to the circuit 220.

[0068] When the circuit 310 detects a rising or falling edge on the common mode of the voltage INP-INM, that is to say when a rising or falling edge is detected on the two terminals INP and INM at the same time, a signal EDGE_DET changes state. The control unit 321, depending on the state of this signal EDGE_DET, and from the signal FOSC and / or a clock signal CLK from the clock signal generator 227, generates and modifies the state of signals AZ, MASKON, NOTCH, NOTCHB, CHOP, and CHOPB. The AZ and MASKON signals control the unity gain amplifier 320, the NOTCH and NOTCHB signals control the filter 212, and the CHOP and CHOPB signals control the shaping circuits 218 and 220. The CHOPB signal is the inverse signal of the CHOP signal, and the NOTCHB signal is the inverse signal of the NOTCH signal.

[0069] Following detection of a change in the common mode of the input voltage by the detector 310, the signal EDGE_DET changes state and the control unit 321, in reaction, opens the first path 201, i.e. opens either the circuit 220 and / or the filter 212 for a first duration. To do this, during this first duration, otherwise called the masking duration, the signals NOTCH and / or CHOP - and respectively the signals CHOPB and NOTCHB - are suspended.

[0070] In response to the detection of a change in the common mode of the input voltage by the detector 310, the control unit 321 can also modify, during the first duration (which is for example a few microseconds), the state of the signals AZ and MASKON so that the output of the unity gain amplifier 320 is connected to the node NVOMI,NVOPI. The unity gain amplifier 320 thus stores, or copies, onto the capacitive node NVOMI,NVOPI the voltage offset of the second amplifier stage 216, at the time of opening of the first path, in order to then force it, or apply it, to the node NVOMI,NVOPI during the first duration. This makes it possible to reduce the return time during a variation in the common mode of the input voltage by starting again from the voltage offset present before the opening of the first path.

[0071] [Fig.4] schematically represents circuits of [Fig.3].

[0072] More particularly, [Fig.4] represents circuits 212, 220 and 320 of circuit 300.

[0073] In the example shown, the circuit 220 comprises: - a switch 401 controlled by the signal CHOP and connecting the channel receiving the potential VOM to the node NVOMI; - a switch 403 controlled by the CHOPB signal and connecting the channel receiving the VOM potential to the NVOPI node; - a switch 402 controlled by the CHOP signal and connecting the channel receiving the VOP potential to the NVOPI node; and - a switch 408 controlled by the CHOPB signal and connecting the channel receiving the VOP potential to the NVOMI node.

[0074] In the example of [Fig.4], the circuit 212 comprises: - a capacity 420 connecting a node N1CN to a node N1CP, a capacity 421 connecting a node N2CN to a node N2CP, and a capacity 426 connecting the two paths of the node NVOMF,NVOPF; - a switch 409 controlled by the NOTCH signal and connecting the NVOMI node to the N1CN node; - a switch 416 controlled by the NOTCHB signal and connecting the NVOMF node to the N1CN node; - a switch 411 controlled by the NOTCHB signal and connecting the NVOMI node to the N2CN node; - a switch 413 controlled by the NOTCH signal and connecting the NVOMF node to the N2CN node; - a switch 407 controlled by the NOTCH signal and connecting the NVOPI node to the N1CP node; - a switch 414 controlled by the NOTCHB signal and connecting the NVOPF node to the N1CP node; - a switch 405 controlled by the NOTCHB signal and connecting the NVOPI node to the N2CP node; - a switch 412 controlled by the NOTCH signal and connecting the NVOPF node to the N2CP node.

[0075] In the example of [Fig.4], the circuit 320 comprises two amplifier stages unity gain amplifiers 450 and 460 each acting on a channel of the first path. A switch 440 controlled by the MASKON signal connects the unity gain amplifier stage 450 to the NVOPI node. The unity gain amplifier stage 450 is further connected, preferably connected, to the NVOPF node. A switch 462 controlled by the MASKON signal connects the unity gain amplifier stage 460 to the NVOMI node. The unity gain amplifier stage 460 is further connected, preferably connected, to the NVOMF node.

[0076] [Fig.5] represents a timing diagram of the operation of the circuits of [Fig.4]. More specifically, the example in [Fig.5] represents the common mode INP / INM, the EDGE_DET signal, the MASKON signal, the CHOP signal and the NOTCH signal as a function of time.

[0077] Before a time tl, the common mode INP / INM is at 0V, the EDGE_DET and MASKON signals are in the low state and the CHOP and NOTCH signals form square wave type signals with a duty cycle of 50%, the frequency of the CHOP signal being double that of the NOTCH signal.

[0078] At time t1, the common mode voltage INP / INM varies abruptly with a rising edge from 0V to 48V. This causes a pulse on the EDGE_DET signal which causes the MASKON signal to go high and the CHOP and NOTCH signals to go low until a time t2.

[0079] At time t2, the MASKON signal returns to a low level and the oscillations of the CHOP and NOTCH signals resume.

[0080] At a time t3, after time t2, the common mode INP / INM suddenly returns with a falling edge to 0V which causes the generation of a pulse on the signal EDGE_DET and consequently the setting to the high state of the signal MASKON and the setting to a low level of the signals CHOP and NOTCH until a time t4. At time t2, the signal MASKON returns to a low level and the oscillations of the signals CHOP and NOTCH resume.

[0081] The AZ signal is not shown in [Fig.5] but it has the same frequency as the NOTCH signal except that it is not suspended during the masking time when the NOTCH signal is suspended.

[0082] [Fig. 6] represents a circuit of [Fig. 3] according to one embodiment. More particularly, [Fig. 6] represents functions of the circuit 321 for the generation of the signals NOTCH, NOTCHB, CHOP, CHOPB, and AZ.

[0083] The circuit 321 comprises a first circuit with a flip-flop 617 (FF, Flip Flop in English), for example of type D, receiving on a clock input CK the signal FOSC. An output Q of this flip-flop 617 is connected to a clock input CK of another flip-flop of type 619. The data input D of the flip-flop 619 is connected to the inverse output QB of an additional flip-flop 618 of type D. The clock input CK of the flip-flop 618 is connected to the data input D as well as to the inverse output QB of the flip-flop 617. The data input D of the flip-flop 618 is connected to the output Q of the flip-flop 619 and to a data input D of a flip-flop 620 of type LD. The state of the signal on the output Q of this flip-flop 620 is the state of the signal CHOP. A GN input of the 620 flip-flop is configured to receive a HOLDON2 signal, which when high for example, suspends and maintains the output state Q regardless of the state of the signal on the D input.In other words, the signal HOLDON2, depending on its state, activates or deactivates the circuit 220. The inverse output QB of the flip-flop 619 is connected to the data input D of a flip-flop 623 of type LD. The state of the signal on the output Q of this flip-flop 623 is the state of the signal CHOPB. An input GN of the flip-flop 623 is configured to receive the signal HOLDON2. An output Q of the flip-flop 618 is connected to an input of a logic gate 625 of type AND whose other input is configured to receive a signal HOLDOFF which, depending on its state, activates or deactivates the circuit 212. An output of the logic gate 625 is connected to the clock input CK of a flip-flop of type D whose data input D is looped back to its . inverse output QB. The state of the NOTCH signal is found on the Q output of this 626 flip-flop and the state of the NOTCHB signal is found on the inverse output QB of this 626 flip-flop.

[0084] The circuit 321 comprises a second circuit comprising a D-type flip-flop 627 whose data input D is connected to its inverse output QB and whose clock input is configured to receive the signal CLK. The state of the output signal on the output Q of this flip-flop 627 is the state of the signal AZ.

[0085] Flip-flops 617,618,619,626 and 627 are configured to receive a reset signal RSTB.

[0086] The circuit 321 comprises a third circuit comprising an AND-type logic gate 613 configured to receive as input the state of the signal CLK and the state of a signal CNTON. The output of this logic gate 614 is connected to the clock input CK of a D-type flip-flop 614 whose data input D is looped back to its inverse output QB. The signal on the Q output of the flip-flop 614 is called A0 and the signal on the inverse output QB is called A0B. The third circuit further comprises two other flip-flops 615 and 616 similar to flip-flop 614. The clock input of flip-flop 615 is connected to the Q output of flip-flop 614 and the clock input CK of flip-flop 616 is connected to the output of flip-flop 615. The signal on the Q output of flip-flop 615 is called A1 and the signal on the inverse output QB of this flip-flop is called A1B. The signal on the Q output of flip-flop 616 is called A2 and the signal on the inverse output QB of this flip-flop is called A2B.

[0087] Flip-flops 614, 615 and 616 are configured to receive a reset signal RSTCNTB.

[0088] The circuit 321 comprises a fourth circuit comprising logic gates 636 and 637 each configured to perform an AND type function from the signals A2, A1, A0B and A2, A1B, A0 respectively. The respective outputs of the logic gates 636 and 637 are connected to the inputs of a logic gate 638 configured to perform an OR type logic function from the outputs of the logic gates 636 and 637. The output CNTONB of the logic gate 638 is connected to an inverter 628 whose output gives the signal CNTON. The output of the logic gate 638 is further connected to the D input of a D-type flip-flop 640 whose clock input CK is configured to receive the CLK signal inverted with an inverter 639. The Q output of this flip-flop 640 gives the HOLDOFF signal and is connected to the D input of another D-type flip-flop 642 whose clock input is configured to receive the CLK signal.The inverse output QB of the flip-flop 642 gives the signal HOLDON2 and is connected to two inverters in series 631,632 to give the signal MASKON.

[0089] The circuit 321 further comprises a fifth circuit having an inverter 631 configured to receive the signal EDGE_DET and connected, preferably connected, to an input of a 632 logic gate of the AND type receiving on another input the signal RSTB. An output of the 632 logic gate is the signal RSTCNTB.

[0090] [Fig.7] represents a circuit of [Fig.3] according to one embodiment. More In particular, [Fig.7] represents an exemplary embodiment of the circuit 310 for the detection of the rising edge of the common mode voltage between INP and INM.

[0091] In the example shown, a capacity 720 connects the INM node and a ND1 node, and another capacity 721 connects the INM node and a ND2 node.

[0092] The example shown comprises a first branch 723 having: a resistor 710 connecting the node ND1 to ground GND; three series diodes 712, 717 and 719 connecting the node ND1 to ground; and a diode 708, placed in reverse with respect to the diodes 712, 717, 719 which has its cathode connected to the node ND1 and its anode connected to ground. The example shown also comprises a second branch 722 similar to the first branch 723 but where the node ND2 replaces the node ND1.

[0093] Node ND1 is connected, preferably connected, to a control node of an NMOS transistor 726, and node ND2 is connected, preferably connected, to a control node of an NMOS transistor 724. A conduction node of transistor 724 is connected, preferably connected, to ground and a conduction node of transistor 726 is connected, preferably connected, to a node NTH1. Transistors 724 and 726 have a conduction node in common.

[0094] In the example shown, a transistor 728 is connected, preferably connected, to the voltage rail VCC via a resistor 725. The transistor 728 has a conduction node connected, preferably connected, to the node NTH1 and a control node connected, preferably connected, to a threshold detector 730 (trigger in English), such as for example a Schmitt trigger. The control node of the transistor 728 receives the voltage VREG. The amplifier 730 is also connected, preferably connected, as an input to the node NTH1 and is referenced to ground. An output of the amplifier 730 is the signal EDGE_DET.

[0095] When a rising edge is detected on INM and INP at the same time, this creates a pulse on the EDGE_DET signal at the output of amplifier 730.

[0096] [Fig.8] represents a circuit of [Fig.3] according to one embodiment. More In particular, [Fig.8] represents an exemplary embodiment of the circuit 310 for the detection of the falling edge of the common mode voltage between INP and INM.

[0097] In the example shown, a capacity 821 connects the INM node and a ND3 node, and another capacity 828 connects the INM node and a ND4 node.

[0098] The example shown comprises a first branch 820 having: a resistor 810 connecting the node ND3 to the voltage rail VCC; three series diodes 812, 817, 819 connecting the node ND1 to the voltage rail VCC; and a diode 808, placed in reverse with respect to the diodes 812, 817, 819 which has its cathode connected to the voltage rail VCC and its anode connected to node ND3. The example shown also includes a second branch 822 similar to the first branch 820 but where node ND4 replaces node ND3.

[0099] Node ND3 is connected, preferably connected, to a control node of a PMOS transistor 826, and node ND4 is connected, preferably connected, to a control node of a PMOS transistor 823. A conduction node of transistor 823 is connected, preferably connected, to the voltage rail VCC and a conduction node of transistor 826 is connected, preferably connected, to a node NTH2 via a PMOS transistor 829. Transistors 826 and 823 have a conduction node in common.

[0100] The example shown comprises another branch 832 having: a resistor 830 connecting the node NTH2 to ground; three series diodes 823,824,825 connecting the node NTH2 to ground; and a diode 835, placed in reverse with respect to the diodes 823,824,825 which has its cathode connected to the node NTH2 and its anode connected to ground.

[0101] In the example shown, a threshold detector 840, such as a Schmitt trigger, is connected, preferably connected, to the input of the node NTH2 and is referenced to ground. The threshold detector 840 also receives the voltage VREG. An output of the amplifier 840 is the signal EDGE_DET.

[0102] When a falling edge is detected on INM and INP at the same time, this creates a pulse on the EDGE_DET signal at the output of amplifier 840.

[0103] [Fig.9] represents a circuit of [Fig.3] according to one embodiment. More particularly, [Fig.9] represents one embodiment of the circuit 320.

[0104] In the example shown, the unity gain amplifier 320 comprises an amplifier stage 930 (AVOUT) whose output node NVOUT is configured to be connected respectively to the node NVOMI or NVOPI via the respective switches 440 or 462. The amplifier stage 930 is connected, preferably connected, to the voltage rail VREG and is referenced to ground.

[0105] The amplifier 320 further comprises a first and a second differential amplifier circuit 924,926 (AZ AVI) whose respective input nodes IM are connected to the node NVOMI, respectively NVOPI, and whose other respective input nodes IP are connected to the node NVOMF, respectively NVOPF. Respective output nodes OM of the amplifier circuits 924,926 are connected to the same input node NVINT of the amplifier stage 930 (AVOUT). The circuits 924,926 are connected, preferably connected, to the voltage rail VREG, are referenced to ground, and are configured to receive the state of the signals AZ and AZB which is the inverse of the signal AZ. The circuits 924 and 926 receive the signals AZ and AZB in an inverted manner and are therefore used in turn. While one of the two is used to deliver the follower voltage on VOUT, the other measures its input voltage offset to be able to compensate it later. The alternation of use between circuits 924 and 926 is done at the frequency of the AZ signal.

[0106] [Fig. 10] represents a circuit of [Fig.9] according to one embodiment.

[0107] More particularly, [Fig. 10] represents an exemplary embodiment of the circuit 930.

[0108] In the example shown, a capacitor 1024 connects the NVINT node to the NVOUT node and a capacitor 1030 connects the NVOUT node to ground. The NVINT node is also connected, preferably connected, to a control node of an NMOS transistor 1026 whose conduction node is connected, preferably connected, to ground and another conduction node is connected, preferably connected, to the NVOUT node. A PMOS transistor 1020, whose control node is controlled by a voltage VBP, connects the NVOUT node to the voltage rail VREG.

[0109] [Fig. 11] represents a circuit of [Fig.9] according to one embodiment. More particularly, [Fig. 11] represents an embodiment of circuits 924,926.

[0110] In the example shown, the nodes IP and IM are connected to a node NC0 via a switch 1102 controlled by the signal AZ and a switch 1104 controlled by the signal AZB respectively.

[0111] The voltage rail VREG is connected to ground by two PMOS transistors 1110,1128 and two NMOS transistors 1124,1122 connected in series. Transistors 1128 and 1124 have a common conduction node named NC6.

[0112] A PMOS transistor 1112, whose control node is configured to receive the voltage VBP, connects the voltage rail VREG to a node NC3. A PMOS transistor 1114 and an NMOS transistor 1120 in series connect the node NC3 to ground. A PMOS transistor 1116 and an NMOS transistor 1118 in series also connect the node NC3 and ground. The control node of the transistor 1116 is configured to receive the signal present on IP and the control node of the transistor 1114 is configured to be connected, preferably connected, to the node NC0. The control node of the transistor 1122 is connected, preferably connected, to the control node of the transistor 1120.

[0113] The voltage rail VREG is further connected to ground by two PMOS transistors 1132, 1130 and two NMOS transistors 1134, 1136 in series. The control node of transistor 1136 is connected, preferably connected, to the control node of transistor 1118; the control node of transistor 1134 is connected, preferably connected, to the control node of transistor 1124; the control node of transistor 1130 is connected, preferably connected, to the control node of transistor 1128; and the control node of transistor 1132 is connected, preferably connected, to the control node of transistor 1110. The conduction node NC2, common to transistors 1130 and 1134, is connected, preferably connected, to a node NCI which is the control node of transistor 1132. The conduction node NC5, common to transistors 1120 and 1114, is connected, preferably connected, to the control node of transistor 1122. The conduction node NC4, common to transistors 1118 and 1116, is connected, preferably connected, to the control node of transistor 1118.

[0114] A PMOS transistor 1138, controlled by the VPB signal, connects a node NC9 to the voltage rail VREG. A PMOS transistor 1140 connects the node NC5 to the node NC9. A PMOS transistor 1142 connects the node NC4 to the node NC9.

[0115] The control node of transistor 1140 is connected to the NVINT node by via a switch 1160 controlled by the signal AZ. The control node of the transistor 1140 is further connected to ground via a resistor 1139 in series with a capacitor 1143.

[0116] The control node NC7 of the transistor 1142 is connected to ground via a resistor 1152 in series with a capacitor 1162. The control node of the transistor 1142 is further connected to the node NVINT via a switch 1150 controlled by the signal AZ in series with a switch 1154 controlled by the signal AZB. The switch 1150 is further connected, preferably connected, to the conduction node NC6 common to the transistors 1124 and 1128.

[0117] [Fig. 12] represents a timing diagram of operation of a circuit of [Fig. 1] when a circuit of [Fig. 3] is used. More particularly, [Fig. 12] represents the output voltage OM-OP of the amplifier circuit 300 as well as the common mode voltage between INP and INM.

[0118] Before a time t' 1, the common mode voltage INM / INP is at 0V and the output voltage is stable at 3.5V.

[0119] At a time t' 1, the common mode voltage INM / INP suddenly increases to 48V, which creates instability in the output voltage as well as a temporary overshoot.

[0120] At a time t'2, 1.3 ps after time t' 1, the output voltage returns to a value range of between ±0.5% of the value before change of the common mode voltage INM / INP. The return time is therefore improved by the circuit 300 of [Fig.3] in comparison with the return time of the circuit 102 of [Fig.2].

[0121] [Fig. 13] schematically represents a motor system according to one embodiment. The system comprises a control circuit which supplies the motor 108 with three phases. The current which passes through each phase is for example measured using a resistor 106 to the terminals of which the circuit 300 is connected.

[0122] The control circuit comprises for example three branches in parallel and connecting a voltage rail VM to ground. Each branch comprises two power transistors respectively called 1302,1312; 1304,1306; 1308,1310. The conduction node common to the transistors of the same branch is connected, preferably connected, to one of the phases of the motor.

[0123] To measure the current in each of these branches, a resistor 106 is inserted between transistor 1312 and ground, and / or between transistor 1306 and ground, and / or between transistor 1310 and ground. A circuit similar to circuit 109 with circuit 300 is then connected across each resistor 106.

[0124] Such a control circuit makes it possible to carry out current measurements with precision, even during voltage changes on the different phases.

[0125] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. In particular, even if the unity gain amplifier 320 is associated, in [Fig. 3], with the detector 310 and the unit 321, the person skilled in the art may consider implementing only the detector and the control unit 321. Furthermore, even if the detection of rising and falling edges is described in separate Figures 7 and 8, the detector 310 may include both of these circuits.

[0126] Finally, the practical implementation of the embodiments and variants described is within the reach of the person skilled in the art from the functional indications given above. In particular, with regard to the amplifier stage formed by the circuits 216, 218, 220 which is configured to compensate for an offset voltage present at its input, it is possible to replace the circuits 218 and 220 with an assembly with automatic compensation of the offset of the input voltage (Auto Zero, in English).

Claims

Claims

1. A multi-path amplifier circuit (300) comprising: first and second amplification paths (201, 202) for an input voltage, connected in parallel, the first path comprising a first amplifier stage (216, 218, 220), a second amplifier stage (226) and a band-stop filter (NOTCH FILTER) between a first node (NOMF, NVOPF) connected to the second amplifier stage (226) and a second node (NVOMI, NVOPI) connected to an output of the first amplifier stage (216, 218, 220); and a control unit (321) configured to, following detection of a common mode change in the input voltage and for a first duration, open said first path (201) and connect the first node (NVOMF, NVOPF) to the second node (NVOMI, NVOPI) with a unity gain amplifier (320).

2. A circuit according to claim 1, wherein the second path (202) is taken when frequencies of the input voltage are higher than a first frequency and wherein the first path (201) is taken when frequencies of the input voltage are lower than this first frequency.

3. A circuit according to claim 1 or 2, wherein the first amplifier stage (216,218,220) is configured to compensate for an offset voltage present at its input.

4. The circuit of claim 3, wherein the first amplifier stage (216,218,220) comprises a first amplifier (216) connecting, a first shaping circuit (218) configured to modulate an input voltage of the first amplifier (216), and a second shaping circuit (220), configured to demodulate an output voltage of the first amplifier (216).

5. A circuit according to any one of claims 1 to 4, wherein the unity gain amplifier (320) is configured to implement offset compensation of its input voltage.

6. The circuit of claim 5, wherein the unity gain amplifier (320) is configured to copy the input voltage offset of the second amplifier stage (226) to the second node with an offset less than or equal to 50pV during the first duration.

7. Circuit according to claim 5 or 6, in which the unity gain amplifier (320) comprises: an amplifier stage (AVOUT) one output of which is configured to be connected to the second node (NVOMI, NVOPI), a first and a second differential amplifier circuit (AZ AVI) configured to, each in turn, measure and compensate their respective voltage offset.

8. Circuit according to claim 7, in which the first and second differential amplifier circuits (AZ AVI) each have: respective first inputs (IM) connected to the second node (NVOMI, NVOPI), respective second inputs (IP) connected to the first node (NVOMF, NVOMP), and respective outputs connected to an input node (NVINT) of the amplifier stage (AVOUT).

9. Circuit according to any one of claims 1 to 8, in which the detection of change of common mode of the input voltage is implemented by a detector (310) of rising and / or falling edge of the common mode of the input voltage.

10. A circuit according to any one of claims 1 to 9, wherein the amplifier circuit (300) comprises: a fourth amplifier (228) connecting an output node (OM,OP) of the amplifier circuit (300) and an output of the second amplifier stage (226); and a first capacitive element (C2) connecting said output node (OM,OP) and said output of the second amplifier stage (226).

11. Circuit according to claim 10, in which a second capacitive element (Cl) connects the second node (NVOMI, NVOPI) and the output node (OM, OP) of the amplifier circuit (300).

12. Circuit according to any one of claims 1 to 11, in which the second node (NVOMI, NVOPI) is connected to a third capacitive element (C3).

13. A method of operating a multipath amplifier circuit (300) according to any one of the preceding claims, the method comprising, following detection of a common mode change in the input voltage and for a first duration, implementing a control unit (321) of the circuit (300) to: - open the first path, and - connect the first node (NVOMF, NVOPF) to the second node (NVOMI, NVOPI) with a unity gain amplifier (320).

14. Electronic current determining device comprising a measuring resistor (106) and an amplifier circuit (300) according to any one of claims 1 to 13, wherein the input voltage of the amplifier circuit is taken between two terminals of said resistor (106).

15. A system for controlling a motor (108) comprising a motor (108) and a device according to claim 14 implemented on at least one supply phase of the motor (108).

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