Electromagnetic radiation detector

Abstract

The invention relates to a detector of electromagnetic radiation, comprising an absorber configured to absorb the electromagnetic radiation, a MOS-FET type transistor thermally coupled to the absorber, and a control circuit. The transistor comprises a source and a drain doped with a first conductivity type, a channel, and a gate electrically insulated from the channel by a gate dielectric layer of the transistor. The control circuit is electrically connected to the source, the drain and the gate, and configured to apply an electric potential difference between the gate and the source less than or equal to a threshold voltage of the transistor. The gate is made of silicon doped with a second conductivity type opposite to the first conductivity type with a majority charge carrier concentration less than or equal to 1019 cm-3. The gate dielectric layer has a thickness less than or equal to 50 nm. Figure for abstract: Figure 1A

Description

Title of the invention: Detector of electromagnetic radiation Technical field

[0001] The field of the invention is that of the detection of electromagnetic radiation, in particular infrared or terahertz, more precisely that of thermal detectors of the bolometer type using a thermometer comprising a field effect transistor. The invention also relates to a method of manufacturing such a detector. STATE OF THE PRIOR ART

[0002] A detector of electromagnetic radiation, also called a photodetector, may comprise a matrix of at least one pixel each comprising a thermal detector of the bolometer type. Each bolometer comprises a micro-board suspended above a substrate by thermal insulation arms. The micro-board comprises an absorber capable of transforming the electromagnetic radiation into thermal energy, and a thermometer thermally coupled to the absorber and adapted to provide an electrical signal representative of a temperature variation of the absorber. The detector further comprises a control circuit integrated in and on the substrate. It is electrically connected to the thermometer via the thermal insulation arms and is configured to read the electrical signal provided by the thermometer.

[0003] The thermometer may comprise a sensitive material whose electrical resistivity varies depending on the temperature of the material, such as vanadium oxide (VOx). Patent application WO201855276 proposes a solution for which the sensitive material is replaced by a field effect transistor. The device described in this patent application makes it possible to improve the response time of prior art transistor bolometers. It is also suitable for pixel sizes of less than 10 pm.

[0004] In this document, the thermometer comprises a MOS type transistor. The transistor comprises a "mid-gap" type metal gate allowing the gate voltage to be lowered in operation in a range between 50 mV and 75 mV. Thus, a temperature variation of the transistor channel causes a large variation in the drain current, which is the electrical signal read by the control circuit. The thermometer is therefore particularly sensitive.

[0005] Patent application WO2021123616 proposes a technical improvement making it possible to increase the signal-to-noise ratio of the electrical signal read by the control circuit. The thermometer of the device described in this document also comprises a field-effect transistor that includes a front gate made of a "mid-gap" type metal. The drain current of the transistor constitutes the electrical signal read by the control circuit. The transistor also has a back gate, on one side of a channel of the transistor opposite the front gate.

[0006] In WO2021123616, it is proposed to generate a blocking layer at one of two opposite faces of the transistor channel, both extending parallel to the front gate. The blocking layer may be a charge carrier accumulation or inversion layer. It makes it possible to reduce the influence of a gate voltage variation on the drain current, and consequently to increase the signal-to-noise ratio.

[0007] The blocking layer appears for specific gate bias voltages that are quite high, up to 7 V or even 12.5 V in absolute value, which are incompatible with a standard control circuit designed to generally deliver a bias voltage of 3 V or less. It is possible to lower them in absolute value either by superficially doping the channel or by forming a gate oxide of the particular transistor. More precisely, in the latter case, the gate oxide consists of two sub-layers made of particular materials making it possible to generate an electrostatic dipole between the front gate and the channel. However, both of these possibilities have the disadvantage of being difficult to manufacture. Statement of the invention

[0008] The invention aims to remedy at least in part the drawbacks of the prior art, and more particularly to propose a sensitive thermal detector, comprising an improved signal-to-noise ratio, compatible with a standard control circuit.

[0009] For this purpose, the subject of the invention is a detector of electromagnetic radiation, comprising an absorber configured to absorb the electromagnetic radiation, a MOS-FET type transistor thermally coupled to the absorber. The MOS-FET type transistor comprises a source doped with a first conductivity type, a drain doped with the first conductivity type, a channel extending from the source to the drain, a gate electrically insulated from the channel by a gate dielectric layer of the transistor.

[0010] The detector further comprises a control circuit electrically connected to the source, the drain and the gate; and configured to apply an electrical potential difference between the gate and the source less than or equal in absolute value to a threshold voltage of the transistor. The gate is made of silicon doped with a second conductivity type opposite to the first conductivity type with a majority charge carrier concentration less than or equal to 1019 cm 3. The dielectric layer of grid has a thickness less than or equal to 50 nm.

[0011] Some preferred but non-limiting aspects of this detector are as follows.

[0012] The detector may further comprise a substrate, a micro-board of a dielectric material suspended above the substrate, and a semiconductor portion extending over a lower face of the micro-board in which the drain, channel and source may be housed.

[0013] The absorber may extend over a portion of the micro-board devoid of the semiconductor portion.

[0014] The transistor may further comprise a rear gate electrically connected to the control circuit and electrically isolated from the channel by the micro-board.

[0015] The rear grid may be a part of the absorber.

[0016] The micro-board may have a thickness of between 10 nm and 150 nm.

[0017] The drain and the gate can be connected to the control circuit by a first arm thermal isolation, the source can be electrically connected to the control circuit by a second thermal isolation arm, and the micro-board can be suspended above the substrate by the first and second thermal isolation arms.

[0018] The rear grid can be electrically connected to the source by a rear face electrical contact passing right through the micro-board, and the source can be electrically connected to the second thermal insulation arm by a source electrode opposite the rear face electrical contact.

[0019] The transistor may be a depletion transistor.

[0020] The transistor may be an enhancement-mode transistor.

[0021] The invention also relates to a method for manufacturing a detector according to any one of the preceding characteristics, comprising the following steps of forming the gate: forming a sacrificial pad; forming spacers on flanks of the sacrificial pad; conformal deposition of a first barrier layer on the spacers and the sacrificial pad; deposition of a planarizing semiconductor layer so as to completely cover the first barrier layer, polishing the planarizing semiconductor layer with a stop on the first barrier layer to obtain a first sacrificial layer; etching a gate opening passing right through the first barrier layer through an upper surface of the first barrier layer opposite the sacrificial pad, the opening having dimensions strictly smaller than dimensions of the sacrificial pad;removal of the sacrificial pad to obtain a cavity in place of the sacrificial pad; filling the cavity with silicon so as to plug the gate opening and thus obtain the gate.;

[0022] The sacrificial pad may be formed on a semiconductor portion in which the drain, channel, and source may be accommodated, and the sacrificial pad may shield the channel. during a source and drain installation step.

[0023] The sacrificial pad can be made of silicon.

[0024] The cavity filling step may comprise deposition of an in-situ doped planarizing semiconductor layer, so as to completely fill a volume of the cavity in communication with the gate opening and to cover the first sacrificial layer and the first barrier layer; polishing of the planarizing semiconductor layer with stopping on the first sacrificial layer.

[0025] The manufacturing method may further comprise a release etch of the micro-board during which the first sacrificial layer is selectively etched relative to the first barrier layer and the gate. Brief description of the drawings

[0026] Other aspects, aims, advantages and characteristics of the invention will appear better on reading the following detailed description of preferred embodiments thereof, given by way of non-limiting example, and made with reference to the appended drawings in which:

[0027] [Fig.1A] is a schematic view along a section plane AA of an example of a photodetector according to the invention;

[0028] [Fig.1B] is a schematic view along a section plane BB of the example photodetector;

[0029] [Fig.2] is a partial top view of the example photodetector on which the section planes AA and BB are represented;

[0030] [Fig.3] illustrates a polarization diagram of a transistor implemented in the photodetector example;

[0031] [Fig.4] shows simulation results by design assistance software;

[0032] Figures 5A to 5N illustrate intermediate steps of a method of manufacturing a first intermediate structure;

[0033] [Fig.6A] is a schematic sectional view of the first intermediate structure;

[0034] [Fig.6B] is a schematic sectional view of a second intermediate structure to be assembled with the first intermediate structure to obtain the photodetector example.

[0035] DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS

[0036] In the figures and in the remainder of the description, the same references represent identical or similar elements. In addition, the different elements are not shown to scale so as to enhance the clarity of the figures. Furthermore, the different embodiments and variants are not mutually exclusive and may be combined with each other. Unless otherwise indicated, the terms "substantially", "approximately", "in the order of" mean within 10%, and preferably to within 5%. Furthermore, the terms “between ... and ...” and equivalents mean that the limits are included, unless otherwise stated.

[0037] The invention relates to a detector of electromagnetic radiation, preferably in the infrared or terahertz range. The photodetector comprises a matrix of at least one pixel. The pixels may for example have a size of between 5 pm and 12 pm, in particular when the electromagnetic radiation has a wavelength of between 8 pm and 14 pm, i.e. in the far infrared range.

[0038] Each pixel comprises an absorber configured to absorb electromagnetic radiation and a thermometer. The thermometer comprises a MOS-FET type transistor thermally coupled to the absorber, such that the temperature of the transistor increases as the power of the electromagnetic radiation absorbed by the absorber increases. The transistor is electrically connected to a control circuit. It has a source and a drain doped with a first conductivity type, and a gate made of a semiconductor material doped with a second conductivity type. The gate is electrically insulated from a channel of the transistor by a gate dielectric layer of the transistor.

[0039] In operation, the control circuit applies an electrical potential difference between the gate and the source less than or equal in absolute value to a threshold voltage of the transistor, advantageously constant. Thus, the transistor operates in a so-called low inversion regime. In this regime, the drain current is sensitive to variations in parameters of the transistor, such as for example a fluctuation in the gate voltage or a variation in the temperature of the channel, here proportional to a variation in the power of the electromagnetic radiation absorbed by the absorber.

[0040] In the context of the invention, the second conductivity type is opposite to the first conductivity type, the gate has a majority charge carrier concentration less than a maximum concentration identified by the inventors, and the thickness of the gate dielectric layer has a thickness less than or equal to a maximum thickness also identified by the inventors. The inventors have found that in operation, the combination of these characteristics creates a depleted zone in the gate in the vicinity of the gate dielectric layer. The inventors have further identified that the occurrence of this depleted zone in combination with the conductivity type of the gate results in increasing the temperature-dependent current coefficient (TCC) of the transistor, while reducing the sensitivity of the drain current to variations in transistor parameters other than temperature.Thus, the sensitivity of the detector is increased along with a signal-to-noise ratio. The TCC value can be increased up to 25% compared to transistors implementing a "mid-gap" type metal gate. of the prior art.

[0041]

[0042] A MOS-FET (or Metal-Oxide-Semiconductor Field Effect Transistor) is a field-effect transistor comprising a channel and an electrostatic control gate electrically insulated from the channel by a dielectric layer of the transistor's gate. The gate is not necessarily metallic, contrary to what a literal translation of the English name might suggest. It can be made of a semiconductor material, such as doped polycrystalline silicon. Applying a bias voltage to the gate allows the channel's conductivity to be modulated to control an electric current flowing in the channel between a source and a drain of the transistor. This electric current is called the drain current ID. The temperature coefficient of current variation (TCC) is an important characteristic of a MOS-FET transistor. It is given by the relationship TCC = — ' °where Id is the dT transistor drain current and T temperature.

[0043] A depleted region or zone of a semiconductor layer is understood to mean a region within which the concentration of mobile charge carriers is substantially reduced, for example under the effect of diffusion, an electric field or recombinations. The region has a concentration of mobile charge carriers strictly lower than the concentration of doping species of the same type as the mobile charge carriers in the region. The region may be completely devoid of mobile or free charge carriers. A depleted region or zone may be identified on simulation results.

[0044] In the description, two elements are "thermally coupled" when a thermal conduction path links the two elements such that heat can be efficiently transferred from one to the other. The two elements may be in physical contact with each other. They may also be separated from each other by a medium of low thermal resistance, for example less than or equal to 1E3 K / W. Alternatively or additionally, heat may be transferred from one to the other by convection and / or radiation.

[0045] By layer is meant here and for the remainder of the description, an area consisting of one or more sub-layers of a material whose thickness along a z axis is less, for example ten times, or even twenty times, than its longitudinal dimensions of width and length in an xy plane perpendicular to the z axis. A layer can be structured. When it consists of several sub-layers, the sub-layers can be made of different materials. The sub-layer(s) extend in planes substantially parallel to the xy plane.

[0046] Particular embodiments will be described relating to a detector of electromagnetic radiation comprising an absorber configured to absorb the electromagnetic radiation, thermally coupled to a MOS-FET type transistor. However, these embodiments can be adapted to other optoelectronic devices, such as for example a fingerprint sensor exploiting a difference in thermal conductivity between the peaks and valleys of fingerprints. In this case, the heat can for example be transferred from the finger to the absorber by thermal conduction.

[0047] An example of a photodetector according to the invention will be described in connection with Figures 1A, 1B and 2. A single pixel of the photodetector is shown in these figures but the photodetector may comprise several pixels identical to that shown, for example arranged in a matrix. [Fig. 2] is a schematic top view of the pixel in which only certain characteristics of the photodetector have been shown for the sake of clarity. Figures 1A and 1B are partial views along the section planes AA and BB, respectively, shown in [Fig. 2]. For the sake of clarity, only two extreme parts of the respective section planes are shown here.

[0048] In this example, the MOS-FET type transistor may be an enhancement-mode NMOS type transistor. Alternatively, the MOS-FET type transistor may be a depletion-mode NMOS type transistor, an enhancement-mode PMOS type transistor, or a depletion-mode PMOS type transistor, without departing from the scope of the invention.

[0049] The photodetector 1 comprises a substrate 100, a control circuit (not shown) and a matrix of at least one pixel. The matrix extends parallel to the substrate 100. The pixel comprises a micro-board 160, an absorber 170 and a MOS-FET type transistor. The micro-board 160 is suspended above the substrate 100. The substrate 100 comprises a substantially planar upper face 100.1 on the same side as the micro-board 160 relative to the substrate 100.

[0050] Here and for the remainder of the description, a direct three-dimensional orthogonal reference frame (X, Y, Z) is defined, where the X and Y axes form a plane parallel to the upper face 100.1 of the substrate 100, and where the Z axis is oriented orthogonally to the upper face 100.1, from the upper face 100.1 towards the micro-board 160. When the photodetector 1 comprises a matrix of several pixels, the X axis and / or the Y axis are oriented along respective axes of the matrix. In the remainder of the description, the terms “vertical” and “vertically” are understood as relating to an orientation substantially parallel to the Z axis, and the terms “horizontal” and “horizontally” as relating to an orientation substantially parallel to the (X, Y) plane. Furthermore, the terms “lower” and “upper” are understood as relating to an increasing positioning when moving away from the substrate 100 in the +Z direction.

[0051] The substrate 100 may for example be, at least in part, derived from a wafer, for example made of silicon, and may possibly have undergone cutting and / or thinning steps. It may comprise a stack of interconnections comprising one or more levels of conductive lines extending parallel to the plane (X, Y), possibly interconnected with each other by conductive vias. Where appropriate, the upper face 100.1 of the substrate 100 is an upper face of the stack of interconnections. The control circuit is integrated in and / or on the substrate 100 and may comprise conductive lines and / or vias of the stack of interconnections.

[0052] The micro-board 160 is here made of one or more electrically insulating materials, advantageously dielectric, for example silicon oxide (SiO). It may comprise on one or more of its faces an electrically insulating layer, for example a layer serving to protect the micro-board 160 during etching. It extends parallel to the upper face 100.1 of the substrate 100. It is for example rectangular or square in shape in a plane parallel to the plane (X, Y).

[0053] The MOS-FET transistor comprises a drain 150.3, a source 150.1 and a channel 150.2 extending parallel to the plane (X, Y) from the drain 150.3 to the source 150.1. The drain 150.3, the source 150.1 and the channel 150.2 are housed in a semiconductor portion 150 made of a monocrystalline semiconductor material, for example silicon (Si) or silicon-germanium (SiGe). The semiconductor portion 150 extends here on a lower face of the micro-board 160 so as to be in physical contact with the latter. It has for example a thickness measured parallel to the Z axis of between 5 nm and 100 nm, preferably between 15 nm and 50 nm. The drain 150.3 and the source 150.1 are doped with a first conductivity type and may include regions having different dopant atom concentrations and / or dopant atoms of different natures. In this particular example, the drain 150.3 and the source 150.1 are N-type doped; the channel 150.2 is P-type or intrinsic doped.

[0054] The transistor comprises a gate 135 and a gate dielectric layer 140. The gate 135 is electrically insulated from the channel by the gate dielectric layer 140. The gate dielectric layer 140 comprises one or more sub-layers, each made of a dielectric material. The dielectric material may for example be a silicon oxide (SiO) or a hafnium dioxide (HfO2). In this example, the gate dielectric layer 140 is a single layer of silicon oxide (SiO).

[0055] The gate 135 is made of a semiconductor material doped with a second conductivity type opposite to the first conductivity type. In this example, the gate 135 is made of polycrystalline or amorphous silicon. It may be partly silicided, that is to say that the gate 135 may comprise a region made of a silicide, located on one side of the gate 135 opposite the gate dielectric layer 140. Here it is doped with the P type. since the drain 150.3 and the source 150.1 are N-type doped. For example, it has a thickness measured parallel to the Z axis of between 10 nm and 200 nm, preferably between 25 nm and 100 nm.

[0056] The gate dielectric layer 140 is interposed between the channel 150.2 and the gate 135, in physical contact with the channel 150.2 and the gate 135. It has a thickness measured parallel to the Z axis less than a maximum thickness and the gate 135 has a majority charge carrier concentration less than a maximum concentration, such that in operation, a depleted zone 135.1 appears in the gate 135. The thickness of the gate dielectric layer 140 is sufficiently small so that a Fermi level of the gate 135 aligns with a Fermi level of the channel 150.2 so as to bend gap energy bands of the gate 135 in the vicinity of the gate dielectric layer 140. The depleted zone 135.1 is shown by a dotted line in FIGS. 1A and 1B. It extends deep into the gate from the gate dielectric layer 140. For example, it has a thickness between 2 nm and 15 nm.For example, it can be identified on simulation results.

[0057] In the case where the gate is made of polycrystalline or amorphous silicon, as in this example, the maximum thickness is equal to 50 nm and the maximum concentration is equal to 1019 cm3. The thickness of the gate dielectric layer 140 is for example between 3 nm and 50 nm, preferably between 4 nm and 20 nm, or even between 4 nm and 15 nm. The average concentration of majority charge carriers of the gate 135 is for example between 5.1015 cm3 and 1019 cm3, preferably between 1016 cm3 and 5.1018 cm3.

[0058] The absorber 170 extends over a face of the micro-board 160 opposite the semiconductor portion 150, so as to be in contact with the micro-board 160. This is an upper face of the micro-board 160 since the semiconductor portion 150 extends over the lower face. The absorber 170 is a metal layer. It advantageously has a resistance substantially equal to the impedance of vacuum, namely 377 Q / square. It may comprise one or more metal sub-layers of Ti, TiN, NiCr, Al, Au, W, Cu, AlCu, etc. The absorber 170 is here a layer of titanium nitride (TiN) with a thickness of between 3 nm and 50 nm, preferably between 3 nm and 10 nm. The absorber 170 may also comprise an antenna.

[0059] In this example, the absorber 170 comprises a portion facing the channel 150.2. The micro-board 160 has a thickness measured parallel to the Z axis at the channel that is sufficiently small to allow thermal coupling between the absorber 170 and the channel 150.2, and to be able to apply an electric field in the channel 150.2 when the absorber 170 is electrically polarized. The thickness of the micro-board 160 is sufficiently large to ensure good mechanical strength. In the case of a micro-board 160 made of silicon oxide (SiO), as in this example, the micro-board 160 has a thickness of between 10 nm and 150 nm, preferably between 10 nm and 50 nm, for example equal to 25 nm.

[0060] The absorber 170 preferably extends over the entire upper face of the microboard 160, as shown here. Advantageously, it extends over a portion of the microboard 160 devoid of the semiconductor portion 150, that is to say it extends over a portion of the upper face which is not opposite the semiconductor portion 150. Thus, the absorption of electromagnetic radiation by the absorber is maximized.

[0061] Here, the gate 135 has a closed ring shape in a plane parallel to the plane (X, Y). The semiconductor portion 150 also has a closed ring shape in this plane. The gate 135 and the semiconductor portion 150 each have, for example, a substantially constant horizontal width along the ring. The gate 135 is here centered at all points on the semiconductor portion 150.

[0062] Optional spacers 136 are in contact with opposite sides of the gate 135. The drain 150.3 and the source 150.1 extend here in respective parts of the semiconductor portion 150 opposite the spacers 136. The limits between the drain 150.3, the channel 150.2 and the source 150.1 are shown schematically by dotted lines in FIGS. 1A and 1B. The spacers 136 may be flush with a lower face of the gate 135 opposite the gate dielectric layer 140. They are made of one or more electrically insulating materials, for example one or more dielectric materials such as silicon oxide (SiO) or silicon nitride (SiN). Here they are made of silicon nitride (SiN).

[0063] The micro-board 160 is suspended above the substrate 100 by thermal insulation arms 120, two arms in the example shown. In other words, the micro-board 160 is held above the substrate 100 by the arms so as not to be in physical contact with the substrate 100.

[0064] The thermal insulation arms 120 are arranged between the micro-board 160 and the substrate 100. They extend in a plane parallel to the plane (X, Y). Each thermal insulation arm 120 has a proximal end fixed to the micro-board 160 by an electrode 121, 123, 125, and a distal end resting on an anchoring pillar 105, 115. Each thermal insulation arm 120 is electrically conductive. It has a cross-section and a length making it possible to thermally isolate the micro-board 160 and the transistor from the substrate 100 and the control circuit. The smaller the cross-sectional area and / or the longer the length of a thermal insulation arm 120, the better the thermal insulation of the micro-board 160. To increase the length, it is for example possible to give each thermal insulation arm 120 a serpentine shape as shown in [Fig.2].Each thermal insulation arm 120 may have a conductive metal core. of electricity, surrounded by an insulating sheath, for example made of an etch-resistant material used to remove a sacrificial material on which the micro-board 160 rests during an intermediate step of a manufacturing process. In this example, the core is made of titanium nitride (TiN) and the sheath is made of amorphous silicon, capable of resisting etching by hydrofluoric acid in the vapor phase.

[0065] Here, a first thermal insulation arm 120 has its proximal end fixed to the micro-board 160 by a source electrode 121 in contact with the source 150.1 of the transistor. The source electrode 121 is made of an electrically conductive material. It is in contact with the core of the first thermal insulation arm 120. The distal end of the first thermal insulation arm 120 rests on an upper anchoring pillar 115, which itself rests on a lower anchoring pillar 105. The upper anchoring pillar 115 is in contact with the core of the first thermal insulation arm 120 and the lower anchoring pillar 105 is electrically connected to the control circuit, so that the source 150.1 is electrically connected to the control circuit by the source electrode 121, the first thermal insulation arm 120 and the lower and upper anchoring pillars 105, 115.

[0066] A second thermal isolation arm 120 has its proximal end attached to the micro-board 160 by a gate electrode 125 in contact with the gate 135 and a drain electrode 123 in contact with the drain 150.3. The drain and gate electrodes 123, 125 are in contact with the core of the second thermal isolation arm 120, so that the gate 135 and the drain 150.3 are short-circuited. The distal end of the second thermal isolation arm 120 rests on an additional upper anchoring pillar 115, which itself rests on an additional lower anchoring pillar 105. The additional upper anchor pillar 115 is in contact with the core of the second thermal insulation arm 120 and the additional lower anchor pillar 105 is electrically connected to the control circuit, so that the grid 135 and the drain 150.3 are electrically connected to the control circuit by the second thermal insulation arm 120, the lower and upper anchor pillars 105, 115, and, respectively, the gate electrode 125 and the drain electrode 123. .

[0067] The lower and upper anchoring pillars 105, 115 are made of metal, for example of the same metal material. In the latter case, there may not be an interface between the lower anchoring pillar 105 and the upper anchoring pillar 115. The lower anchoring pillars 105 are for example all of identical shape and size. The upper anchoring pillars 115 are for example all of identical shape and size. The lower and upper anchoring pillars 105, 115 are here of cylindrical shape of the same diameter, with a longitudinal axis parallel to the Z axis. In this example, they are made of copper, possibly coated with a protective coating.

[0068] The source, drain and gate electrodes 121, 123, 125 are metallic. They have for example a tungsten (W) core surrounded by a first titanium nitride (TiN) coating, itself surrounded by a second titanium (Ti) coating. Here they are cylindrical in shape with the same diameter, with a longitudinal axis parallel to the Z axis.

[0069] In this example, the pixel further comprises a rear face electrical contact 128 electrically connecting the absorber 170 to the source 150.1. More precisely, the rear face electrical contact 128 is a part of the absorber 170 matching a through opening 161 extending from the upper face to the lower face of the micro-board 160. The through opening 161 here has a cylindrical shape coaxial with the source electrode 121. In this case, the part of the absorber 170 facing the channel 150.2 constitutes an optional rear gate of the transistor, at the same electrical potential as the source 150.1.

[0070] The photodetector 1 further comprises a lower barrier layer 110 and an upper barrier layer 130, which are optional. The lower barrier layer 110 extends over the upper face of the substrate 100. The lower anchoring pillars 105 pass right through the lower barrier layer 110, so as to leave no space between the lower barrier layer 110 and the lower anchoring pillars 105. The upper barrier layer 130 extends over the lower face of the micro-board 160, over the gate 135, the spacers 136, over lateral flanks of the gate dielectric layer 140 and over lateral flanks of the micro-board 160. The source, drain and gate electrodes 121, 123, 125 pass right through the upper barrier layer 130, so as to leave no space between the lower barrier layer 110 and the source, drain and gate electrodes 121, 123, 125.The lower and upper barrier layers 110, 130 are made of a material capable of resisting etching used to remove a sacrificial material on which the micro-board 160 rests during an intermediate step of a manufacturing process.

[0071] The photodetector example 1 described in connection with Figures 1A, 1B, 2 is advantageous because it allows the micro-board 160 to be suspended with only two thermal isolation arms 120, and therefore to isolate the micro-board 160 and the MOS-FET type transistor optimally. However, in accordance with the biasing scheme of [Fig. 3], the electrical potentials VG, Vs, VD, VBg applied respectively to the gate 135, the drain 150.3, the source 150.1 and the optional rear gate can be fixed independently of each other, without departing from the scope of this invention. The gate 135, the source 150.1, the drain 150.3 and the rear gate can each be electrically connected to the control circuit via or without the intermediary of a thermal isolation arm. The thermal insulation arms 120 are therefore optional and can be any number less than or equal to 4 when present.

[0072] In [Fig.4], simulation results of the photodetector example are presented. 1 of figures 1A, 1B and 2 obtained by design assistance software (TCAD software, or Technology Computer Aided Design, in English). The transistor is of the N-MOS type. The channel 150.2 has a length L equal to 0.5 pm, that is to say that the drain 150.3 is separated at all points from the source 150.1 by a minimum distance equal to 0.5 pm under the gate 135. The length L is commonly called the gate length in the technical field. The gate width W is the length of a center line separating the drain 150.3 from the source 150.1 and extending from one end to the other of the channel 150.2. When the canal has a closed ring shape, the midline also has a closed ring shape.

[0073] The thickness of the gate dielectric layer 140 is equal to 9 nm. The gate dielectric layer 140 is made of silicon oxide (SiO). The electrical potentials VBg and Vs, respectively applied to the rear gate and to the source, are equal to 0V. The electrical potential difference between the gate 135 and the source 150.1 varies so as to vary the drain current ID.

[0074] In [Fig.4], the value of the TCC (ordinate axis in %.K ') is given as a function of Id.W / L (abscissa axis in amperes) for three different concentrations of majority charge carriers in the gate 135 (curves C1, C2 and C3), here of acceptor type, and for a prior art MOS-FET transistor comprising a metal gate of the "mid-gap" type (curve C0). The TCC curve for the metal gate of the "mid-gap" type is always lower than the other two curves. The value of the TCC increases when the concentration of majority charge carriers in the gate 135 decreases. The gain in TCC compared to a “mid-gap” type metal grid is thus equal to 6% for an acceptor type doping concentration Na equal to 1019 cm3 (curve Cl), equal to 14% for Na equal to 1018 cm3 (curve C2), and equal to 25% for Na equal to 1016 cm3 (curve C3).

[0075] The inventors have further verified that the TCC does not vary substantially with a variation in the thickness of the gate dielectric layer 140. The relative variation in the TCC is for example strictly less than 2% for a variation in the thickness of the gate dielectric layer 140 of between 5 nm and 20 nm, a normalized drain current ID.W / L varying between 10 14 A and 5.10 4 A and a concentration of dopant atoms of acceptor type Na in the gate 135 equal to 1017 cm3.

[0076] The inventors have also verified that the TCC does not vary substantially with a variation in the thickness of the gate 135. The variation in the TCC is for example substantially zero for a variation in the thickness of the gate 135 of between 25 nm and 150 nm, and a concentration of doping atoms of the Na acceptor type in the gate 135 equal to 1017 cm 3.

[0077] An example of a method for manufacturing a photodetector 1 according to the invention will now be described in connection with FIGS. 5A to 5N, 6A and 6B. In this example, the photodetector 1 comprises an enhancement-mode NMOS transistor. However, it is easy to modify the dopings of the manufacturing process to obtain a photodetector 1 comprising a depletion-mode NMOS transistor, or an enhancement-mode PMOS transistor, or a depletion-mode PMOS transistor. Figures 5A to 5N illustrate intermediate steps of the exemplary manufacturing process aimed at obtaining a first intermediate structure 10 as illustrated in [Fig. 6A].

[0078] In [Fig.5A], an assembly is provided comprising a temporary substrate 200, a buried dielectric layer 210 and an upper semiconductor layer. The buried dielectric layer 210 is interposed and in contact with the temporary substrate 200 and the upper semiconductor layer. The temporary substrate 200 has an upper face located at the interface between the temporary substrate 200 and the buried dielectric layer 210. The upper semiconductor layer may be doped or intrinsic. The assembly may for example be a silicon on insulator or SOI type plate, for “Silicon on Insulator” in English. The upper semiconductor layer and the temporary substrate 200 are then made of monocrystalline silicon, and the buried dielectric layer 210 is made of silicon oxide (SiO). Here, the assembly is an SOI plate, for example 200 mm or 300 mm in diameter, and the upper semiconductor layer is made of P-doped monocrystalline silicon.

[0079] The buried dielectric layer 210 preferably has a thickness of between 10 nm and 150 nm, preferably between 10 nm and 50 nm, for example equal to 25 nm. The upper semiconductor layer has for example a thickness of between 5 nm and 100 nm, preferably between 15 nm and 40 nm.

[0080] The entire thickness of the upper semiconductor layer is then locally etched to obtain a semiconductor portion 150 intended to accommodate a source 150.1, a channel 150.2 and a drain 150.3 of a MOS-FET transistor. The semiconductor portion 150 may have any shape in a plane parallel to the upper face of the temporary substrate 200. It has an upper face and flanks. The upper face of the semiconductor portion 150 joins the flanks on a side of the semiconductor portion 150 opposite the buried dielectric layer 210. The semiconductor portion 150 may have a width measured parallel to the upper face that is substantially constant. Here, it has a closed, substantially rectangular ring shape.

[0081] In [Fig.5B], a conformal layer is formed on the sides and the upper face of the semiconductor portion 150. The conformal layer is intended to be a gate dielectric layer 140 of the transistor. It is made of a dielectric material. It can be obtained by deposition, or, when it is made of silicon oxide (SiO), as in this example, by thermal oxidation.

[0082] The conformal layer typically has a thickness of between 3 nm and 50 nm, at level of the upper face of the semiconductor portion 150.

[0083] In [Fig.5C], a planarizing sacrificial layer 215 is formed. The planarizing sacrificial layer 215 is made of a material that can be selectively etched relative to the gate dielectric layer 140. It may, for example, be made of amorphous or polycrystalline silicon, or of a polymer. Here, it is made of polycrystalline silicon, deposited by low-pressure chemical vapor deposition, or LPCVD (Liquid Phase Chemical Vapor Deposition).

[0084] The planarizing sacrificial layer 215 has a surface that is substantially flat and parallel to the upper face of the temporary substrate 200 facing the semiconductor portion 150, preferably facing a substantial part of the upper face of the temporary substrate 200.

[0085] In [Fig.5D], a sacrificial pad 220 is formed. For this, the planarizing sacrificial layer 215 is locally etched right through to obtain the sacrificial pad 220. The sacrificial pad 220 has flanks that are substantially orthogonal to the upper face of the temporary substrate 200, joined by an upper face of the sacrificial pad 220 located on one side of the sacrificial pad 220 opposite the temporary substrate 200. It has a width equal to the minimum distance separating two opposite flanks of the sacrificial pad 220 in a plane parallel to the upper face of the temporary substrate 200, and a thickness measured perpendicular to the upper face. It rests entirely on a central region of the semiconductor portion 150, so as to separate, from one another, two opposite regions of the semiconductor portion 150, located on either side of the central region. The width of the sacrificial pad 220 defines a gate length of the transistor.

[0086] In [Fig.5E], a first ion implantation of first dopant ions is carried out over the entire structure obtained in the step of [Fig.5D], followed by activation of the first dopant ions. During this step, the sacrificial pad 220 protects the part of the semiconductor portion 150 intended to be the channel 150.2 of the transistor and receives a quantity of first dopant ions to obtain a doped sacrificial pad 221, doped at least in part. The opposite regions of the semiconductor portion 150 become doped regions 231, doped with the same type as the doped sacrificial pad 221, in this example of type N. The energy of the first dopant ions is preferentially chosen to dope the entire thickness of the semiconductor portion 150 at the level of the opposite regions. The dose of first dopant ions is for example chosen to obtain a concentration of first dopant atoms in the doped regions 231 between 1017 at.cm3 ​​and 1020 at.cm3.The first dopant atoms come from the first dopant ions and are of a first type of conductivity.

[0087] In [Fig.5F], spacers 136 are formed on the sides of the doped sacrificial pad 221. For this, a conformal dielectric layer can be deposited on the di layer buried electrical layer 210, the gate dielectric layer 140 and the doped sacrificial pad 221. The dielectric layer is in this example, a silicon nitride (SiN) layer deposited by LPCVD. The dielectric layer is then etched anisotropically, perpendicular to the upper face of the temporary substrate 200, over its entire thickness to keep residues only at the sides of the doped sacrificial pad 221. The residues are the spacers 136.

[0088] Once the spacers 136 have been formed, a second ion implantation of second dopant ions is carried out. During this step, the doped sacrificial pad 221 protects the part of the semiconductor portion 150 intended to be the channel 150.2 of the transistor and receives a quantity of second dopant ions to obtain a doubly doped sacrificial pad 222. In addition, the spacers 136 protect a part of the doped region 231 so that only a part of each doped region 231 receives a quantity of second dopant ions to become a doubly doped region 232.

[0089] The energy of the second dopant ions is preferably chosen to dope the entire thickness of the semiconductor portion 150 with second dopant atoms at the doubly doped regions 232. The second dopant atoms are of the first conductivity type. The dose of second dopant ions is for example chosen to obtain a total concentration of dopant atoms in the doubly doped regions 232 of between 1019 at.cm3 ​​and 1021 at.cm3.

[0090] In this exemplary manufacturing method, it is possible to omit the first or second implantation sub-step. It is also possible to omit the sub-step of forming the spacers 136.

[0091] In [Fig.5G], a first barrier layer 241 is deposited conformally on the doubly doped sacrificial pad 222, the spacers 136, the gate dielectric layer 140 and the buried dielectric layer 210. The first barrier layer 241 is intended to protect the elements that it covers during a subsequent step of etching sacrificial layers, called release etching. The first barrier layer 241 is for example made of alumina (A12O3) or aluminum nitride (AIN), so as to resist etching by hydrofluoric acid (HF) in the vapor phase.

[0092] In [Fig.5H], a planarizing layer 250 is deposited so as to completely cover the first barrier layer 241. The planarizing layer 250 is made of an electrically insulating material, for example dielectric. It is capable of being etched during the release etching. In this example, it is made of silicon oxide (SiO).

[0093] In [Fig.51], a chemical-mechanical polishing (CMP) of the planarizing layer 250 is carried out with a stop on the first barrier layer 241 to obtain a first sacrificial layer 251. At the end of this step, the first barrier layer 241 has an upper surface facing the doubly doped sacrificial pad 222 flush with the first sacrificial layer 251.

[0094] In [Fig.5J], the first barrier layer 241 is locally etched right through its upper surface to obtain a gate opening 225. The gate opening 225 has all its dimensions along directions of a plane parallel to the upper face of the temporary substrate 200 strictly smaller than the dimensions of the doubly doped sacrificial pad 222 along the same directions. A difference in dimension between the doubly doped sacrificial pad 222 and the gate opening 225 is for example sufficient to compensate for alignment errors during a photolithography sub-step implemented to define the gate opening 225 during the step of [Fig.5J].

[0095] At the end of this step, the parts of the first barrier layer 241 in physical contact with the doubly doped sacrificial pad 222 each constitute a protective flap 241.1. Preferably, each protective flap 241.1 has all its dimensions in a plane parallel to the upper face of the temporary substrate 200 sufficient to protect the spacers 136 and the gate dielectric layer 140, during the release etching. They are for example all greater than 50 nm, or even greater than 100 nm.

[0096] An attack on the spacers 136 during the release etching is likely to generate parasitic charges altering the operation of the photodetector 1. An attack on the gate dielectric layer 140 during the release etching is likely to induce a parasitic gate current of the transistor and / or a reduction in the TCC and / or greater detection noise, when the photodetector 1 is in operation.

[0097] In [Fig.5K], the doubly doped sacrificial pad 222 is removed. To do this, the entire doubly doped sacrificial pad 222 is etched selectively with respect to the first barrier layer 241 and the first sacrificial layer 251, preferably by wet etching. A cavity 226 is thus obtained in place of the doubly doped sacrificial pad 222. When the planarizing sacrificial layer 215 is made of amorphous or polycrystalline silicon, the doubly doped sacrificial pad 222 can be etched with a solution of TMAH, or HF concentrated at 1%. When the planarizing sacrificial layer 215 is made of a polymer, the doubly doped sacrificial pad 222 can be etched with an oxygen plasma.

[0098] The steps of Figures 5L and 5M aim to fill the cavity 226 with a semiconductor material to obtain a gate 135 of the transistor. In [Fig.5L], a planarizing semiconductor layer 260 is conformally deposited so as to completely fill a volume of the cavity 226 in communication with the gate opening 225. The planarizing semiconductor layer 260 completely covers the gate dielectric layer 140 inside the cavity 226. Preferably, it fills substantially the entire cavity 226, as shown here. In this case, it covers before gently the first sacrificial layer 251 and the first barrier layer 241 at the level of the protective flaps 241.1, as shown in [Fig.5L]. The planarizing semiconductor layer 260 is here doped in situ, with a second type of conductivity opposite to the first type of conductivity. It is made of a semiconductor material resistant to release etching. In this example, it is made of polycrystalline or amorphous silicon, for release etching using hydrofluoric acid (HF) in the vapor phase.

[0099] In [Fig.5M], when the planarizing semiconductor layer 260 covers the first sacrificial layer 251, a chemical-mechanical polishing (CMP) of the planarizing semiconductor layer 260 is carried out with a stop on the first sacrificial layer 251, to obtain a residual part of the planarizing semiconductor layer 260 located in the cavity 226. When the planarizing semiconductor layer 260 has not been doped in situ, that is to say simultaneously with the deposition of the planarizing semiconductor layer 260, the residual part is doped with the second conductivity type following the planarization sub-step, for example by implantation or diffusion of doping species. The residual part is intended to be a gate 135 of the transistor. Since the first sacrificial layer 251 is flush with the first barrier layer 241 and the polishing stops on the first sacrificial layer 251, the gate 135 has a top surface 135.2 flush with the first barrier layer 241 and blocking the gate opening 225. .

[0100] The planarizing semiconductor layer 260 being made of a semiconductor material resistant to release etching, the gate 135 is not damaged during the release etching although it is not covered by the first barrier layer 241 at its top surface 135.2. The first barrier layer 241 and the top surface 135.2 of the gate 135 together protect the spacers 136 during the release etching.

[0101] In [Fig.5N], a second sacrificial layer 252 is deposited, preferably in the same material as that of the first sacrificial layer 251. The second sacrificial layer 252 is made of an electrically insulating material, for example dielectric, here silicon oxide (SiO). A drain electrode 123, a gate electrode 125 and a source electrode 121 (not shown) are formed, by sub-steps of photolithography, etching, deposition and polishing. The source, drain and gate electrodes 121, 123, 125 pass right through the second sacrificial layer 252. The source and drain electrodes extend through the first sacrificial layer 251, the first barrier layer 241 and the gate dielectric layer 140, to respective double-doped regions 232. The grid electrode 125 is in physical contact with the top surface 135.2 of the grid 135.The source, drain and gate electrodes 121, 123, 125 are flush with an upper face of the . second sacrificial layer 252. Each source electrode 121 and each drain electrode 123 have a section in contact with the first barrier layer 241 over its entire periphery.

[0102] At the end of the step of [Fig.5N], one or more thermal insulation arms 120 are formed by photolithography, etching and deposition sub-steps. A third sacrificial layer 253 is then deposited on the second sacrificial layer 252 and each thermal insulation arm 120, preferably in the same material as that of the first sacrificial layer 251 and / or the second sacrificial layer 252. The third sacrificial layer 253 is made of an electrically insulating material, for example dielectric, here silicon oxide (SiO). Upper anchoring pillars 115 are then formed extending into the third sacrificial layer 253 from an upper face of the third sacrificial layer 253 located on one side of the third sacrificial layer 253 opposite the temporary substrate 200, until reaching a thermal insulation arm 120. A first intermediate structure 10 is thus obtained, shown schematically in [Fig. 6A].

[0103] The upper face of the third sacrificial layer 253 constitutes, with ends of the upper anchoring pillars 115, a first face to be bonded 253.1 of the first intermediate structure 10. The first face to be bonded 253.1 has surface condition, roughness and flatness characteristics allowing direct hybrid bonding.

[0104] [Fig.6B] is a schematic sectional view of a second intermediate structure 20 to be assembled with the first intermediate structure 10 to obtain the photodetector 1. The second intermediate structure 20 comprises, superimposed, a substrate 100, a lower barrier layer 110 and a fourth sacrificial layer 254. The lower barrier layer 110 is interposed and in contact with the substrate 100 and the fourth sacrificial layer 254.

[0105] The fourth sacrificial layer 254 is preferably made of the same material as that of the first sacrificial layer 251 and / or the second sacrificial layer 252 and / or the third sacrificial layer 253. The fourth sacrificial layer 254 is made of an electrically insulating material, for example dielectric, here silicon oxide (SiO).

[0106] The substrate 100 comprises a control circuit. The second intermediate structure 20 comprises one or more lower anchoring pillars 105. Each lower anchoring pillar 105 passes right through the fourth sacrificial layer 254 and the lower barrier layer 110, and extends to a connection pad of the control circuit. When the photodetector 1 comprises a matrix of several pixels, the upper anchoring pillars 115 are repeated at the pixel pitch of the photodetector 1. The substrate 100 or the second intermediate structure 20 may be provided by a foundry of electronic chips, at least in part.

[0107] The second intermediate structure 20 comprises a second face to be bonded 254.1 on a side opposite the substrate 100. The second face to be bonded 254.1 comprises ends of the upper anchoring pillars 115 and a surface of the fourth sacrificial layer 254. It has surface condition, roughness and flatness characteristics allowing hybrid direct bonding.

[0108] In a final step, the first face to be bonded 253.1 is brought into contact with the second face to be bonded 254.1 so as to bring a lower anchoring pillar 105 into contact with a respective upper anchoring pillar 115, and the third sacrificial layer 253 into contact with the fourth sacrificial layer 254. The first face to be bonded 253.1 and the second face to be bonded 254.1 together constitute a bonding interface. The bonding interface is optionally reinforced by heat treatment.

[0109] The temporary substrate 200 is then removed by sub-steps of lapping and / or polishing and / or wet or dry etching. The thickness of the buried dielectric layer 210 may optionally then be adjusted by one or more sub-steps of deposition and / or polishing and / or etching. This may for example be advantageous for obtaining a thickness of the micro-board 160 giving the micro-board 160 particular mechanical and / or electrical properties from an assembly taken from standard SOI plates.

[0110] A metal layer, for example titanium nitride (TiN), is deposited on the buried dielectric layer 210. Preferably, the metal layer has a thickness allowing it to be adapted to the impedance of the vacuum. The metal layer and the buried dielectric layer 210 are etched locally, from one side to the other, until the first barrier layer 241 is reached, without exceeding it, so as to delimit a micro-plate 160 in the buried dielectric layer 210 in contact with the transistor. The residual part of the metal layer constitutes an absorber 170 of the photodetector 1.

[0111] An additional barrier layer is deposited completely covering the absorber 170, the micro-board 160 and the first barrier layer 241. A vent is made through the additional barrier layer and the first barrier layer 241 in a region within which they are both in contact. The release etching is carried out. For this, the first, second, third and fourth sacrificial layers 251, 252, 253, 253 are etched selectively with respect to the first barrier layer 241, the lower barrier layer 110 and the grid 135, for example by hydrofluoric acid in the vapor phase.

[0112] Particular embodiments have just been described. Different variants and modifications will appear to those skilled in the art.

Claims

Claims

1. Detector (1) of electromagnetic radiation, comprising: • an absorber (170) configured to absorb the electromagnetic radiation, • a MOS-FET type transistor thermally coupled to the absorber (170), comprising • a source (150.1) doped with a first conductivity type, • a drain (150.3) doped with the first conductivity type, • a channel (150.2) extending from the source (150.1) to the drain (150.3), • a gate (135) electrically insulated from the channel (150.2) by a gate dielectric layer (140) of the transistor, • a control circuit electrically connected to the source (150.1), to the drain (150.3) and to the gate (135); and configured to apply an electrical potential difference between the gate (135) and the source (150.1) less than or equal in absolute value to a threshold voltage of the transistor, the detector (1) being characterized in that • the gate (135) is made of silicon doped with a second type of conductivity opposite to the first type of conductivity with a concentration of majority charge carriers less than or equal to 1019 cm 3, and in that • the gate dielectric layer (140) has a thickness less than or equal to 50 nm.

2. A detector (1) according to claim 1, further comprising a substrate (100), a micro-board (160) of a dielectric material suspended above the substrate (100), and a semiconductor portion (150) extending on a lower face of the micro-board (160) in which the drain (150.3), the channel (150.2) and source (150.1) are housed.

3. Detector (1) according to claim 2, wherein the absorber (170) extends over a part of the micro-board (160) devoid of the portion semiconductor (150).

4. Detector (1) according to any one of claims 2 or 3, wherein the transistor further comprises a back gate electrically connected to the control circuit and electrically isolated from the channel (150.2) by the micro-board (160).

5. A detector (1) according to claim 4, wherein the rear grid is a part of the absorber (170).

6. Detector (1) according to claim 5, wherein the micro-board (160) has a thickness between 10 nm and 150 nm.

7. The detector (1) of any one of claims 2 to 6, wherein the drain (150.3) and the gate (135) are connected to the control circuit by a first thermal isolation arm (120), the source (150.1) is electrically connected to the control circuit by a second thermal isolation arm (120), and the micro-board (160) is suspended above the substrate (100) by the first and second thermal isolation arms (120).

8. Detector (1) according to claims 4 and 7, wherein the rear grid is electrically connected to the source (150.1) by a rear face electrical contact (128) passing right through the micro-board (160), and the source (150.1) is electrically connected to the second thermal insulation arm (120) by a source electrode (121) opposite the rear face electrical contact (128).

9. A detector (1) according to any preceding claim, wherein the transistor is a depletion transistor.

10. A detector (1) according to any one of claims 1 to 8, wherein the transistor is an enhancement-mode transistor.

11. A method of manufacturing a detector (1) according to any one of claims 1 to 10, comprising the following steps of forming the gate (135): • forming a sacrificial pad (222), • forming spacers (136) on sides of the sacrificial pad (222), • conformal deposition of a first barrier layer (241) on the spacers (136) and the sacrificial pad (222), • deposition of a planarizing semiconductor layer (260) so as to completely cover the first barrier layer (241), • polishing the planarizing semiconductor layer (260) with a stop on the first barrier layer (241) to obtain a first sacrificial layer (251), • etching a gate opening (225) passing right through the first barrier layer (241) through an upper surface of the first barrier layer (241) opposite the sacrificial pad (222), the opening having dimensions strictly smaller than the dimensions of the sacrificial pad (222), • removing the sacrificial pad (220) to obtain a cavity (226) in place of the sacrificial pad (222), • filling the cavity (226) with silicon so as to plug the gate opening (225) and thus obtain the gate (135).

12. A manufacturing method according to claim 11, wherein the sacrificial pad (222) is formed on a semiconductor portion (150) in which the drain (150.3), the channel (150.2) and source (150.1) are housed, and the sacrificial pad (220) protects the channel (150.2) during a step of implanting the source (150.1) and the drain (150.3).

13. A manufacturing method according to any one of claims 11 or 12, wherein the sacrificial pad (220) is made of silicon.

14. Manufacturing method according to any one of claims 11 to 13, in which the step of filling the cavity (226) comprises: • a deposition of a planarizing semiconductor layer (260) doped in-situ, so as to completely fill a volume of the cavity (226) in communication with the gate opening (225) and to cover the first sacrificial layer (251) and the first barrier layer (241), • a polishing of the planarizing semiconductor layer (260) with stopping on the first sacrificial layer (251).

15. A manufacturing method according to any one of claims 11 to 14, wherein the detector (1) is a detector according to any one of claims 2 to 8, further comprising a release etching of the micro-board (160) during which the first sacrificial layer- (251) is selectively etched with respect to the first barrier layer (241) and the gate (135).

Images