Photon counting detector

Abstract

Photon Counting Detector This description relates to a photon counting detector comprising a photon-to-charge conversion layer covered with several electrodes, each connected to a readout circuit (RDc), in which: each readout circuit (RDc) is configured to generate an active detection signal (evt) when charges are collected by the electrode to which the readout circuit (RDc) is connected; each readout circuit, called the central circuit (RDc), is configured to implement charge sharing correction by exchanging signals (evtc, evtn, evts, evte, evtw, valc, valn, vals, vale, valw) with readout circuits, called adjacent circuits of the central circuit (RDc), connected to electrodes adjacent to the electrode to which the central circuit is connected, called the central electrode; and each central circuit (RDc) is configured to selectively turn on and off (CSC-EN;EN) the load sharing correction in said central circuit on the basis at least of the detection signal (evt) generated by said central circuit. Figure for the abbreviation: Fig. 6;

Description

Title of the invention: Photon counting detector technical field

[0001] The present description relates generally to electronic circuits, and, more particularly, to photon counting detectors (PDCs), also called, more generally, particle counting detectors. Previous technique

[0002] Many electronic systems include a photon-counting detector. This is the case, for example, with photon-counting spectral scanners, used for medical imaging. In a photon-counting spectral scanner, the detected particles are, for example, photons of X-ray radiation, that is, radiation in the wavelength range from, for example, approximately 0.01 nm to approximately 10 nm.

[0003] Fig. 1 illustrates by means of a schematic, cross-sectional and partial view, an example of a photon counting detector 1.

[0004] The detector 1 includes a layer 100 for photoconversion of the photons (or particles) to be detected into charges. The layer 100 is configured so that a photon to be detected, received by the layer 100, is converted into charges by the layer 100, the number of charges resulting from a photon being, for example, determined by the photon's energy. The layer 100 is generally made of a semiconductor material. For example, to detect photons from X-rays, the layer 100 comprises cadmium telluride. By way of illustration, in [Fig. 1], a photon incident on the layer 100 is schematically represented by an arrow 101, and the set of charges generated in the layer 100 by this photon 101 is schematically represented by a disk 103.

[0005] The charges are collected by electrodes 102 covering layer 100. For example, each electrode belongs to a pixel of the photon-counting detector, each pixel comprising, for example, a single electrode 102. For example, the electrodes 102 cover one of the two principal faces of layer 100, for example, the principal face of layer 100 opposite the principal face receiving the incident photons to be detected. In the example of [Fig. 1], the electrodes cover the lower face of layer 100.

[0006] Each electrode 102 is connected to a corresponding readout circuit RD of the detector 1. By way of example, each circuit RD belongs to a pixel of the photon-counting detector, each pixel comprising one circuit RD. Each circuit RD receives a signal lmp represents the evolution over time of the quantity of charge collected by the electrode 102 to which it is connected. For example, each lmp signal is a current exhibiting a pulse each time charges resulting from a photon incident on layer 100 are collected by the electrode 102 providing this lmp signal.

[0007] Typically, each readout circuit RD is configured to provide, from the received lmp signal, an OUT signal including an indication that charges have been collected by the electrode 102 connected to this RD circuit, and, in addition, information representative of the quantity of charges collected.For example, this OUT signal indicates each time that a pulse of the lmp signal is received by the RD circuit, and a range of values ​​in which the maximum level of this pulse lies, this maximum level being representative of the amount of charge collected by electrode 102 during the lmp pulse, therefore of the energy of the photon.

[0008] Typically, the output signals OUT of the RD circuits of the pixels of detector 1 are supplied to a PROCESS processing circuit. This PROCESS circuit is configured, based on the number of photons detected by each pixel of detector 1 and their energy levels, to determine properties of an object or living being traversed by ionizing radiation before this radiation reaches detector 1. For example, the PROCESS circuit is configured to generate an image of the object or living being placed in the path of the radiation, for example an image of the different materials or tissues that respectively compose this object or living being.

[0009] However, as schematically illustrated in [Fig. 1] by two arrows 104, in certain cases, the charges 103 generated by a photon can be collected by two neighboring or adjacent electrodes 102. This phenomenon is called charge sharing. Each circuit RD connected to one of these two electrodes 102 then indicates, via its OUT signal, that its electrode 102 has collected charges, i.e., that this circuit RD has detected a photon. Furthermore, each circuit RD connected to one of these two electrodes also provides, via its OUT signal, an indication of the amount of charge collected by its electrode, i.e., an indication of the energy level of the detected photon.

[0010] To take into account charge sharing phenomena in a photon counting detector, a known solution consists of implementing signal exchanges between readout circuits RD connected to adjacent electrodes 102, and, in addition, implementing a charge sharing correction in these circuits RD.

[0011] The charge sharing correction consists, based on the signals exchanged between RD circuits connected to adjacent electrodes, of detecting when at least two adjacent electrodes 102 collect charges simultaneously. When adjacent electrodes 102 collect charges simultaneously, the reading circuits The RDs connected to these electrodes decide that all the collected charges originate from the same photon. Furthermore, based on the exchanged signals, these RD readout circuits also determine which of these 102 electrodes, and therefore which of the circuits connected to these 102 electrodes, should receive all the collected charges. In other words, based on the signals they exchange, the RD circuits determine which pixel involved in the charge sharing should receive all the collected charges.

[0012] There are many known readout circuits implementing charge sharing correction. Such circuits are described, for example, in document EP 2936208 (or US 9329283), in the article entitled "The Medipix3RX: a high resolution, zero dead-time pixel detector readout chip allowing spectroscopic imaging", by R Ballabriga, J Alozy, G Blaj, M Campbell, M Fiederle, E Frojdh, EHM Heijne, X Llopart, M Pichotka, S Procz, published in "Journal of Instrumentation", Volume 8, in February 2013, or in the article entitled "Multi-energy inter-pixel coincidence counters for charge sharing correction and compensation in photon counting detectors" by Taguchi K., published in "Med Phys." in June 2020.

[0013] Fig. 2 schematically represents, in part and in block form, a photon counting detector 2 in which the readout circuits RD connected to adjacent electrodes 102 of detector 2 exchange signals with each other and implement, on the basis of the exchanged signals, a charge sharing correction.

[0014] Detector 2 includes many elements in common with detector 1, and only the differences between these two detectors are detailed here.

[0015] In [Fig. 2], electrodes 102 of detector 2 are shown in a top view, with layer 100 not shown. Typically, the electrodes are arranged in a matrix comprising rows and columns of electrodes 102. In [Fig. 2], a matrix of nine electrodes 102 arranged in three rows and three columns is illustrated. In practice, the number of rows and columns is greater, and the matrix shown in [Fig. 2] corresponds, for example, to only a portion of a matrix of electrodes 102 of detector 2.

[0016] In [Fig.2], a central electrode 102 is surrounded by eight electrodes 102 adjacent to the central electrode 102, these eight electrodes being respectively located to the north, south, east, west, northeast, northwest, southeast and southwest of the central electrode 102.

[0017] In [Fig.2], the central electrode is referenced 102c, and the adjacent electrodes located to the north, south, east, west, northeast, northwest, southeast and southwest of the central electrode 102c are respectively referenced 102n, 102s, 102e, 102w, 102ne, 102nw, 102se and 102sw.

[0018] The central electrode 102c is connected to a circuit RD called the central circuit, and each of the electrodes adjacent to the central electrode 102c is connected to a circuit RD, the circuits RD connected to the adjacent electrodes being called adjacent circuits. In [Fig. 2], the circuits RD connected to the respective electrodes 102c, 102n, 102s, 102e, 102w, 102ne, 102nw, 102se and 102sw are respectively referenced as RDc, RDn, RDs, RDe, RDw, RDne, RDnw, RDse and RDsw.

[0019] Although, in the example of [Fig.2], the RD circuits are arranged relative to each other in the same way as the electrodes 102 to which these RD circuits are connected, this is not necessarily the case in practice.

[0020] In detector 2, each electrode 102 can be viewed as a central electrode 102c surrounded (or bordered) by one or more adjacent electrodes 102, and what will be described for the example in [Fig. 2] can be generalized to the other electrodes 102 of detector 2. By extension, in detector 2, each circuit RD can be viewed as a central circuit RDc exchanging signals with one or more adjacent circuits RD connected respectively to one or more electrodes adjacent to the central electrode 102c to which the central circuit RDc is connected, and what will be described for the example in [Fig. 2] can be generalized to the other circuits RD of detector 2.

[0021] In the example in [Fig. 2], the central circuit RDc is configured to exchange signals with the adjacent circuits RDn, RDe, RDw, and RDs connected to the respective adjacent electrodes 102n, 102e, 102w, and 102s. Optionally, the central circuit RDc is further configured to exchange signals with the adjacent circuits RDse, RDsw, RDne, and RDnw connected to the respective adjacent electrodes 102se, 102sw, 102ne, and 102n, as in the example in [Fig. 2]. In [Fig. 2], the signals exchanged between the central circuit and each of the adjacent circuits are represented by a double arrow 200.

[0022] Preferably, the RD circuits are identical circuits. To this end, when the central electrode 102c is an electrode located at the edge of the matrix and there is therefore no adjacent electrode on one side of the central electrode 102, the signals 200 that the central circuit RDc would have received from one or more adjacent RD circuits connected to one or more absent adjacent electrodes are, for example, replaced by inactive or corrupted signals. For example, when a central electrode 102c has no adjacent electrode 102e, the signals that the central circuit RDc would have received from the adjacent circuit RDe are, for example, replaced by inactive or corrupted signals.

[0023] The RDc circuit is configured to implement a load sharing correction from the 200 signals that it exchanges with adjacent RD circuits.

[0024] Known photon counting detectors in which charge sharing correction is implemented directly at the level of the reading circuits connected to the electrodes of these detectors have various disadvantages. Summary of the invention

[0025] There is a need to overcome all or part of the drawbacks of known photon counting detectors as described above.

[0026] One embodiment overcomes all or part of the drawbacks of known photon counting detectors as described above.

[0027] One embodiment provides a photon counting detector comprising a photon-to-charge conversion layer covered with several electrodes, each connected to a readout circuit, in which: Each reading circuit is configured to generate an active detection signal when charges are collected by the electrode to which the reading circuit is connected; Each readout circuit, called the central circuit, is configured to implement charge sharing correction by exchanging signals with readout circuits, called central circuit adjacent circuits, connected to electrodes adjacent to the electrode to which the central circuit is connected, called the central electrode; and each central circuit is configured to selectively turn charge sharing correction on and off in said central circuit on the basis at least of the sensing signal generated by said central circuit.

[0028] According to one embodiment: Each central circuit is adapted to send the detection signal it generates to each of the adjacent circuits of the central circuit, each of the adjacent circuits of said central circuit being adapted to send the detection signal it generates to said central circuit.

[0029] According to one embodiment, each central circuit is configured to disable load sharing correction in said central circuit if an average number of active states of the detection signal generated by the central circuit is greater than a threshold.

[0030] According to one embodiment, each central circuit is configured to disable load sharing correction in said central circuit if an average number of active states of the detection signal generated by the central circuit and of the detection signals that the central circuit receives from the circuits adjacent to the central circuit is greater than a threshold.

[0031] According to one embodiment, each central circuit is configured to disable load sharing correction in said central circuit for a time delay period after the end of each active state of the detection signal generated by the central circuit.

[0032] According to one embodiment, each central circuit is configured to disable load sharing correction in said central circuit if a number of active states of the detection signals that the central circuit receives from the adjacent circuits of the central circuit during an active state of the detection signal generated by the central circuit is greater than a threshold.

[0033] According to one embodiment, each central circuit is configured to disable charge sharing correction in said central circuit if the central circuit and the adjacent circuit(s) of the central circuit that send active detection signals during an active state of the detection signal generated by the central circuit are connected to electrodes arranged relative to each other in a pattern corresponding to an abnormal charge sharing.

[0034] According to one embodiment, each central circuit includes a charge sharing detection circuit configured to detect that the central electrode and one or more of the electrodes adjacent to the central electrode are involved in charge sharing, from the detection signal generated in the central circuit and respectively from the detection signal(s) sent to the central circuit by respectively the adjacent circuit(s) connected respectively to said one or more adjacent electrodes.

[0035] According to one embodiment: Each reading circuit is configured to generate an initial signal representative of the amount of charge collected by the electrode to which the reading circuit is connected; and Each central circuit is adapted to send the first signal it generates to each of said adjacent circuits of the central circuit, each of said adjacent circuits of said central circuit being adapted to send the first signal it generates to said central circuit.

[0036] According to one embodiment, the charge sharing detection circuit of each central circuit is configured, when it detects that the central electrode and one or more of the adjacent electrodes are involved in charge sharing, to determine to which of the electrodes involved in charge sharing is assigned a sum of the charges collected by the electrodes involved in charge sharing.

[0037] According to one embodiment, the charge-sharing detection circuit is configured to determine to which of the electrodes involved in charge sharing is assigned the sum of the charges collected by the electrodes involved in charge sharing from: of the detection signal generated by the central circuit and of the detection signal(s) sent to the central circuit by the adjacent circuit(s) connected respectively to said one or more adjacent electrodes involved in charge sharing, or of the first signal generated by the central circuit and of the first signal(s) sent to the central circuit by the adjacent circuit(s) connected respectively to said one or more adjacent electrodes involved in the charge sharing.

[0038] According to one embodiment, each central circuit is configured: when the charge sharing correction is active in the central circuit, to provide an output signal representative of the sum of the charges collected by the central electrode and said one or more adjacent electrodes involved in charge sharing if this sum of charges is attributed to the central electrode, and of a zero amount of charge otherwise; and when charge sharing correction is inactive in the central circuit, to provide an output signal representative of the charges collected by the central electrode only.

[0039] According to one embodiment, the reading circuits are identical. Brief description of the drawings

[0040] These features and advantages, as well as others, will be described in detail in the following non-limiting description of particular embodiments in relation to the accompanying figures, among which:

[0041] the [Fig.1], described above, represents an example of a photon counting detector;

[0042] the [Fig.2] described above, represents an example of a photon counting detector in which a charge sharing correction is implemented;

[0043] [Fig.3] represents, schematically and in block form, an example of a photon counting detector in which a charge sharing correction is implemented;

[0044] [Fig.4] schematically represents an example of a detector circuit of [Fig.3];

[0045] [Fig. 5] schematically represents another example of a detector circuit from [Fig. 3]; and

[0046] [Fig.6] represents, schematically and in block form, an embodiment of a photon counting detector in which a charge sharing correction is implemented;

[0047] [Fig.7] represents, schematically and in block form, another embodiment of a detector circuit of [Fig.6];

[0048] [Fig.8] represents, schematically and in block form, another embodiment of a detector circuit of [Fig.5];

[0049] [Fig.9] represents an example of the implementation of a control circuit forming part of the circuits described in relation to Figures 6, 7 and 8;

[0050] [Fig. 10] represents timing diagrams illustrating the operation of the circuit of [Fig. 9];

[0051] [Fig. 11] represents another example of the implementation of a control circuit forming part of the circuits described in relation to Figures 6, 7 and 8;

[0052] [Fig. 12] represents timing diagrams illustrating the operation of the circuit in [Fig. 11], Description of embodiments

[0053] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0054] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0055] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0056] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0057] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0058] Figure 3 represents, in more detail, an example of the RD circuits of detector 2 of Figure 2.

[0059] In the example of [Fig. 3], a central circuit RDc connected to a central electrode 102c (not shown in [Fig. 3]) only exchanges signals 200 with the adjacent circuits RDs, RDn, RDw and RDe connected to the respective adjacent electrodes 102s, 102n, 102w and 102e. In other words, in [Fig. 3], for a given central electrode 102c, the charge sharing correction is only implemented between this electrode 102c and its adjacent electrodes 102n, 102e, 102s and 102s.

[0060] A person skilled in the art will be able to adapt what will be described in relation to the example in [Fig.3], to the case of a central circuit RDc exchanging signals 200 with adjacent circuits RDc, RDn, RDs, RDe, RDw, RDne, RDnw, RDse and RDsw. Put another way, a person skilled in the art will be able to adapt what will be described in relation to the example of [Fig.3] to a case where, for a given central electrode 102c, the charge sharing correction is implemented between this electrode 102c and its adjacent electrodes 102n, 102e, 102s, 102w, 102ne, 102nw, 102se and 102sw.

[0061] In the example in [Fig. 3], each circuit RD is configured to generate a signal evt indicating when the electrode 102 to which that circuit RD is connected is collecting charges. For example, in each circuit RD, the signal evt is active when the electrode 102 connected to that circuit RD is collecting charges, or, in other words, when the circuit RD receives an lmp pulse from that electrode 102. For example, the signal evt is a binary signal with two states. As an example, each circuit RD includes a circuit 300 configured to generate the signal evt from the lmp signal received by the circuit RD. For example, the circuit 300 is configured to provide the signal evt in the active state when the lmp signal is above a threshold, and in the inactive state otherwise.

[0062] When two RD circuits exchange signals 200 to implement a load sharing correction, each of these two RD circuits is adapted to send the signal evt that it generates to the other circuit, as illustrated in [Fig.3] by dashed lines in the RD circuits and solid arrows 200 between the RD circuits.

[0063] For example, in [Fig. 3], the RDc circuit transmits its signal evt directly to each of the adjacent circuits RDn, RDe, RDs and RDw, and each of the adjacent circuits RDn, RDe, RDs and RDw transmits its signal evt directly to the central circuit RDc. In the signals 200 transmitted from the RDc circuit to the adjacent circuits RDn, RDe, RDs and RDw, we therefore find the signal evt generated by the RDc circuit, referenced evtc in [Fig. 3], and in the signals 200 transmitted from the adjacent circuits RDn, RDe, RDs and RDw to the central circuit RDc, we therefore find the signals evt generated by the circuits RDn, RDe, RDs and RDw, referenced respectively evtn, evte, evts and evtw in [Fig. 3].

[0064] Furthermore, although not illustrated in detail in [Fig. 3], each RD circuit is configured to generate a signal, for example an internal signal within the RD circuit, representative of the amount of charge received by the electrode 102 to which that RD circuit is connected. For example, each RD circuit is configured, at each pulse of the lmp signal it receives, to generate a signal (not shown in [Fig. 3]) indicating a range of values ​​within which the maximum value reached by the pulse lies.

[0065] When two RD circuits exchange signals 200 to implement a load-sharing correction, each of these two RD circuits is then adapted to send to the other of these two RD circuits the signal representing the quantity of charges received by electrode 102 connected to this circuit RD, as illustrated in [Fig.3] by solid arrows 200 between circuits RD.

[0066] By way of example, in [Fig. 3], the RDc circuit transmits a valc signal, representative of the charges collected by its electrode 102c, to each of the adjacent circuits RDn, RDe, RDs, and RDw. For example, the RDc circuit is configured to generate a first signal (not shown in [Fig. 3]) representative of the charges collected by its electrode 102c, and is further adapted to transmit this first signal, then referenced as valc, to its adjacent circuits RDn, RDe, RDs, and RDw. In other words, the RDc circuit includes a first signal representative of the charges collected by its electrode 102c and is adapted to transmit this first signal in the form of the valc signal to its adjacent circuits RDn, RDe, RDs, and RDw. This first signal can be analog or digital.

[0067] By way of example, conversely, the adjacent circuits RDn, RDe, RDs and RDw transmit to the circuit RDc respective signals vain, vale, vais and valw representing the charges collected by the respective electrodes 102n, 102e, 102n and 102w connected to the respective circuits RDn, RDe, RDs and RDw. For example, each of the adjacent circuits RDn, RDe, RDs and RDw is configured to generate a first signal (not shown in [Fig.3]) representative of the charges collected by the electrode 102n, 102e, 102n, 102w to which this adjacent circuit is connected, and is further adapted to transmit this first signal, then referenced respectively vain, vale, vais and valw, to the central circuit RDc. Put another way, each adjacent circuit RDn, RDe, RDs, RDw includes a first signal representative of the charges collected by its electrode, and is adapted to transmit this first signal in the form of the respective signal vain, vale, vais, valw to the central circuit RDc.

[0068] Based on the signal evt that it generates and the signals evtn, evte, evts and evtw that it receives from the adjacent circuits RDn, RDe, RDs and RDw, the circuit RDc is configured to detect when a sharing of charges occurs between the central electrode 102c and at least one of the adjacent electrodes 102n, 102e, 102s and 102w. For example, the RDc circuit includes a charge sharing detection circuit (not shown in [Fig.3]) configured to detect that the central electrode 102c and one or more adjacent electrodes 102n, 102e, 102s and 102w are involved in charge sharing, from the signal evt generated in the RDc circuit and the signals evtn, evte, evts and evtw that the RDc circuit receives from its adjacent circuits RDn, RDe, RDs and RDw.

[0069] When the central circuit RDc and one or more of its adjacent circuits RDn, RDe, RDs, and RDw are involved in charge sharing, these reading circuits are each configured to determine to which of the electrodes 102c, 102n, 102e, 102s, 102w connected to these circuits RDc, RDn, RDe, RDs, RDw the sum of the collected charges, or, in other words, the sum of the received energies, should be allocated. This allocation of the sum of the collected charges is, for example, implemented by the load sharing detection circuits of the RD circuits involved in load sharing.

[0070] By way of example, when the central circuit RDc and one or more of the adjacent circuits RDn, RDe, RDs and RDw are involved in a charge sharing, the central circuit RDc is configured to determine to which of the electrodes involved in the charge sharing is assigned the sum of the charges collected by these electrodes, on the basis of the signal evt of the circuit RDc and the signals evt, evtn, evte, evts and evtw, for example on the basis of the order of arrival of the active states of these signals evt, evtn, evte, evts and evtw, for example by assigning this sum to the electrode corresponding to the signal evt, evtn, evte, evts or evtw which switched to the active state first during the charge sharing.

[0071] By way of alternative example, when the central circuit RDc and one or more of the adjacent circuits RDn, RDe, RDs and RDw are involved in a charge sharing, the central circuit RDc is configured to determine to which of the electrodes involved in the charge sharing is assigned the sum of the charges collected by these electrodes, on the basis of the signal representative of the charges collected by the electrode 102c which is generated by this circuit RDc, and the signals vain, vale, vais and valw which it receives from its adjacent circuits, for example by assigning this sum to the electrode corresponding to the pulse lmp of greatest amplitude.

[0072] When the RDc circuit detects a charge sharing in which it is involved, if this RDc circuit determines that the sum of the charges collected during the charge sharing is allocated to it, this RDc circuit provides an output signal OUT (not shown in [Fig. 3]) representing this sum. Conversely, if this RDc circuit determines that the sum of the charges collected during the charge sharing is not allocated to it, this RDc circuit provides an output signal representing a zero charge quantity.

[0073] Figure 4 schematically represents an example of an implementation of the RDc circuit of Figure 3. In this example, when the RDc circuit is involved in load sharing and the sum of the charges collected during the load sharing is allocated to the RDc circuit, the RDc circuit is configured to calculate the sum of the collected charges numerically.

[0074] The RDc circuit receives the lmp signal from electrode 102c (not shown in [Fig. 4]). This lmp signal, for example a current, can be shaped, for example amplified, by an FE circuit of the RDc circuit. The FE circuit receives the lmp signal and provides the shaped signal Impfe.

[0075] The Impfe signal is supplied to a NUM circuit of the RDc circuit. The NUM circuit generates the evt signal of the RDc circuit from the Impfe signal it receives. For example, the NUM circuit provides the active evt signal as soon as the analog signal Impfe is greater than a threshold, and inactive otherwise. The NUM circuit corresponds, in this example, to circuit 300 of the RDc circuit of [Fig.3].

[0076] The NUM circuit is further configured to provide a digital sign signal from the Impfe signal. The sign signal is therefore a signal generated by the RDc circuit and is representative of the amount of charge received by the electrode 102c. The sign signal corresponds to the first signal of the RDc circuit described in relation to [Fig. 3].

[0077] For example, the NUM circuit is a digital discriminator configured to compare the Impfe signal it receives to several thresholds, and to provide a digital sign indicating, for each of these thresholds, whether the Impfe signal is above or below the threshold. The evt signal is, for example, derived from the sign signal, and indicates, for example, whether the Impfe signal is greater than or less than the lowest threshold of the NUM circuit.

[0078] In the example in [Fig. 4], the RDc circuit includes the FE circuit, and the NUM circuit therefore receives the Impfe signal. In other examples, the RDc circuit does not include an FE circuit, and the NUM circuit directly receives the lmp signal.

[0079] The sign and evt signals are provided to a load sharing detection circuit 400 of the RD circuit.

[0080] Circuit 400 is configured to transmit the evtc signal to the adjacent circuits RDn, RDe, RDs, RDw of circuit RDc, and to receive the evtn, evte, evts, evtw signals from the circuits adjacent to circuit RDc. In the example in [Fig. 4], the evtc signal is active if the evt signal is active, and inactive otherwise. As an example, circuit 400 includes a PROC circuit configured to receive the evt, evtn, evte, evts, and evtw signals and to provide the evtc signal.

[0081] From the evt signal and the evtn, evte, evts, and evtw signals, the 400 circuit is configured to detect whether the RDc circuit is involved in load sharing with its adjacent circuits RDn, RDe, RDs, and RDw and, furthermore, when so, which of these adjacent circuits is also involved in this load sharing. In the example in [Fig. 4], these functions are implemented by the PROC circuit. For example, the PROC circuit provides a sel signal indicating which adjacent circuit(s) is / are involved in the load sharing.

[0082] The circuit 400 is further configured to transmit the valc signal to the adjacent circuits RDn, RDe, RDs, RDw of the RDc circuit, and to receive the vain, vale, vais, valw signals from the circuits adjacent to the RDc circuit. In the example in [Fig. 4], these valc, vain, vale, vais, valw signals are digital signals. In the example in [Fig. 4], the valc signal corresponds, for example, to the digital sign signal generated by the RDc circuit and representative of the amount of charge collected by the electrode 102c. By way of example, the circuit 400 includes a configured SUM circuit to receive the signals sign, vain, vale, vais and valw and to provide the valc signal from the sign signal.

[0083] The 400 circuit is configured, when a load sharing involving the RDc circuit is detected and the adjacent circuit(s) RDn, RDe, RDs, RDw involved in this load sharing have been determined (identified), to determine whether the sum of the charges collected during the load sharing should be allocated to the RDc circuit. In the example in [Fig. 4], this functionality of the 400 circuit is implemented based on the signals evt, evtn, evte, evts, and evtw by the PROC circuit, which provides an active win signal if the sum of the collected charges is allocated to the RDc circuit, and an inactive signal otherwise. As an alternative example not shown, this functionality can be implemented based on the signals sign, vain, vale, vais, and valw, for example, by the SUM circuit.

[0084] When the sum of the collected charges is allocated to circuit RDc, circuit 400 is configured to provide, from the signals sign, win, vale, vais, and valw, an OUT signal representing this sum. Conversely, when the sum of the collected charges is allocated to one of the adjacent circuits RDn, RDe, RDs, and RDw of circuit RDc, circuit 400 is configured to provide an OUT signal representing zero collected charges. In the case where no charge sharing is detected, circuit 400 is configured to provide an OUT signal representing only the amount of charge received by electrode 102c, for example, from the sign signal. As an example, in [Fig. 4], this functionality is implemented by the SUM circuit, for example, based on the signals sel, win, sign, win, vale, vais, and valw.

[0085] Figure 5 schematically represents another example of the implementation of the RDc circuit of Figure 3. In this example, when the RDc circuit is involved in load sharing and the sum of the charges collected during the load sharing is allocated to the RDc circuit, the RDc circuit is configured to calculate the sum of the collected charges in an analog manner.

[0086] The RDc circuit of [Fig.5] includes elements in common with the RDc circuit of [Fig.4], and only the differences between these two circuits are highlighted here.

[0087] The RDc circuit receives the lmp signal from electrode 102c (not shown in [Fig.4]). The FE circuit receives the lmp signal and provides the shaped signal Impfe.

[0088] The Impfe signal is supplied to a load-sharing detection circuit 500 of the RDc circuit. In the example in [Fig. 5], the RDc circuit includes the FE circuit, and the 500 circuit therefore receives the Impfe signal. In other examples, the RDc circuit does not include an FE circuit, and the 500 circuit directly receives the Impfe signal.

[0089] Circuit 500 provides the valc signal from the Impfe signal. The Impfe signal (lmp if circuit FE is omitted) is therefore a signal generated by circuit RDc and is representative of the amount of charge received by electrode 102c. The signal Impfe (lmp if the FE circuit is omitted) corresponds to the first signal of the RDc circuit described in relation to [Fig. 3]. In the example, the signal valc is identical to the analog signal Impfe.

[0090] The 500 circuit receives the signals vain, vale, vais and valw. In the example of [Fig.5], the signals valc, vale, vain, vais and valw are analog signals.

[0091] From the signal Impfe, the circuit 500 provides an analog signal sum representing the amount of charge collected by the central electrode 102c to the NUM circuit. More specifically, when no charge sharing is detected, the signal sum is identical to the signal Impfe, and, when charge sharing is detected by the circuit 500 and the adjacent circuit(s) RDn, RDe, RDs and RDw involved in the charge sharing have been identified by the circuit 500, the signal sum is representative of the sum of the charges collected during the charge sharing and is, for example, equal to the sum of the signal Impfe of the circuit RDc and the signals vain, vale, vais and valw of the adjacent circuits involved in the charge sharing.

[0092] By way of example, the transmission of the valc signal to adjacent circuits and the provision of the sum signal is implemented by a SUMa circuit of the 500 circuit. By way of example, the SUMa circuit receives the Impfe, vain, vale, vais and valw signals, and a sel signal indicating the adjacent circuit(s) involved in the load sharing when a load sharing is detected, the SUMa circuit providing the sum signal to the NUM circuit.

[0093] The NUM circuit generates the detection signal evt of the RDc circuit from the sum signal it receives. For example, the NUM circuit provides the active evt signal as soon as the analog sum signal is above a threshold, and inactive otherwise. In other words, the NUM circuit corresponds, in this example, to circuit 300 of the RDc circuit in [Fig. 3].

[0094] The NUM circuit is further configured to provide a digital sign signal from the sum signal.

[0095] For example, the NUM circuit is a digital discriminator configured to compare the sum signal it receives to several thresholds, and to provide a digital sign indicating, for each of these thresholds, whether the sum signal is above or below the threshold. The evt signal is, for example, derived from the val signal, and indicates, for example, whether the val signal is greater than or less than the lowest threshold of the NUM circuit.

[0096] The val and evt signals are provided to the load sharing detection circuit 500 of the RD circuit.

[0097] Circuit 500 is configured to transmit the evtc signal to the adjacent circuits RDn, RDe, RDs, RDw of circuit RDc, and to receive the evtn, evte, evts, evtw signals from the circuits adjacent to circuit RDc. In the example in [Fig. 5], the evtc signal is active if the evt signal is active, and inactive otherwise. As an example, circuit 500 includes a PROC circuit configured to receive the evt, evtn, evte, evts and evtw signals and to provide the evtc signal.

[0098] From the evt signal and the evtn, evte, evts, and evtw signals, the 500 circuit is configured to detect whether the RDc circuit is involved in load sharing with its adjacent circuits RDn, RDe, RDs, and RDw and, furthermore, if so, which of these adjacent circuits are also involved in this load sharing. In the example in [Fig. 5], these functions are implemented by the PROC circuit. For example, the PROC circuit provides the sel signal indicating which adjacent circuit(s) are involved in the load sharing.

[0099] The 500 circuit is configured, when a load sharing involving the RDc circuit is detected and the adjacent circuit(s) RDn, RDe, RDs, RDw involved in this load sharing have been determined, to determine whether the sum of the charges collected during the load sharing should be allocated to the RDc circuit. In the example in [Fig. 5], this functionality of the 500 circuit is implemented based on the signals evt, evtn, evte, evts, and evtw by the PROC circuit, which provides an active win signal if the sum of the collected charges is allocated to the RDc circuit, and an inactive signal otherwise. As an alternative example not shown, this functionality can be implemented based on the signals Impfe, vain, vale, vais, and valw, for example, by the SUMa circuit.

[0100] When the sum of the collected charges is allocated to circuit RDc, circuit 500 is configured to provide, from the signals Impfe, vain, vale, vais, and valw, an OUT signal representing this sum. Conversely, when the sum of the collected charges is allocated to one of the adjacent circuits RDn, RDe, RDs, and RDw of circuit RDc, circuit 500 is configured to provide an OUT signal representing zero collected charges. In the case where no charge sharing is detected, circuit 500 is configured to provide an OUT signal representing only the amount of charge received by electrode 102c, for example, from the Impfe signal. As an example, in [Fig. 5], this functionality is implemented by circuit SUMn, for example, based on the win and sign signals.

[0101] By way of example, the operation of the RDc circuit in [Fig. 5] is as follows. The 500 circuit, for example its SUMa circuit, receives a pulse from the analog signal Impfe and transmits it to the NUM circuit as a corresponding pulse from the sum signal. For example, when the SUMa circuit receives a pulse from the analog signal Impfe, this analog pulse is initially present in the sum signal, before the load-sharing correction function is implemented. The NUM circuit then generates the active evt signal and the corresponding sign signal. In a first case, based on the signals evt, evtn, evts, evte, and evtw, the 500 circuit, for example its PROC circuit, determines that the circuit RDc is not involved in charge sharing (win signal inactive). Circuit 500, for example its SUMn circuit, then provides the OUT signal representing the amount of charge collected by electrode 102c only, based on the sign signal. In a second case, based on the evt, evtn, evts, evte, and evtw signals, Circuit 500, for example its PROC circuit, determines that circuit RDc is involved in charge sharing and identifies the adjacent circuit(s) also involved by means of the sel signal. Circuit 500, for example its SUMa circuit, then updates the sum signal accordingly, which results in the sign signal being updated. For example, in a second case where charge sharing correction is implemented, the sum signal then corresponds to the analog sum of the Impfe signal and the win, vale, vais, and valw signals of the adjacent circuits involved.If the sum of the collected charges is allocated to the RDc circuit (win signal active), the 500 circuit, for example its SUMn circuit, provides the OUT signal from the sign signal so that the OUT signal represents the sum of the collected charges. Conversely, if the sum of the collected charges is not allocated to the RDc circuit (win signal inactive), the 500 circuit, for example its SUMn circuit, provides the OUT signal representing a zero amount of collected charges.

[0102] In Figures 4 and 5, although the sel and win signals are represented as separate digital signals, a person skilled in the art will understand that these two signals can be seen as two parts of one and the same digital signal generated by the 400 circuit in [Fig.4] and by the 500 circuit in [Fig.5], for example by the PROC circuits.

[0103] Examples of charge sharing correction implementations directly in the RD readout circuits of a photon counting detector have been described above in relation to Figures 2, 3, 4 and 5.

[0104] The charge-sharing corrections described above, as well as known charge-sharing corrections, suffer from a drawback. Indeed, with the charge-sharing corrections described, it is not possible to determine, or distinguish, whether the charges collected simultaneously by electrode 102c and by at least one of the electrodes adjacent to electrode 102c result from a single photon and a "true" charge sharing, or from several photons each generating charges collected by an electrode covering the part of layer 100 in which that photon generated charges.

[0105] For example, if a first photon is received by the part of layer 100 opposite electrode 102c and, while the charges from this first photon are being collected by electrode 102c, a second photon is received by the part of layer 100 opposite the adjacent electrode 102n, then electrode 102n will collect the charges from the second photon at least in part while electrode 102c collects the charges from the first photon. The RDc and RDn circuits then detect that they are both involved in a charge sharing, and assign the sum of the collected charges to one or the other of the electrodes 102c and 102n, which degrades the operation of the photon counting detector.

[0106] To overcome this drawback, it is proposed here to add in each RD circuit the ability to selectively activate and deactivate the load sharing correction in that RD circuit.

[0107] In particular, it is intended that each RD circuit is configured to selectively activate and deactivate the load sharing correction that it implements on the basis at least of the evt signal that this circuit generates.

[0108] Indeed, the switching in the active state of the signal evt in an RD circuit is representative of the photon flux received by the pixel comprising this RD circuit. Now, when two RD circuits detect that they are involved in charge sharing, it is more likely that the charges collected by the electrodes connected to these two circuits come from a single photon than from two distinct photons when the detector receives a low flux of photons incident on the 100 layer, whereas, conversely, it is more likely that the charges collected by the electrodes connected to these two circuits come from two distinct photons than from a single photon when the detector receives a high flux of photons incident on the 100 layer.

[0109] According to one embodiment, each RD circuit is configured to deactivate the charge-sharing correction it implements if the average number of active states of its evt signal exceeds a threshold. Indeed, the average number of active states of the evt signal of an RD circuit is representative of the average flux of photons incident on the corresponding portion of layer 100, that is, the portion of layer 100 opposite the electrode to which the circuit is connected. For example, the circuit is further configured to reactivate the charge-sharing correction when this average number of active states of the evt signal falls below the threshold.

[0110] According to another embodiment, each central circuit RDc is configured to deactivate the load-sharing correction it implements if the average number of active states of its signal evt and the signals evtn, evte, evts, evtw that it receives from its adjacent circuits exceeds a threshold. Indeed, the average number of active states of the signals evt, evtn, evte, evts, evtw is representative of the average flux of photons incident on the portion of layer 100 corresponding to this central circuit and on the portions of the layer corresponding to the adjacent circuits. By way of example, the central circuit is further configured to reactivate the load-sharing correction when this average number of active states falls below the threshold.

[0111] According to yet another embodiment, each circuit RD is configured, at the end of each active state of the signal evt generated by that circuit RD, to deactivate The load sharing correction in this RD circuit is deactivated for a time delay, and then, for example, reactivated at the end of this delay. Thus, when the frequency of the active states of the signal evt exceeds a threshold, the load sharing correction remains deactivated.

[0112] According to yet another embodiment, each central circuit RDc is configured to disable the load sharing correction that it implements if the number of active states of the signals evtn, evts, evte and evtw that the central circuit RDc receives from these circuits during an active state of the signal evt generated by this central circuit RDc is greater than a threshold.

[0113] According to yet another embodiment, each central circuit is configured to disable the charge-sharing correction it implements if, when the RDc circuit detects charge sharing, the electrodes connected to the RDc circuit and the adjacent RD circuits involved in the detected charge sharing are arranged relative to each other in a pattern corresponding to abnormal charge sharing, or, in other words, in a pattern in which charges collected simultaneously by these electrodes are more likely to originate from distinct photons than from a single photon. For example, this is the case as soon as the RD circuit detects charge sharing in which at least three electrodes from the set comprising the central electrode 102c and the adjacent electrodes 102e, 102n, 102s, and 102w are involved in the charge sharing.

[0114] Fig. 6 represents schematically and in block form an embodiment of a photon counting detector in which a charge sharing correction is implemented.

[0115] In particular, [Fig. 6] illustrates a central circuit RDc of detector 2 which has been modified to add the function of selectively disabling the load sharing correction. Thus, unless otherwise indicated, everything indicated for detector 2 and the RD circuits of this detector 2 in relation to Figures 2 and 3 applies to the RDc circuit of [Fig. 6].

[0116] Furthermore, although [Fig.6] represents only a central circuit RDc, in practice the other circuits RD of detector 2, in particular the adjacent circuits of this circuit RDc, are identical to the central circuit RDc of [Fig.6].

[0117] Compared to the RDc circuit of [Fig.3], the RDc circuit of [Fig.6] further includes a CSC-EN control circuit configured to selectively activate and deactivate the load sharing correction implemented in this RDc circuit, on the basis at least of the evt signal generated by the RDc circuit, for example by its 300 circuit. The CSC-EN circuit therefore receives the evt signal.

[0118] In embodiments where the CSC-EN circuit controls the activation and deactivation of the load sharing correction based on the evt signal and the signals evtn, evte, evts and evtw received by the RDc circuit, the CSC-EN circuit also receives the signals evtn, evte, evts and evtw as illustrated in the example in [Fig.6].

[0119] For example, the CSC-EN circuit is configured to provide a binary EN signal controlling the activation and deactivation of the load sharing correction in the RDc circuit. For example, the inactive state of the EN signal controls the deactivation of the load sharing correction and the active state of the EN signal controls the activation of the load sharing correction.

[0120] According to one embodiment, the CSC-EN circuit deactivates load sharing correction (EN inactive) if the average number of active states of the evt signal exceeds a threshold. For example, the CSC-EN circuit is further configured to reactivate load sharing correction (EN active) when this average number of active states of the evt signal falls below the threshold.

[0121] According to another embodiment, the CSC-EN circuit disables load sharing correction (EN inactive) if the average number of active states of its signal evt and the signals evtn, evte, evts, evtw that it receives exceeds a threshold. For example, the CSC-EN circuit is further configured to re-enable load sharing correction when this average number of active states falls below the threshold.

[0122] According to yet another embodiment, the CSC-EN circuit deactivates the load sharing correction (EN inactive) at the end of each active state of the evt signal for a time delay period, then, for example, reactivates the load sharing correction (EN active) at the end of this time delay period, provided, of course, that another time delay period is not in progress.

[0123] According to yet another embodiment, the CSC-EN circuit deactivates the load sharing correction (EN inactive) if the number of active states of the signals evtn, evts, evte, and evtw that the central circuit RDc receives from its circuits during an active state of the signal evt exceeds a threshold. For example, the CSC-EN circuit reactivates the load sharing correction at the end of this active state of the signal evt.

[0124] According to yet another embodiment, the CSC-EN circuit deactivates the charge sharing correction (EN inactive) if, when the RDc circuit detects charge sharing, the electrodes connected to the RDc circuit and the adjacent RD circuits involved in the charge sharing are arranged relative to each other in a pattern corresponding to abnormal charge sharing. By way of example, the CSC-EN circuit implements this function based on the evt, evts, evte, evtw, and evtn signals that it receives.

[0125] The way in which the load sharing correction in the RDc circuit is deactivated by the CSC-EN circuit depends on how this correction is implemented. burden sharing as will be illustrated below in relation to figures 7 and 8.

[0126] Fig. 7 represents schematically and in block form an example of an embodiment of the RDc circuit of Fig. 6.

[0127] The RDc circuit of [Fig.7] includes many elements in common with the RDc circuit of [Fig.4], and only the differences between these two circuits are highlighted here.

[0128] Compared to the RDc circuit of [Fig. 4], the RDc circuit of [Fig. 7] includes the CSC-EN circuit. The CSC-EN circuit receives the evt signal, and, in the example of [Fig. 7], the evtw, evte, evts, and evtn signals. However, when the selective activation and deactivation of the load-sharing correction is based solely on the evt signal, the CSC-EN circuit does not receive the evtw, evte, evts, and evtn signals. The CSC-EN circuit provides the EN signal. The EN signal is supplied to the 400 circuit.

[0129] When the charge sharing correction is active (EN active), the circuit 400 operates as described in relation to [Fig. 4]. Conversely, when the charge sharing correction is inactive (EN inactive), the circuit 400 is configured to provide an OUT signal in which the indication of the amount of charge collected by the electrode 102c is determined from the sign signal alone.

[0130] For example, to disable charge sharing correction when the EN signal is inactive, the 400 circuit is configured to ignore the active states of the evt signal, that is, to consider the evt signal as always being inactive. For example, the PROC circuit receives the EN signal. As a result, when charge sharing correction is inactive, the evt signal is always inactive, and adjacent circuits therefore cannot involve the RDc circuit in charge sharing. Furthermore, the OUT signal provides an indication of the charges collected by electrode 102c only from the sign signal. For example, the OUT signal receives the sign signal directly. For example, the SUM circuit receives the EN signal and, when the EN signal is inactive, provides the sign signal directly to the OUT signal, without taking into account any other signals it receives.

[0131] As an alternative example, to disable charge sharing correction when the EN signal is inactive, the 400 circuit is configured to ignore the active states of the evte, evts, evtn, and evtw signals, and to force the evte signal to the inactive state. Thus, the 400 circuit of the RDc circuit does not detect any charge sharing with its adjacent RDs, RDe, RDw, and RDn circuits, and, conversely, the 400 circuits of the RDs, RDe, RDw, and RDn circuits do not detect any charge sharing with the central RDc circuit. As an example, the PROC circuit receives the EN signal and implements the above functions. In addition, the OUT signal provides an indication of the charges collected by electrode 102c only from the sign signal. For example, from the Because the PROC circuit considers the evtn, evts, evte and evtw signals as always inactive, the sel signal does not indicate that adjacent circuits are involved in load sharing, and the SUM circuit then directly provides the sign signal to the OUT signal.

[0132] By way of example, to ignore the active state of a received signal, the 400 circuit includes a multiplexer taking as input the received signal and a signal that is always inactive, and the multiplexer is controlled by the EN signal. The output signal of the multiplexer is then the signal actually used by the 400 circuit.

[0133] By way of example, to force a signal it supplies into an inactive state, the circuit 400 includes a multiplexer taking as input the signal to be transmitted and a signal that is always inactive, and the multiplexer is controlled by the EN signal. The signal at the output of the multiplexer is then the signal actually transmitted by the circuit 400.

[0134] Figure 8 represents, schematically and in block form, an example of the implementation method of the RDc circuit of [Fig.6].

[0135] The RDc circuit of [Fig.8] includes many elements in common with the RDc circuit of [Fig.5], and only the differences between these two circuits are highlighted here.

[0136] Compared to the RDc circuit of [Fig. 5], the RDc circuit of [Fig. 8] includes the CSC-EN circuit. The CSC-EN circuit receives the evt signal, and, in the example of [Fig. 8], the evtw, evte, evts, and evtn signals. However, when the selective activation and deactivation of the load-sharing correction is based solely on the evt signal, the CSC-EN circuit does not receive the evtw, evte, evts, and evtn signals. The CSC-EN circuit provides the EN signal. The EN signal is supplied to the 500 circuit.

[0137] When the charge sharing correction is active (EN active), the circuit 500 operates as described in relation to [Fig. 5]. Conversely, when the charge sharing correction is inactive (EN inactive), the circuit 500 is configured to provide a sum signal determined solely from the Impfe signal, so that, in the OUT signal, the indication of the amount of charge collected by the electrode 102c is determined solely from the Impfe signal.

[0138] For example, to disable charge sharing correction when the EN signal is inactive, the 500 circuit is configured to ignore the active states of the evt signal, that is, to consider the evt signal as always being in the inactive state. For example, the PROC circuit receives the EN signal. As a result, when charge sharing correction is inactive, the evt signal is always inactive, and adjacent circuits therefore cannot involve the RDc circuit in charge sharing. Furthermore, the OUT signal provides an indication of the charges collected by electrode 102c only from the Impfe signal. For example, because the evt signal is considered inactive by the PROC circuit, no charge sharing involving the circuit RDc is not detected by the PROC circuit, and the sel signal does not indicate any of the adjacent read circuits. It follows that the sum signal, and therefore the sign signal, are determined solely by the Impfe signal, and consequently, in the OUT signal, the indication of the amount of charge collected by electrode 102c is determined solely by the Impfe signal.

[0139] As an alternative example, to disable charge sharing correction when the EN signal is inactive, circuit 500 is configured to ignore the active states of the evte, evts, evtn, and evtw signals, and to force the evtc signal to the inactive state. Thus, circuit 500 of circuit RDc detects no charge sharing with its adjacent circuits RDs, RDe, RDw, and RDn, and, conversely, circuits 400 of circuits RDs, RDe, RDw, and RDn detect no charge sharing with the central circuit RDc. As an example, the PROC circuit receives the EN signal and implements the above functions. In addition, the OUT signal provides an indication of the charges collected by electrode 102c only from the Impfe signal. For example, because the PROC circuit considers the evtn, evts, evte and evtw signals to always be inactive, the sel signal does not indicate that adjacent circuits are involved in load sharing.It follows that the sum signal, and therefore the sign signal, are determined solely by the Impfe signal, and it follows that, in the OUT signal, the indication of the quantity of charge collected by electrode 102c is determined solely by the Impfe signal.

[0140] By way of example, to ignore the active state of a received signal, the 500 circuit includes a multiplexer taking as input the received signal and a signal that is always inactive, and the multiplexer is controlled by the EN signal. The output signal of the multiplexer is then the signal actually used by the 500 circuit.

[0141] By way of example, to force a signal it supplies into an inactive state, the circuit 500 includes a multiplexer taking as input the signal to be transmitted and a signal that is always inactive, and the multiplexer is controlled by the EN signal. The signal at the output of the multiplexer is then the signal actually transmitted by the circuit 400.

[0142] Examples of implementations in which, when charge sharing is detected by an RDc circuit and this RDc circuit has determined the adjacent readout circuit(s) involved in the charge sharing, the allocation in the RDc circuit of the sum of the collected charges to one or the other of the readout circuits involved in the charge sharing is based on the signals evt, evtn, evts, evte, and evtw. Those skilled in the art will be able to adapt these examples to the case where, in the RDc circuit, the allocation of the sum of the collected charges is based on the signal representing the amount of charge collected by electrode 102c, which is generated in the RDc circuit (sign in [Fig. 7] and Impfe in [Fig. 8]) and the signals vale, vais, valw, and vain.

[0143] Furthermore, in the examples described in relation to Figures 3 to 8, the RDc circuit exchanges signals with the adjacent circuits RDn, RDe, RDw and RDs only, so that the charge sharing correction is implemented when the charge sharing involves electrode 102c and one or more of the adjacent electrodes 102e, 102w, 102s and 102n only. A person skilled in the art will be able to adapt these examples to the case where the RDc circuit exchanges signals with the adjacent circuits RDn, RDe, RDw, RDs, RDse, RDsw, RDne and RDnw, so that the load sharing correction is implemented when the load sharing involves electrode 102c and one or more of the adjacent electrodes 102e, 102w, 102s, 102n, 102ne, 102nw, 102se and 102sw.

[0144] Figure 9 represents an example of implementation of the CSC-EN circuit described in relation to Figures 6, 7 and 8. Figure 10 represents timing diagrams illustrating the operation of the CSC-EN circuit of Figure 9.

[0145] In this example, the CSC-EN circuit of the RDc circuit is configured to disable the load sharing correction implemented in the RDc circuit if the average number of active states of the signal evt generated in the RDc circuit exceeds a threshold Vth. The comparison of the average number of active states of the signal evt to the threshold Vth is, in this example, implemented with a hysteresis H on the value of the threshold Vth.

[0146] The CSC-EN circuit includes a PBF low-pass filter receiving the signal evt and providing a signal evtm having a value determined by the average number of active states of the signal evt.

[0147] The CSC-EN circuit further includes a CMP comparator receiving the evtm signal and comparing it to the threshold Vth, in this example by applying a hysteresis of value H. The output of the CMP comparator provides the EN signal.

[0148] In this example, the active state of the signal EN is a high state, and the active state of the signal evt is also a high state.

[0149] Thus, as can be seen in [Fig. 10], when the frequency of the active states of the evt signal is relatively low (left side of [Fig. 10]), the evtm signal is below the threshold Vth, i.e., below Vth-H in this example. The EN signal is then active (EN in the high state), and the correction is active. When the frequency of the active states of the evt signal is relatively high (right side of [Fig. 10]), the evtm signal is above the threshold Vth, i.e., above the threshold Vth+H in this example. The EN signal is then inactive (EN in the low state), and the correction is deactivated.

[0150] A person skilled in the art will be able to adapt the above example to the case where the CSC-EN circuit determines the state of the EN signal from the average number of active states of the signals evt, evtn, evtw, evts etc...

[0151] Fig. 11 represents another example of implementation of the CSC-EN circuit described in relation to Figures 6, 7 and 8. Fig. 12 represents timing diagrams illustrating the operation of the CSC-EN circuit of Fig. 11.

[0152] In this example, the CSC-EN circuit of the RDc circuit is configured to disable the load sharing correction implemented in the RDc circuit for a time duration At after each end of the active state of the evt signal.

[0153] The CSC-EN circuit includes a retriggerable monostable circuit MONO. The MONO circuit is configured to provide the EN signal in the active state by default, and to force the EN signal to the inactive state for a duration At after each end of the active state of the evt signal. Thus, the MONO circuit receives the evt signal at a control input and provides the EN signal at its output.

[0154] In this example, the active state of the signal EN is a high state, and the active state of the signal evt is also a high state.

[0155] Thus, as can be seen in [Fig. 12], when two successive active states of the signal evt are relatively far apart (on the left in [Fig. 12]), at the end of the first of the two active states of the signal evt (time t0), the signal EN is forced into the inactive state for the duration At, then returns to the active state at the end of the duration At (time t1), before the next active state of the signal evt occurs (time t2). The load-sharing correction will therefore be active for these two active states of the signal evt. On the other hand, when two successive active states of the signal evt are relatively close to each other (right in [Fig. 12]), at the end of the first of the two active states of the signal evt (time t3), the signal EN is forced into the inactive state for the duration At and the next active state of the signal evt (time t4) occurs while the duration At has not entirely elapsed.The load sharing correction will therefore be inactive for this second active state of the signal evt. Furthermore, the end of the active state occurring during the duration At re-engages the MONO circuit, and a new duration At begins (time t5).

[0156] Two examples of implementations of the CSC-EN circuit have been described in relation to Figures 9 to 12. A person skilled in the art will be able to foresee other implementations of the CSC-EN circuit. For example, a person skilled in the art will be able to implement CSC-EN circuits corresponding to the different operating alternatives of the CSC-EN circuit described in relation to [Fig. 3].

[0157] More generally, from this description, a person skilled in the art will be able to add, in a known reading circuit implementing a load sharing correction, the function of selectively activating and deactivating the load sharing correction on the basis of at least a detection signal generated in this circuit, and, furthermore, to adapt the circuit accordingly.

[0158] For example, in each reading circuit 22 of [Fig. 4] of document EP 2936208 (or US 9329283), the person skilled in the art will be able to add the function selective activation and deactivation of the load sharing correction based at least on the H1 signal generated in this reading circuit 22.

[0159] As another example, in the readout circuit of [Fig.3] in the article "The Medipix3RX: a high resolution, zero dead-time pixel detector readout chip allowing spectroscopic imaging", a person skilled in the art will be able to add the function of selectively enabling and disabling the charge sharing correction on the basis at least of the DiscOutLocal signal generated in this circuit.

[0160] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0161] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. Photon counting detector (1,2) comprising a photon-to-charge conversion layer (100) covered with several electrodes (102) each connected to a readout circuit (RD), wherein: each readout circuit (RD) is configured to generate an active detection signal (evt) when charges are collected by the electrode (102) to which the readout circuit (RD) is connected; Each readout circuit, called the central circuit (RDc), is configured to implement a load-sharing correction by exchanging signals (200; evtc, evtn, evts, evte, evtw, valc, vain, vais, vale, valw) with readout circuits, called adjacent circuits (RDn, RDs, RDe, RDw) of the central circuit (RDc), connected to electrodes adjacent (102n, 102s, 102e, 102w) to the electrode to which the central circuit is connected, called the central electrode (102c); and each central circuit (RDc) is configured to selectively turn on and off (CSC-EN;EN) the load sharing correction in said central circuit on the basis at least of the detection signal (evt) generated by said central circuit.;

2. Detector according to claim 1, wherein: each central circuit (RDc) is adapted to send the detection signal (evtc) that it generates to each of the adjacent circuits (RDn, RDs, RDe, RDw) of the central circuit (RDc), each of the adjacent circuits (RDn, RDs, RDe, RDw) of said central circuit (RDc) being adapted to send the detection signal (evtn, evts, evte, evtw) that it generates to said central circuit.

3. Detector according to claim 2, wherein each central circuit (RDc) is configured to disable load sharing correction in said central circuit (RDc) if an average number of active states of the detection signal (evt) generated by the central circuit (RDc) is greater than a threshold (Vth).

4. Detector according to claim 2, wherein each central circuit (RDc) is configured to disable load sharing correction in said central circuit (RDc) if an average number of active states of the detection signal (evt) generated by the central circuit (RDc) and detection signals (evtn, evts, evte, evtw) than the circuit central (RDc) receives from adjacent circuits (RDn, RDs, RDe, RDw) of the central circuit (RDc) is greater than a threshold.

5. Detector according to claim 2, wherein each central circuit (RDc) is configured to disable load sharing correction in said central circuit (RDc) for a time delay (At) after an end of each active state of the detection signal (evt) generated by the central circuit (RDc).

6. Detector according to claim 2, wherein each central circuit (RDc) is configured to disable load sharing correction in said central circuit (RDc) if a number of active states of the detection signals (evtn, evts, evte, evtw) that the central circuit (RDc) receives from the adjacent circuits (RDn, RDs, RDe, RDw) of the central circuit (RDc) during an active state of the detection signal (evt) generated by the central circuit is greater than a threshold.

7. Detector according to claim 2, wherein each central circuit (RDc) is configured to disable charge sharing correction in said central circuit (RDc) if the central circuit (RDc) and the adjacent circuit(s) (RDn, RDs, RDe, RDw) of the central circuit (RDc) which send active detection signals (evtn, evts, evte, evtw) during an active state of the detection signal (evt) generated by the central circuit (RDc) are connected to electrodes (102; 102c, 102n, 102s, 102e, 102w) arranged relative to each other in a pattern corresponding to an abnormal charge sharing.

8. Detector according to any one of claims 2 to 7, wherein: each central circuit (RDc) comprises a charge sharing detection circuit (400; 500) configured to detect that the central electrode (102c) and one or more of the electrodes adjacent (102n, 102s, 102e, 102w) to the central electrode are involved in charge sharing, from the detection signal (evt) generated in the central circuit and respectively from the detection signal(s) (evtn, evts, evte, evtw) sent to the central circuit (RDc) by respectively the adjacent circuit(s) (RDn, RDs, RDe, RDw) connected respectively to said one or more adjacent electrodes (102n, 102s, 102e, 102w).

9. Detector according to claim 8, wherein: each readout circuit (RD; RDc, RDn, RDs, RDe, RDw) is configured to generate a first representative signal (Impfe; sign) of a quantity of charges collected by the electrode (102; 102c, 102n, 102s, 102e, 102w) to which the reading circuit is connected; and each central circuit (RDc) is adapted to send the first signal (Impfe; sign; valc) that it generates to each of said adjacent circuits (RDn, RDs, RDe, RDw) of the central circuit (RDc), each of said adjacent circuits (RDn, RDs, RDe, RDw) of said central circuit (RDc) being adapted to send the first signal (Impfe; sign; vain, vais, vale, valw) that it generates to said central circuit.

10. Detector according to claim 9, wherein the charge sharing detection circuit (400, 500) of each central circuit (RDc) is configured, when it detects that the central electrode (102c) and one or more of the adjacent electrodes (102n, 102s, 102e, 102w) are involved in charge sharing, to determine to which of the electrodes involved in charge sharing is assigned a sum of the charges collected by the electrodes involved in charge sharing.

11. Detector according to claim 9, wherein the charge-sharing detection circuit (400, 500) is configured to determine to which of the electrodes involved in charge sharing is assigned the sum of the charges collected by the electrodes involved in charge sharing from: the detection signal (evt) generated by the central circuit (RDc) and the detection signal(s) (evtn, evts, evte, evtw) sent to the central circuit (RDc) by the adjacent circuit(s) (RDn, RDs, RDe, RDw) connected respectively to said one or more adjacent electrode(s) (102n, 102s, 102e, 102w) involved in charge sharing, or the first signal (Impfe, sign) generated by the central circuit (RDc) and the first signal(s) (vain, vais, vale, valw) sent to the central circuit by the adjacent circuit(s) (RDn, RDs, RDe, RDw) connected respectively to said one or more adjacent electrodes (102n, 102s, 102e,102w) involved in load sharing.

12. Detector according to claim 10 or 11, wherein each central circuit (RDc) is configured: when the charge sharing correction is active in the central circuit, to provide an output signal (OUT) representative of the sum of the charges collected by the central electrode (102c) and said one or more adjacent electrodes (102n, 102s, 102e, 102w) involved in charge sharing if this sum of charges is attributed to the central electrode (102c), and of a zero amount of charge otherwise; and when the charge sharing correction is inactive in the central circuit (RDc), to provide an output signal (OUT) representative of the charges collected by the central electrode (102c) only.

13. Detector according to any one of claims 1 to 12, wherein the reading circuits (RD; RDc, RDn, RDs, RDe, RDw) are identical.

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