Method for manufacturing interconnectors for an electronic device

Abstract

Interconnect Fabrication Method for an Electronic Device This description relates to an interconnect fabrication method for an electronic device comprising the steps: a) providing a substrate (100) in which a first chip is formed, assembled to a second chip (200) by hybrid bonding, and on which conductive pads (110) are positioned, the second chip (200) comprising through-vias (220), b) forming conductive wires (150) on the connection pads (110), and optionally on the through-vias (220), c) depositing a layer of insulating material (410) on the substrate (100) and on the second chip (200), to encapsulate the conductive wires (150), d) thinning the layer of insulating material (410), e) forming conductive elements on the layer of insulating material, the conductive elements being connected either to the conductive pads (110) or to the vias (220). Figure for the abstract: Fig. 2D

Description

Title of the invention: Method for manufacturing an interconnect for an electronic device. Technical field

[0001] The present description relates generally to the field of electronic devices and, more particularly, to electronic devices comprising chips assembled by direct bonding onto substrates ('Die to Wafer') and their integration onto external devices by a technique of reverse transfer ('Flip-Chip'). Previous technique

[0002] In a heterogeneous D2W (die-to-wafer) integration, the active face of an upper chip is hybrid-bonded to the active face of a lower chip formed on a substrate. When it is necessary to have connections directly on both chips (for example, to have a power / distribution network without ohmic drop), through-hole vias (TSVs) are formed in the upper chip. Interconnecting elements (pillars or bumps) are then formed. Some of the interconnecting elements are formed on the TSVs and thus connected to the upper chip via the TSVs, and others are formed on connection pads positioned on the substrate and connected to the lower chip. The resulting electronic component can then be assembled to an external element, such as a printed circuit board.

[0003] However, even with very thin upper chips (typically between 20 and 30 µm thick), the height difference between the base of the various interconnecting elements is significant. The resulting interconnecting elements are therefore non-coplanar. Mounting the electronic component on a printed circuit board is then impossible and / or can cause thermomechanical stress within the final device, thus reducing its reliability over time. Summary of the invention

[0004] There is a need for electronic components comprising a substrate in which a chip is formed and on which another chip is mounted, for example by means of a die-to-wafer (D2W) bonding process, the electronic components being able to be easily assembled to external elements, typically printed circuits, by a flip chip technique in a durable and reliable manner.

[0005] This object is achieved by a manufacturing process for an interconnect for an electronic device comprising the following steps: a) provide an assembly comprising a substrate in which a first chip is formed, a first face of a second chip being assembled to the first chip by hybrid bonding, the second chip comprising through-vias emerging on a second face of the second chip, conductive pads being positioned on the substrate and connected to the first chip, b) form conductive wires on the connection points, c) deposit a layer of insulating material on the first face of the substrate and on the second chip, so as to encapsulate the conductive wires, d) thin the layer of insulating material, with the conductive wires accessible from an upper surface of the insulating material layer, e) form conductive elements on the insulating material layer opposite the conductive pads and opposite the vias, the conductive elements being connected either to the conductive pads or to the vias, thereby obtaining interconnections for the first chip and interconnections for the second chip.

[0006] According to one embodiment, the method includes a step b') in which conducting wires are formed on the through vias, conducting pads being able to be arranged between the through vias and the conducting wires.

[0007] According to one embodiment, the method comprises, between step d) and step e), a step in which the insulating material is engraved to form openings opposite through-vias and in which the openings are filled with a conductive material to form conductive pads, an upper face of the insulating material being at the same level as an upper face of the conductive pads.

[0008] According to one embodiment, the conductive elements are electrically conductive pillars.

[0009] According to one embodiment, step e) is carried out according to the following substeps: - apply a primer layer to the insulating material layer, preferably applying the primer layer across the entire plate, - to form a resin layer having openings opposite the conductive areas and opposite the vias, - to form the conductive elements through the openings in the resin, - remove the resin and remove the part of the primer layer not covered by the conductive elements.

[0010] According to one embodiment, the conductive elements are brazing balls.

[0011] According to one embodiment, step e) is carried out according to the following substeps: - deposit conductive layers on the insulating material layer opposite the conductive areas and opposite the vias, - to form the conductive elements on the conductive surfaces.

[0012] According to one embodiment, one or more conductive wires are formed on each connection area of ​​the first chip and / or on each conductive pad covering the vias.

[0013] This object is reached by an electronic device comprising a substrate in which a first chip is formed, a first face of a second chip being assembled to the first chip by hybrid bonding, the second chip comprising through-vias emerging on a second face of the second chip, conductive pads being positioned on the substrate and connected to the first chip, interconnections for the first chip being formed on the connection pads, the interconnections comprising from the connection pads: conductive wires and conductive elements, interconnections for the second chip being formed on the through-vias, the interconnections comprising conductive elements, conductive wires being able to be arranged between the through-vias and the conductive elements, a layer of insulating material covering the first face of the substrate and the second chip and surrounding the conductive wires,the conductive elements are arranged on the layer of insulating material.

[0014] According to one embodiment, the conductive elements are brazing balls or conductive pillars.

[0015] This object is reached by an assembly comprising a device as defined above, and an external device, such as a printed circuit board, comprising connection pads, the conductive elements being assembled on the connection pads of the external device.

[0016] This object is achieved by an assembly as defined above, the process comprising a step during which the conductive elements are assembled on the connection ranges of the external device, for example during a soldering step. Brief description of the drawings

[0017] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0018] [Fig.1A], [Fig.1B], [Fig.1C], [Fig.1D], [Fig.1E], [Fig.1F] and [Fig.1G] schematically represent different stages of a manufacturing process for a D2W type electronic component according to a particular embodiment;

[0019] Figures [Fig. 2A], [Fig. 2B], [Fig. 2C], [Fig. 2D], [Fig. 2E] and [Fig. 2F] schematically represent different stages of a manufacturing process of a D2W type electronic component according to another particular embodiment;

[0020] Fig. 3A, Fig. 3B, Fig. 3C, Fig. 3D, Fig. 3E, Fig. 3F, Fig. 3G, Fig. 3H and Fig. 31 schematically represent different stages of a manufacturing process for a D2W type electronic component according to another particular embodiment;

[0021] [Fig.4] is a schematic representation, in cross-section and side view, of a D2W type electronic component according to another particular embodiment;

[0022] [Fig. 5] is a schematic cross-sectional representation of a conducting wire on a connection range, according to another particular embodiment,

[0023] [Fig.6] is a schematic cross-sectional representation of a D2W type electronic component assembled to an external element, according to another particular embodiment.

[0024] The different elements in the figures are not necessarily represented at a uniform scale to make them more legible. Description of the implementation methods

[0025] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0026] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0027] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0028] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures in a normal position of use.

[0029] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean at 10%, preferably at 5%.

[0030] We will now describe in detail the manufacturing process of an interconnect for an electronic component with reference to Figures 1 to IG, Figures 2A to 2F and Figures 3A to 31, as well as Figures 4 and 5.

[0031] The process comprises the following steps: a) provide an assembly comprising a substrate 100 in which a first chip is formed, a first face 101 of a second chip 200 being assembled to the first chip for example by hybrid bonding, the second chip 200 comprising through vias 220 emerging on a second face 201 of the second chip 200 and forming conductive contacts, conductive pads (110) being positioned on the substrate (100) and connected to the first chip (figures IA, 2A, 3A), b) form conductive wires 150 on the connection ranges 110 (figures IB, 2B, 3B), c) deposit a layer of insulating material 410 on the substrate and on the second chip, the insulating material enclosing the conductive wires 150 (figures IC, 2C, 3C), d) thin the layer of insulating material 410, the conductive wires 150 being accessible from a top face of the layer of insulating material 410 (figures 1D, 2D, 3D) e) form conductive elements 160, 190 on the layer of insulating material (410) opposite the conductive pads 110 and opposite the vias 220, part of the conductive elements 160, 190 being connected to the conductive pads (110) and the other part of the conductive elements 160, 190 being connected to the vias (220), thereby obtaining interconnections for the first chip and interconnections for the second chip 200 (figures IG, 2F, 31).

[0032] The upper faces of the conducting elements 160, 190 are at the same distance from the first face 101 of the substrate 100.

[0033] According to one embodiment, the method may include an additional step b'), between step a) and step c) in which conducting wires 150 are formed opposite the vias 220 and electrically connected to the vias 220.

[0034] Thus, the interconnections of the electronic components are formed in two stages: - initially, the lower part of the interconnections of the first chip is formed (i.e., the 150 conductive wires deposited during step b)), and possibly the lower part of the interconnections of the second chip is formed (i.e., the 150 conductive wires deposited during step b')), and - in a second step, the conductive elements 160, 190 are deposited to simultaneously form the upper part of the interconnections of the first chip and either the interconnections of the second chip 200 or the upper part of the interconnections of the second chip (if step b') is implemented).

[0035] The resulting interconnections are coplanar. With such a process, it is possible to achieve a very fine pitch (for example, on the order of 100 pm or even 60 pm).

[0036] The assembly provided in step a) includes the substrate 100 in which the first chip (or lower chip) and the second chip 200 (or upper chip) are formed (figures IA, 2A, 3A) mounted on the substrate 100.

[0037] The substrate 100 comprises a first face 101 and a second face 102. The connection pads 120 of the first chip are positioned on the first face of the substrate 100. Connection pads 110, connected to the first chip, are also positioned on the first face 101 of the substrate 100, on either side of the connection pads 120. The connection pads 120 are used to connect the first chip to the second chip 200. The connection pads 110 are used to connect the first chip to an external element 500.

[0038] The second chip 200 comprises a first face 201 (front face or active face) and a second face 202 (rear face).

[0039] The first face 201 of the second chip 200 is positioned opposite the first chip. Their active faces are positioned opposite each other. The first face 201 of the second chip 200 includes connection pads 210 for connecting it to the first chip.

[0040] The first chip and the second chip are joined together by a die-to-wafer (D2W) assembly obtained by hybrid bonding. A low chip-to-chip impedance is obtained.

[0041] The second chip 200 also includes through-silicon vias 220 (TSV). The vias 220 run from the first face 201 of the second chip 200 to the second face 202 of the chip 200. The through-silicon vias 220 open onto the second face 202 of the second chip 200 and form conductive contacts used to connect the second chip 200 to an external element.

[0042] The second chip 200 has a thickness, for example, less than 60pm, for example less than or equal to 30pm (for example between 20 and 30pm) or less than 1Opm (for example between 6 and 1Opm).

[0043] In the figures, the assembly of a single first chip and a single second chip is shown to make the figures more legible. However, a plurality of first chips can be formed in the substrate 100 and a plurality of second chips 200 can be assembled to the plurality of first chips. In order to separate the different first chip / second chip assemblies, the process includes a step, after step e), in which the substrate 100 is cut.

[0044] During step b), conductive wires 150 are formed on the connection areas 110 (figures IB, 2B, 3B).

[0045] Before carrying out step b'), in which conducting wires 150 are formed on the vias 220, a conducting pad 230 is preferably placed on the vias 220 to provide a larger surface area for forming the conducting wires 150 (Figures IB, 2B). Steps b) and b') can be carried out simultaneously or consecutively.

[0046] The 150 conductive wires can be formed by a wire bonding technique.

[0047] In the various figures representing the steps of the manufacturing process of the electronic component, a U-shaped conductive wire is formed on the connection pads and, optionally, on the conductive pads 230. However, as shown in [Fig. 5], it would be possible to form one or more straight wires 150 on each conductive pad 110 and optionally on each conductive pad 230. It would also be possible to form conductive wires connecting two connection pads 110 and / or two conductive pads 230, the conductive wires 150 being cut during the thinning step in order to avoid short circuits in the device.

[0048] The conducting wires 150 are, for example, made of copper or gold. They have a diameter of, for example, between 20 and 30 µm, for example on the order of 25 µm.

[0049] In step c), a layer of insulating material 410 is deposited on the substrate 100 and on the second chip 200. The insulating material completely encases the conductive wires 150. The layer of insulating material 410 completely covers the first face 101 of the substrate 100 and the second face 202 of the second chip 200.

[0050] The insulating material 410 is, for example, a polymer, preferably a polyimide (PI) or a polybenzoxazole (PBO), or an oxide.

[0051] The insulating material layer 410 acts as a buffer layer and absorbs part of the mechanical stresses applied to the conducting wires 150.

[0052] In step d), the insulating material 410 is thinned. Since the conducting wires are completely enclosed by the layer of insulating material 410 in step c), this makes the upper part of the conducting wires 150 accessible and allows their height to be leveled ([Fig. 3D]). A flat upper surface of the insulating material / conducting wires is obtained.

[0053] If step b') is not carried out, after step d), the method includes a step in which the insulating material 410 is etched to form openings 411 opposite vias 220 ([Fig. 3E]). The openings 411 are then filled with a conductive material to form conductive pads 230, so that the upper face of the insulating material is at the same level as the upper face of the conductive material ([Fig. 3F]). In other words, the upper face of the conductive material and the upper face of the insulating material are coplanar.

[0054] The openings formed in the insulating material 410 are, for example, made by photolithography or by laser engraving.

[0055] The conductive material forming the conductive pads 230 is, for example, copper. The copper can be coated with a layer, for example of gold or nickel, to prevent its oxidation.

[0056] During step e), the conductive elements 160, 190 are formed, on the one hand, on the conductive wires 150 positioned on the conductive pads 110 and, on the other hand, on the vias 220 or on the conductive wires 150 positioned on the vias 220.

[0057] At the end of this step, the interconnections of the second chip 200 and the first chip are formed.

[0058] Part of the conductive elements 160, 190 covers the passivation layer 420, which improves resistance to mechanical stress.

[0059] According to an alternative embodiment, for example shown in Figures 1E to 1G and 3G to 3G, step e) can be carried out according to the following substeps: - deposit a seed layer 310 to cover the accessible conductive wires 150, the seed layer 310 preferably being deposited on the entire plate (figures 1E, 3G), - to form, on the primer layer 310, a layer of resin 420 having openings 421 (figures 1F, 3H), - form the conductive elements 160 through the openings 421 in the resin layer 420, then deposit a layer of solder, - remove the resin 420 and then the part of the primer layer 310 not covered by the conductive elements 160, - Preferably, a reflow is performed to melt the solder layer and form solder pads 171 on the conductive elements 160 (Figures IG, 31).

[0060] According to this embodiment, the conductive elements 160 are, for example, in the form of pillars. These may be copper pillars. The height of the resin layer 420 is preferably greater than the desired height of the pillars. The upper part of the pillars is thus well defined.

[0061] The brazing layer can be made of a tin-based alloy, for example an SnAgCu alloy.

[0062] The primer layer 310 allows the conductive elements 160 to grow by electrolytic deposition. The primer layer 310 is, for example, made of TiCu.

[0063] The resin is, for example, a photoresin. Conventional photolithography techniques can be used to form a resin layer with openings.

[0064] According to another embodiment, for example shown in Figures 2E and 2F, step e) is carried out according to the following substeps: - to form conductive layers 180 on the conductive wires 150, the conductive layers 180 being connected to the conductive wires 150 ([Fig.2E]), - form the conductive elements 190 on the conductive layers 180 ([Fig.2F]).

[0065] According to this embodiment, the conductive elements 190 are brazing balls. They can be deposited through a mask or by an automatic ball placement tool.

[0066] The conductive layers 180 are made of metal or a metal alloy. They are, for example, made of aluminum ('AluCap') or NiAu.

[0067] The brazing balls 190 can be made of a tin-based alloy, for example an SnAgCu alloy.

[0068] It is possible to combine these different embodiments, for example to obtain the structure shown in [Fig. 4]. This structure is obtained by carrying out the steps shown in Figures 3A to 3F and then forming conductive layers 180 on the vias 220 (the conductive layers 180 being connected to the vias 220) and on the conductive wires 150 formed on the connection areas 110. A conductive element 190 is then formed on the conductive layers 180.

[0069] As previously stated, after the implementation of steps a) to e), a cutting step, during which the chips are separated, can be carried out.

[0070] The resulting electronic device comprises ([Fig.1G], 2F, [Fig.31] and [Fig.4]): - a first interconnection group formed on the substrate 100 and connected to the first connection pads 110, and - a second interconnection group formed on the second face 202 of the second chip 200 and connected to the vias 220.

[0071] The first interconnection group allows the substrate chip 100 to be connected to the external element 500 and the second interconnection group allows the second chip 200 to be connected to the external element 500.

[0072] The interconnections of the first interconnection group comprise a first part (or lower part) formed of the conducting wires 150 on which rests a second part (or upper part) formed of the conducting element 160, 190. More particularly, the interconnections of the first interconnection group may comprise successively from the conducting areas 110: conducting wires 150, a starter layer 310, a conducting element 160, optionally a solder pad 171. The conducting element 160 may have a surface identical to the surface of the starter layer 310 (Figures IG, 31).

[0073] Alternatively, the interconnections of the first interconnection group may successively comprise, from the conductive areas 110: a starter layer 310, conductive wires 150, a conductive layer 180, a conductive element 190 ([Fig.2F], [Fig.4]). The conductive element 190 can have a surface area greater than the surface area of ​​the conductive layer 180.

[0074] The interconnections of the second interconnection group include the conductive element 160, 190. More particularly, the interconnections of the second interconnection group include successively from the through vias 220: a conductive pad 230 in contact with the through vias 220, conductive wires 150, a starter layer 310, a conductive element 160, optionally a solder pad 171 ([Fig.1G]).

[0075] Alternatively, the interconnections of the second interconnection group may successively comprise, starting from the through vias 220: a conductive pad 230, conductive wires 150, a conductive layer 180, a conductive element 190 ([Fig. 2F]). The conductive element 190 may have a larger surface area than the conductive layer 180.

[0076] Alternatively, the interconnections of the second interconnection group may successively comprise from the through vias 220: a conductive pad 230, a starter layer 310, a conductive element 160, optionally a solder pad 171 ([Fig.31]).

[0077] Alternatively, the interconnections of the second interconnection group may successively comprise from the through vias 220: a conductive layer 180, a conductive element 190 ([Fig.4]).

[0078] The conductive elements 160, 190 of the first interconnection group and the second interconnection group rest on the passivation layer 420, which reduces the mechanical stress on the interconnections.

[0079] The upper faces of the conductive elements 160, 190 are equidistant from the first face 101 of the substrate 100, which facilitates the positioning and assembly of the interconnections with an external element 500, such as a printed circuit board (PCB) or a laminated substrate ([Fig. 6]). In [Fig. 6], the electronic component of [Fig. 1G] is shown; it is evident that the other components described above could also be used.

[0080] Since the interconnections are coplanar, the electronic device can be assembled by any conventional technique, for example by wire bonding or by bumping.

[0081] In particular, the method of assembling the device to an external element 500 includes a step in which the interconnections are aligned and brought into contact with the connection pads 510 of the device 500 and a step, for example of brazing, in which the interconnections are fixed to the connection pads 510 of the external element 500. Brazing ensures electrical and mechanical contact between the device and the external element. It can be carried out either by adding the additional solder paste either with a brazing flux which deoxidizes and maintains the device during the reflow step of the 190 solder balls or the 171 solder pads on the 510 connection ranges.

[0082] The electronic device can be an analog memory device. It can be used in systems requiring a large number of inputs / outputs (I / O) (or LO (for Input / Output)). It is particularly interesting for the automotive field (especially for a Microcontroller Unit (MCU)) or for personal (consumer) devices.

[0083] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0084] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. A method for manufacturing an interconnect for an electronic device comprising the following steps: a) providing an assembly comprising a substrate (100) in which a first chip is formed, a first face (101) of a second chip (200) being bonded to the first chip by hybrid bonding, the second chip (200) comprising through-vias (220) emerging on a second face (201) of the second chip (200), conductive pads (110) being positioned on the substrate (100) and connected to the first chip; b) forming conductive wires (150) on the connection pads (110); c) depositing a layer of insulating material (410) on the first face of the substrate (100) and on the second chip (200) so as to encapsulate the conductive wires (150); d) thinning the layer of insulating material (410), the conductive wires (150) being accessible from an upper face of the insulating material layer (410), e) form conductive elements (160,190) on the insulating material layer (410) opposite the conductive pads (110) and opposite the vias (220), the conductive elements (160, 190) being connected either to the conductive pads (110) or to the vias (220), thereby obtaining interconnections for the first chip and interconnections for the second chip (200).

2. A method according to claim 1, comprising a step b') in which conducting wires (150) are formed on the through vias (220), conducting pads (230) being able to be arranged between the through vias (220) and the conducting wires (150).

3. A method according to claim 1, comprising, between step d) and step e), a step in which the insulating material (410) is engraved to form openings (411) opposite through-vias (220) and in which the openings (411) are filled with a conductive material to form conductive studs (230), an upper face of the insulating material (410) being at the same level as an upper face of the conductive studs (230).

4. A method according to any one of claims 1 to 3, wherein the conducting elements (160) are electrically conductive pillars.

5. A method according to the preceding claim, wherein step e) is carried out according to the following substeps: - depositing a primer layer (310) on the insulating material layer (410), the primer layer (310) preferably being deposited full plate, - forming a resin layer (420) having openings (421) opposite the conductive areas (110) and opposite the vias (220), - forming the conductive elements (160) through the openings (421) of the resin (420), - removing the resin (420) and removing the part of the primer layer (310) not covered by the conductive elements (160).

6. A method according to any one of claims 1 to 3, wherein the conductive elements (190) are brazing beads.

7. A method according to the preceding claim, wherein step e) is carried out according to the following substeps: - depositing conductive layers (180) on the insulating material layer (410) opposite the conductive areas (110) and opposite the vias (220), - forming the conductive elements (190) on the conductive areas (180).

8. A method according to any one of the preceding claims, wherein one or more conductive wires (150) are formed on each connection pad (110) of the first chip and / or on each conductive pad (230) covering the vias.

9. Electronic device comprising a substrate (100) in which a first chip (200) is formed, a first face (101) of a second chip (200) being assembled to the first chip by hybrid bonding, the second chip (200) comprising through-vias (220) emerging on a second face (201) of the second chip (200), conductive pads (110) being positioned on the substrate (100) and connected to the first chip, interconnections for the first chip being formed on the connection pads (110), the interconnections comprising from the connection pads (110): conductive wires (150) and conductive elements (160, 190), interconnections for the second chip (200) being formed on the through vias (220), the interconnections comprising conductive elements (160, 190), conductive wires (150) being able to be arranged between the through vias (220) and the conductive elements (160, 190), a layer of insulating material (410) covering the first face (101) of the substrate (100) and the second chip (200) and surrounding the conductive wires (150), the conductive elements (160, 190) being arranged on the layer of insulating material (410).

10. Device according to the preceding claim, wherein the conductive elements (160, 190) are brazing balls (190) or conductive pillars (160).

11. Assembly comprising a device as defined in any one of claims 9 and 10, and an external device (500), such as a printed circuit board (500), comprising connection pads (510), the conductive elements (160, 190) being assembled on the connection pads (510) of the external device (500).

12. A method for manufacturing an assembly as defined in claim 11, the method comprising a step in which the conductive elements (160, 190) are assembled on the connection ranges (510) of the external device (500), for example during a brazing step.

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