Electronic device

Abstract

Electronic Device This description relates to an electronic device (14) comprising a first attack protection circuit, the first circuit comprising a memory (18) configured to contain a first configurable parameter (PPA) corresponding to the acceptable performance loss, the first circuit comprising at least two distinct ground current disturbance modules (22), the first circuit being configured to, when the protection is activated: - generate operating phases; - during each phase, multiply the frequency of a clock signal (CLK) by a first percentage (CLK_PERF); and - during each phase, implement at least a portion of the disturbance modules, the first percentage (CLK_PERF) and the parameters of the disturbance modules being determined at the beginning of the phase such that the acceptable performance loss (PPA) is not exceeded. Figure for the abstract: Fig. 3

Description

Title of the invention: Electronic device technical field

[0001] This description relates generally to electronic devices and more specifically to devices protected against attacks. Previous technique

[0002] Electronic devices routinely use encrypted or hidden data, or more generally, data that the manufacturer or user wishes to keep secret from outsiders. There are numerous methods that can be used by such outsiders, attackers, or hackers. These methods can be non-invasive, for example, side-channel attacks, invasive, or semi-invasive, for example, fault injection attacks.

[0003] There is a need to protect electronic devices against these methods. Summary of the invention

[0004] An embodiment provides an electronic device comprising a first attack protection circuit, the first circuit comprising a memory configured to contain a first configurable parameter corresponding to the acceptable performance loss, the first circuit comprising at least two distinct ground current disturbance modules, the first circuit being configured to, when the protection is activated: generate operating phases; during each phase, multiply the frequency of a clock signal by a first percentage; and during each phase, implement at least a part of the disturbance modules, the first percentage and the parameters of the disturbance modules being determined at the beginning of the phase in such a way that the acceptable performance loss is not exceeded.

[0005] Another embodiment provides a method for controlling an electronic device comprising a first circuit for protection against attacks, the first circuit comprising a memory containing a first configurable parameter corresponding to the acceptable performance loss, the first circuit comprising at least two distinct ground current disturbance modules, the method comprising, when the protection is activated: the generation by the first circuit of the operating phases; during each phase, the multiplication by the first circuit of the frequency of a clock signal by a first percentage; and during each phase, the implementation by the first circuit of at least a portion of the disturbance modules, the first percentage, and the parameters of the modules disturbances being determined at the beginning of the phase in such a way that the acceptable performance loss is not exceeded.

[0006] According to one embodiment, the acceptable performance loss corresponds to the maximum additional time required to perform an action when the protection is activated compared to the time required to perform the same action when the protection is deactivated.

[0007] According to one embodiment, the attacks against which the device is protected include the measurement of the ground current.

[0008] According to one embodiment, the device includes a random number generator.

[0009] According to one embodiment, a second configurable parameter is contained in the memory, the second parameter corresponding to the acceptable overconsumption of power, the device comprising a second circuit for measuring the consumption of the device and comparing it with the second parameter.

[0010] According to one embodiment, the first circuit is configured to randomly choose the first percentage at the beginning of each phase between a value equal to 100% minus the first parameter and a second percentage.

[0011] According to one embodiment, the first circuit is configured to decrease the second percentage if the second circuit detects that the consumption of the device is greater than the second parameter.

[0012] According to one embodiment, the first circuit is configured to disable the protection if the value of 100% minus the second percentage becomes greater than the first parameter.

[0013] According to one embodiment, the duration of the phases is random.

[0014] According to one embodiment, the first circuit is configured so that, at each phase, randomly select the perturbation modules implemented during the phase.

[0015] According to one embodiment, the disturbance modules are divided into first and second categories, the first category comprising disturbances whose implementation leads to a decrease in the performance of the device equal to its rate of occurrence and the second category whose implementation does not lead to a decrease in the performance of the device.

[0016] According to one embodiment, the first circuit is configured to randomly determine, at the beginning of each phase, for each disturbance module implemented during the phase, an occurrence rate.

[0017] According to one embodiment, the first circuit is configured to determine, at the beginning of each phase, randomly and successively for each disturbance module of the first category implemented during the phase, the occurrence rate of said disturbance module between 0% and the subtraction of the sum of the rates of the appearance of the disturbance modules of the first category already determined and of the difference between the parameter CLK_PERF and 100% to the first parameter. Brief description of the drawings

[0018] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0019] [Fig.1] illustrates a type of electronic device attack;

[0020] Figure [Fig. 2] schematically illustrates the operation of one embodiment of a countermeasure against an attack;

[0021] [Fig.3] schematically represents an embodiment of a device protected against attacks;

[0022] [Fig.4] represents in more detail part of the embodiment of [Fig.3];

[0023] [Fig.5] is a chronogram illustrating the operation of a part of the embodiment of [Fig.5];

[0024] [Fig.6] represents the operation of a part of the embodiment of [Fig.5];

[0025] [Fig.7] is a chronogram illustrating the operation of a part of the embodiment of [Fig.5];

[0026] [Fig. 8] represents the operation of a part of the embodiment of [Fig. 5]; and

[0027] [Fig.9] is a timing diagram illustrating the operation of part of the embodiment of [Fig.5]. Description of the implementation methods

[0028] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0029] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0030] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0031] In the following description, when referring to absolute positional qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative positional qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to Orientation qualifiers, such as the terms "horizontal", "vertical", etc., refer to the orientation of the figures unless otherwise specified.

[0032] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0033] The device can, for example, be used in the industrial sector. More Specifically, the device is intended for use in green energy development and infrastructure electrification, such as charging stations and solar power integration. It can also be used in the Internet of Things (IoT) and smart home applications. For example, it is designed for use in the power and energy circuits of equipment that includes components such as 800V or 1200V thyristors, 1200V ultrafast diodes and silicon carbide diodes, transient voltage suppression diodes, and electromagnetic discharge protection. The device can also be used in cloud computing, 5G networks, data centers, and servers. It incorporates, for example, wide-bandgap materials.

[0034] The device is intended, for example, for use in personal electronics, for example, to increase radio frequency content, in 5G connectivity devices, or more generally in connected devices. The device is, for example, a smartphone or part of an Internet of Things network. The device is, for example, connected via 5G, Wi-Fi, or ultra-white band. The device includes, for example, high-speed interfaces, with, for example, advanced filtering and protection against electromagnetic discharge.

[0035] The device is intended, for example, for use in communication equipment, or in computers and peripherals. For example, the device can be used in 5G infrastructure and dedicated data centers. The device includes, for example, silicon carbide diodes, power Schottky transistors, electromagnetic discharge protection, and transient voltage suppression diodes. The device can also be used in satellites, including, for example, integrated passive devices for radio frequency applications.

[0036] Figure 1 illustrates a type of attack on an electronic device. More specifically, Figure 1 represents the ground current Im of an electronic device, for example, an electronic chip, as a function of time t. Ground current is understood to be the current measured at the device's ground. Alternatively, Figure 1 can represent the electromagnetic emissions of the electronic device as a function of time t. Subsequently, the impact of the embodiments is described in relation to the ground current. This impact is equivalent on the electromagnetic emissions of the device.

[0037] During the operation of the electronic device, variations in the ground current can form recognizable patterns. In particular, ground current variation patterns can appear periodically or during specific events in the operation of the electronic device. Such patterns 10 are shown in [Fig. 1], surrounded by a dashed outline. Such patterns appear, for example, during steps involving high power consumption, such as an encryption step, a memory read, or a data transmission step.

[0038] During certain attacks against the device, the attacker seeks to recognize such patterns 10. Once the pattern to be recognized has been determined, the attacker can wait for the occurrence of said pattern and, after a delay D, carry out an attack 12. The attack 12 is, for example, a fault injection attack or a side-channel attack. The attack is, for example, carried out systematically each time the pattern 10 occurs.

[0039] Such a process makes it possible to obtain information on the operation of the device, and in particular on the consumption of the device.

[0040] Figure 2 schematically illustrates the operation of one embodiment of a countermeasure against an attack. More precisely, Figure 2 illustrates part of a device 14. The device 14 includes, for example, a countermeasure according to one embodiment. The countermeasure is implemented at least in part by block 16.

[0041] Block 16 receives three parameters EN, SA, PPA. The parameters SA and PPA are chosen by the manufacturer or the user, preferably by the user. The three parameters are, for example, contained in a memory region of the device 14, for example in a register.

[0042] The first parameter EN corresponds to an activation parameter. Thus, the parameter EN takes a first value to activate the countermeasure and a second value to deactivate the countermeasure. The user can therefore choose whether the countermeasure is activated or deactivated by modifying the value of the parameter EN. The parameter takes, for example, the value corresponding to the periodic activation of the countermeasure.

[0043] The second parameter SA corresponds to the acceptable overconsumption during the implementation of the countermeasure. More precisely, the second parameter SA corresponds to the power consumption value of the device 14 above which the device must consider that too much power is being consumed. Thus, the second parameter SA corresponds to the power value above which the device must reduce the power consumption of the countermeasure.

[0044] The third PPA parameter corresponds to the acceptable performance loss. More precisely, the third PPA parameter corresponds to the additional time required to perform an action when the countermeasure is activated. The PPA parameter corresponds, for example, to a percentage of the time required to perform an action. Thus, if the PPA parameter is, for example, equal to 30%, an action cannot take, when the countermeasure is activated, more than 130% of the time that the action would take in the absence of the countermeasure. By action, we mean an action performed by the device 14, for example, reading from memory, transferring data, performing a logical calculation, encrypting or decrypting data, etc.

[0045] Block 16 is configured to implement random perturbations P, enabling the disruption of the attack described in relation to [Fig. 1]. More specifically, block 16 is configured to randomly modify the ground current Im and to disrupt pattern detection on the current Im according to the parameters EN, SA, and PPA. Thus, block 16 is configured to modify the ground current Im and disrupt pattern detection on the current Im in such a way that the power used does not cause the power consumption of device 14 to exceed the acceptable overconsumption and that the performance loss remains below the acceptable performance loss.

[0046] Figure 3 schematically represents an embodiment of a device protected against attacks. More specifically, Figure 3 represents in more detail device 14 of Figure 2.

[0047] The device 14 includes a memory or register bank 18. The memory 18 is preferably at least partially modifiable by the user of the device. The memory 18 includes the parameters SA, PPA, and EN. The parameters SA, PPA, and EN can be modified, preferably by the user of the device 14.

[0048] The device 14 includes a RAND random number generator 19. The generator 19 is preferably configured to be able to provide several random numbers simultaneously.

[0049] The device 14 includes a clock 21. The clock 21 is configured to provide a clock signal CLK. The clock signal preferably has a variable frequency and a constant amplitude. Preferably, the clock signal CLK has a frequency equal to the value of a parameter CLK_PERF, preferably a percentage, multiplied by a constant frequency value FCLK. Thus, the frequency of the clock signal CLK is lower than the frequency FCLK. The value of the parameter CLK_PERF is less than a parameter CLK_PERF_MAX. The clock signal CLK is used by the circuit generating the countermeasure. The clock signal is preferably used by a part of the device 14 other than the components used for generating the countermeasure. Preferably, the circuits of device 14 performing the functions of the chip are synchronized with the clock signal CLK.

[0050] The device 14 includes an assembly 20 configured to implement disturbances on the ground current. The assembly 20 includes a block 22 configured to implement one or more disturbances of the ground current and a block 24 configured to parameterize said disturbances. Thus, the block 22 includes one or more disturbance implementation modules. More specifically, when the countermeasure is activated, i.e., when the parameter EN has the first value, the assembly 20 generates successive disturbance phases. During each phase, at least one disturbance is implemented by the block 22. Preferably, during each phase, at least one parameter of each disturbance is random.

[0051] The disturbances that can be implemented by block 22 are, for example, divided into two categories.

[0052] A first category of disturbances corresponds to disturbances in which noise is added between two portions of a signal. Thus, the same signal takes longer to be transmitted. Such a disturbance leads to a decrease in the device's performance, but a slight increase in power consumption.

[0053] A second category of disturbances corresponds to disturbances in which noise is added to a portion of the signal. The noise is thus generated simultaneously with the signal. The signal duration is not affected by the noise. Such a disturbance does not lead to a decrease in the device's performance, but does result in an increase in power consumption.

[0054] For example, the first category of disturbances includes the insertion of false instructions into circuits, for example, into logic circuits, the implementation of false memory accesses, and the modification of the clock signal frequency. For example, the second category of disturbances includes the addition of noise to voltage regulators and the injection of random current into the ground current. Another type of disturbance corresponds to the generation of electromagnetic noise, which can be of the first or second category.

[0055] In one embodiment, the duration of the phases is constant and fixed, for example by the manufacturer or the user. In a preferred embodiment, the duration of the phases is random. Thus, at the beginning of each phase, the duration of the following phase is determined from a random number Tl generated by the generator 19. Preferably, the value of the phase duration is then equal to Tl times a time step, for example, equal to Tl times the period of the clock signal CLK, for example, equal to Tl times the period corresponding to the frequency FCLK. Preferably, the random value Tl is chosen from a range determined by parameters T_MIN and T_MAX.

[0056] The T_MIN and T_MAX parameters are preferably controlled by register 18. For example, the T_MIN and T_MAX parameters are fixed by the manufacturer and cannot be changed once fixed. Alternatively, the T_MIN and T_MAX parameters can be changed by the user.

[0057] Once the duration of the phase is determined, assembly 20 determines which perturbations to implement from among the possible perturbations that can be implemented by block 22. In one embodiment, all the possible perturbations are implemented during each phase. In another embodiment, a constant number of perturbations are implemented, the perturbations implemented being chosen randomly, for example, using a random number generated by generator 19. In yet another embodiment, both the number of perturbations implemented and the choice of perturbations are random, for example, based on one or more random numbers generated by generator 19.

[0058] For example, register 18 includes activation parameters EN1, EN2, ..., Enp. Each activation parameter corresponds to a disturbance. The value p thus corresponds to the number of possible disturbances, each disturbance being able to be activated or deactivated depending on the value of the corresponding activation parameter. Thus, when the disturbances to be implemented are chosen, the activation parameters take the values ​​corresponding to the activated or deactivated state of the disturbance.

[0059] The perturbation configurations, for example the AMP amplitude of each perturbation and the OCC occurrence rate of each occurrence, are chosen, for example, according to the SA and PPA parameters. By occurrence rate, we mean the percentage of the time required to perform an action during which the perturbation is implemented. For a perturbation of the first category, the occurrence rate corresponds to the percentage of the time required to perform an action plus the presence of the perturbation. Thus, if the occurrence rate of the first-category perturbation is 4%, an action that is performed in 100% of a time T in the absence of the perturbation will then be performed in 104% of the time T.

[0060] The device 14 includes a circuit 26 configured to compare the power consumption of assembly 20 with the overconsumption parameter SA. Thus, when the consumption of assembly 22 exceeds the SA parameter, an error signal ER is provided to assembly 20. The disturbances implemented during the following phase are then adapted to reduce consumption or to reduce the risk of overconsumption.

[0061] Preferably, during each phase, the disturbances are synchronized to the CLK clock signal, the frequency of which is preferably random. At the beginning of each phase, the CLK_PERF parameter is thus determined randomly, for example at using a random number generated by generator 19. The parameter CLK_PERF corresponds, for example, to a percentage. The frequency of the clock signal CLK thus corresponds, for example, to this percentage multiplied by the constant frequency FCLK. For example, the value of the parameter CLK_PERF is chosen below the value CLK_PERF_MAX, which corresponds to the maximum value that the parameter CLK_PERF can take. The values ​​CLK_PERF and CLK_PERF_MAX are preferably contained in register 18. The value of the parameter CLK_PERF_MAX can, for example, be modified by assembly 20, for example, in response to the detection of overconsumption by circuit 26.

[0062] The operation of assembly 20 will be described in more detail later.

[0063] Figure 4 shows in more detail a part of the embodiment of Figure 3. More specifically, Figure 4 shows in more detail block 24.

[0064] Block 24 includes a phase generation block 28. Block 28 is configured to receive the parameters T_MIN and T_MAX, as well as random numbers RAND generated by generator 19 of [Fig. 3]. Block 28 also preferably receives the activation parameter EN and the clock signal CLK.

[0065] The operation of block 28 will be described in more detail in relation to [Fig.5].

[0066] Block 24 includes an overconsumption management block 30. Block 30 is configured to receive the CLK_PERF and CLK_PERF_MAX parameters as well as the ER error signal indicating the detection of overconsumption. Block 30 also preferably receives the EN activation parameter and the CLK clock signal.

[0067] The operation of block 30 will be described in more detail in relation to figures 6 and 7.

[0068] Block 24 includes a performance loss management block 32. Block 32 is configured to receive the CLK_PERF and PPA parameters as well as the EN1, EN2, ..., Enp activation signals for disturbances. Block 32 also preferably receives the EN activation parameter and the CLK clock signal.

[0069] The operation of block 32 will be described in more detail in relation to figures 8 and 9.

[0070] Figure 5 is a timing diagram illustrating the operation of a part of the embodiment of Figure 4. More specifically, Figure 5 is a timing diagram illustrating the operation of phase generation block 28. More specifically, Figure 5 illustrates the example in which the duration of the phases is random.

[0071] Figure 5 illustrates the activation, operation, and deactivation of the countermeasure. Thus, at time t1, the parameter EN takes a high value indicating the activation of the countermeasure. At time t2, the parameter EN takes a low value indicating the deactivation of the countermeasure. The countermeasure is therefore active between times t1 and t2.

[0072] Between the activation of the countermeasure and the first rising edge of the clock signal CLK, occurring at time t3, block 28 receives the values ​​of the parameters T_MIN and T_MAX. In the example in [Fig. 5], the parameters T_MIN and T_MAX have values ​​of 10 and 38, respectively.

[0073] At time t3, block 28 receives a random RAND value, preferably generated by generator 19. The RAND value is between the parameters T_MIN and T_MAX. In the example in [Fig. 5], the RAND value generated at time t3 is equal to 23.

[0074] A PI phase thus begins at time t3. The duration of the PI phase is equal to the product of the RAND value and a time step. Preferably, the time step is equal to the period of the clock signal. Thus, the PI phase has a duration equal to 23 cycles of the clock signal.

[0075] Block 28 preferably includes a CNT counter for determining the end of the PL phase. Thus, when the counter counts 23 cycles of the clock signal, the PI phase is complete. The PI phase thus ends at time t4.

[0076] At time t5, following time t4 and corresponding to the first rising edge after time t4, a phase P2 begins and a new random number RAND is generated between the parameters T_MIN and T_MAX. In the example in [Fig. 5], the RAND value of phase P2 is 13. After a duration equal to 13 times the period of the clock signal, phase P2 is complete. Phase P2 thus ends at time t6.

[0077] Similarly, at time t7, following time t6 and corresponding to the first rising edge after time t6, a phase P3 begins and a new random number RAND is generated between the parameters T_MIN and T_MAX. In the example in [Fig. 5], the RAND value of phase P3 is 32. After a duration equal to 32 times the period of the clock signal, phase P3 is complete. Phase P3 thus ends at time t8.

[0078] Time t8 is located after time t2. At the rising edge following time t8, the EN parameter has a low value indicating that the countermeasure is deactivated. Thus, the block does not generate a phase after phase P3.

[0079] More generally, when the EN parameter has the countermeasure activation value, block 28 generates phases of random durations by generating a random number at the beginning of each phase and using a counter to determine the end of the phase.

[0080] According to one embodiment, the clock signal CLK corresponds to the clock signal having a frequency modified by the parameter CLK_PERF. According to another embodiment, the clock signal used to determine the phase duration corresponds to the clock signal having the fixed frequency FCLK.

[0081] Figure 6 illustrates the operation of a part of the embodiment of the [Fig. 5]. More specifically, [Fig. 6] illustrates the operation of block 30 for managing overconsumption. [Fig. 6] represents an algorithm illustrating the operation of block 30.

[0082] For each phase P, block 30 determines (block 34) the parameter CLK_PERF. The parameter CLK_PERF is chosen randomly between the value of the parameter CLK_PERF_MAX and a value equal to the subtraction of the parameter PPA, expressed as a percentage, from 100%. Thus, the parameter CLK_PERF is chosen randomly between the value of the parameter CLK_PERF_MAX and a value equal to 100% - PPA. The parameter CLK_PERF corresponds to the multiplier applied to the clock signal frequency. Thus, if the value of the parameter CLK_PERF is equal to 80%, the frequency of the clock signal used by assembly 20 and, for example, at least part of device 14, is equal to 80% of the clock signal CLK.

[0083] During phase P, block 30 waits (block 36 "ER?") for the arrival of an error signal generated by circuit 26 of device 26. In other words, block 30 waits for the appearance of overconsumption, measured by circuit 26 and indicated by the error signal ER.

[0084] If no overconsumption is detected (output N of block 36) before the end of phase P, block 30 does nothing more and the next phase begins.

[0085] When overconsumption is detected (output Y of block 36), block 30 determines (block 38) "100%-CLK_PERF_MAX-K <PPA") s'il est possible de diminuer le paramètre CLK_PERF_MAX d'une valeur de préférence constante K tout en respectant le paramètre de perte de performance acceptable. Autrement dit, le bloc 30 détermine si la soustraction du paramètre CLK_PERF_MAX et de la valeur K à cent pourcent est inférieur ou égale au paramètre PPA, autrement dit, si la valeur de 100%-CLK_PERF_MAX-K est inférieure ou égale au paramètre PPA. La valeur K est de préférence un pourcentage. La valeur K est par exemple égale à 10%. La valeur K est par exemple déterminée par le fabricant ou par l'utilisateur. La valeur K est par exemple un paramètre modifiable contenu dans le registre 18.

[0086] If it is not possible to decrease the CLK_PERF_MAX parameter (output N of block 38), the countermeasure is, for example, deactivated. In other words, the EN activation parameter takes the value corresponding to the deactivation of the countermeasure (block 40 "EN=ENb"). The countermeasure can then be reactivated, for example, after parameters have been adjusted.

[0087] If it is possible to decrease the parameter CLK_PERF_MAX (output Y of block 38), the value of the parameter CLK_PERF_MAX is decreased by the value K (block 42 "CLK_PERF_MAX-K"). The block then waits for the next phase P.

[0088] Decreasing the clock signal frequency results in decreased performance, i.e., an increase in the time required to perform a The same action, but also results in a decrease in power consumption. Thus, decreasing the CLK_PERF_MAX parameter leads to a decrease in the maximum possible clock signal frequency and a reduction in the risk of overconsumption.

[0089] Figure 7 is a timing diagram illustrating the operation of part of the mode of realization of [Fig.5]. More precisely, [Fig.7] represents: - the P phases; - consumption C; - the ER error signal; - the CLK_PERF_MAX parameter; and - the CLK_PERF parameter.

[0090] At time t1O, a PI phase begins. The parameter CLK_PERF_MAX is, in the example of [Fig. 7], equal to 100%. At time t1O, the parameter CLK_PERF is chosen between CLK_PERF_MAX and 100%-PPA. For example, in the example of [Fig. 7], the parameter PPA is equal to 40%. Thus, the parameter CLK_PERF is chosen between 60% and 100%. In the example of [Fig. 7], the value of the parameter CLK_PERF is equal to 80% during the PL phase.

[0091] The PI phase ends at time tl 1. The circuit 26 did not detect any overconsumption during the PI phase, meaning that the consumption C did not exceed the value of the parameter SA. Thus, the ER signal did not take the high value shown in the example in [Fig. 7], which represents the detection of overconsumption. The value of the parameter CLK_PERF_MAX remains unchanged.

[0092] At time tl2, a phase P2 begins. The parameter CLK_PERF_MAX is still equal to 100%. At time tl2, the parameter CLK_PERF is still chosen between CLK_PERF_MAX and 100%-PPA, that is, still between 60% and 100%. In the example in [Fig. 7], the value of the parameter CLK_PERF is equal to 70% during phase P2.

[0093] At time t13, the consumption C exceeds the value of the parameter SA. The ER signal thus takes the high value indicating this exceedance. The value of the parameter CLK_PERF_MAX decreases by the value K, here equal to 10%. The parameter CLK_PERF_MAX is equal to 90% after the ER signal has been processed. The parameter CLK_PERF_MAX remains equal to 90% during phase P2. The value of the parameter CLK_PERF is not modified during a phase. Phase P2 ends at time 114.

[0094] At time tl5, a P3 phase begins. The parameter CLK_PERF_MAX is now equal to 90%. At time tl5, the parameter CLK_PERF is chosen between CLK_PERF_MAX and 100%-PPA, that is, still between 60% and 90%. In In the example of [Fig.7], the value of the parameter CLK_PERF is equal to 90% during phase P3.

[0095] At time tl6, the consumption C exceeds the value of the parameter SA. The ER signal thus takes the high value indicating this exceedance. The value of the parameter CLK_PERF_MAX decreases further by the value K, here equal to 10%. The parameter CLK_PERF_MAX is equal to 80% after the ER signal management. The parameter CLK_PERF_MAX becomes equal to 80% during phase P3. The value of the parameter CLK_PERF is not modified during a phase. Phase P3 ends at time 117.

[0096] Preferably, if overconsumption is detected during a phase P, the value of the parameter CLK_PERF_MAX is modified before the value of the parameter CLK_PERF of the next phase is determined.

[0097] Figure 8 illustrates the operation of a part of the embodiment of Figure 5. More specifically, Figure 8 illustrates the operation of block 32 for managing performance loss. Figure 8 represents an algorithm illustrating the operation of block 32.

[0098] For each phase P, block 32 determines (block 34) the parameter CLK_PERF. This is the same step as that described in relation to [Fig. 6]. This step is performed only once for each phase, and the value of the parameter CLK_PERF is used for the management of blocks 30 and 32. In other words, the parameter CLK_PERF used in the algorithms of Figures 6 and 8 is the same parameter with the same value.

[0099] For each phase P, block 32 then determines (block 44 "CM_RAND") a list of perturbations to be implemented. The perturbations are chosen from the possible perturbations in block 22 of [Fig. 3]. In one embodiment, the number of perturbations chosen is fixed. In another embodiment, the number of perturbations chosen is variable, for example, random. The perturbations are, for example, chosen randomly.

[0100] For each selected disturbance (block 46 "CM"), block 32 determines (block 48 "CM=C1") whether the disturbance belongs to the first category defined in relation to [Fig. 3]. In other words, block 32 determines whether implementing the disturbance will result in a decrease in performance.

[0101] If the disturbance is not of the first category (output N of block 48), block 32 determines the parameters of the disturbance. For example, block 32 determines the occurrence rate of the disturbance and the amplitude of the disturbance. In one embodiment, the parameters of these disturbances are constant from one phase to another. In another embodiment, the parameters of these disturbances are random, for example, obtained from random numbers generated by generator 19.

[0102] If the disturbance is of the first category (output Y of block 48), that is to say if the implementation of this disturbance leads to a decrease in the performance of the device, block 32 determines the parameters of the disturbance so that the total performance loss remains less than the maximum acceptable performance loss, that is to say less than the PPA parameter.

[0103] Thus, for each disturbance in the first category, block 32 calculates the acceptable performance loss based on the performance losses due to the value of the parameter CLK_PERF and the performance losses caused by disturbances in the first category already processed. Once the acceptable performance loss is determined, block 32 determines the parameters of the disturbance, in particular the occurrence rate of the disturbance, preferably randomly, such that the performance loss of said disturbance is less than the calculated acceptable performance loss. Block 32 then proceeds to the next disturbance, such that the parameters of all the disturbances selected in the step of block 44 are determined.

[0104] If the PPA parameter is reached before all first category disturbances are parameterized, said remaining disturbances are preferably not implemented.

[0105] Figure 9 is a timing diagram illustrating the operation of part of the mode of the realization of [Fig. 5]. In the example of [Fig. 9], block 32 selected three disturbances CM1, CM2, and CM3 from the first category. Block 32 may also have selected disturbances from the second category. More precisely, [Fig. 9] represents: - the P phases; - the CLK_PERF parameter; - the OCC_CM1 occurrence rate of the CM1 disturbance; - the occurrence rate 0CC_CM2 of the CM2 disturbance; - the occurrence rate 0CC_CM3 of the CM3 disturbance; and - the total performance loss P_LOSS.

[0106] During the PI phase of this example, the CLK_PERF parameter is equal to 80%. Therefore, decreasing the clock signal frequency results in a performance loss of 20%. In other words, the same action of device 14 synchronized to the clock signal takes 20% longer than without the countermeasure. The acceptable performance loss parameter (PPA) is 30% in this example. Thus, it is still possible to reduce performance by 10%.

[0107] Block 32 thus determines the occurrence rate of perturbation CM1. This occurrence rate is chosen, preferably randomly, between 0% and 10%. In phase 1 of the example in [Fig. 9], this occurrence rate is equal to 4%.

[0108] The total performance loss caused by the decrease in clock signal frequency and the CM1 disturbance is 24%. Thus, it is still possible to reduce performance by 6%. Block 32 therefore determines the occurrence rate of the CM2 disturbance. This occurrence rate is chosen, preferably randomly, between 0% and 6%. In phase 1 of the example in [Fig. 9], this occurrence rate is equal to 2%.

[0109] The total performance loss caused by the decrease in clock signal frequency and the CM1 and CM2 disturbances is 26%. Thus, it is still possible to reduce performance by 4%. Block 32 therefore determines the occurrence rate of the CM4 disturbance. This occurrence rate is chosen, preferably randomly, between 0% and 4%. In phase 1 of the example in [Fig. 9], this occurrence rate is equal to 1%.

[0110] The total P_LOSS loss of device performance is therefore 27% in the PL phase

[0111] Similarly, in phase P2, the parameter CLK_PERF is equal to 90%. Thus, the performance loss caused by the decrease in the clock signal frequency is 10%. Therefore, 20% remains that can be attributed to disturbances CM1, CM2, and CM3 without exceeding the PPA parameter. Block 32 successively determines the values ​​of the occurrence rates OCC_CM1, OCC_CM2, and OCC_CM3. In the example of [Fig. 9], the occurrence rates OCC_CM1, OCC_CM2, and OCC_CM3 have the values ​​2%, 10%, and 8%, respectively. The total performance loss P_LOSS of the device is therefore 30% in phase P2.

[0112] In phase P3, the parameter CLK_PERF is equal to 100%. Thus, the performance loss caused by the decrease in the clock signal frequency is 0%. Therefore, 30% remains that can be attributed to disturbances CM1, CM2, and CM3 without exceeding the PPA parameter. Block 32 successively determines the values ​​of the occurrence rates OCC_CM1, OCC_CM2, and OCC_CM3. In the example of [Fig. 9], the occurrence rates OCC_CM1, OCC_CM2, and OCC_CM3 have the values ​​9%, 10%, and 3%. The total performance loss P_LOSS of the device is therefore 22% in phase P3.

[0113] More generally, the occurrence rate 0CC_CMn of a disturbance CMn, for n greater than 1, is chosen randomly between 0% and the subtraction of the sum of the occurrence rates of the disturbances Cm, where m is less than n, and the difference between the parameter CLK_PERF and the value of the parameter PPA. In other words, the occurrence rate 0CC_CMn of a disturbance CMn is chosen to follow the following equation: 0< OCCCMn <PPA-(lQ0%-CLKJPERF]-

[0114] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0115] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. Electronic device (14) comprising a first attack protection circuit, the first circuit comprising a memory (18) configured to contain a first configurable parameter (PPA) corresponding to the acceptable performance loss, the first circuit comprising at least two distinct ground current disturbance modules (22), the first circuit being configured to, when the protection is activated: - generate operating phases (P, PI, P2, P3); - during each phase, multiply the frequency of a clock signal (CLK) by a first percentage (CLK_PERF); and - during each phase, implement at least a portion of the disturbance modules, the first percentage (CLK_PERF) and the parameters of the disturbance modules being determined at the beginning of the phase such that the acceptable performance loss (PPA) is not exceeded.

2. Device according to claim 1, wherein the acceptable performance loss corresponds to the maximum additional time required to perform an action when the protection is activated compared to the time required to perform the same action when the protection is deactivated.

3. Device according to claim 1 or 2, wherein the attacks against which the device is protected include the measurement of ground current.

4. Device according to any one of claims 1 to 3, wherein the device comprises a random number generator (19).

5. Device according to any one of claims 1 to 4, wherein a second configurable parameter (SA) is contained in the memory (18), the second parameter (SA) corresponding to the acceptable overconsumption of power, the device comprising a second circuit (26) for measuring the consumption of the device and comparing it with the second parameter (26).

6. Device according to any one of claims 1 to 5, wherein the first circuit is configured to randomly choose the first percentage (CLK_PERF) at the beginning of each phase between a value equal to 100% less the first parameter and a second percentage (CLK_PERF_MAX).

7. Device according to claim 6, wherein the first circuit is configured to decrease the second percentage (CLK_PERF_MAX) if the second circuit (26) detects that the consumption of the device is greater than the second parameter (PPA).

8. Device according to claim 7, wherein the first circuit is configured to disable the protection if the value of 100% less the second percentage (CLK_PERF_MAX) becomes greater than the first parameter (PPA).

9. Device according to any one of claims 1 to 8, wherein the duration of the phases is random.

10. Device according to any one of claims 1 to 9, wherein the first circuit is configured to, at each phase, randomly select the disturbance modules implemented during the phase.

11. Device according to any one of claims 1 to 10, wherein the disturbance modules are divided into first and second categories, the first category comprising disturbances whose implementation results in a decrease in the performance of the device equal to its rate of occurrence and the second category whose implementation does not result in a decrease in the performance of the device.

12. Device according to any one of claims 1 to 11, wherein the first circuit is configured to randomly determine, at the beginning of each phase, for each disturbance module implemented during the phase, an occurrence rate.

13. Device according to claims 11 and 12, wherein the first circuit is configured to determine, at the beginning of each phase, randomly and successively for each first category disturbance module implemented during the phase, the occurrence rate of said disturbance module between 0% and the subtraction of the sum of the occurrence rates of the first category disturbance modules already determined and the difference between the parameter CLK_PERF and 100% to the first parameter (PPA).

14. A method for controlling an electronic device (14) comprising a first circuit for protection against attacks, the first circuit comprising a memory (18) in which is contained a first configurable parameter (PPA) corresponding to the loss of acceptable performance, the first circuit comprising at least two separate disturbance modules (22) of the ground current, the method comprising, when the protection is activated: - the generation by the first circuit of the operating phases (P, PI, P2, P3); - during each phase, the multiplication by the first circuit of the frequency of a clock signal (CLK) by a first percentage (CLK_PERF); and - during each phase, the implementation by the first circuit of at least a part of the disturbance modules, the first percentage (CLK_PERF) and the parameters of the disturbance modules being determined at the beginning of the phase in such a way that the acceptable performance loss (PPA) is not exceeded.

15. Control method according to claim 14 applied to an electronic device according to any one of claims 1 to 13.

Images