Method for manufacturing a microelectronic device
The described manufacturing process addresses the challenge of germanium protrusion in microelectronic devices by using selective epitaxy and controlled encapsulation followed by CMP, ensuring uniform planarization and improved optical performance.
Patent Information
- Authority / Receiving Office
- FR · FR
- Patent Type
- Applications
- Current Assignee / Owner
- COMMISSARIAT A LENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
- Filing Date
- 2024-12-03
- Publication Date
- 2026-06-05
AI Technical Summary
Existing methods for fabricating microelectronic devices, such as photodiodes, face challenges in achieving uniformity and preventing germanium protrusion from cavities during epitaxy, leading to planarization defects and reduced optical properties.
A manufacturing process involving selective epitaxy followed by encapsulation with a controlled thickness of an encapsulation layer and chemical mechanical polishing (CMP) to remove protruding epitaxial material, ensuring uniform planarization across varying cavity dimensions.
The process achieves uniform planarization, minimizes defects, and enhances optical performance by maintaining the integrity of the epitaxial material, particularly in photodiodes, by reducing non-uniformity and preventing germanium detachment.
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Abstract
Description
Title of the invention: Method for manufacturing a microelectronic device technical field
[0001] This description relates generally to the field of microelectronics, and more particularly to the fabrication of microelectronic devices requiring the implementation of a localized selective epitaxy step followed by a planarization step.
[0002] The invention is particularly interesting for the realization of photodiodes, electro-absorption modulators or even Germanium, GeSn or SiGe lasers on Silicon. Previous technique
[0003] To fabricate certain microelectronic devices, for example photodiodes, it is sometimes necessary to selectively grow germanium by epitaxy in a cavity whose base is a silicon crystal. To do this, a mask made of a material on which germanium does not grow is deposited onto a silicon substrate. The mask is, for example, made of SiO2. Growth windows, called 'seed windows', are formed in the mask by etching to locally expose the silicon surface. During the etching step, the silicon can also be etched to create cavities in the substrate.
[0004] The growth of germanium then takes place in cavities. The sides of the cavities comprise SiO2 and Si in the case where the substrate has been etched.
[0005] To obtain photodiodes with optimized operation, the cavity formed must be filled but the germanium must not protrude from the cavity.
[0006] There are three methods for carrying out a non-overflowing silicon epitaxy.
[0007] First, as described in reference [1], epitaxy is flush-mounted. However, this method is not feasible when the substrate includes cavities of different sizes and / or depths, because the growth rate varies depending on the cavity sizes. To remove germanium islands protruding from the surface of the silicon substrate, a peroxide and water solution can be used to smooth the surface of the photodiode as described in reference [2].
[0008] A second method consists of performing an overhanging epitaxy of the cavities and then implementing a planarization step, for example by chemical mechano-polishing (CMP), to remove the protruding portion of the germanium. For the same device comprising different cavity sizes, the germanium can protrude from a height of 300 nm to more than 1 pm. However, during the step of planarisation, the mechanical effect exerted on these structures generates a detachment of germanium, which creates planarisation defects and the epitaxial material can be deteriorated [3, 4].
[0009] A final method consists of depositing, after selective epitaxy, a thin layer of another material (e.g., SiO2 or SiN) to protect the germanium during the CMP step and prevent its alteration. This method also allows for filling cavity edges when the epitaxy is not completely overflowing [5]. However, the cavity is not filled solely with germanium, which can reduce the optical properties of the device. Summary of the invention
[0010] There is a need for a manufacturing process for a microelectronic device, allowing for a good quality epitaxial material in a cavity.
[0011] This goal is achieved by a method for manufacturing a microelectronic device, for example a photonic device, in particular a photodiode, comprising the following steps: a) provide a substrate comprising a cavity formed from a first principal face of the substrate, the bottom of the cavity being made of a first material, the first principal face of the substrate being made of a second material, b) to carry out selective epitaxy of a third material in the cavity of the substrate, until the epitaxially grown material fills the cavity and overflows the cavity by a thickness known as the overflow thickness, thereby obtaining an epitaxially grown structure, c) to deposit an encapsulation layer of a fourth material on the substrate and on the epitaxially grown structure, d) perform a CMP thinning step to remove the encapsulation layer and the portion of the epitaxial structure protruding from the first principal face of the substrate, the thickness of the deposited encapsulation layer being between 20 and 200% of the overflow thickness.
[0012] According to a particular embodiment, the thickness of the encapsulation layer is between 20 and 100%, preferably between 20 and 50% of the overflow thickness.
[0013] According to a particular embodiment, the bottom of the cavities is made of a semiconductor material, preferably single-crystal, and even more preferably single-crystal silicon.
[0014] According to a particular embodiment, the encapsulation layer is made of silicon oxide, the encapsulation layer preferably being deposited by PECVD.
[0015] According to a particular embodiment, the second material is silicon oxide.
[0016] According to a particular embodiment, the third material is a semiconductor material, preferably germanium or one of its alloys, for example GeSn or SiGe.
[0017] According to a particular embodiment, the substrate comprises several cavities of different or identical dimensions.
[0018] According to a particular embodiment, the cavities have different dimensions and step b) is carried out until the epitaxial material overflows from all the cavities.
[0019] According to a particular embodiment, a stop layer, for example in SiN, is disposed in the substrate and the thinning step is stopped when the stop layer is reached.
[0020] This goal is also achieved by a microelectronic device, for example a photonic device, comprising a substrate, a cavity being formed from a first main face of the substrate, the bottom of the cavity being in a first material, the first main face of the substrate being in a second material, the cavity being completely filled by a third epitaxial semiconductor material.
[0021] According to a particular embodiment, the bottom of the cavity is made of single-crystal silicon, the second material is made of silicon oxide and the third epitaxial material is made of SiGe, GeSn or Ge.
[0022] According to a particular embodiment, the device is a photodiode. Brief description of the drawings
[0023] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:
[0024] [Fig.1A], [Fig.1B], [Fig.1C] and [Fig.1D] schematically represent different stages of a manufacturing process for a microelectronic device, according to a particular embodiment of the invention;
[0025] [Fig.2A], [Fig.2B], [Fig.2C] and [Fig.2D] schematically represent different stages of a manufacturing process for a microelectronic device, according to another particular embodiment of the invention;
[0026] [Fig.3A], [Fig.3B], [Fig.3C] and [Fig.3D] schematically represent different stages of a manufacturing process for a photonic device, according to another particular embodiment of the invention;
[0027] [Fig.4] represents, schematically and in cross-section, a photonic device, according to another particular embodiment of the invention;
[0028] [Fig.5A], [Fig.5B] and [Fig.5C] are images obtained by scanning electron microscopy (SEM) of a modulator during different stages of its manufacturing process, respectively, after selective epitaxy of SiGe, after encapsulation with SiO2 and after thinning by CMP of the SiGe and the SiO2 encapsulation layer, according to another particular embodiment of the invention;
[0029] [Fig.6] is a picture obtained by SEM of a modulator after thinning by CMP of SiGe, according to an example given for comparison;
[0030] [Fig.7A], [Fig.7B] and [Fig.7C] are images obtained by SEM of different photodiodes on 300 mm substrates after CMP thinning of the SiGe and the SiO2 encapsulation layer, according to another particular embodiment of the invention;
[0031] [Fig.8A] and [Fig.8B] are images obtained by SEM of different photodiodes on 200 mm substrates after CMP thinning of the SiGe and the SiO2 encapsulation layer, according to another particular embodiment of the invention;
[0032] [Fig.9] is a picture obtained by SEM of a photodiode on a 300 mm substrate after CMP thinning of SiGe, according to an example given for comparison.
[0033] The different elements are not necessarily represented at a uniform scale to make the figures more legible. Description of the implementation methods
[0034] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.
[0035] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.
[0036] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.
[0037] In the following description, when referring to absolute positional qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative positional qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to Orientation qualifiers, such as the terms "horizontal", "vertical", etc., refer to the orientation of the figures unless otherwise specified.
[0038] Unless otherwise specified, the expressions "approximately", "about", "Significantly" and "on the order of" mean at 10%, preferably at 5%.
[0039] By included between X and Y, it is meant that the bounds X and Y are included.
[0040] In the figures, only one cavity is shown in the substrate for better readability, but several cavities can be formed in the same substrate.
[0041] The process that will be described below is particularly interesting for manufacturing a microelectronic device, preferably a photonic device, in particular a photodiode. While the description specifically mentions a method for manufacturing a photodiode, the process could be used to manufacture other devices, for example, lasers, particularly those made of germanium or SiGe integrated on silicon, or electro-absorption modulators.
[0042] We will now describe the manufacturing process of the device with reference to Figures IA in 1D, Figures 2A in 2D, Figures 3A in 3D and [Fig. 4]. The process comprises at least the following steps: a) provide a substrate 100 comprising a cavity 150 formed from a first main face 101 of the substrate 100, the bottom 151 of the cavity 150 being made of a first material, the first face 101 of the substrate 100 being made of a second material (figures IA, 2A, 3B), b) to carry out a selective epitaxy of a third material in the cavity 150 of the substrate 100, until the epitaxially formed material fills the cavity 150 and overflows from the cavity 150, thereby obtaining an epitaxially formed structure 200 comprising a first part 201 filling the cavity 150 and a second part 202 locally covering the first main face 101 of the substrate 100 at the periphery of the cavity 150 and overflowing from the first main face 101 of the substrate 100 by a thickness called the overflow (figures IB, 2B, 3C), c) deposit an encapsulation layer 300 in a fourth material on the substrate 100 and on the epitaxial structure 200, the thickness of the deposited encapsulation layer 300 being between 20 and 200%, preferably between 20 and 100%, and even more preferably between 20 and 50% (for example 30%), of the overflow thickness (figures IC, 2C, 3D), d) perform a chemical mechanical polishing (CMP) thinning step to remove the portion 202 of the epitaxial structure 200 protruding from the first principal face 101 of the substrate 100 (Figures 1D, 2D, 3D).
[0043] The process incorporates both a step of encapsulating a structure Overflowing epitaxial 200 and a planarization step. This process is particularly advantageous.
[0044] With such a process, it is possible to fill cavities 150 having dimensions ranging from a few hundred nm to several tens of micrometers, since if the epitaxial material overflows from the cavities, it is easily removed, unlike some prior art processes.
[0045] The planarization step thins both the encapsulation layer 300 and the overhanging epitaxial layer 200 at the same rate. The thickness of the encapsulation layer 300 is preferably less than the thickness of the step to be planarized. It is not necessary to deposit a thickness greater than that of the step to be planarized because it is not necessary to be already flat at the start of the CMP (Cold Molding Process). This reduces the non-uniformity of the surface after planarization (a parameter dependent on the thicknesses to be consumed). In the process, the non-uniformity that can result from the CMP process is minimized since, even when depositing an encapsulation layer 300 with a thickness half that of the step to be planarized, both materials are consumed at the same rate.
[0046] By reducing the deposited thickness, the uniformity of the CMP step is improved. This allows the thickness of the epitaxial material to be reduced closer to the substrate.
[0047] During the fabrication of a photodiode, the germanium growth, which protrudes significantly from the cavity, is planarized as close as possible to the waveguide height (approximately 40 nm). The risk of detachment is eliminated by encapsulating the epitaxially grown material. Thinning by CMP remains controlled because the encapsulation thickness is much smaller than the protrusion of the epitaxially grown material. This improves the component's performance.
[0048] Finally, in the case of a photodiode, there is no faceting of the third material which would be detrimental to its operation, in particular by causing significant losses of the optical signal by reflections on the facets.
[0049] We will now describe in more detail the different stages of the process.
[0050] The substrate 100 supplied in step a) comprises a first main face 101 and a second main face 102. At least one cavity 150 is formed from the first main face 101 of the substrate 100. By at least one, it is understood that one cavity 150 or several cavities 150 can be formed from the first main face 101.
[0051] The cavities 150 may have identical or different dimensions. The dimensions of the cavities 150 are, for example, between a few hundred nanometers and several tens of micrometers.
[0052] Subsequently, we will describe more particularly a cavity 150, but what is described for said cavity can be applied to other cavities which would be in the substrate 100.
[0053] The cavity 150 comprises a bottom 151 and a side wall 152. It is a hole opening onto the first main face 101 of the substrate 100.
[0054] The bottom 151 of the cavity 150 is made of a first material configured to allow the initiation of the growth of the third material by epitaxy. It acts as a growth layer ('seed layer'). The first material is preferably a semiconductor material, more preferably a crystalline semiconductor, and more particularly a single-crystal semiconductor. For example, it is single-crystal silicon.
[0055] The first principal face 101 of the substrate 100 is made of a second material that does not allow the growth of the third material by epitaxy. During step b), the epitaxially grown material does not grow from the first face 101 of the substrate 100. The epitaxy of the third material is thus selective.
[0056] Preferably, at least the upper part of the lateral wall 152 (or flank) of the cavity 150 is made of a second material, to prevent the growth of epitaxial material from the top of the cavity 150. The lower part of the lateral wall 151 can be made of the first material. This will promote the initiation of growth of epitaxial material from the bottom of the cavity 150.
[0057] By upper part of cavity 150, we mean the part of cavity 150 closest to the first face 101. By lower part of cavity 150, we mean the part of cavity 150 closest to the bottom 151 of cavity 150.
[0058] The upper part can be at least 40 nm thick.
[0059] Alternatively, the entire side wall 152 is made of first material or second material.
[0060] For example, in the case of selective epitaxy in germanium or SiGe, the bottom 151 of the cavity 150 is made of silicon and the first principal face 101 of the substrate 100 is made of silicon oxide. Growth is selective on silicon.
[0061] According to a particular embodiment, for example shown in Figures 2A to 2D, 3A to 3D and 4, the substrate 100 can be formed of a SOI (Silicon on Insulator) substrate covered with a passivation layer 120 of oxide, that is to say, the substrate 100 comprises successively a silicon support substrate 140, a silicon oxide layer 130 (BOX), a single-crystal silicon layer 110 and the passivation layer 120. The cavity 150 formed in this substrate 100 passes through the passivation layer 120 and opens into the silicon layer 110. Growth thus starts on a crystalline Si seed. The passivation layer 120 prevents the growth of germanium on the first principal face 101 of the substrate 100 (where Ge should not grow). The upper part of the flanks 152 of the cavity 150 is made of silicon oxide to prevent the growth of Ge from this part of the flanks. The cavities 150 can be formed by photolithography.
[0062] For certain applications, a waveguide can be formed in the substrate. More specifically, the waveguide is formed in layer 110 of the SOI.
[0063] According to one embodiment, the substrate is formed of several layers. A difference in refractive index between the core and the cladding allows a waveguide to be formed.
[0064] As shown in Figures 3A to 3D and 4, the silicon layer 110 can be structured and / or doped. In particular, the cavity 150 can be positioned between a first n-doped silicon portion 112 and a second p-doped silicon portion 113. The photodiode is a silicon-germanium-silicon double heterojunction photodiode comprising a horizontal stack including an n-doped silicon layer 112, an intrinsic germanium layer 200 and a p-doped silicon layer 113.
[0065] Before step b) of growth, a pretreatment step can be carried out. This may consist of a cleaning step (for example, using a hydrofluoric acid solution) and / or a heat treatment step (for example, annealing at a temperature between 750 and 1000°C under hydrogen). The pretreatment makes it possible to obtain a surface suitable for growth.
[0066] In step b), the third material is epitaxially grown. It can be epitaxially grown, for example, by ultra-high vacuum chemical vapor deposition (UHV-CVD). Growth can be carried out at a temperature, for example, between 300 and 750 °C. The temperature is chosen to accommodate the difference in lattice parameters between the first and third materials without island formation, thus obtaining epitaxially grown layers of good crystalline quality. Growth can be a two-step process at two temperatures (a low temperature, for example, between 300 and 450 °C, and a high temperature, for example, between 600 and 800 °C). The pressure is, for example, between 10 and 150 torr (i.e., between 1333.22 and 19998.4 Pa).
[0067] Since the growth is not perfectly planar, it is possible to observe different facets of the Ge crystal during growth. The growth of the epitaxial material is continued until it overflows the cavity 150. This improves the quality of the material, particularly by reducing dislocations in the Ge layer. For optical applications, and especially in the case of a photodiode, this prevents degradation of light coupling through multiple reflections.
[0068] The epitaxial structure 200 has a mushroom-shaped structure. A first part 201 of the structure 200 completely fills the cavity 150 and a second part 202 of the structure 200 covers the first part 201 and extends over the first main face 101 of the substrate 100.
[0069] The emerging part 202 of the structure 200 has a thickness 'e' called the overhang thickness. The overhang thickness e corresponds to the largest thickness that protrudes compared to the first face 101 of the substrate 100. The overflow thickness of the third epitaxially coated material depends on the dimensions of the devices. Overflow epitaxy is necessary to fill each cavity. Larger cavities take longer to fill, and therefore smaller cavities will have a greater overflow thickness. The thickness of the encapsulation layer 300 then depends on the greater overflow thickness.
[0070] The description specifically mentions a selective germanium epitaxy in cavities having a silicon base and a silicon oxide encapsulating layer. Other materials could be used instead of germanium: for example, a silicon alloy, in particular SiGe (having, for example, up to 30 atomic percent of Si) or GeSn (having, for example, up to 10 atomic percent of Sn). Similarly, other material combinations could be used, such as silicon and silicon oxide, or polycrystalline silicon and silicon oxide. It is also possible to encapsulate copper with silicon oxide, the CMP then being a CMP on SiO2 and copper. The copper can be deposited by electrochemical deposition (ECD).
[0071] After the growth step, an encapsulation layer 300 is deposited to cover at least the epitaxial structure 200 and preferably the first main face of the substrate 100 (step c)). The encapsulation layer 300 is preferably deposited full plate.
[0072] The encapsulation layer 300 can be deposited for example by plasma-enhanced chemical vapor deposition (PECVD).
[0073] This is a layer 300 acting as a sacrificial layer. This encapsulation layer 300 reduces the mechanical action exerted on the epitaxial material and prevents detachment.
[0074] The sacrificial layer 300 also allows addressing overflows of different thicknesses obtained during the same epitaxial step for cavities of different dimensions.
[0075] The encapsulation layer 300 has a thickness between 20 and 200% of the overflow thickness.
[0076] The thickness of the encapsulation layer 300 is preferably between 20 and 100%, and even more preferably between 20 and 50%, and very preferably between 20 and 40% (for example about 30%) of the overflow thickness.
[0077] The encapsulation layer 300 is made of a fourth material. Preferably, it is made of the same material as the passivation layer. The fourth material is, for example, SiO2, particularly in the case of an epitaxial layer of germanium or one of its alloys (SiGe, GeSn).
[0078] In step d), a CMP step is then implemented (step d). This step leads to obtaining a flat surface. This step is non-selective. It allows for the polishing of both the encapsulation layer 300 deposited in step c) and the epitaxial structure 200. The materials are thinned simultaneously and at the same rate. It is thus possible, in the case of a photodiode, to get as close as possible to the silicon waveguide in order to limit the photodiode thickness. This reduces the response time in the case of vertical or lateral photodiodes. And therefore, reducing the germanium thickness improves the performance of the photodiodes.
[0079] As shown in Figures 2A to 2D and in [Fig. 4], the substrate 100 may include a stopping layer 160. The stopping layer 160 is positioned in a plane parallel to the bottom 151 of the cavities 150. It is located between the bottom 151 of the cavities 150 and the first main face 101 of the substrate 100. The cavity 150 may pass through the stopping layer 160. For example, in the case of a photodiode, it is possible to integrate the stopping layer 160 between the waveguide and the first main face 101 of the substrate 100 in order to improve the stopping of the thinning and to further reduce the non-uniformity of the planarization process.
[0080] With such a process, very good uniformity can be obtained over large areas, and in particular over an entire plate (for example, with a uniformity of around 2% over the thickness of the arrest layer).
[0081] The arrest layer 160 is separated from the first material by the thinnest possible thickness, for example, by a thickness between 10 and 20 nm. The arrest layer 160 could be in contact with the first material.
[0082] The arrest layer 160 can be made of SiN. Depending on the different materials of the substrate and the epitaxial material, it is also possible to choose arrest layers made of SiC or SiO2.
[0083] Following step d), the process may include subsequent steps, for example, encapsulation and / or contact formation steps on the p 113 and n 112 zones. These steps may be carried out by means of etching, filling, and CMP steps. The thinner the device, the smaller the contact points can be.
[0084] The resulting device comprises a substrate 100 having a first main face 101 and a second main face 102, a cavity 150 being formed from the first main face 101 of the substrate 100. The bottom 151 of the cavity 150 is made of a first material, preferably a semiconductor. The first main face 101 of the substrate 100 is made of a second material. The cavity 150 is completely filled by a third epitaxial semiconductor material 200 (in other words, there are no other materials in the cavity 150).
[0085] The first semiconductor material and the third semiconductor material are, preferably, crystalline materials, even more preferably single-crystal semiconductor materials.
[0086] The substrate 100 comprises, for example, successively: a silicon support substrate 140, a silicon oxide layer 130 (“BOX”), and a silicon layer 110 which can be structured and / or doped and a passivation layer 120.
[0087] The epitaxial material 200 is preferably germanium, GeSn or SiGe.
[0088] The epitaxial material 200 can be arranged between a first n-doped silicon portion (Si-) 112 and a second p-doped silicon portion (Si+) 113 to form a PIN photodiode. The epitaxial material 200 is the intrinsic material in the PIN photodiode. The photodiode is a double heterojunction.
[0089] The absorption zone of the photodiode corresponds to the epitaxial germanium. This absorption zone is a region configured to absorb at least part of the light flux and generate electrical charges.
[0090] The photodiode can be coupled to a waveguide. The coupling can be evanescent. For example, evanescent coupling can be achieved with a waveguide formed in the SOI 110 layer and germanium epitaxially deposited on top of it. Direct coupling is also possible with a waveguide formed in the 110 layer when the cavity is etched into the SOI 110 layer.
[0091] Illustrative and non-limiting example
[0092] In this first example, a modulator was manufactured.
[0093] After carrying out a selective overflow epitaxy of germanium in a cavity whose bottom is made of silicon ([Fig.5A]), the germanium was encapsulated by a layer of SiO2 encapsulation ([Fig.5B]), then a non-selective CMP step was implemented ([Fig.5C]).
[0094] For comparison, a modulator was fabricated according to the following steps: selective epitaxial implantation of germanium in cavities of different sizes, followed by the planarization step. In the comparative example, there is no encapsulation step. The resulting device shows pull-off marks ([Fig. 6]).
[0095] Photodiodes were fabricated on 300 mm substrates (Figures 7A, 7B and 7C) and 200 mm substrates (Figures 8A and 8B). Several different masks were tested. Photodiodes ranging from 300 nm wide to about one hundred microns were thus fabricated.
[0096] SEM observations show that the structure of the photodiodes is free of defects.
[0097] For comparison, photodiodes were manufactured without depositing encapsulation layers. After CMP, peel marks are visible ([Fig.9]).
[0098] This confirms that it is thanks to the presence of the encapsulation layer, deposited before the CMP, that the germanium does not show any pull-off marks.
[0099] The main performance characteristics obtained with this process are as follows: - a local topography after CMP of less than 20nm, - an oxide thickness after CMP thinning of at least 50 nm.
[0100] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.
[0101] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.
[0102] REFERENCES [1] Ryzhak et al., « Sélective Epitaxy of Germanium on Silicon for the fabrication of CMOS compatible short-wavelength infrared photodetectors », Mater. Sci. Semicond. Process. (2024), 176, 108308 [2] US 2010 / 0151619 Al [3] Bae et al., « Chemical mechanical planarization mechanism of epitaxially grown Ge-film for sequential integrating 3D-structured transistor cells », J. Korean Phys. Soc. (2022), 81, 12, 1262-1268 [4] JP 6696735 B2 [5] WO 2020 / 096620 Al
Claims
Demands
1. A method for manufacturing a microelectronic device, for example a photonic device, in particular a photodiode, comprising the following steps: a) providing a substrate (100) comprising a cavity (150) formed from a first principal face (101) of the substrate (100), the bottom (151) of the cavity (150) being made of a first material, the first principal face (101) of the substrate (100) being made of a second material, b) carrying out a selective epitaxy of a third material in the cavity (150) of the substrate (100), until the epitaxially grown material fills the cavity and overflows the cavity by a thickness called the overflow thickness, thereby obtaining an epitaxially grown structure (200), c) depositing an encapsulation layer (300) of a fourth material on the substrate (100) and on the epitaxially grown structure (200),d) perform a CMP thinning step to remove the encapsulation layer (300) and the portion of the epitaxial structure (200) protruding from the first main face (101) of the substrate (100), the thickness of the deposited encapsulation layer (300) being between 20 and 200% of the overflow thickness.
2. A method according to the preceding claim, wherein the thickness of the encapsulation layer (300) is between 20 and 100%, preferably between 20 and 50% of the overflow thickness.
3. A method according to any one of the preceding claims, wherein the bottom (151) of the cavity (150) is made of a semiconductor material, preferably single-crystal, and even more preferably single-crystal silicon.
4. A method according to any one of the preceding claims, wherein the encapsulation layer (300) is made of silicon oxide, the encapsulation layer (300) preferably being deposited by PECVD.
5. A method according to any one of the preceding claims, wherein the second material is silicon oxide.
6. A method according to any one of the preceding claims, wherein the third material is a semiconductor material, preferably germanium or one of its alloys, for example GeSn or SiGe.
7. A method according to any one of the preceding claims, wherein the substrate (100) comprises several cavities (150) of different or identical dimensions.
8. A method according to the preceding claim, wherein the cavities (150) have different dimensions and wherein step b) is carried out until the epitaxial material (200) overflows from all the cavities (150).
9. A method according to any one of the preceding claims, wherein a stop layer (160), for example of SiN, is disposed in the substrate (100) and wherein the thinning step is stopped when the stop layer (160) is reached.
10. Microelectronic device, for example a photonic device, comprising a substrate (100), a cavity (150) being formed from a first principal face (101) of the substrate (100), the bottom (151) of the cavity (150) being of a first material, the first principal face (101) of the substrate (100) being of a second material, the cavity (150) being completely filled by a third epitaxial semiconductor material (200).
11. Device according to claim 10, wherein the bottom (151) of the cavity is made of single-crystal silicon, the second material is made of silicon oxide and the third epitaxial material is made of SiGe, GeSn or Ge.
12. Device according to any one of claims 10 and 11, wherein the device is a photodiode.