Random number generation

Abstract

Random Number Generation This description concerns a method for generating random numbers adapted for use with a discrete chaotic system. Its implementation consists of a first function composed of an integer n and a second affine function which, for an input value between zero and one, inclusive, provides an output value between zero and one, inclusive. Figure for the abbreviation: Fig. 6

Description

Title of the invention: Random number generation technical field

[0001] This description relates generally to electronic systems and devices, and more particularly to the generation of random numbers within these electronic systems and devices. Previous technique

[0002] Random number generators are devices adapted to produce sequences of numbers for which there is no deterministic link between a number and its predecessor(s).

[0003] Random number generators are used in all sorts of fields, but particularly in the field of computer security. Random numbers are typically used for data encryption, for example for generating encryption and / or decryption keys, or for implementing authentication procedures.

[0004] The generation of a random number can be carried out based, for example, on physical phenomena, on analog signal processing, and / or on digital signal processing.

[0005] It would be desirable to be able to improve, at least in part, certain aspects of random number generators and associated random number generation methods. Summary of the invention

[0006] There is a need for a more efficient and reliable generation of random numbers.

[0007] There is a need for such methods of generating random numbers.

[0008] There is a need for such random number generators.

[0009] One embodiment overcomes all or part of the disadvantages of known random number generation.

[0010] One embodiment provides for the generation of random numbers using a discrete chaotic system.

[0011] One embodiment provides for the generation of random numbers using a discrete chaotic system.

[0012] One embodiment provides for the generation of random numbers using a discrete chaotic system based on the use of affine functions.

[0013] One embodiment provides for the generation of random numbers using a discrete chaotic system based on the use of affine functions.

[0014] One embodiment provides a method for generating random numbers adapted to use a discrete chaotic system using for its implementation a first function composed of an integer n of second affine functions which, at an input value between zero and one, zero and one inclusive, provide an output value between zero and one, zero and one inclusive.

[0015] Another embodiment provides for a random number generator comprising a circuit implementing a discrete chaotic system using for its implementation a first function composed of an integer n of second affine functions which, at an input value between zero and one, zero and one inclusive, provide an output value between zero and one, zero and one inclusive.

[0016] According to one embodiment, said discrete chaotic system further uses a comparison of a value to at least one threshold.

[0017] According to one embodiment, the integer n is even.

[0018] According to one embodiment, the integer n is a power of two.

[0019] According to one embodiment, the integer n is equal to 2 or 4.

[0020] According to one embodiment, said second affine functions all have a negative slope.

[0021] According to one embodiment, said second affine functions all have a positive slope.

[0022] According to one embodiment, a first part of said second affine functions have a negative slope and a second part of said affine functions have a positive slope.

[0023] According to one embodiment, said discrete chaotic system is implemented by an electronic circuit in which said input and output values ​​are current values.

[0024] According to one embodiment, said discrete chaotic system is implemented by an electronic circuit in which said input and output values ​​are voltage values.

[0025] According to one embodiment, said input value is included in a first set included in a second set being the set of real numbers between zero and one, this first set being reduced by 10 to 30% of the values ​​compared to the second set, said second value being included in this first set.

[0026] Another embodiment provides an authentication method using a method described above.

[0027] Another embodiment provides for an electronic device comprising a random number generator as described above.

[0028] Another embodiment provides for an electronic device adapted to implement the process described above. Brief description of the drawings

[0029] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0030] [Fig.1] represents an embodiment of an electronic device;

[0031] [Fig.2] represents an embodiment of a random number generator;

[0032] [Fig.3] represents curves illustrating discrete chaotic systems;

[0033] [Fig.4] represents graphs illustrating discrete chaotic systems;

[0034] [Fig. 5] represents a curve illustrating an example of a first system discreetly chaotic;

[0035] [Fig.6] represents a block diagram illustrating the operation of the discrete chaotic system of [Fig.5];

[0036] [Fig.7] represents an electrical diagram of an electronic circuit adapted to implement the discrete chaotic system of [Fig.5];

[0037] Figure 8 represents a curve illustrating an example of a second discrete chaotic system; and

[0038] [Fig.9] represents an electrical diagram of an electronic circuit adapted to implement the discrete chaotic system of [Fig.8]. Description of the implementation methods

[0039] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0040] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. Unless otherwise specified, when reference is made to two interconnected elements, this means directly connected without any intermediate elements other than conductors, and when reference is made to two coupled elements, this means that these two elements can be connected or linked via one or more other elements.

[0041] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0042] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0043] The embodiments described below relate to the generation of random numbers, that is, a method for generating random numbers and a random number generator. More particularly, the embodiments described below propose to use a discrete chaotic system to generate random numbers. A dynamic system is said to be chaotic if it is sensitive to one or more initial conditions and if it exhibits a recurrence phenomenon. A chaotic system is said to be discrete when its recurrence phenomenon is artificially driven by a discrete temporal notion. Discrete chaotic systems have, for example, been used to simulate demographic behaviors, but inventors have discovered that they can also be used for generating random numbers.Different types of discrete random systems are described in relation to Figures 3 and 4. Two examples of practical implementations of such systems are described in detail in relation to Figures 5 to 9.

[0044] Moreover, the embodiments described below are particularly suitable for use in applications in the field of computer security, for example for the encryption of data, such as secret data, and for example for the implementation of authentication processes.

[0045] Furthermore, the embodiments described above are particularly suitable for use in any type of industrial market using random number generators. More specifically, such a random number generator may be intended for: - the automotive industry, for example in the field of automotive electrification or in the field of advanced driver assistance systems (ADAS); - the industrial industry, for example in the field of green energy, in the field of infrastructure electrification, the Internet of Things (IoT) and Smart Homes, where electricity and energy consumption and data exchange are key elements; - the personal electronics industry, for example in the field of mobile telephony and the Internet of Things (IoT), as well as in the field of broadband interfaces - the communications equipment, computer and peripherals industry, for example in the field of infrastructure and data centers, and in the field of low Earth orbit (LEO) satellites; and - the security industry, such as transaction security and in particular banking transaction security, and the fight against counterfeiting.

[0046] Fig. 1 is a block diagram representing, very schematically, an architecture of an example of an electronic device 100 adapted to implement random number generation.

[0047] The electronic device 100 includes, for example, a processor 101 (CPU) adapted to implement various processing of data stored in memories and / or provided by other circuits of the device 100. According to one embodiment, the processor 101 can be adapted to generate random numbers.

[0048] According to one example, the electronic device 100 further comprises different types of memory 102 (MEM), including, for example, non-volatile memory, volatile memory, and / or read-only memory. Each memory 102 is adapted to store different types of data.

[0049] In one example, the electronic device 100 further comprises, for example, a secure element 103 (SE) adapted to handle sensitive and / or secret data. The secure element 103 may include its own processor(s), its own memory(ies), etc. In one embodiment, the secure element 101 may be adapted to generate random numbers or may include a circuit adapted to generate random numbers.

[0050] According to one example, the electronic device 100 may further include interface circuits 104 (IN / OUT) adapted to send and / or receive data from outside the device 100. The interface circuits 104 may further be adapted to implement a data display, for example, a display screen.

[0051] According to one example, the electronic device 100 further comprises various circuits 105 (FCT1) and 106 (FCT2) adapted to perform different functions. By way of example, the circuits 105 and 106 may include measurement circuits, data conversion circuits, etc. According to one embodiment, the circuits 105 and 106 may include a circuit adapted to generate random numbers.

[0052] According to one example, the electronic device 100 further comprises one or more data buses 107 adapted to transfer data between its different components.

[0053] More specifically, the electronic device 100 is adapted to implement at least one computer program product comprising program code instructions recorded on a medium usable in a computer, including computer-readable programming means to implement a random number generation process according to one embodiment.

[0054] According to one example, the electronic device 100 can be adapted to process sensitive data, such as secret data, and can, for this purpose, implement one or more encryption algorithms. The random number generation implemented by device 100 can be used in the execution of this or these encryption algorithms.

[0055] According to another example, the electronic device 100 can be adapted to implement one or more authentication processes, for example to identify itself to other electronic devices or, for example, to identify some of its internal components to each other. The device 100 can, for this purpose, use random numbers.

[0056] Figure 2 represents, very schematically and in block form, a mode of realization of a 200 random number generator circuit, or 200 random number generator (RNG).

[0057] According to one embodiment, the generator 200 is a discrete electronic circuit adapted for use in an electronic device of the type of device 100 described in relation to [Fig. 1]. According to another variant, the generator 200 is a computer program adapted to implement a method for generating random numbers.

[0058] In one embodiment, the generator 200 comprises a circuit 201 (CDS) adapted to implement a discrete chaotic system. In one embodiment, the circuit 201 is a discrete electronic circuit. In another variant, the circuit 201 is a computer program adapted to implement a discrete chaotic system.

[0059] The generator 200 is adapted to provide, as output, a series of data bits whose distribution of values, zero or one, is random. The inventors discovered that it is possible to use the mathematical model of a discrete chaotic system for this purpose. Indeed, a discrete chaotic system consists of the successive application of one or more mathematical functions. To this end, an initial value is provided to the system, the function is applied once, and then the function is iteratively applied to the previously obtained result for a certain number of iterations, for example, more than 100 to 1000 iterations. After an initialization phase where the distribution of the values ​​obtained is not random, called the Lyapunov horizon, the distribution becomes random. Examples of mathematical functions used are described in detail below.

[0060] Figure 3 includes graphs illustrating different types of functions mathematics that can be used to implement a discrete chaotic system.

[0061] According to one embodiment, the mathematical functions considered here are mathematical functions whose domain of definition, or domain, is equal to its codomain. According to a first embodiment, the domain of definition of this function is the set of real numbers between zero and one, with zero and one included in this set. According to a second embodiment, the domain The definition of this function is a set included in the set of real numbers between zero and one, this first set being reduced by 10 to 30% of the values. This second embodiment is described in more detail with reference to Figures 8 and 9.

[0062] In one embodiment, the mathematical functions considered here are functions composed of the assembly of several affine functions. More particularly, the domain of definition is divided into several intervals, and a different affine function is used on each interval. In one embodiment, the mathematical functions considered here are composed of a number n of affine functions, n being an integer. In one embodiment, n is an even integer, preferably a power of two. In a preferred embodiment, n is equal to two or four.

[0063] A first type of function 310 uses only affine functions with negative slopes. This first type of function 310 is the preferred type of function for implementing the embodiments concerned here. For a function 311, the domain of definition is divided into two intervals, and two affine functions are used. For a function 312, the domain of definition is divided into four intervals, and four affine functions are used. For a function 313, the domain of definition is divided into eight intervals, and eight affine functions are used.

[0064] A second type of function 320 uses affine functions having positive and negative slopes. For a function 321, the domain of definition is divided into two intervals, and two affine functions are used. For a function 322, the domain of definition is divided into four intervals, and four affine functions are used. For a function 323, the domain of definition is divided into eight intervals, and eight affine functions are used.

[0065] A third type of function 330 uses only affine functions with positive slopes. For a function 331, the domain of definition is divided into two intervals, and two affine functions are used. For a function 332, the domain of definition is divided into four intervals, and four affine functions are used. For a function 333, the domain of definition is divided into eight intervals, and eight affine functions are used.

[0066] [Fig.4] includes three views (A), (B) and (C) each illustrating a graph showing the implementation of a discrete chaotic system using a function of the type of function 311 described in relation to [Fig.3].

[0067] Each of these views illustrates the distribution of values ​​obtained at each iteration of a discrete chaotic system.

[0068] View (A) illustrates, by means of a graph 401, the implementation of this discrete chaotic system after completion of four rounds, or four iterations.

[0069] View (B) illustrates, by means of a graph 401, the implementation of this discrete chaotic system after completion of one hundred turns.

[0070] View (C) illustrates, by means of a graph 401, the implementation of this discrete chaotic system after the completion of a thousand turns.

[0071] Figures 5 and 6 illustrate a more particular example of a function of the type of function 311 described in relation to [Fig.3] used for setting up a discrete chaotic system for generating random numbers.

[0072] The [Fig.5] is a curve illustrating a function 501 of the type of the function 311 described in relation to the [Fig.3].

[0073] According to one embodiment, the function 501 is adapted to be used to implement a discrete chaotic system.

[0074] According to one embodiment, the domain of definition of the function 501 is the set of real numbers between zero and one, and the codomain of the function 501 is the set of real numbers between zero and one, zero and one being included in this domain.

[0075] The function 501 is obtained by combining two affine functions 501A and 501B with negative slopes. In one embodiment, the domain of function 501A is the set of real numbers from zero to a real number Xth, including zero and Xth, and the domain of function 501B is the set of real numbers from the real number Xth to one, including Xth and one. The real number Xth is called the threshold value of the function 501.

[0076] According to a particular example, the real number Xth is equal to 0.5. In this case, the mathematical expression of the affine function 501A is as follows: [Math 1] 50 IA : X*)= l-2*x

[0077] In the same way, the mathematical expression of the affine function 501B is as follows: [Math 1] 50IB : X^) = 2-2*x

[0078] Fig. 6 is a block diagram illustrating the implementation of function 501 described in relation to Fig. 5 for the execution of a discrete chaotic system.

[0079] At a step 601 (X>Xth), the input data to which the function 501 is applied is compared to the real number Xth. For example, during the implementation of a discrete chaotic system, the input data is either initialization data if the current turn is the first turn, or the output data from the previous turn. If this data is less than the actual Xth (Output Y), the next step is a 602 (501A) step, otherwise the next step is a 603 (501B) step.

[0080] At step 602, the affine function 501A is applied to the input data.

[0081] At step 603, the affine function 501B is applied to the input data.

[0082] In the case of implementing a discrete chaotic system, a step 604 (X<-Y), successive to steps 602 and 603, is implemented. In this step 604, the data obtained in step 602 or 603 is stored for use in a subsequent iteration.

[0083] The [Fig.7] is an example of an electronic circuit 700 adapted to implement the function 501 described in relation to the [Fig.1].

[0084] For example, the electronic circuit 700 is a current implementation of function 501. In other words, the input and output values ​​of function 501 are current values. It would be within the scope of a person skilled in the art to design a voltage implementation of function 501, that is, an implementation of function 501 where the input and output values ​​are voltage or potential values.

[0085] According to one example, the circuit 700 comprises two initial current sources adapted to supply a multiple of a current In701. It is considered that the value of this current In701 represents, at the start-up of the circuit 700, the initial value imposed on the function 501. Then, during the subsequent operation of the circuit 700, that is, during the implementation of the various iterations of the discrete chaotic system using the function 501, the value of the current In701 corresponds to the image value obtained at the output of the function 501. In practice, the circuit 700 comprises a current source SIn701 adapted to supply the current In701, and a current source S2In701 adapted to supply twice the current In701. According to one example, the sources SIn701 and S2In701 are supplied by a supply potential VDD700.

[0086] According to one example, the circuit 700 further comprises three second current sources SIref701-1, SIref701-2, and SIref701-3, all adapted to provide a reference current Iref701. The value of the reference current Iref701 represents the threshold value Xth of the function 501. According to one example, the current source SIref701-1 is adapted to be supplied by the current source SIn701 and is connected, preferably connected, to a node providing a reference potential GND701. The midpoint node between the current sources SIn701 and SIref701-1 allows for the implementation of a condition Cond701 executing step 601 described in relation to [Fig. 6]. According to one example, the current source SIref701-2 is adapted to be powered by the current source S2In701 via a switch 1701, and is connected, preferably connected, to a node providing a reference potential GND701.According to one example, switch 1701 is controlled by condition Cond701, that is, by the potential supplied by the mid node between current sources Sin701. and SIref701-l. According to an example, the current source SIref701-3 is adapted to be powered by the current source S2In701, and is connected, preferably connected, to a node providing a reference potential GND701.

[0087] According to one example, the circuit 700 further comprises a resistor R701 and a first current mirror circuit. According to one example, a first terminal of the resistor R701 receives the supply potential VDD700, and a second terminal of the resistor R701 is preferably connected to an output terminal of the first current mirror circuit.

[0088] According to one example, this first current mirror is formed using metal-oxide-semiconductor field-effect transistors (MOSFETs). Furthermore, this first current mirror uses N-channel MOS transistors. More specifically, the first current mirror comprises two transistors, M701 and M702. A first conduction terminal of transistor M701, forming an output terminal of the first current mirror, is connected, preferably connected, to the second terminal of resistor R701, and a second conduction terminal of transistor M701 is connected, preferably connected, to the node providing the reference potential GND700.A first conduction terminal of transistor M702, forming an input terminal of the first current mirror, is connected, preferably connected, to the control terminal of transistor M702, and a second conduction terminal of transistor M702 is connected, preferably connected, to the node providing the reference potential GND700.

[0089] According to one example, the circuit 700 further comprises a switch 1702 and a capacitor C701 arranged within the first current mirror. More specifically, a first conductor terminal of the switch 1702 is connected, preferably connected, to the conduction terminal of the transistor M701, and a second conduction terminal of the switch 1702 is connected, preferably connected, to the conduction terminal of the transistor M702. A control terminal of the switch 1702 (not shown in [Fig. 7]) is adapted to receive a clock signal that synchronizes the operation of the circuit 700. A first terminal of the capacitor C701 is connected, preferably connected, to the control terminal of the transistor M701, and a second terminal of the capacitor C701 is connected, preferably connected, to the node receiving the reference potential GND700.

[0090] According to one example, the circuit 700 further comprises a second current mirror circuit. According to one example, this second current mirror is formed using P-channel MOS transistors, or P-type MOS transistors, or PMOS transistors. More particularly, the second current mirror comprises two transistors M703 and M704. A first conduction terminal of transistor M703, forming a The output terminal of the second current mirror is connected, preferably connected, to the second terminal of resistor R701, and a second conduction terminal of transistor M703 is connected, preferably connected, to the node providing the supply potential VDD700. A first conduction terminal of transistor M704, forming an input terminal of the second current mirror, is connected, preferably connected, to the control terminal of transistor M704, and a second conduction terminal of transistor M704 is connected, preferably connected, to the node providing the supply potential VDD700.

[0091] According to one example, the circuit 700 further comprises a switch 1703 and a capacitor C702 arranged within the second current mirror. More specifically, a first conduction terminal of the switch 1703 is connected, preferably connected, to the conduction terminal of the transistor M703, and a second conduction terminal of the switch 1703 is connected, preferably connected, to the conduction terminal of the transistor M704. A control terminal of the switch 1703 (not shown in [Fig. 7]) is adapted to receive the inverse of the clock signal that drives the operation of the circuit 700. A first terminal of the capacitor C702 is connected, preferably connected, to the control terminal of the transistor M703, and a second terminal of the capacitor C702 is connected, preferably connected, to the node receiving the reference potential GND700.The second conduction terminal of transistor M704 provides a current In+1701 whose value corresponds to the output value of function 501. This current is available at the output node of current source S2In701.

[0092] The [Fig.8] is a curve illustrating a function 801 of the type of the function 311 described in relation to the [Fig.3].

[0093] According to one embodiment, the function 801 is adapted to be used to implement a discrete chaotic system.

[0094] According to one embodiment, the domain of definition of function 801 corresponds to the domain of definition of function 501 described in relation to [Fig. 5], reduced by 10 to 30%. In other words, the domain of definition of function 801 is the set of real numbers between zero and one, reduced by 10 to 30%. These margins can be introduced to overcome practical implementation problems with function 501 described in relation to [Fig. 5]. The codomain of function 801 is then the set of real numbers between zero and one, with zero and one included in this domain. However, when the output value of function 801 is no longer within its domain of definition, it is artificially associated with a boundary value of this domain.

[0095] According to one embodiment, like function 501, function 801 is obtained by combining two affine functions 801A and 801B with slope coefficients negatives. According to one embodiment, the function 801A has as its domain of definition the set of real numbers between zero and a real number Xth2 reduced by 10 to 30%, and the function 801B has as its domain of definition the set of real numbers between the real number Xth2 and one, reduced by 10 to 30%. The real number Xth2 is called the threshold value of the function 801.

[0096] [Fig. 9] is an example of an electronic circuit 900 adapted to implement the function 801 described in relation to [Fig. 1].

[0097] For example, the electronic circuit 900 is a current implementation of function 801. In other words, the input and output values ​​of function 801 are current values. It would be within the scope of a person skilled in the art to design a voltage implementation of function 801, that is, an implementation of function 801 where the input and output values ​​are voltage or potential values.

[0098] According to one example, the circuit 900 comprises four initial current sources adapted to provide a multiple of a current In901. It is considered that the value of this current In901 represents, at the start-up of the circuit 900, the initial value imposed on the function 801. Then, during the subsequent operation of the circuit 900, that is to say during the implementation of the different iterations of the discrete chaotic system using the function 801, the value of the current In901 corresponds to the image value obtained at the output of the function 801. In practice, the circuit 900 comprises three current sources SIn901-1, SIn901-2 and SIn901-3 adapted to provide the current In901, and a current source S2In901 adapted to provide twice the current In901. As an example, the SIn901 and S2In901 sources are both powered by a VDD900 supply potential.

[0099] According to one example, the circuit 900 further comprises seven second current sources SIref901, S2Iref901-1, S2Iref901-2, SIref901-3, SIref901-4, S3Iref901-1 and S3Iref901-2, all adapted to provide a multiple of a reference current Iref901. The value of the reference current Iref901 represents the thresholds separating the different affine functions, but also the shift thresholds of these affine functions.

[0100] According to one example, the current source SIref901 is adapted to be supplied by the current source SIn901-l, and is connected, preferably connected, to a node providing a reference potential GND901. The midpoint node between the current sources SIn901-l and SIref901 allows the implementation of a condition Cond901 executing a comparison between a value obtained by the function 901 and a threshold value represented by the current Iref901.

[0101] According to one example, the current source S2Iref901-1 is adapted to be supplied by the current source SIn901-2, and is connected, preferably connected, to the node providing the reference potential GND901. The midpoint node between the current sources SIn901-2 and S2Iref901-1 allows for the implementation of a Cond902 condition. performing a comparison between a value obtained by function 901 and a threshold value represented by twice the current Iref901.

[0102] According to one example, the current source S3Iref901-l is adapted to be supplied by the current source SIn901-3, and is connected, preferably connected, to the node providing the reference potential GND901. The midpoint node between the current sources SIn901-3 and S3Iref901-l allows for the implementation of a condition Cond903 performing a comparison between a value obtained by the function 901 and a threshold value represented by three times the current Iref901.

[0103] According to one example, the circuit 900 further comprises a control circuit 910 (CTRL) adapted to receive the result of the conditions Cond901, Cond902 and Cond903 and to provide control potentials.

[0104] According to one example, the current source S2Iref901-2 is adapted to be supplied by the current source S2In901 via a switch 1901, and is connected, preferably connected, to the node providing the reference potential GND901. According to one example, the switch 1901 is controlled by the control circuit 910.

[0105] According to one example, the current source S2Iref901-2 is adapted to be supplied by the current source S2In901 via a switch 1901, and is connected, preferably connected, to the node providing the reference potential GND901. According to one example, the switch 1901 is controlled by the control circuit 910.

[0106] According to one example, the current source S2Iref901-4 is adapted to be supplied by the current source S2In901 via a switch 1903, and is connected, preferably connected, to the node providing the reference potential GND901. According to one example, the switch 1903 is controlled by the control circuit 910.

[0107] According to one example, the current source S3Iref901-2 is adapted to be powered by the current source S2In901, and is connected, preferably connected, to the node providing the reference potential GND901.

[0108] According to one example, the circuit 900 further comprises a resistor R901 and a first current mirror circuit. According to one example, a first terminal of the resistor R901 receives the supply potential VDD900, and a second terminal of the resistor R901 is preferably connected to an output terminal of the first current mirror circuit.

[0109] According to one example, this first current mirror is formed using NMOS transistors. More particularly, the first current mirror comprises two transistors, M901 and M902. A first conduction terminal of transistor M901, forming an output terminal of the first current mirror, is connected, preferably connected, to the second terminal of resistor R901, and a second conduction terminal of transistor M901 is connected, preferably connected, to the node providing the reference potential GND900. A first conduction terminal of transistor M902, forming an input terminal of the first current mirror, is connected, preferably connected, to the control terminal of transistor M902, and a second conduction terminal of transistor M902 is connected, preferably connected, to the node providing the reference potential GND900.

[0110] According to one example, the circuit 900 further comprises a switch 1904 and a capacitor C901 arranged within the first current mirror. More specifically, a first conductor terminal of switch 1904 is connected, preferably connected, to the conduction terminal of transistor M901, and a second conduction terminal of switch 1904 is connected, preferably connected, to the conduction terminal of transistor M902. A control terminal of switch 1904 (not shown in [Fig. 9]) is adapted to receive a clock signal that synchronizes the operation of the circuit 900. A first terminal of capacitor C901 is connected, preferably connected, to the control terminal of transistor M901, and a second terminal of capacitor C901 is connected, preferably connected, to the node receiving the reference potential GND900.

[0111] According to one example, the circuit 900 further comprises a second current mirror circuit. According to one example, this second current mirror is formed using PMOS transistors. More specifically, the second current mirror comprises two transistors, M903 and M904. A first conduction terminal of transistor M903, forming an output terminal of the second current mirror, is connected, preferably connected, to the second terminal of resistor R901, and a second conduction terminal of transistor M903 is connected, preferably connected, to the node providing the supply potential VDD900. A first conduction terminal of transistor M904, forming an input terminal of the second current mirror, is connected, preferably connected, to the control terminal of transistor M904, and a second conduction terminal of transistor M904 is connected, preferably connected, to the node providing the supply potential VDD900.

[0112] According to one example, the circuit 900 further comprises a switch 1905 and a capacitor C902 arranged within the second current mirror. More specifically, a first conduction terminal of switch 1905 is connected, preferably connected, to the conduction terminal of transistor M903, and a second conduction terminal of switch 1905 is connected, preferably connected, to the conduction terminal of transistor M904. A control terminal of switch 1905 (not shown in [Fig. 9]) is adapted to receive the inverse of the clock signal that drives the operation of circuit 900. A first terminal of capacitor C902 is connected, preferably connected, to the control terminal of transistor M903, and a second terminal of capacitor C902 is connected, preferably connected, to the node receiving the reference potential GND900. The second conduction terminal The transistor M904 provides a current In+1901 whose value corresponds to the output value of function 801. This current is available at the output node of the current source S2In901.

[0113] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0114] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. A method for generating random numbers adapted to use a discrete chaotic system (201) using for its implementation a first function (311, 312, 313, 321, 322, 323, 331, 332, 333 ; 501 ; 801) composed of an integer n of second affine functions (501A, 501B ; 801A, 801B) which, at an input value between zero and one, zero and one inclusive, provide an output value between zero and one, zero and one inclusive.

2. Random number generator (200) comprising a circuit implementing a discrete chaotic system (201) using for its implementation a first function (311, 312, 313, 321, 322, 323, 331, 332, 333 ; 501 ; 801) composed of an integer n of second affine functions (501A, 501B ; 801A, 801B) which, at an input value between zero and one, zero and one inclusive, provide an output value between zero and one, zero and one inclusive.

3. Method according to claim 1 or generator according to claim 2, wherein said discrete chaotic system (201) further uses a comparison of a value to at least one threshold (Xth).

4. Method according to claim 1 or 3, or generator according to claim 2 or 3, wherein the integer n is even.

5. Method or generator according to claim 4, wherein the integer n is a power of two.

6. Method or generator according to claim 5, wherein the integer n is equal to 2 or 4.

7. A method according to any one of claims 1, 3 to 6, or a generator according to any one of claims 2 to 6, wherein said second affine functions (501A, 501B; 801A, 801B) all have a negative slope.

8. A method according to any one of claims 1, 3 to 6, or a generator according to any one of claims 2 to 6, wherein said second affine functions all have a positive slope.

9. A method according to any one of claims 1, 3 to 6, or a generator according to any one of claims 2 to 6, wherein a first part of said second affine functions have a negative slope and a second part of said affine functions have a positive slope.

10. Method according to any one of claims 1, 3 to 9, or generator according to any one of claims 2 to 9, wherein said discrete chaotic system (201) is implemented by an electronic circuit (700; 900) in which said input and output values ​​are current values.

11. A method according to any one of claims 1, 3 to 9, or a generator according to any one of claims 2 to 9, wherein said discrete chaotic system is implemented by an electronic circuit in which said input and output values ​​are voltage values.

12. A method according to any one of claims 1, 3 to 11, or a generator according to any one of claims 2 to 11, wherein said input value is included in a first set included in a second set being the set of real numbers between zero and one, this first set being reduced by 10 to 30% of the values ​​compared to the second set, said second value being included in this first set.

13. Authentication method using a method according to any one of claims 1, 3 to 12.

14. Electronic device (100) comprising a random number generator (200) according to any one of claims 2 to 12.

15. Electronic device adapted to implement the method according to claim 13.

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