Method for manufacturing an electronic device
By employing a bipolar transistor structure with a dual-material extrinsic base region and a polycrystalline silicon or silicon nitride spacer, the method addresses the issue of increased base resistance in bipolar transistor manufacturing, achieving reduced resistance and thinner transistor designs.
Patent Information
- Authority / Receiving Office
- FR · FR
- Patent Type
- Applications
- Current Assignee / Owner
- STMICROELECTRONICS INT NV
- Filing Date
- 2024-12-18
- Publication Date
- 2026-06-19
Smart Images
Figure 00000000_0000_ABST
Abstract
Description
Title of the invention: Method for manufacturing an electronic device. Technical field.
[0001] This description relates generally to electronic devices and their manufacturing processes and more specifically to devices comprising a bipolar transistor and their manufacturing processes. Previous technique
[0002] A bipolar transistor is a semiconductor-based electronic device belonging to the transistor family. Its operating principle is based on two PN junctions, one forward-biased and the other reverse-biased.
[0003] The manufacturing processes for bipolar transistors include, for example, steps for forming an extrinsic base. Such steps can be problematic. Summary of the invention
[0004] An embodiment provides a method for manufacturing an electronic device comprising a bipolar transistor, the bipolar transistor comprising: a collector region; an emitter region; an intrinsic base region, the intrinsic base region being made of a single-crystal semiconductor material, the intrinsic base region resting on an upper face of the collector region and the emitter region resting on an upper face of the intrinsic base region; an extrinsic base region, the extrinsic base region comprising a first part made of a single-crystal semiconductor material and a second part made of a polycrystalline semiconductor material; and a first layer made of a material on which it is possible to grow the material of the second part by epitaxy, the method comprising: a.a. the formation of the first part by epitaxial growth from the upper face of the intrinsic basal region; and b. the formation of the second part by epitaxial growth from the upper face of the first layer.
[0005] Another embodiment provides an electronic device comprising a bipolar transistor, the bipolar transistor comprising: a collector region; an emitter region; an intrinsic base region, the intrinsic base region being made of a single-crystal semiconductor material, the intrinsic base region resting on an upper face of the collector region and the emitter region resting on an upper face of the intrinsic base region; an extrinsic base region, the extrinsic base region comprising a first part made of a single-crystal semiconductor material and a second part in a polycrystalline semiconductor material; and a first layer in a material on which it is possible to grow the material of the second part by epitaxy, the first part resting on the upper face of the intrinsic base region and the second part resting on the first layer.
[0006] According to one embodiment, the transistor comprises a second layer of a silicide-type material covering at least partially the first part and at least partially covering the second part.
[0007] According to one embodiment, the second layer is in contact with the first part.
[0008] According to one embodiment, the intrinsic base region is in contact with the collector region and with the emitter region.
[0009] According to one embodiment, the first layer is separated from the intrinsic base region by a portion of insulating material.
[0010] According to one embodiment, the transistor includes a spacer extending over the intrinsic base region, surrounding the interface area between the emitter region and the intrinsic base region.
[0011] According to one embodiment, the method comprises, before steps a and b: c. the formation of the collector region in a support; d. the formation of a stack of insulating layers in which the first layer is located; e. the formation in the stack of insulating layers of a first cavity traversing the stack of insulating layers and of a second cavity at the location of the intrinsic base region; f. the formation of the intrinsic base in the second cavity; g. the formation of the spacer along the walls of the first cavity.
[0012] According to one embodiment, the process comprises, before steps a and b and after step g: h. the formation of the emitter region; i. the encapsulation of the emitter region; and j. the etching of the layers of the stack of insulating layers so as to expose at least partially the first layer and the top face of the intrinsic base region.
[0013] According to one embodiment, the spacer is made of polycrystalline silicon.
[0014] According to one embodiment, the spacer is made of silicon nitride.
[0015] According to one embodiment, the process comprises, after steps a and b, the formation of the second layer at least partially on the first part and at least partially on the second part.
[0016] According to one embodiment, steps a. and b. are carried out simultaneously. Brief description of the drawings
[0017] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:
[0018] Fig. 1 represents an embodiment of an electronic device comprising a bipolar transistor;
[0019] Fig. 2A, Fig. 2B, Fig. 2C, Fig. 2D, Fig. 2E, Fig. 2F, and Fig. 2G represent structures resulting from steps in a manufacturing process for the device in Fig. 1; and
[0020] [Fig.3A], [Fig.3B], [Fig.3C] and [Fig.3D] represent structures resulting from steps of another manufacturing process of a device comprising a bipolar transistor according to another embodiment. Description of the implementation methods
[0021] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.
[0022] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.
[0023] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.
[0024] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.
[0025] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean to within 10% or 10°, preferably to within 5% or 5°.
[0026] Fig. 1 represents an embodiment of an electronic device 10 comprising a bipolar transistor 12.
[0027] The device 10 comprises a support 14, for example a semiconductor substrate, for example silicon. The transistor 12 is formed in and on the support 14. The support 14 includes in particular a doped region (not shown) constituting the collector 15 of bipolar transistor 12. Said doped region is doped with a first type of conductivity, N or P.
[0028] The transistor 12 further comprises an intrinsic base region 16. The region 16 is located on, preferably in contact with, an upper face 14a of the support 14. The region 16 is preferably in contact with the collector region (not shown). The region 16 is made of a doped semiconductor material with a second type of conductivity, opposite to the first type of conductivity. The region 16 is made of a single-crystal material. The region 16 is, for example, silicon, for example, epitaxial silicon. The region 16 is, for example, SiGe, for example, epitaxial SiGe. The region 16 has, for example, a variable dopant concentration. For example, there is a dopant concentration gradient in the region 16.
[0029] Region 16, for example, has the shape of a rectangular parallelepiped. Region 16 includes a lower face, preferably in contact with the collector region of the support 14. Region 16 includes an upper face, opposite the lower face and preferably substantially parallel to the lower face of region 16. Region 16 further includes lateral faces, connecting the upper and lower faces.
[0030] The device 10 further comprises an insulating layer 18. The layer 18 is made of a first insulating material, preferably silicon oxide. The layer 18 surrounds the region 16. The layer 18 covers the upper face 14a of the support 14. The layer 18 is preferably in contact with the upper face 14a of the support 14. The layer 18 is in lateral contact with the region 16, that is, in contact with the lateral faces of the region 16. More precisely, a lower part of the region 16, and therefore a lower part of the lateral faces of the region 16, is surrounded by, and in contact with, the layer 18. By lower part of the region 16 is meant the part closest to the support 14.
[0031] The device 10 comprises a layer 20. The layer 20 is made of a material that allows the epitaxial growth of a semiconductor material. Preferably, the layer 20 is made of a material that allows a semiconductor material to grow non-selectively on said layer 20, for example during a selective epitaxial growth step. The layer 20 is, for example, made of amorphous silicon, polycrystalline silicon, or silicon nitride.
[0032] The layer 20 rests on, and is preferably in contact with, the layer 18. The layer 20 surrounds the region 16, more precisely surrounds an intermediate part of the region 16, and therefore an intermediate part of the lateral faces of the region 16. The intermediate part of the region 16 is separated from the support 14 by the lower part of the region 16.
[0033] Layer 20 is separated from region 16 by a layer 22. Layer 22 is made of an insulating material. Layer 22 is, for example, made of the same material as layer 18, for example the first material, for example silicon oxide.
[0034] The bipolar transistor 12 includes an extrinsic base region 24. The region 24 surrounds the region 16, and more precisely surrounds an upper portion of the region 16, and therefore an upper portion of the lateral faces of the region 16. The upper portion of the region 16 is the part of the region 16 furthest from the support 14. The region 24 also covers a peripheral portion of the upper face of the region 16. The thickness of the region 24 is thus greater than the thickness of the upper portion of the region 16.
[0035] Region 24 includes a portion 24a. Portion 24a is made of polycrystalline semiconductor material. Portion 24a is made of a doped material with the same type of conductivity as that of region 16. Portion 24a is, for example, made of silicon, for example, epitaxially coated silicon. Portion 24a is, for example, made of SiGe, for example, epitaxially coated SiGe. Portion 24a covers, for example, completely, layer 20. Portion 24a is preferably in contact with the upper face of layer 20. Portion 24a covers, for example, at least partially, layer 28. Portion 24a is preferably in contact with at least a part of the upper face of layer 22.
[0036] Region 24 includes a portion 24b. Portion 24b is made of a single-crystal semiconductor material. Portion 24b is made of a doped material with the same type of conductivity as that of region 16. Portion 24b is, for example, made of silicon, for example, epitaxial silicon. Portion 24b is, for example, made of SiGe, for example, epitaxial SiGe. Portion 24b partially covers the upper face of region 16, more precisely, covers the peripheral part of the upper face of layer 16. Portion 24b is preferably in contact with said peripheral part of the upper face of layer 16. In the example of [Fig. 1], portion 24b further covers, and is preferably in contact with, an upper part of the lateral faces of region 16. Alternatively, the upper part of the lateral faces of region 16 is covered by portion 24a.
[0037] Part 24b is, for example, uniformly doped. Part 24b is also more heavily doped than region 16, preferably at least ten times more heavily doped.
[0038] The extrinsic base region 24 thus comprises a polycrystalline portion 24a and a single-crystal portion 24b. The single-crystal portion 24b of the extrinsic base region is in vertical contact with the intrinsic base region 16. The single-crystal portion 24b of the extrinsic base region is therefore not in exclusively lateral contact with the intrinsic base region 16.
[0039] For example, the greater the distance to the support 14, the greater the width of part 24b. By width of part 24b, we mean the distance between the lateral face of the region 24 closest to the region 16 and the opposite lateral face of part 24b. In other words, the portion of part 24a closest to the region 16 is located between part 24b and the support 14. The remainder of part 24a is not located between part 24b and the support 14.
[0040] The bipolar transistor 12 further comprises a layer 26 including a horizontal portion extending over a part of the upper face of the region 16 and a vertical portion extending over the lateral face of the portion 24b closest to the region 26. A central portion 16a of the upper face of the region 16 is not covered by the layer 26. The layer 26 is covered by a spacer 28. The spacer 28 does not cover said central portion 16a.
[0041] Layer 26 is, for example, made of the same material as layers 18 and 22. Spacer 28 is, for example, made of the same material as layer 20, but preferably with a different doping. Preferably, spacer 28 is made of amorphous silicon.
[0042] Part 24b is partially covered by insulating layers 30 and 32. The portion of part 24b closest to layer 26 is covered by insulating layers 30 and 32. Layer 30 is in contact with part 24b. Layer 32 at least partially covers layer 30. The lateral faces of layers 30 and 32 closest to layer 26 are preferably covered by layer 26. Layer 30 is, for example, made of the same material as layer 26, for example, silicon dioxide. Layer 30 is preferably made of a different insulating material than layer 32. For example, layer 32 is silicon nitride. A portion of the upper face of part 24b is not covered by layers 30 and 32. Preferably, the portion of the upper face of part 24b furthest from layer 26 is not covered by layers 30 and 32.
[0043] The device 10 comprises a layer 34 covering at least partially part of part 24a and at least partially part 24b. Preferably, the entire portion of the upper face of part 24b not covered by layer 30 is covered by layer 34. Layer 34 is, for example, made of a low resistivity material, for example a metal silicide, for example titanium silicide (TiSi), cobalt silicide (CoSi2), or nickel silicide (NiSi).
[0044] The transistor 12 includes an emitter region 36. The region 36 is made of a semiconductor material, for example silicon, for example epitaxial silicon. The region 36 is preferably doped with the same type of conductivity as the collector region (not shown). The region 36 is, for example, made of a polycrystalline material. The region 36 is for example made of polycrystalline or epitaxially monocrystalline silicon doped with arsenic or phosphorus.
[0045] Region 36 covers the central part of region 16 and is thus in contact with region 16. Region 36 also covers spacer 28, layer 26 and layer 32. Region 36 does not cover, and is not in contact with, layer 34 or region 24.
[0046] The upper face of the region 36 is covered by a layer 38. The layer 38 is, for example, made of the same material as the layer 34.
[0047] The device 10 further includes contact pads configured to provide bias voltages to the collector, base, and emitter. One contact pad is thus, for example, in contact with layer 38 so as to bias the emitter. Another contact pad is, for example, in contact with layer 34 so as to bias the base. Another contact pad is, for example, in contact with the substrate so as to bias the collector.
[0048] Since region 16 and part 24b are made of single-crystal materials, the interface between the intrinsic and extrinsic bases does not result in a significant increase in base resistance, unlike an interface between polycrystalline and single-crystal materials. Layer 34, covering parts 24a and 24b, does not significantly disrupt the electrical connection between the base contact pad and part 24b.
[0049] Fig. 2A, Fig. 2B, Fig. 2C, Fig. 2D, Fig. 2E, Fig. 2F, Fig. 2G, and Fig. 2H represent structures resulting from steps, preferably successive, of a manufacturing process for the device in Fig. 1.
[0050] Fig. 2A represents a structure resulting from a step in a manufacturing process of the device in Fig. 1.
[0051] During this step, the collector region 15 is formed in the support 14.
[0052] During this step, the insulating layer 18 is formed on the support 14. During In this step, layer 18 preferably completely covers the upper face 14a of layer 14.
[0053] Furthermore, the step in [Fig.2A] includes the formation of layer 20. Layer 20 covers layer 18. During this step, layer 20 preferably completely covers the upper face of layer 18. Layer 20 is thus completely separated from the support 14 by layer 18.
[0054] Fig. 2B represents a structure resulting from a step in a manufacturing process of the device in Fig. 1.
[0055] During this step, layer 20 is etched. More precisely, the portions of layer 20 located at the positions of layer 22 and region 16 are removed. Preferably, only the portions of layer 20 still present in the structure of [Fig. 1] are retained during the etching step of [Fig. 2B].
[0056] The step in [Fig.2B] further includes the formation, preferably over the whole structure, on the upper face of the structure of a stack 40 of insulating layers 44, 46, 48 and 50.
[0057] Layer 44 covers, and is preferably in contact with, layer 20 and the portion of layer 18 exposed by the etching step of layer 20. Layer 46 covers, and is preferably in contact with, layer 44. Layer 48 covers, and is preferably in contact with, layer 46. Layer 50 covers, and is preferably in contact with, layer 48.
[0058] Layer 44 is made of the same material as layer 22 of [Fig. 1]. Layer 44 is preferably made of the same material as layer 18, for example, silicon dioxide. Layer 48 is made of the same material as layer 30 of [Fig. 1]. Layer 48 is preferably made of the same material as layer 44, for example, silicon dioxide. Layer 46 is, for example, made of silicon nitride. Layer 50 is made of the same material as layer 32. Layer 50 is preferably made of the same material as layer 46. The materials of layers 44 and 48 and of layers 46 and 50 are preferably selectively etchable with respect to each other.
[0059] Fig. 2C represents a structure resulting from a step in a manufacturing process of the device in Fig. 1.
[0060] The step in [Fig. 2C] includes an etching step of a cavity 52. The cavity passes through layers 18, 44, 46, 48, and 50. Preferably, the cavity 52 does not extend into the substrate 14. Similarly, the cavity 52 does not extend into layer 20. The cavity 52 thus passes through layer 44 at a location where layer 20 has been etched. More precisely, the cavity 52, which corresponds to the emitter window, is located at the location of layer 26, spacer 28, and region 36.
[0061] The step in [Fig.2C] further includes a deoxidation step of layers 18 and 44. Thus, a cavity 54 is formed in layers 18 and 44 so as to remove layers 18 and 44 at locations in region 16.
[0062] Fig. 2D represents a structure resulting from a step in a manufacturing process of the device in Fig. 1.
[0063] During this step, region 16 is formed. More precisely, region 16 is formed at the location of the engraved portion of layers 18 and 44. Thus, region 16 is formed in cavity 54 and in the lower part of cavity 52, such that the upper face of region 16 is coplanar with the upper face of layer 44. Region 16 is formed, for example, by epitaxy.
[0064] Fig. 2E represents a structure resulting from a step in a manufacturing process of the device in Fig. 1.
[0065] During this step, a stack 55 of layers 56 and 58 is formed conformally on the structure resulting from the step in [Fig. 2D]. Layer 56 is in the The material of layer 26 is an insulating material, for example, silicon oxide. Layer 58 is made of the same material as spacer 28. The material of layer 56 is different from the material of layer 58. The thicknesses of layers 56 and 58 are chosen so that layers 56 and 58 do not fill cavity 52.
[0066] Fig. 2F represents a structure resulting from a step in a manufacturing process of the device in Fig. 1.
[0067] During this step, layer 58 is etched anisotropically. Spacer 28 is thus formed from layer 58. The portions of layer 56 not covered by spacer 28 are then etched to form layer 26.
[0068] During this step, a stack 59 of layers 60 and 62 is formed conformally on the structure resulting from the step in [Fig. 2E]. In particular, the stack 59 rests on layer 50, layer 26, spacer 28, and region 16. Layer 60 is made of the same material as region 36 so as to form the emitter region. Layer 62 is made of a passivation material, for example, the same material as layer 48, for example, silicon oxide.
[0069] Fig. 2G represents a structure resulting from a step in a manufacturing process of the device in Fig. 1.
[0070] The step in [Fig. 2G] includes an etching step of layers 50, 60, and 62. The etching is, for example, anisotropic etching. Layers 50 and 60 are etched to form region 36 and layer 32. Layer 62 is etched along the same plane. Thus, layer 62 resulting from the etching step in [Fig. 2G] completely covers the upper surface of region 36, preferably only the upper surface of region 36.
[0071] The step in [Fig. 2G] further includes the formation of an encapsulation layer 64. Layer 64 is, for example, made of the same material as layer 38. Layer 64 covers the lateral walls of layers 50, 60, and 62.
[0072] The step in [Fig.2G] further includes etching the portions of layer 48 not covered by layers 32 and 64. Layer 48 is thus etched so as to form layer 30. The emitter region is thus encapsulated by layers 26, 30, 62, 64.
[0073] The step in [Fig. 2G] further includes etching layer 46. Layer 46 is preferably removed entirely. In particular, the portion of layer 46 located between layer 30 and support 14, i.e., below layer 30, is removed. A portion of the intrinsic base region 16 is thus exposed.
[0074] The step in [Fig. 2G] further comprises etching layer 44 so as to form layer 22. More specifically, layer 44 is etched until layer 20 is exposed. Thus, the portion of layer 44 located at the same level as layer 20 Layer 20, that is, the layer located between layer 20 and region 16, is not etched. The layer 22 remaining after etching has a face coplanar with the upper face of layer 20.
[0075] The process further includes subsequent steps to the steps in [Fig.2G].
[0076] The process thus comprises the formation of the extrinsic base region 24. The The formation of region 24 is achieved through selective epitaxy. Thus, region 24 grows, by epitaxy, from the portion of region 16 exposed by the removal of layer 46 and from layer 20.
[0077] Epitaxial growth from region 16 allows the formation of part 24b. The growth of part 24b occurs from the upper surface of region 16. Thus, the contact between region 16 and part 24b is a vertical contact. Part 24b, like region 26, is made of a single-crystal semiconductor material.
[0078] Similarly, epitaxial growth from layer 20 allows the formation of part 24a. The growth of part 24a occurs from the upper surface of layer 20. Thus, the contact between layer 20 and part 24a is a vertical contact. Part 24a, like layer 20, is made of a polycrystalline semiconductor material.
[0079] The simultaneous growth of parts 24a and 24b ensures the shape of the interface between parts 24a and 24b. More precisely, the simultaneous growth ensures that part 24b extends further from layer 26 at the upper face of region 24 than at the lower face of region 24. A portion of the upper face of part 24a is thus exposed and is not covered by either layer 30 or part 24a.
[0080] The process includes removing layer 62. The process further includes forming layer 38 and layer 34. Layers 38 and 34 are, for example, made of the same material. Layers 38 and 34 are, for example, formed simultaneously by the formation of a single layer. Layer 38 thus covers the upper surface of region 36. Layer 34 covers part 24a and at least partially part 24b.
[0081] The process includes, for example, an additional step of forming spacers not shown on the side walls of layers 32 and 38 and of region 36.
[0082] During the manufacturing process steps of the device, the structure is heated, for example during annealing steps. During these steps, the dopants of layer 60, and subsequently of region 36, are diffused into the spacers 28. Thus, the spacers 28 gradually become part of region 36 during the manufacturing process.
[0083] Figures [Fig. 3A], [Fig. 3B], and [Fig. 3C] represent structures resulting from steps, preferably successive, of another manufacturing process for a device. 70 comprising a bipolar transistor according to another embodiment. More specifically, Figures 3A to 3C represent structures resulting from steps of a manufacturing process for a device comprising a bipolar transistor differing from transistor 12 in that the transistor of device 70 does not include the spacers 28.
[0084] The manufacturing process for device 70 comprises the steps of Figures 2A to 2D as described above.
[0085] Fig. 3A represents a structure resulting from a step in the manufacturing process of device 70, following the step in Fig. 2D.
[0086] The step in [Fig. 3A] differs from the step in [Fig. 2E] in that layer 58 is replaced by a layer 72 made of a material that can be selectively etched with respect to the material of layer 26, for example, silicon nitride. Layer 72 is preferably identical to layer 58 except for the difference in material.
[0087] Fig. 3B represents a structure resulting from a step in the manufacturing process of device 70.
[0088] During the step in [Fig. 3B], layer 72 is etched anisotropically. A spacer 74 is thus formed from layer 72. The spacer 74 is located at the position of spacer 28 of device 10. The spacer 74 differs from spacer 28 in that the spacer 74 is made of silicon nitride.
[0089] Figure 3C represents a structure resulting from a step in the manufacturing process of the device 70. The structure of Figure 3C results from the same steps that result in the structure of Figure 2F. More specifically, the stack 59 of layers 60 and 62 is formed conformally on the structure resulting from the step in Figure 3B. In particular, the stack 59 rests on layer 50, layer 26, and region 16. Layer 60 is made of the same material as region 36 so as to form the emitter region. Layer 62 is made of a passivation material, for example, the same material as layer 48, for example, silicon oxide.
[0090] Fig. 3D represents a structure resulting from a step in the manufacturing process of the device 70. During this step, the process includes the removal, for example by engraving, of the spacers 74. The process then includes the steps described in relation to Figures 2G and 2H.
[0091] One advantage of the described embodiments is that they allow for a reduction in the base resistance of the bipolar transistor. Indeed, the formation of an electrical bond between the base contact pad and the intrinsic base by layer 34 and portion 24b avoids the formation of an electrical bond across an interface between a monocrystalline semiconductor material and a polycrystalline semiconductor material.
[0092] Another advantage of the described embodiments is that they allow the cavity of the emitter to be filled with a single material.
[0093] An advantage of the embodiment shown in Figures 3A to 3C is that it allows for a reduction in the overall thickness of the bipolar transistor. This reduces the emitter resistance. Furthermore, it allows for a reduction in the width of the spacers located on the side walls of regions 36.
[0094] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.
[0095] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.
Claims
Demands
1. Method of manufacturing an electronic device (10, 70) comprising a bipolar transistor (12), the bipolar transistor comprising: - a collector region (15); - an emitter region (36); - an intrinsic base region (16), the intrinsic base region (16) being made of a single-crystal semiconductor material, the intrinsic base region (16) resting on an upper face of the collector region and the emitter region (36) resting on an upper face of the intrinsic base region (16); - an extrinsic base region (24, 24a, 24b), the extrinsic base region (24, 24a, 24b) comprising a first part (24b) made of a single-crystal semiconductor material and a second part (24a) made of a polycrystalline semiconductor material; and - a first layer (20) of a material on which it is possible to grow the material of the second part (24a) by epitaxy, the process comprising: a.the formation of the first part (24b) by epitaxial growth from the upper face of the intrinsic base region (16); and b. the formation of the second part (24a) by epitaxial growth from the upper face of the first layer (20).
2. Method according to claim 1, wherein the transistor comprises a second layer (34) of a silicide-type material covering at least partially the first part (24b) and covering at least partially the second part (24a).
3. Method according to claim 2, wherein the second layer (34) is in contact with the first part (24b).
4. Method according to claim 1 to 3, wherein the intrinsic base region (16) is in contact with the collector region and with the emitter region (36).
5. A method according to any one of claims 1 to 4, wherein the first layer (20) is separated from the intrinsic base region (16) by a portion (22) of insulating material.
6. A method according to any one of claims 1 to 5, wherein the transistor comprises a spacer (28) extending above the intrinsic base region (16), surrounding the interface zone between the emitter region (36) and the intrinsic base region (16).
7. A method according to claim 6, wherein the method comprises, prior to steps a and b: c. the formation of the collector region in a support (14); d. the formation of a stack of insulating layers (18, 44, 46, 48, 50) in which the first layer (20) is located; e. the formation in the stack of insulating layers (18, 44, 46, 48, 50) of a first cavity (52) traversing the stack of insulating layers (18, 44, 46, 48, 50) and of a second cavity (54) at the location of the intrinsic base region (16); f. the formation of the intrinsic base (16) in the second cavity (54); g. the formation of the spacer (28) along the walls of the first cavity (52).
8. A method according to claim 7, wherein the method comprises, before steps a and b and after step g: h. the formation of the emitter region (36); i. the encapsulation of the emitter region (36); and j. the etching of the layers of the insulating layer stack (18, 44, 46, 48, 50) so as to at least partially uncover the first layer (20) and the top face of the intrinsic base region (16).
9. A method according to any one of claims 6 to 8 or a device according to claim 7, wherein the spacer is made of polycrystalline silicon.
10. A method according to any one of claims 6 to 9, wherein the spacer is made of silicon nitride.
11. A method according to any one of claims 1 to 10, wherein the method comprises, after steps a and b, the formation of the second layer (34) at least partially on the first part (24b) and at least partially on the second part (24a).
12. A method according to any one of claims 1 to 11, wherein steps a. and b. are carried out simultaneously.
13. Electronic device (10, 70) comprising a bipolar transistor (12), the bipolar transistor comprising: - a collector region (15); - an emitter region (36); - an intrinsic base region (16), the intrinsic base region (16) being in a single-crystal semiconductor material, the intrinsic base region (16) resting on an upper face of the collector region and the emitter region (36) resting on an upper face of the intrinsic base region (16); - an extrinsic core region (24, 24a, 24b), the extrinsic core region (24, 24a, 24b) comprising a first part (24b) of a single-crystal semiconductor material and a second part (24a) of a polycrystalline semiconductor material; and - a first layer (20) of a material on which it is possible to grow the material of the second part (24a) by epitaxy, the first part (24b) resting on the upper face of the intrinsic base region (16) and the second part (24a) resting on the first layer (20).