METHOD FOR MANUFACTURING A MATRIX COMPRISING AT LEAST TWO MEMORY CELLS AND ASSOCIATED MATRIX

Abstract

The invention relates to a method for manufacturing a memory cell array comprising at least two memory cells, the method comprising the steps of: supplying a substrate; forming at least a first and a second cavity in the substrate; the first and second cavities being oriented such that the second cavity undergoes a rotation through a non-zero angle about an axis normal to the substrate with respect to said first cavity, said method comprising the following steps carried out in each of the cavities: deposition of a first conductive layer; deposition of an active layer; deposition of a second conductive layer; the method further comprising at least one ion implantation step such that the areas of the active layers exposed to the implantation of the first and second cavities, which are oriented differently, are different. Figure to be published with the abstract: none

Description

Title of the invention: METHOD FOR MANUFACTURING A MATRIX COMPRISING AT LEAST TWO MEMORY CELLS AND ASSOCIATED MATRIX TECHNICAL FIELD OF THE INVENTION

[0001] The present invention relates generally to the field of microelectronics. It relates more particularly to the field of non-volatile memories.

[0002] In particular, the invention relates to a method for manufacturing a memory cell matrix, notably based on ferroelectric materials. It also relates to a memory cell matrix. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0003] For applications which require information storage even when the electrical voltage is cut off, non-volatile memories of the EEPROM or FLASH type are conventionally used.

[0004] Other types of emerging non-volatile memories based on active materials such as ferroelectric materials (FeRAM memories) or materials such as oxides (OxRAM memories) constitute a promising alternative to FLASH or EEPROM type memories.

[0005] Ferroelectric memories of the FeRAM type (for "Ferroelectric Random Access Memory," according to the commonly used Anglo-Saxon acronym) have the main advantage of being non-volatile, meaning they retain stored information even when the power is turned off. They also offer the advantages of lower energy consumption and faster read and write times compared to other emerging or mature types of non-volatile memories such as FLASH memories.

[0006] Ferroelectric memories of the FeRAM type are generally in the form of a stack in which a layer of ferroelectric material is positioned between two metallic electrodes. Ferroelectric memories are capacitive type memories exhibiting two remanent polarization states, +Pr and -Pr. The operation of these memories relies on the properties of the ferroelectric material placed between the two metallic electrodes.

[0007] More particularly, concerning the operation of ferroelectric memories of the FeRAM type, by applying a potential difference between the two electrodes creating an electric field with a value greater than a positive coercive field +Ec, the ferroelectric memory is placed in a polarization state high remanent +Pr and by applying a potential difference creating an electric field with a value lower than the negative coercive field -Ec, the ferroelectric memory is placed in a low remanent polarization state -Pr. Thus, during memory writing, a current peak is measured during the reversal of the ferroelectric domains which occurs when the applied electric field is greater than the coercive field.

[0008] The high remanent polarization state +Pr then corresponds to the binary logic state '0' and the low remanent polarization state -Pr to the binary logic state '1', which allows the storage of information.

[0009] Moreover, when the application of the potential difference between the two metallic electrodes is stopped, the remanent polarization state remains: this then explains the non-volatile nature of ferroelectric memories.

[0010] For the read operation, it is assumed that the memory is in a given state and a voltage is applied. This voltage is, for example, positive, greater than the voltage creating an electric field with a value greater than the positive coercive field +Ec. Thus, if the memory was already in the high remanent bias state +Pr, this bias state remains unchanged and no current peak is observed (or a very small current peak may be observed). Conversely, if the memory was in the low remanent bias state -Pr, a much larger current peak is observed. The consequence of this read operation is that it is destructive of the bias state. It is therefore necessary to rewrite the initial bias state after the read operation if this state has been modified.

[0011] Ferroelectric memories of the FeRAM type can, for example, be integrated into memory arrays with which logical operations can be performed. In this case, each FeRAM memory is generally connected in series to a transistor T to form a 1T-1C type memory cell (or bitcell, according to English terminology) (for one transistor and one ferroelectric capacitive memory C). By way of illustration only, [Fig. 1] represents part of an array composed of two types of horizontal lines, word lines WL (World Line, according to English terminology) and source lines SL (Source Line, according to English terminology), and vertical lines, called bit lines BL (Bit Line, according to English terminology). Here, two memory cells are shown, each comprising a ferroelectric memory (C0 and C1) and a transistor (T0 and T1) in series.The WL lines are connected to the transistor gates to activate them. The BL bit lines are connected to the transistor sources or drains, and the source lines are connected to the ferroelectric memory electrode not connected to the series transistor. Figure 1 also shows a simplified equivalent dielectric capacitance CBL of the BL bit line. A cell is read in [Fig. 1]. Applying a voltage pulse higher than the voltage creates an electric field with a value greater than the coercive field on the SL line. It is possible to read both cells T1-Cl and T2-C2 simultaneously (parallel reading). This reading is performed, for example, using a Voltage Sense Amplifier (SA) located at the end of the BL line. The SA has two inputs and allows comparison of an external reference voltage Vref to the VBL voltage. Thus, depending on the measured VBL voltage and the chosen reference voltage Vref, it is possible to perform logical operations, such as AND or OR operations.The VBL voltage corresponds approximately to the sum of the voltages across the two capacitive ferroelectric memories CO and CL. It should be noted, of course, that other memory layout configurations are also possible, in which, for example, the SL is parallel to the BL, or the accumulation occurs at the SL source line and not at the BL bit line. Figure 2 shows the value of the VBL voltage as a function of the logic states "0" or "1" of the ferroelectric memories CO and Cl: VBL is a voltage that depends on the capacitance sharing between the capacitors of the memories CO and Cl and the capacitor CBL.During the read operation of a ferroelectric memory, the state "0" can be considered to consist only of the dielectric charge of the capacitor, while the state "1" is the sum of this dielectric charge and the ferroelectric contribution (obtained during the prior programming of the memory), thus resulting in an increase in the voltage across the memory. Figure 2 shows four values ​​of VBL corresponding to the logical combinations "00", "01", "10", and "11" of the two ferroelectric memories CO and CL. By choosing a relevant value for the reference voltage Vref, it is possible to perform a logical operation on the logical states of the CO and CL memories: the voltage Vref,AND allows for an "AND" operation, while the voltage Vrefj0R allows for an "OR" operation. This operation is performed by comparing the voltage VBL to the reference voltage. The table shown in Figure 2 illustrates this.Figure 3 shows that both operations are indeed performed according to the chosen reference voltage (A representing the logic state of memory CO and B the logic state of memory Cl). However, Figure 2 also shows that it is not possible to distinguish between the two states "01" and "10," which correspond to approximately the same voltage VBL. In other words, the contribution to the voltage VBL is the same for both memory points. This result is quite understandable since the ferroelectric memories C0 and Cl are identical in terms of both the materials used and their geometry. Furthermore, in state "1," it can be shown that the value of... The voltage of each ferroelectric memory depends directly on the surface area S of the active ferroelectric layer forming the memory.

[0012] A solution that would allow discrimination between two memory locations with different bit weights (i.e., with different voltage contributions) could consist of designing ferroelectric memories of different sizes. Figure 4 shows a matrix of three planar ferroelectric memories, each memory being made by stacking a lower TiN electrode, a ferroelectric layer of Hfo.5Zro.5O2 (HZO), and a top TiN layer. The three memories differ from one another in that the surface area of ​​the ferroelectric active layer is different for each memory, ranging from an area of ​​S for the first memory to an area of ​​S / 2 for the second and an area of ​​S / 4 for the third.

[0013] The disadvantage of such a solution based on planar layers is that it results in a large surface footprint.

[0014] To reduce this footprint, one solution is to use a three-dimensional (3D) approach. In other words, as illustrated in [Fig. 5], the ferroelectric memories are fabricated in 3D cavities to reduce the overall footprint and provide a ferroelectric active layer surface that extends both to the bottom of the cavity and to the lateral surfaces. [Fig. 5] thus shows three ferroelectric memories M1, M2, and M3, each fabricated as a cavity comprising, successively, a lower TiN electrode, a ferroelectric HZO layer, and an upper TiN layer. Each of the three memories has a different aspect ratio defined by the ratio h / l1, where h1 is the height of the memory M1 relative to the base plane and l1 is the width of the memory M1 (or the diameter in the case of a circular bottom surface).Such a solution reduces the footprint while maintaining the capacity value by utilizing the lateral surfaces of the cavities. However, there are also some drawbacks, particularly regarding the manufacturing process: cavities of different widths are not etched at exactly the same speed; filling the cavities with a conductive material is more complex than depositing it on a flat surface.

[0015] It may also prove useful to have on the same matrix a cointegration of OxRAM memories and FeRAM memories due to the limitation either in reading for FeRAM or in writing for OxRAM.

[0016] OxRAM, or "oxide-based RAM," is a non-volatile resistive memory. This memory can exhibit at least two resistive states, corresponding to a highly resistive state ("HRS" for "High Resistance State") and a low resistance state. Low resistance state (LRS) under the application of a voltage. OxRAM memories have a MIM (Metal-Insulator-Metal) structure comprising an active material with variable electrical resistance, generally a transition metal oxide (e.g., WO3, HfO2, Ta2O5, TiO2...), sandwiched between two metallic electrodes. One of the two electrodes often has a metallic layer, for example, made of Ti, which creates oxygen vacancies in the active layer of the OxRAM, based, for example, on hafnium dioxide, when this conductive layer is in contact with the active layer of the OxRAM. The transition from the HRS to the LRS state is governed by the formation and breaking of a conductive filament between the two electrodes. This conductive filament is created by the presence of oxygen vacancies in the active layer of the memory.By changing the potentials applied to the electrodes, it is possible to modify the filament distribution, and thus modify the electrical conduction between the two electrodes. In the active layer, the electrically conductive filament is either broken or, conversely, reformed to vary the resistance level of the memory cell, during cycles of writing and then resetting this cell (SET operations, when the filament is reformed resulting in the LRS state, and RESET operations resulting in the HRS state, when the filament is broken again by applying a SET voltage, VSet or RESET voltage, Vreset, respectively to the electrode terminals). The use of filamentary memory includes a "forming" stage, during which the filament is formed for the first time in the active layer, which is initially filamentless. The active layer is initially completely electrically insulating. During the initial "forming" stage, an electrically conductive filament is formed within the active layer, essentially creating a controlled breakdown of this layer. The filament thus formed then extends completely through the active layer, electrically connecting the lower and upper electrodes. To achieve this forming stage, one can, for example, apply an electrical voltage between the lower and upper electrodes of the memory cell, and then gradually increase the value of this voltage until a threshold voltage, called the forming voltage (Vforming), is reached, beyond which the active layer breaks down.After this "forming" stage, the memory cell is ready for use. The conductive filament can then be broken, then reformed, then broken again, and so on, at a voltage value lower than the forming voltage (Vforming).

[0017] OxRAM memories have the main qualities of being non-volatile, that is to say, retaining the stored information even when the power is turned off, and of having short read and write times compared to other types of memory. non-volatile such as FLASH memories, can be massively integrated onto chips due to the reduced spatial dimensions and thinness of the active layers and allow for "back end" integration compatible with CMOS technology.

[0018] The cointegration of OxRAM and FeRAM memories on the same chip relies on relatively complex manufacturing processes which can be improved. Summary of the invention

[0019] The present invention aims to propose a method for manufacturing a matrix comprising three-dimensional memory cells having different active surfaces, said method being simpler to implement than the solutions presented previously.

[0020] The invention relates in particular to a method for manufacturing a memory cell matrix comprising at least two memory cells, the method comprising the steps of: - provision of a substrate; - formation of at least one first and a second cavities in the substrate; the first and second cavities being oriented such that the second cavity undergoes a rotation through a non-zero angle around an axis of direction normal to the substrate with respect to said first cavity, said method comprising the following steps implemented in each of the cavities: - deposition of a first conductive layer; - deposition of an active layer; - deposition of a second conductive layer; the process further comprising at least one ion implantation step so that the areas of the active layers exposed to the implantation of the first and second cavities, oriented differently, are different.

[0021] An active layer is understood to be a memory layer, that is to say a layer made of a material having the ability to switch reversibly and non-volatilely between two physical states varying a specific property (conductance, capacitance...).

[0022] Thanks to the invention, ion implantation is used to amorphize a portion of the active layer of each memory cell, thereby removing the properties of that portion of the active layer, for example, its ferroelectric nature. By operating in this way, the developed active area is reduced. With at least one constant and identical implantation step for each cavity, the invention allows Furthermore, this results in different non-amorphized surfaces. By rotating the cavities relative to each other, the implantation will act on different surfaces due to the different orientations of the cavities, creating different amorphizations and therefore different developed active surfaces. Thus, in the case of a matrix containing ferroelectric memory cells, the active layer of each FeRAM-type memory is a ferroelectric layer crystallized in an orthorhombic state or an antiferroelectric layer crystallized in a tetragonal state: at least one implantation will amorphize certain crystallized areas of each layer by removing its ferroelectric or antiferroelectric properties, but the amorphization will not occur in the same locations on the surface for the two active layers. In this way, two memory cells with different active surfaces but with identical dimensions and materials are obtained.

[0023] In addition to the characteristics mentioned in the preceding paragraphs, the process according to the invention may have one or more additional characteristics from among the following, considered individually or in all technically possible combinations:

[0024] Each of the first and second conductive layers are metallic layers.

[0025] Each of the said first and second cavities: • has the same geometry and dimensions; • comprises a side wall and a bottom wall, said bottom wall having a plurality of sides, at least two of which have different lengths.

[0026] Thus, the method according to the invention uses at least two cavities that are identical from a geometric and material point of view, but these two cavities are rotated relative to each other. Since the base of each cavity has at least two sides of different lengths (i.e., the base of the cavity is neither square nor circular, for example), the areas of each active layer seen by the implant are different, even with identical cells. According to this embodiment, the angle of rotation of the second cavity relative to the first is not equal to 180° in order to avoid the same areas being exposed.

[0027] The bottom wall has a shape with an even number of sides formed by a plurality of opposite sides of the same length, with at least two pairs of sides having different lengths.

[0028] The memory cells are at least partly ferroelectric FeRAM memories, the active layer being a ferroelectric or antiferroelectric layer.

[0029] The memory cells are at least partly OxRAM memories, the active layer being a metal oxide-based layer.

[0030] The memory cell matrix comprises at least one FeRAM memory and at least one OxRAM memory. According to this latter embodiment, a cointegration of FeRAM and OxRAM memory cells is therefore obtained.

[0031] The active layer material is hafnium dioxide HfO2 doped with Si or an HfxZri alloy XO2, with 0 <x<l ou du nitrure d’aluminium et de scandium AIScN. On notera que le matériau de la couche active tel que le dioxyde d’hafnium HfO2 peut également être dopé avec l’un des éléments suivants : N, Gd, Y, Sc, Ge avec un pourcentage de dopage compris entre 0 et 10% et préférentiellement entre 0.5 et 3%.

[0032] The implantation dose is between 1.1014cm2 and 1.1017cm2 and the acceleration voltage is between 0.2kV and 1OkV.

[0033] The implantation for the purpose of amorphizing the active layer is carried out from one of the following atoms: Ge, As, Sb, In, P, Si, Ga, C or B.

[0034] The method according to the invention comprises two ion implantation steps in two different directions to target different surfaces of each of the active layers.

[0035] The first implantation is carried out with a rotation angle of the substrate in the plane of the substrate of 0° and the second implantation is carried out with a rotation angle of the substrate in the plane of the substrate of 180°. In this case, the conditions relating to the second implantation are preferably identical to those of the first implantation, only the rotation angle of the substrate being modified.

[0036] The implantation is carried out with an angle of inclination between the ion beam and the normal to the surface of the substrate strictly less than 90° and preferably between 10 and 40°.

[0037] The first and second cavities are oriented so that the second cavity undergoes a rotation of an angle of 90° around an axis of direction normal to the substrate with respect to said first cavity.

[0038] According to a first embodiment, the implantation can be carried out through the second conductive layer using an accelerating voltage high enough to pass through it.

[0039] According to a second embodiment, the process according to the invention comprises the steps of: • removal of the second conductive layer, the implantation being carried out directly in the active layer after removal of the second conductive layer; • Deposition of a new conductive layer on the active layer after implantation.

[0040] The invention also relates to a matrix comprising at least two memory cells including: - at least one first and one second cavity in a substrate, the first and second cavities being oriented such that the second cavity has a rotation through a non-zero angle about an axis normal to the substrate with respect to said first cavity, each of the first and second cavities comprising: • a first conductive layer forming a lower electrode; • an active layer; • a second conductive layer forming an upper electrode; the active layers of the first and second cavities having different implanted areas. BRIEF DESCRIPTION OF THE FIGURES

[0041] Other features and advantages of the invention will become clear from the description given below, by way of example and not limitation, with reference to the accompanying figures, among which:

[0042] [Fig.1] illustrates part of a ferroelectric memory matrix in a 1T-1C configuration,

[0043] [Fig.2] represents the bit line voltage values ​​as a function of the logic states of the memories in [Fig.1],

[0044] [Fig.3] is a table showing the results of two logical operations "and" and "or » produced from the matrix of [Fig.1],

[0045] [Fig.4] shows a schematic cross-sectional view of planar ferroelectric capacitors with different HZO-based active surfaces,

[0046] [Fig.5] illustrates a schematic cross-sectional view of three-dimensional ferroelectric capacitors with different HZO-based active surfaces,

[0047] [Fig.6] shows a top view and a top view of an implantation simulation illustrating the method according to the invention, which will be detailed with reference to Figures 7 to 18,

[0048] [Fig.7], [Fig.8], [Fig.9], [Fig.10], [Fig.11] and [Fig.12] illustrate the different stages of the process according to a first embodiment of the invention,

[0049] [Fig. 13], [Fig. 14], [Fig. 15] and [Fig. 16] illustrate the different stages of the process according to a second embodiment of the invention,

[0050] [Fig. 17] illustrates a variant of the method according to the invention,

[0051] [Fig. 18] illustrates a variant of the process according to the invention.

[0052] For clarity, identical or similar elements are identified by identical reference signs throughout the figures. DETAILED DESCRIPTION

[0053] The present invention aims to improve the manufacture of memory cells, in particular ferroelectric ones.

[0054] Figure 6 shows a top view and a side view of an implantation simulation illustrating the method according to the invention, which will be detailed with reference to Figures 7 to 18.

[0055] Fig. 6 shows two cavities 10 and 20 in top view and side view.

[0056] Each of the cavities 10 and 20 comprises: • a back wall 11 and 21 • two side walls, respectively 12 and 13 for cavity 10 (references 12 and 13 representing each side of the side wall of cavity 10) and 22 and 23 for cavity 20 (references 22 and 23 representing each side of the side wall of cavity 20).

[0057] Each of the cavities 10 and 20 is hollow and advantageously initially made of the same material, for example ferroelectric (i.e., the side walls and the bottom wall). As a reminder, to obtain ferroelectric properties, the active material is most often a material crystallized in an orthorhombic or tetragonal phase.

[0058] By way of illustration only, the side walls of each of the cavities are inclined at the same non-zero angle with respect to the normal to the base wall, it being understood that the invention also applies to a non-inclined wall (i.e. normal to the plane of the substrate).

[0059] The cavities 10 and 20 are preferably, but not exclusively, strictly identical in terms of geometry, and the active material from which they initially compose is the same. The bottom walls 11 and 21 here have, for illustrative purposes only, a rectangular shape with a width L and a length 1. The width L is different from the length 1. We will see later that the bottom walls can have a more complex shape.

[0060] As illustrated in [Fig.6], the two identically shaped cavities 10 and 20 are rotated relative to each other by a non-zero angle, here 90°.

[0061] The invention is based on the performance of at least one ion implantation step in a given direction carried out both on the active layer forming the cavity 10 and on the active layer forming the cavity 20.

[0062] In the present case, two successive ion implantations 14 and 15 are made on each of the active layers of the cavities 10 and 20.

[0063] For the record, two implantation angles can be defined as necessary to parameterize the ion beam with respect to the crystal lattice. These angles are the tilt angle (T) and the twist angle (R). The tilt angle (T) is the angle between the ion beam and the normal to the surface of the target substrate, here the plane of the base wall. The twist angle (R) is the angle between the projection of the incident beam onto the plane of the substrate and the axis of the substrate's flat or notch (here represented by line AA').

[0064] The first ion implantation 14 is carried out with a twist angle equal to 0 and a non-zero tilt angle (the tilt angle may be zero in the present case).

[0065] The second ion implantation 15 is carried out with the same tilt angle as the first ion implantation 14 and a twist angle of 180°.

[0066] By operating in this way, it is observed that each of the ion implantations will reach different surface areas of the cavities 10 and 20. These surface areas are represented by hatched areas 16 (for cavity 10) and 17 (for cavity 20).

[0067] We will describe in more detail the implantation conditions with reference to the figures describing the whole process.

[0068] The ion implantations 14 and 15 will amorphize (i.e., cause the loss of crystallographic, and therefore ferroelectric, properties) the material of the active layers. By varying the orientation of the cavities (one being rotated relative to the other, here by 90°), a different amorphization is created, resulting in different developed ferroelectric surfaces.

[0069] It should be noted that a single implantation in a given direction (14 or 15) also allows obtaining a different amorphization on the surfaces of the cavities 10 and 20. On the other hand, it is advisable not to carry out four implantations, one with a twist angle of 0°, one with a twist angle of 90°, one with a twist angle of 180° and a last one with a twist angle of 270°: in this case, the surfaces reached on the two cavities would be identical.

[0070] Figures 7 to 12 illustrate the different stages of the manufacturing process according to a first embodiment of the invention.

[0071] As can be seen in [Fig. 7], the manufacturing process first comprises a step 100 of supplying a substrate or support layer 200 on which the ferroelectric memory cell array will be formed. This support layer 200 is provided with a connection layer 201 for connecting the ferroelectric memory cells to lower metallic levels. It should be noted that this support layer 200 may include components already present, for example, selection transistors on a first level.

[0072] The manufacturing process then proceeds to a step 101 ([Fig. 8]), in which two cavities 202 and 203 (in which two ferroelectric memory cells 100 will be formed) are created. This step 101 is carried out by anisotropic etching to form the bottom walls 204, 206 and the side walls 205, 207 of the respective cavities 202 and 203. This is, for example, a dry chemical etching.

[0073] As described previously, the side wall of each cavity is made so as to form a non-zero angle of inclination with respect to the normal to the bottom wall.

[0074] The etching masks are advantageously chosen so that the two cavities 202 and 203 have identical geometry but are rotated 90° relative to each other. It should be noted that the invention could also be applied with different masks to obtain cavities of different geometries; however, the method according to the invention finds a particularly interesting application for the production of memory cells of the same geometry and made of the same material. The 90° angle is given by way of illustration only; the invention applies as long as the cavities are rotated at a non-zero angle relative to each other. Furthermore, the bottom walls 204 and 206 of the respective cavities 202 and 203 have a rectangular shape with a length 1 different from the width L.

[0075] The manufacturing process then proceeds with a step 102 in [Fig. 9] of deposition, preferably conformal, of a first conductive layer 208 (respectively 211), a ferroelectric active layer 209 (respectively 212), and a second conductive layer 210 (respectively 213) in the cavity 202 (respectively 203). In this description, "conformal deposition" means a deposition carried out in such a way that the layer has a substantially constant thickness at every point. The first conductive layers 208 and 211 will form the lower electrodes ("bottom electrode" in English terminology) of the memory cells, and the second conductive layers will form the upper electrodes ("top electrode" in English terminology) of the memory cells.

[0076] The material of the first conductive layers 208, 211 can be, for example, W, a Ti / TiN bilayer, or TiN. The material of the second conductive layers 210, 213 can be W or TiN.

[0077] The active layers 209, 212 are here layers of ferroelectric material, for example based on hafnium dioxide HfO2. Hafnium dioxide can be doped with a dopant element. Here, the dopant element preferably used is silicon Si.

[0078] Alternatively, the ferroelectric material layer may comprise an alloy of the form HfxZri XO2, with 0 <x<l. Par exemple, il est possible d’utiliser un alliage ternaire comme le Hf0.5Zro.502 en tant que matériau ferroélectrique.

[0079] In certain cases, it may be necessary to then carry out a heat treatment on the stack of the three layers so that the active layer crystallizes in a phase giving it ferroelectric properties, for example orthorhombic or tetragonal.

[0080] The manufacturing process then continues in step 103 ([Fig. 10]), during which a first ion implantation 214 is performed in a manner similar to the first ion implantation described with reference to [Fig. 6]. The first ion implantation 214 is performed with a twist angle of 0 and a tilt angle that is not zero (but may be zero). It should be noted that the tilt angle is preferably between 10° and 40° so as to be sufficient for the ion beam to reach the side walls but not so high as to prevent the beam from reaching the back wall.

[0081] The atoms chosen for implantation are preferably heavy species, for example Ge, As, or Sb, it being understood that lighter species can also be used within the scope of the invention, for example B. Since the objective is to amorphize the implanted areas of the active layers 209 and 212, it is necessary to choose accelerating voltages and implantation doses adapted to penetrate the second conductive layer to reach the active layer. We will see in the second embodiment that direct implantation into the active layer is also possible within the scope of the invention.

[0082] Preferably, the implantation dose is between 1.101 4 cm 2 and 1.1017 cm2, for example on the order of 1.1015 cm 2. The implantation dose will be higher the lighter the species implanted.

[0083] Preferably, the acceleration voltage will be between 0.2kV and 10kV, for example on the order of 1kV. The acceleration voltage will be higher the heavier the implanted species.

[0084] The manufacturing process continues in step 104 ([Fig. 11]), during which a second ion implantation 215 is performed, identical to the second ion implantation described with reference to [Fig. 6]. The second ion implantation 215 is performed with a twist angle of 180° and a tilt angle that is non-zero and identical to that of the first implantation (but may be zero). The atoms chosen for implantation, the dose, and the accelerating voltage for this second implantation are preferably identical to those of the first implantation 214.

[0085] As described with reference to [Fig.6], different surfaces with ferroelectric properties are thus obtained for each of the active layers 209 and 212 with identical geometry and cavity materials.

[0086] The process according to the first embodiment of the invention then continues with a step 105 ([Fig. 12]) of filling each of the cavities with a material metallic 216, for example W, followed by a CMP (Chemical Mechanical Polishing) step.

[0087] At the end of the manufacturing process according to this first embodiment, a matrix 217 is thus obtained comprising at least two memory cells 218 and 219 (it being understood that the invention is not limited to two, the matrix being able to comprise more than two devices), here ferroelectric FeRAM devices, comprising: - at least one first and a second cavity 202 and 203 formed in a support layer 200, each of the first and second cavities: • having the same geometry and dimensions; • comprising a side wall and a bottom wall, said bottom wall having a plurality of sides, at least two of which have different lengths; • a first conductive layer 208, 211 forming a lower electrode; • an active layer 209, 212, here ferroelectric; • a second conductive layer 210, 213 forming a top electrode.

[0088] The first and second cavities are arranged so that the second cavity is rotated (here by 90°) with respect to the first cavity along an axis of direction normal to the support layer 200. The active layers each have a different implanted surface: in the case of ferroelectric layers, the layers will have a different part of their surface amorphized, thus losing its ferroelectric properties.

[0089] Figures 13 to 16 illustrate the different stages of the manufacturing process according to a second embodiment of the invention.

[0090] The first three steps of the process according to this second embodiment are not illustrated and are identical to steps 100, 101 and 102 of figures 7 to 9.

[0091] The process then continues with a step 300 illustrated in [Fig. 13] during which the second conductive layers 210 and 213 are removed, for example by etching. It should be noted that the presence of the second conductive layer can be important during a possible annealing process that confers the ferroelectric properties (and the appropriate crystallization) of the active layer 209, 212, which is why it is deposited and then removed.

[0092] The process then includes a first implantation step 301 222 ([Fig. 14]) similar to step 103 of [Fig. 10], the only difference being that the first implantation 222 is done directly in the active layer 209, 212 allowing more efficient control of the implantation in the active layer without going through the second conductive layer 210, 213 as in the case of [Fig. 10].

[0093] The process continues with a second implantation step 302 223 ([Fig. 15]) similar to step 104 of [Fig. 11], the only difference being that the second implantation 223 is done directly in the active layer 209, 212.

[0094] The process then involves depositing a new conductive layer 220 (intended to replace the layer 210 which has undergone a withdrawal) on the active layer 209 in the cavity 202 and a new conductive layer 221 on the active layer 212 in the cavity 203; the conductive layers 220 and 221 respectively act as the upper electrode of the memory cells of the matrix.

[0095] The process then continues with a step of filling each of the cavities with a metallic material 216, for example W, followed by a CMP (Chemical Mechanical Polishing) step as in the case of [Fig. 12].

[0096] At the end of this step, a matrix 217 similar to that of [Fig. 12] is obtained.

[0097] Up to now, the bottom wall has been described with a substantially rectangular shape. The invention is not limited to such a shape and can be applied to more complex shapes to allow working in several directions.

[0098] Thus, [Fig. 17] illustrates the case of a top view of three bottom walls 401, 402, and 403 of the same geometry, simply rotated relative to each other by a non-zero angle. [Fig. 17] also shows the arrows illustrating the two installations 404 and 405 of the same type as those described with reference to [Fig. 6].

[0099] It should be noted that it is thus possible, starting from the same complex geometry, to amorphize different surfaces of the three parts by rotating them relative to each other. As before, the shape of each of the bottom walls has at least two sides of different lengths. Advantageously, the bottom wall has a shape with an even number of sides formed by a plurality of pairs of sides of the same length, with at least two pairs of sides having different lengths. Advantageously, the sides of the same pair are parallel to each other. In the case of a rectangle ([Fig. 6]), there are two pairs of sides, and in the case of [Fig. 17], there are 6 sides formed by 3 pairs of sides. The hatched areas 406, 407, and 408 represent the amorphized areas, while the solid lines 409, 410, and 411 represent the areas that remained ferroelectric after installation.As can be seen, the remaining ferroelectric surfaces are different for the three memory cells associated with the respective bottom walls 401, 402 and 403.

[0100] It should be noted that it is also possible to implement the method according to the invention by combining it with a variation in size or geometry of the cavities produced. In other words, as illustrated in [Fig. 18], the method can be implemented on two first cavities 501 and 502 identical in terms of geometry and materials (as in Figures 6 to 16) and on two second cavities 503 and 504 They are also identical in terms of geometry and materials but different from the first two cavities, for example in terms of dimensions. Here we see that the rectangular back walls of the first cavities are wider and longer than the rectangular back walls of the second cavities.

[0101] Although the invention has been more specifically described in the case of ferroelectric memory cells (FeRAM), the invention could also be applied to other types of memory cells, for example, resistive metal oxide memories (OxRAM), for which the active layers of at least two cells are modified by implantation, with the surfaces of the active layers being implanted on different areas. The implantation can, for example, improve or degrade the performance (forming voltage, endurance, variability) of an OxRAM; thus, by implanting two respective active layers of two OxRAMs differently, it is possible to obtain two OxRAMs with different properties.Another possible application is the cointegration of FeRAM memories with OxRAM memories: one way to achieve this is to start from the same active layer material for both OxRAM and FeRAM by carrying out a different doping depending on the type of memory (FeRAM or OxRAM): thus, thanks to the invention, it is possible to implant and therefore dope two memory cells differently by acting on the effective area of ​​the implanted active layer and thus to obtain depending on the type of implantation either a FeRAM memory or an OxRAM memory.

Claims

Demands

1. A method for manufacturing a memory cell array comprising at least two memory cells, the method comprising the steps of: - supplying a substrate; - forming at least a first and a second cavity in the substrate; the first and second cavities being oriented such that the second cavity undergoes a rotation through a non-zero angle about an axis of direction normal to the substrate with respect to said first cavity, said method comprising the following steps carried out in each of the cavities: - deposition of a first conductive layer; - deposition of an active layer; - deposition of a second conductive layer; the method further comprising at least one ion implantation step such that the areas of the active layers exposed to the implantation of the first and second cavities, which are oriented differently, are different.

2. A method according to the preceding claim in which the first and second conductive layers are metallic layers.

3. A method according to any one of the preceding claims wherein each of said first and second cavities: - has the same geometry and the same dimensions; - comprises a side wall and a bottom wall, said bottom wall having a plurality of sides of which at least two sides have different lengths.

4. Method according to the preceding claim characterized in that the bottom wall has a shape with an even number of sides formed by a plurality of opposite sides of the same length, at least two pairs of sides having different lengths.

5. A method according to any one of the preceding claims characterized in that the memory cells are at least partly ferroelectric FeRAM memories, the active layer being a ferroelectric or antiferroelectric layer.

6. A method according to any one of the preceding claims characterized in that the memory cells are at least partly OxRAM memories, the active layer being a metal oxide-based layer.

7. Method according to claim 5 and claim 6 characterized in that the memory cell matrix comprises at least one FeRAM memory and at least one OxRAM memory.

8. A method according to any one of the preceding claims, characterized in that the active layer material is hafnium dioxide HfO2 doped with Si or an HfxZri alloy XO2, with 0 <x<l ou du AIScN.

9. A method according to any one of the preceding claims characterized in that the implantation dose is between 1.1014cm2 and 1.1017cm2 and the implantation acceleration voltage is between 0.2kV and 10kV.

10. A method according to any one of the preceding claims characterized in that the implantation is carried out from one of the following atoms: Ge, As, Sb, In, P, Si, Ga, C or B.

11. A method according to any one of the preceding claims characterized in that it comprises two ion implantation steps in two different directions to target different surfaces of each of the active layers.

12. Method according to the preceding claim characterized in that the first implantation is carried out with a rotation angle of the substrate in the plane of the substrate of 0° and the second implantation is carried out with a rotation angle of the substrate in the plane of the substrate of 180°.

13. A method according to any one of the preceding claims characterized in that the implantation is carried out with an angle of inclination between the ion beam and the normal to the surface of the substrate strictly less than 90° and preferably between 10 and 40°.

14. A method according to any one of the preceding claims characterized in that the first and second cavities are oriented such that the second cavity undergoes a rotation through an angle of 90° about an axis of direction normal to the substrate with respect to said first cavity.

15. A method according to any one of the preceding claims characterized in that the implantation is carried out through the second conductive layer.

16. A method according to any one of claims 1 to 14 characterized in that it comprises the steps of: - removal of the second conductive layer, the implantation being carried out directly in the active layer after removal of the second conductive layer; - deposition of a new conductive layer on the active layer after implantation.

17. Matrix comprising at least two memory cells comprising: - at least a first and a second cavity in a substrate, the first and second cavities being oriented such that the second cavity has a rotation of a non-zero angle about an axis of direction normal to the substrate with respect to said first cavity, each of the first and second cavities comprising: • a first conductive layer forming a lower electrode; • an active layer; • a second conductive layer forming a upper electrode; the active layers of the first and second cavities having different implanted areas.

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