Three-dimensional photonic chip architecture based on vcsel array, application, and method for calculating structure of dnns
Patent Information
- Application Number
- GB2024017109
- Authority / Receiving Office
- GB · GB
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2022-07-27
- Filing Date
- 2023-03-29
- Publication Date
- 2025-01-01
AI Technical Summary
Existing DNNs optical chips are difficult to miniaturize and integrate, and the light between VCSEL array units is incoherent, making it impossible to use traditional algorithms for DNNs structure design, resulting in low data input rates and inability to meet high-speed data input requirements.
Adopt a three-dimensional photonic chip architecture based on VCSEL array, integrate the DNNs structure through the addressable VCSEL array as the data input layer, use 3D printing and microelectronics process manufacturing to achieve chip integration, and develop a DNNs structure design method specifically for VCSEL arrays. Including constructing the output light field and using the backpropagation algorithm for iterative optimization.
It achieves on-chip all-optical integration of DNNs, reduces the chip size, increases the data input rate to more than 106 times that of existing DNNs, reduces energy consumption, and is suitable for applications such as face recognition, optical computing, and image classification.
Abstract
Description
Three-dimensional photonic chip architecture and applications based on VCSEL arrays, and DNNs structure calculation methods
[0001] This application claims the priority of Chinese patent application No. 202210893985.X filed on July 27, 2022, entitled “Three-dimensional photonic chip architecture and application based on VCSEL array, and DNNs structure calculation method”. The entire content of the Chinese patent application is incorporated into this application by reference. Technical Field
[0002] The embodiments of the present application relate to the technical field of integrated circuits, and specifically to a three-dimensional photonic chip architecture and application based on a VCSEL array, and a DNNs structure calculation method. Background Art
[0003] With the rapid development of artificial intelligence (AI), the computing speed of current electronic chips based on the von Neumann architecture is increasingly insufficient to meet the demands of AI computing. Furthermore, their excessive energy consumption could pose a serious energy crisis in the future. To address this issue, neuromorphic computing, which is based on the human brain architecture and implemented in hardware, is gaining popularity. Among these, optical neural networks (PNNs) are a type of neuromorphic computing that uses light as an information carrier. PNNs operate at the speed of light, and because light propagation is generally passive and energy-free, PNNs offer significant advantages over traditional electronic chips in terms of speed and energy efficiency, and are widely considered the next generation of computing chips.
[0004] Currently, various types of PNNs have been developed, and diffractive neural networks (DNNs) are a unique type of optical network with a three-dimensional architecture. DNNs build neuronal connections based on the diffraction of light. Compared to other PNNs, their three-dimensional architecture has the advantages of high neuronal density and suitability for processing two-dimensional optical data. For example, when performing tasks such as image classification, DNNs do not need to flatten two-dimensional images into one-dimensional time series data like other two-dimensional PNNs or electronic chips, but can directly perform image classification tasks. Therefore, their execution speed is far superior to other types of optical networks.
[0005] However, DNNs currently face the dilemma of being difficult to miniaturize, integrate, and chip-on. Existing DNNs all work by building a relatively large optical path through various spatially separated optical instruments. Even though there have been studies to integrate DNNs with CMOS imaging chips, they still require large lasers and masks for optical image input when performing data input, which is not practical. The volume of the entire working optical path of reported DNNs is tens of centimeters or even above the meter level. In addition, the adjustable data input devices used in existing DNNs are spatial light modulators or digital micromirror arrays, whose maximum modulation rate is only kHz, which is far lower than the frequency of existing electronic chips and cannot meet the needs of high-speed data input.
[0006] The integration of DNNs into chips is crucial for promoting their application and is a pressing challenge. This is due to the lack of an integrated platform or suitable chip architecture suitable for three-dimensional DNNs. The inventors recognized that existing electronic and optical chips are all two-dimensional and, therefore, unsuitable for the integrated design of DNNs.
[0007] In addition, for the design of DNNs structure using VCSEL (Vertical-cavity surface-emitting laser) array as the light source, because the light between VCSEL array units is incoherent, traditional algorithms cannot be used to design the DNNs structure, and there are no relevant literature reports.
[0008] Summary of the Invention
[0009] In response to the shortcomings of the existing technology, the embodiments of the present application provide a three-dimensional photonic chip architecture based on a VCSEL array, which can directly integrate the entire working optical path of DNNs on-chip, reducing its volume from centimeters or meters to millimeters or micrometers. The data input rate of the chip is 10 times that of existing DNNs. 6 More than times, the chip can process more data in a short time; in addition, the embodiment of the present application takes into account the particularity of the VCSEL array and develops a DNNs structure design method specifically for VCSEL arrays as light sources.
[0010] To achieve the above objectives, the technical solutions adopted in the embodiments of the present application are as follows:
[0011] On the one hand, an embodiment of the present application provides a three-dimensional photonic chip architecture based on a VCSEL array, including:
[0012] A data input layer, configured to generate two-dimensional optical data and input the optical data to a data processing layer; the data input layer is an addressable VCSEL array;
[0013] A data processing layer, configured to perform operations on the optical data input by the data input layer;
[0014] The data output layer is used to collect and output the calculation results of the data processing layer;
[0015] The data input layer, the data processing layer and the data output layer are stacked in sequence to form the three-dimensional photonic chip architecture.
[0016] In the above solution, the addressable VCSEL array includes a front-light emitting VCSEL array or a back-light emitting VCSEL array.
[0017] In the above solution, the VCSEL array includes a phase-locked VCSEL array.
[0018] In the above solution, the addressable VCSEL array is controlled by a manually controlled power supply, an external programmable control power supply or a CMOS chip.
[0019] In the above solution, the data processing layer is a DNNs structure, and the DNNs structure is integrated on the addressable VCSEL array.
[0020] In the above solution, the 3D printing prints the DNNs structure on the VCSEL array and supports the DNNs structure by printing support columns.
[0021] In the above solution, the bonding includes setting bonding points between the VCSEL array and the DNNs structure and completing the integration of the two by applying pressure.
[0022] In the above scheme, the DNNs structure is manufactured by 3D printing or microelectronics technology.
[0023] In the above solution, the preparation material of the DNNs structure includes at least one of organic matter, hard transparent material, photochromic material, and phase change material.
[0024] In the above scheme, the DNNs structure also includes pulse DNNs constructed by VCSEL arrays, and the pulse DNNs are composed of multiple diffraction layers, each of which is a VCSEL array, and each VCSEL array serves as a pulse neuron in the DNNs.
[0025] In the above solution, the data output layer is a detector array or a common optical screen.
[0026] In the above solution, the detector array is integrated on the data processing layer by bonding.
[0027] Another aspect of the embodiments of the present application provides an application of a three-dimensional photonic chip architecture based on a VCSEL array, which is used in the fields of face recognition, optical computing, image classification, 6G communication, optical encryption, and autonomous driving.
[0028] The present application also provides a method for calculating a DNNs structure based on a VCSEL array, comprising the following steps:
[0029] Construct the output light field of VCSEL array light in DNNs;
[0030] Calculate the amplitude distribution of the output light field;
[0031] The back propagation algorithm and gradient descent method are used to iterate to obtain the DNNs structure.
[0032] In the above scheme, calculating the amplitude distribution of the output light field includes: individually calculating the output light field obtained on the output plane for each unit in the VCSEL array after passing through the DNNs, and then superimposing the absolute values of the amplitudes of the output light fields of all units in the VCSEL array to obtain the amplitude distribution of the superimposed output light field.
[0033] Beneficial effects of the embodiments of the present application:
[0034] The three-dimensional photonic chip structure of the embodiment of the present application uses an addressable VCSEL array as the data input layer, generating arbitrary two-dimensional optical data that is directly input into the data processing layer for calculation, and then the calculation results are presented by the data output layer. Through the design of this chip architecture, the entire working optical path of DNNs can be directly integrated on the chip, and its volume will be reduced from centimeters or meters to millimeters or microns, which greatly promotes the practical application of DNNs. In addition, by utilizing the high modulation rate (GHz) of the VCSEL array, the data input rate of this chip will be 10 times the existing DNNs data input rate (kHz). 6 The chip can process more data in a shorter time than the traditional optical fiber. Due to the passive nature of light propagation, the chip consumes zero energy during computing, consuming only data input and readout. This significantly reduces energy consumption compared to existing electronic chips, solving the energy challenges faced by AI computing. This chip architecture is suitable for a variety of applications, including facial recognition, optical computing, image classification, 6G communications, optical encryption, and autonomous driving.
[0035] Based on the particularity of VCSEL array light sources, the embodiments of the present application propose a structural calculation method for DNNs. This method solves the problem that existing DNNs structural design algorithms cannot match the incoherent light sources emitted by VCSEL units, making this method applicable to the structural design of DNNs using VCSEL arrays as light sources. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] FIG1 is a side structural diagram of a three-dimensional photonic chip architecture provided in Example 1;
[0037] Figure 1-1 is a schematic diagram of the structure of the multi-layer holographic plate stack in the DNNs structure in Example 1;
[0038] Figure 1-2 shows the integrated DNNs structure in Example 1;
[0039] FIG2 is a side structural diagram of a three-dimensional photonic chip architecture provided in Example 2;
[0040] Figure 2-1 is a schematic diagram of the structure after the DNNs structure is integrated with the addressable VCSEL array in Example 2;
[0041] FIG3 is a side structural diagram of a three-dimensional photonic chip architecture provided in Example 3;
[0042] FIG3-1 is a schematic diagram of the structure of the VCSEL array for backlighting in Example 3;
[0043] Among them: 1. Addressable VCSEL array; 2. DNNs structure; 3. Detector array; 4. Metal bonding point; 5. Light output hole; 6. Support column;
[0044] In the figure, A is holographic version 1, B is holographic version 2, C is holographic version 3, and D is holographic version n. DETAILED DESCRIPTION
[0045] In order to make the purpose, technical solutions and advantages of this application more clear, the present application is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.
[0046] To achieve the above objectives, the technical solutions adopted in the embodiments of the present application are as follows:
[0047] On the one hand, an embodiment of the present application provides a three-dimensional photonic chip architecture based on a VCSEL array, including:
[0048] A data input layer, configured to generate two-dimensional optical data and input the optical data to a data processing layer; the data input layer is an addressable VCSEL array;
[0049] A data processing layer, configured to perform operations on the optical data input by the data input layer;
[0050] The data output layer is used to collect and output the calculation results of the data processing layer;
[0051] The data input layer, the data processing layer, and the data output layer are vertically stacked to form the three-dimensional photonic chip architecture.
[0052] VCSELs are semiconductor lasers. Currently, commonly used infrared VCSELs are generally based on GaAs wafers, with the VCSEL structure grown on GaAs using epitaxial growth technology. Light emitted by VCSELs is perpendicular to the substrate surface, making it easy to create a two-dimensional array. Independent electrodes can be used to address and control the VCSEL array, allowing any number and position of cells in the VCSEL array to be illuminated, thereby generating two-dimensional optical image data.
[0053] The addressable VCSEL array in this application has two functions. First, it serves as a data input layer to input data into the data processing layer and convert the input electrical signal into an optical signal. The addressable VCSEL array can play a role similar to a display screen, generating optical data of arbitrary content, which is input into the DNNs structure for its calculation. Second, the addressable VCSEL array emits lasers perpendicular to the substrate, giving it the advantage of a flat surface. Specifically, the light-emitting surfaces of all units in the addressable VCSEL array are on the same plane with small surface undulations. Since the three-dimensional photonic chip architecture of this application is stacked, this makes the stacking between the data processing layer and the data input layer tighter and more firmly bonded.
[0054] Furthermore, addressable VCSEL arrays can generate two-dimensional optical signals suitable for DNNs structural processing. Not only are they the easiest lasers to implement arrays, but VCSELs also have the advantage of being small in size. The volume of a VCSEL array is only in the micrometer or millimeter range, meeting the small size requirements of the chip.
[0055] In some embodiments, the addressable VCSEL array includes a front-emitting VCSEL array or a back-emitting VCSEL array.
[0056] In some embodiments, the VCSEL array comprises a phase-locked VCSEL array.
[0057] Furthermore, the addressable VCSEL array includes single mode or multi-mode.
[0058] Furthermore, the addressable VCSEL array includes a VCSEL array with a normal modulation bandwidth or a high-speed VCSEL array.
[0059] In some embodiments, the addressable VCSEL array is controlled by a manually controlled power supply, an external programmable control power supply, or a CMOS chip.
[0060] Specifically, CMOS chip control refers to integrating the electrodes of the addressable VCSEL array by bonding using a CMOS integrated circuit chip, and controlling the addressable VCSEL array through the CMOS chip.
[0061] In some embodiments, the data processing layer is a DNNs structure, and the DNNs structure is integrated on the addressable VCSEL array.
[0062] In this application, the DNNs structure is used as a data processing layer and integrated into the addressable VCSEL array. The optical image data generated by the addressable VCSEL array is directly irradiated into the DNNs structure. The transmission and calculation of optical data can be achieved without the need for connecting lines such as wires in electronic devices or the optical waveguide structure on the silicon photonic chip.
[0063] In some embodiments, the DNNs structure is integrated on the addressable VCSEL array by 3D printing or bonding.
[0064] Furthermore, the 3D printing prints a DNNs structure on the VCSEL array and supports the DNNs structure by printing support columns; the bonding includes setting bonding points between the VCSEL array and the DNNs structure and completing the integration of the two by applying pressure.
[0065] In some embodiments, the DNNs structure is manufactured by 3D printing or microelectronics technology.
[0066] Since the DNNs structure itself is also composed of multiple layers of stacked and cascaded holographic plates, for 3D-printed DNNs structures, the multi-layer structure can be directly printed. During the printing process of the multi-layer structure, at least three pillars need to be printed on the addressable VCSEL array to support the DNNs structure; while for the DNNs structure realized by microelectronics technology, the multiple layers of holographic plates need to be integrated together by bonding first.
[0067] Furthermore, when the DNNs structure is manufactured by 3D printing, the addressable VCSEL array is used as a substrate to complete the manufacture of the DNNs structure and the integration of the two; when the DNNs structure is manufactured by a microelectronic process, it includes first processing the DNNs structure on other substrates, and then bonding the DNNs structure to the addressable VCSEL array, wherein the bonding method includes but is not limited to adding bonding points such as metal materials between the DNNs structure and the VCSEL array, and then pressing the two together under high pressure and a specific temperature to achieve integration, wherein the bonding points are set in the peripheral area of the VCSEL array and will not block the transmission of the optical signal emitted by the VCSEL to the DNNs structure.
[0068] In some embodiments, the preparation material of the DNNs structure includes at least one of organic matter, hard transparent material, photochromic material, and phase change material.
[0069] Furthermore, the organic matter includes a transparent photosensitive resin material, including but not limited to photoresist, which is a material used to manufacture DNNs structure using 3D printing.
[0070] Furthermore, hard transparent materials include but are not limited to quartz and sapphire, which are materials used for processing DNNs structures in microelectronic processes. Transparency means that the material has a certain transmittance for the light emitted by VCSEL, and the long-term stability of the chip prepared using this type of material is also relatively excellent.
[0071] Furthermore, photochromic materials are materials whose transmittance can be adjusted by light, and their characteristic is that this transmittance modulation is reversible. Therefore, these properties can be exploited to realize reconfigurable DNNs. For organic and rigid transparent materials, once DNNs are manufactured, they can only perform the specific computational functions for which they were designed. However, for photochromic materials, the functions of DNNs can be reset. That is, once the transmittance of the photochromic material returns to its initial state, the transmittance of the photochromic material can be readjusted to realize DNNs with new functions.
[0072] Furthermore, the phase change material can also achieve the resettable function of DNNs.
[0073] In some embodiments, the DNNs structure further includes pulse DNNs constructed by VCSEL arrays, wherein the pulse DNNs are composed of multiple diffraction layers, each of which is a VCSEL array, and each VCSEL array serves as a pulse neuron in the DNNs.
[0074] In some embodiments, the data output layer is a detector array or a common optical screen.
[0075] Preferably, the data output layer is a detector array, which collects the calculation results of DNNs and serves as a data output port to convert optical data into electrical signals for output.
[0076] For ordinary optical screens as data output layers, the results of DNNs structure calculations can be directly presented on the screen in the form of light intensity distribution. For example, the DNNs structure performs four handwritten digit recognition tasks from 0 to 3, which requires distinguishing different handwritten digits. After DNNs structure calculations, four light spots are output. When the input is the number 0, the first light spot is the brightest, and when the input is the number 3, the fourth light spot is the brightest. The calculation results can be read from the presentation results of the ordinary optical screen.
[0077] Furthermore, the detector array is integrated on the data processing layer by bonding, specifically by setting bonding points on the DNNs structure. The bonding points are set in the peripheral area of the optical signal transmission and will not block the optical signal from being transmitted from the DNNs structure to the detector array.
[0078] The three-dimensional photonic chip architecture based on the VCSEL array in the embodiment of the present application can be used in the fields of face recognition, optical computing, image classification, 6G communication, optical encryption, and autonomous driving.
[0079] The present application also provides a method for calculating a DNNs structure based on a VCSEL array, comprising the following steps:
[0080] Construct the output light field of VCSEL array light in DNNs;
[0081] Calculate the amplitude distribution of the output light field;
[0082] The back propagation algorithm and gradient descent method are used to iterate to obtain the DNNs structure.
[0083] In some embodiments, calculating the amplitude distribution of the output light field includes: individually calculating the output light field obtained on the output plane for each unit in the VCSEL array after passing through the DNNs, and then superimposing the absolute values of the amplitudes of the output light fields of all units in the VCSEL array to obtain the amplitude distribution of the superimposed output light field.
[0084] Based on the particularity of VCSEL array light sources, this application proposes a structural calculation method for DNNs. This method solves the problem that existing DNNs structural design algorithms cannot match the incoherent light sources emitted by VCSEL units, making this method applicable to the structural design of DNNs using VCSEL arrays as light sources.
[0085] Example 1
[0086] A three-dimensional photonic chip architecture based on a VCSEL array, comprising:
[0087] A data input layer, configured to generate two-dimensional optical data and input the optical data to a data processing layer; the data input layer is an addressable VCSEL array;
[0088] A data processing layer, configured to perform operations on the optical data input by the data input layer;
[0089] The data output layer is used to collect and output the calculation results of the data processing layer;
[0090] The data input layer, data processing layer and data output layer are vertically stacked from bottom to top to form the three-dimensional photonic chip architecture. See Figure 1, which is a side structural diagram of the three-dimensional photonic chip architecture provided in this embodiment.
[0091] In this embodiment, the data processing layer is a DNNs structure 2, which is integrated by microelectronic processing. The DNNs structure 2 is made of quartz material. Specifically, a multi-layer quartz holographic plate (A, B, C, D, i.e., holographic plate 1, holographic plate 2, holographic plate 3, holographic plate n) is first bonded by high pressure as shown in Figure 1-1 to obtain an integrated DNNs structure 2 as shown in Figure 1-2, and then a metal bonding point 4 is set between the integrated DNNs structure 2 and the addressable VCSEL array 1 to integrate the two, wherein the metal bonding point 4 is set in the peripheral area of the VCSEL array and will not block the data transmission between the addressable VCSEL array 1 and the DNNs structure 2; the data output layer is a detector array 3, which is bonded by setting a metal bonding point 4 between the DNNs structure 2 and the detector array 3, wherein the metal bonding point 4 is set in the peripheral area of the optical signal transmission and will not block the optical signal from the DNNs structure 2 to the detector array 3.
[0092] The addressable VCSEL array 1 used in this application is an addressable VCSEL array. VCSEL is an active device that can generate laser. The addressable VCSEL array 1 is a light source array composed of multiple VCSELs arranged in two dimensions on a plane. By controlling the on and off of the VCSEL, two-dimensional optical image data can be generated. The addressable VCSEL array 1 is provided with a light output hole 5. The optical image data generated by the addressable VCSEL array 1 is directly irradiated into the DNNs structure 2 through the light output hole 5, propagated inside it to complete the calculation processing, and then an optical signal with the calculation result is output. The optical signal is irradiated on the detector array 3 and is represented in the form of different light intensity distributions. The light is irradiated on different areas of the detector array. The light intensity distribution represents the calculation result of the data. The detector array 3 converts the optical signal into an electrical signal and outputs the calculation result.
[0093] The addressable VCSEL array is a front-emitting VCSEL array.
[0094] Furthermore, the addressable VCSEL array is single-mode or multi-mode, and the addressable VCSEL array includes a VCSEL array with normal modulation bandwidth or a high-speed VCSEL array.
[0095] In this embodiment, there is no limitation on the control mode of the addressable VCSEL array, including one of manual power control, external programmable power control, and CMOS chip control.
[0096] The three-dimensional photonic chip architecture provided in this embodiment can be applied to face recognition, optical computing, image classification, 6G communication, optical encryption, and autonomous driving. For example, in a face recognition system, facial information can be identified more quickly and accurately in a larger database to complete identity confirmation.
[0097] The 3D photonic chip architecture of this embodiment can directly integrate the entire working optical path of DNNs on-chip, reducing its volume from centimeters or meters to millimeters or micrometers, greatly promoting the practical application of DNNs. In addition, by utilizing the high modulation rate (GHz) of the VCSEL array, the data input rate of this chip will be 10 times that of the existing DNNs data input rate (kHz). 6 The chip can process more data in a short time, and based on the characteristics of passive light propagation, the chip has zero energy consumption during operation, and only consumes energy when inputting and reading data. The energy consumption will be much lower than that of existing electronic chips, which can solve the energy problem faced by AI computing.
[0098] Example 2
[0099] A three-dimensional photonic chip architecture based on a VCSEL array, comprising:
[0100] A data input layer, configured to generate two-dimensional optical data and input the optical data to a data processing layer; the data input layer is an addressable VCSEL array;
[0101] A data processing layer, configured to perform operations on the optical data input by the data input layer;
[0102] The data output layer is used to collect and output the calculation results of the data processing layer;
[0103] The data input layer, data processing layer and data output layer are vertically stacked from bottom to top to form the three-dimensional photonic chip architecture. See Figure 2, which is a side structural diagram of the three-dimensional photonic chip architecture provided in this embodiment.
[0104] In this embodiment, the data processing layer is a DNNs structure 2, which is integrated by 3D printing. The DNNs structure 2 is prepared by photoresist. Specifically, a multi-layer holographic plate is directly printed on the addressable VCSEL, including A, B, D, namely holographic plate 1, holographic plate 2...holographic plate n (n>2), as shown in Figure 2-1, and three support pillars 6 are printed on the addressable VCSEL array 1 to support the DNNs structure and obtain an integrated DNNs structure 2, wherein the support pillars 6 are arranged in the peripheral area of the VCSEL array and will not block the data transmission between the addressable VCSEL array 1 and the DNNs structure 2; the data output layer is a detector array 3, and bonding is achieved by setting metal bonding points 4 between the DNNs structure 2 and the detector array 3, wherein the metal bonding points 4 are set in the peripheral area of the optical signal transmission and will not block the optical signal from the DNNs structure 2 to the detector array 3.
[0105] The addressable VCSEL array 1 used in this application is an addressable VCSEL array. VCSEL is an active device that can generate laser. The addressable VCSEL array 1 is a light source array composed of multiple VCSELs arranged in two dimensions on a plane. By controlling the on and off of the VCSEL, two-dimensional optical image data can be generated. The addressable VCSEL array 1 is provided with a light output hole 5. The optical image data generated by the addressable VCSEL array 1 is directly irradiated into the DNNs structure 2 through the light output hole 5, propagated inside it to complete the calculation processing, and then an optical signal with the calculation result is output. The optical signal is irradiated on the detector array 3 and is represented in the form of different light intensity distributions. The light is irradiated on different areas of the detector array. The light intensity distribution represents the calculation result of the data. The detector array 3 converts the optical signal into an electrical signal and outputs the calculation result.
[0106] The addressable VCSEL array is a front-emitting VCSEL array.
[0107] Furthermore, the addressable VCSEL array is single-mode or multi-mode, and the addressable VCSEL array includes a VCSEL array with normal modulation bandwidth or a high-speed VCSEL array.
[0108] In this embodiment, there is no limitation on the control mode of the addressable VCSEL array, including one of manual power control, external programmable power control, and CMOS chip control.
[0109] The three-dimensional photonic chip architecture provided in this embodiment can be applied to face recognition, optical computing, image classification, 6G communication, optical encryption, and autonomous driving.
[0110] The 3D photonic chip architecture of this embodiment can directly integrate the entire working optical path of DNNs on-chip, reducing its volume from centimeters or meters to millimeters or micrometers, greatly promoting the practical application of DNNs. In addition, by utilizing the high modulation rate (GHz) of the VCSEL array, the data input rate of this chip will be 10 times that of the existing DNNs data input rate (kHz). 6 The chip can process more data in a short time, and based on the characteristics of passive light propagation, the chip has zero energy consumption during operation, and only consumes energy when inputting and reading data. The energy consumption will be much lower than that of existing electronic chips, which can solve the energy problem faced by AI computing.
[0111] Example 3
[0112] A three-dimensional photonic chip architecture based on a VCSEL array, comprising:
[0113] A data input layer, configured to generate two-dimensional optical data and input the optical data to a data processing layer; the data input layer is an addressable VCSEL array;
[0114] A data processing layer, configured to perform operations on the optical data input by the data input layer;
[0115] The data output layer is used to collect and output the calculation results of the data processing layer;
[0116] The data input layer, data processing layer and data output layer are vertically stacked from bottom to top to form the three-dimensional photonic chip architecture. See Figure 3, which is a side structural diagram of the three-dimensional photonic chip architecture provided in this embodiment.
[0117] In this embodiment, the data processing layer is a DNNs structure 2, which is integrated through microelectronic processing. The DNNs structure 2 is made of photochromic material. Specifically, the multi-layer photochromic material holographic plate is first bonded by high voltage to obtain an integrated DNNs structure 2, and then a metal bonding point 4 is set between the integrated DNNs structure 2 and the addressable VCSEL array 1 to integrate the two, wherein the metal bonding point 4 is set in the peripheral area of the VCSEL array and will not block the data transmission between the addressable VCSEL array 1 and the DNNs structure 2; the data output layer is a detector array 3, which is bonded by setting a metal bonding point 4 between the DNNs structure 2 and the detector array 3, wherein the metal bonding point 4 is set in the peripheral area of the optical signal transmission and will not block the optical signal from the DNNs structure 2 to the detector array 3.
[0118] The addressable VCSEL array 1 used in this application is an addressable VCSEL array. VCSEL is an active device that can generate laser. The addressable VCSEL array 1 is a light source array composed of multiple VCSELs arranged in two dimensions on a plane. By controlling the on and off of the VCSEL, two-dimensional optical image data can be generated. The addressable VCSEL array 1 is provided with a light output hole 5. The optical image data generated by the addressable VCSEL array 1 is directly irradiated into the DNNs structure 2 through the light output hole 5, propagated inside it to complete the calculation processing, and then an optical signal with the calculation result is output. The optical signal is irradiated on the detector array 3 and is represented in the form of different light intensity distributions. The light is irradiated on different areas of the detector array. The light intensity distribution represents the calculation result of the data. The detector array 3 converts the optical signal into an electrical signal and outputs the calculation result.
[0119] The addressable VCSEL array is a back-emitting VCSEL array, as shown in Figure 3-1. Specifically, the light passes through the substrate of the VCSEL and is emitted from the other side. This structure is more convenient to integrate with the DNNs structure because the back side of the VCSEL has excellent flatness.
[0120] Furthermore, the addressable VCSEL array is single-mode or multi-mode, and the addressable VCSEL array includes a VCSEL array with normal modulation bandwidth or a high-speed VCSEL array.
[0121] In this embodiment, there is no limitation on the control mode of the addressable VCSEL array, including one of manual power control, external programmable power control, and CMOS chip control.
[0122] The three-dimensional photonic chip architecture provided in this embodiment can be applied to face recognition, optical computing, image classification, 6G communication, optical encryption, and autonomous driving.
[0123] The 3D photonic chip architecture of this embodiment can directly integrate the entire working optical path of DNNs on-chip, reducing its volume from centimeters or meters to millimeters or micrometers, greatly promoting the practical application of DNNs. In addition, by utilizing the high modulation rate (GHz) of the VCSEL array, the data input rate of this chip will be 10 times that of the existing DNNs data input rate (kHz). 6 The chip can process more data in a short time, and based on the characteristics of passive light propagation, the chip has zero energy consumption during operation, and only consumes energy when inputting and reading data. The energy consumption will be much lower than that of existing electronic chips, which can solve the energy problem faced by AI computing.
[0124] Example 4
[0125] A method for calculating a DNNs structure based on a VCSEL array comprises the following steps:
[0126] S1. Construct the propagation process and output light field of VCSEL array light in DNNs;
[0127] S2. Calculate the amplitude distribution of the output light field of the VCSEL array light in the DNNs: Calculate the output light field of each unit in the VCSEL array on the output plane after passing through the DNNs. Then, superimpose the absolute values of the amplitudes of the output light fields of all units in the VCSEL array to obtain the amplitude distribution of the superimposed output light field.
[0128] S3. Use the back propagation algorithm and gradient descent method to iterate and obtain the DNNs structure.
[0129] Based on the particularity of VCSEL array light sources, this embodiment proposes a structural calculation method for DNNs. This method solves the problem that existing DNNs structural design algorithms cannot match the incoherent light sources emitted by VCSEL units, making this method applicable to the structural design of DNNs using VCSEL arrays as light sources.
[0130] Specifically:
[0131] Construct the output light field of the VCSEL array light after passing through DNNs;
[0132] Calculate the amplitude distribution of the output light field based on the output light field of the VCSEL array light after passing through the DNNs;
[0133] Define a loss function that outputs the difference between the amplitude distribution of the light field and the target amplitude distribution;
[0134] The back propagation algorithm and gradient descent method are used to iterate repeatedly to optimize the DNNs structure, so that the loss function value is gradually reduced, and finally the DNNs structure is obtained.
[0135] The above are only preferred embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent transformations made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.
Claims
1. A three-dimensional photonic chip architecture based on a VCSEL array, characterized in that: include: A data input layer, for generating two-dimensional optical data and inputting the optical data into a data processing layer; The data input layer is an addressable VCSEL array; A data processing layer, configured to perform operations on the optical data input by the data input layer; The data output layer is used to collect and output the calculation results of the data processing layer; The data input layer, the data processing layer and the data output layer are stacked in sequence to form the three-dimensional photonic chip architecture.
2. A three-dimensional photonic chip architecture based on a VCSEL array according to claim 1, characterized in that: The addressable VCSEL array includes a front-light emitting VCSEL array or a back-light emitting VCSEL array.
3. The three-dimensional photonic chip architecture based on a VCSEL array according to claim 1, characterized in that: The addressable VCSEL array includes a phase-locked VCSEL array.
4. The three-dimensional photonic chip architecture based on a VCSEL array according to claim 1, characterized in that: The addressable VCSEL array is controlled by a manual control power supply, an external programmable control power supply or a CMOS chip.
5. The three-dimensional photonic chip architecture based on a VCSEL array according to claim 1, characterized in that: The data processing layer includes a DNNs structure, and the DNNs structure is integrated on the addressable VCSEL array.
6. The three-dimensional photonic chip architecture based on a VCSEL array according to claim 5, characterized in that: The DNNs structure is integrated on the addressable VCSEL array by 3D printing or bonding.
7. The three-dimensional photonic chip architecture based on a VCSEL array according to claim 6, characterized in that: The 3D printing is used to print a DNNs structure on the VCSEL array and provide support for the DNNs structure by printing support columns.
8. The three-dimensional photonic chip architecture based on a VCSEL array according to claim 6, characterized in that: The bonding is used to set bonding points between the VCSEL array and the DNNs structure and integrate the two under pressure.
9. The three-dimensional photonic chip architecture based on a VCSEL array according to claim 5, characterized in that: The DNNs structure is manufactured based on 3D printing or microelectronics technology.
10. The three-dimensional photonic chip architecture based on a VCSEL array according to claim 5, characterized in that: The preparation material of the DNNs structure includes at least one of organic matter, hard transparent material, photochromic material, and phase change material.
11. The three-dimensional photonic chip architecture based on a VCSEL array according to claim 10, characterized in that: The DNNs structure also includes pulse DNNs constructed by VCSEL arrays, and the pulse DNNs include multiple diffraction layers, each of which is a VCSEL array, and each VCSEL array serves as a pulse neuron in the DNNs.
12. The three-dimensional photonic chip architecture based on a VCSEL array according to claim 1, characterized in that: The data output layer includes a detector array or a common optical screen.
13. The three-dimensional photonic chip architecture based on a VCSEL array according to claim 12, characterized in that: The detector array is integrated on the data processing layer by bonding.
14. The three-dimensional photonic chip architecture based on a VCSEL array according to any one of claims 1 to 13, characterized in that: The architecture is applied to any of the fields of face recognition, optical computing, image classification, 6G communication, optical encryption, and autonomous driving.
15. A method for calculating DNNs structure based on a VCSEL array, characterized in that: The following steps are involved: Construct the output light field of the VCSEL array light after passing through DNNs; Calculate the amplitude distribution of the output light field based on the output light field of the VCSEL array light after passing through the DNNs; Define a loss function that outputs the difference between the amplitude distribution of the light field and the target amplitude distribution; The back propagation algorithm and gradient descent method are used to iterate repeatedly to optimize the DNNs structure, gradually reduce the loss function value, and finally obtain the DNNs structure.
16. The method for calculating the structure of DNNs based on a VCSEL array according to claim 15, wherein: The calculating the amplitude distribution of the output light field comprises: Calculate the output light field of each unit in the VCSEL array on the output plane after passing through DNNs separately; The absolute values of the amplitudes of the output light fields of all units of the VCSEL array are superimposed to obtain the amplitude distribution of the superimposed output light field.