Accelerated parallel processing of 5G NR signal information

Abstract

Apparatuses, systems, and techniques to perform signal processing operations in a fifth generation (5G) new radio (NR) network using one or more parallel processing units (PPU's). In at least one embo

Description

CROSS REFERENCE TO RELATED APPLICATION

[0001] This application claims priority to U.S. Patent Application No. 16 / 716,350, filed December 16, 2019, entitled “ACCELERATED PARALLEL PROCESSING OF 5GNR SIGNAL INFORMATION,” the entire contents of which is incorporated herein by reference in its entirety and for all purposes. FIELD

[0002] At least one embodiment pertains to processing signals in a fifth generation (5G) new radio network. For example, at least one embodiment, pertains to processors or computing systems used to encode and decode 5G signals using one or more graphics processing units, according to various novel techniques described herein. BACKGROUND

[0003] As more and more users migrate to using cellular devices as their primary way of communicating, mobile data traffic is growing at an exponential rate. To handle this rapid growth, new communication standards have been developed that introduce technology layers that facilitate greater wireless network access and throughput of information. Current technologies struggle with meeting throughput and data capacity requirements in new wireless standards as hardware capabilities of network infrastructure must be able to handle challenging levels of information processing. Technology implementing these new standards struggles to satisfy requirements of very low latency, very high throughput, low power consumption, and cloud readiness. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] FIG. 1 illustrates a baseband unit (BBU) in a wireless network, according to at least one embodiment;

[0005] FIG. 2 illustrates a block diagram containing various uplink and downlink signal processing components of a BBU, according to at least one embodiment;

[0006] FIG. 3 illustrates a split architecture for implementing signal processing components of a BBU, according to at least one embodiment;

[0007] FIG. 4 illustrates a general BBU architecture containing parallel processing units (PPUs), such as graphics processing units (GPUs), according to at least one embodiment;

[0008] FIG. 5 illustrates a system for partial or full implementation of signal processing blocks on one or more PPUs, such as GPUs in a BBU, according to at least one embodiment;

[0009] FIG. 6 illustrates a process for performing fifth generation (5G) new radio (NR) baseband operations on one or more PPUs, such as GPUs, according to at least one embodiment;

[0010] FIG. 7 illustrates an example data center system, according to at least one embodiment;

[0011] FIG. 8 A illustrates an example of an autonomous vehicle, according to at least one embodiment;

[0012] FIG. 8B illustrates an example of camera locations and fields of view for the autonomous vehicle of FIG. 8 A, according to at least one embodiment;

[0013] FIG. 8C is a block diagram illustrating an example system architecture for the autonomous vehicle of FIG. 8 A, according to at least one embodiment;

[0014] FIG. 8D is a diagram illustrating a system for communication between cloud-based server(s) and the autonomous vehicle of FIG. 8 A, according to at least one embodiment;

[0015] FIG. 9 is a block diagram illustrating a computer system, according to at least one embodiment;

[0016] FIG. 10 is a block diagram illustrating computer system, according to at least one embodiment;

[0017] FIG. 11 illustrates a computer system, according to at least one embodiment;

[0018] FIG. 12 illustrates a computer system, according at least one embodiment;

[0019] FIG. 13 A illustrates a computer system, according to at least one embodiment;

[0020] FIG. 13B illustrates a computer system, according to at least one embodiment;

[0021] FIG. 13C illustrates a computer system, according to at least one embodiment;

[0022] FIG. 13D illustrates a computer system, according to at least one embodiment;

[0023] FIG. 13E and 13F illustrate a shared programming model, according to at least one embodiment;

[0024] FIG. 14 illustrates exemplary integrated circuits and associated graphics processors, according to at least one embodiment;

[0025] FIGS. 15A-15B illustrate exemplary integrated circuits and associated graphics processors, according to at least one embodiment;

[0026] FIGS. 16A-16B illustrate additional exemplary graphics processor logic according to at least one embodiment;

[0027] FIG. 17 illustrates a computer system, according to at least one embodiment;

[0028] FIG. 18A illustrates a parallel processor, according to at least one embodiment;

[0029] FIG. 18B illustrates a partition unit, according to at least one embodiment;

[0030] FIG. 18C illustrates a processing cluster, according to at least one embodiment;

[0031] FIG. 18D illustrates a graphics multiprocessor, according to at least one embodiment;

[0032] FIG. 19 illustrates a multi-graphics processing unit (GPU) system, according to at least one embodiment;

[0033] FIG. 20 illustrates a graphics processor, according to at least one embodiment;

[0034] FIG. 21 is a block diagram illustrating a processor micro-architecture for a processor, according to at least one embodiment;

[0035] FIG. 22 illustrates at least portions of a graphics processor, according to one or more embodiments;

[0036] FIG. 23 illustrates at least portions of a graphics processor, according to one or more embodiments;

[0037] FIG. 24 illustrates at least portions of a graphics processor, according to one or more embodiments;

[0038] FIG. 25 is a block diagram of a graphics processing engine of a graphics processor in accordance with at least one embodiment;

[0039] FIG. 26 is a block diagram of at least portions of a graphics processor core, according to at least one embodiment;

[0040] FIGS. 27A-27B illustrate thread execution logic including an array of processing elements of a graphics processor core according to at least one embodiment;

[0041] FIG. 28 illustrates a parallel processing unit (“PPU”), according to at least one embodiment;

[0042] FIG. 29 illustrates a general processing cluster (“GPC”), according to at least one embodiment;

[0043] FIG. 30 illustrates a memory partition unit of a parallel processing unit (“PPU”), according to at least one embodiment;

[0044] FIG. 31 illustrates a streaming multi-processor, according to at least one embodiment;

[0045] FIG. 32 illustrates a network for communicating data within a 5G wireless communications network, according to at least one embodiment;

[0046] FIG. 33 illustrates a network architecture for a 5G LTE wireless network, according to at least one embodiment;

[0047] FIG. 34 is a diagram illustrating some basic functionality of a mobile telecommunications network / system operating in accordance with LTE and 5G principles, according to at least one embodiment;

[0048] FIG. 35 illustrates a radio access network which may be part of a 5G network architecture, according to at least one embodiment;

[0049] FIG. 36 provides an example illustration of a 5G mobile communications system in which a plurality of different types of devices is used, according to at least one embodiment;

[0050] FIG. 37 illustrates an example high level system, according to at least one embodiment;

[0051] FIG. 38 illustrates an architecture of a system of a network, according to at least one embodiment;

[0052] FIG. 39 illustrates example components of a device, according to at least one embodiment;

[0053] FIG. 40 illustrates example interfaces of baseband circuitry, according to at least one embodiment;

[0054] FIG. 41 illustrates an example of an uplink channel, according to at least one embodiment;

[0055] FIG. 42 illustrates an architecture of a system of a network, according to at least one embodiment;

[0056] FIG. 43 illustrates a control plane protocol stack, according to at least one embodiment;

[0057] FIG. 44 illustrates a user plane protocol stack, according to at least one embodiment;

[0058] FIG. 45 illustrates components of a core network, according to at least one embodiment; and

[0059] FIG. 46 illustrates components of a system to support network function virtualization (NFV), according to at least one embodiment. DETAILED DESCRIPTION

[0060] FIG. 1 illustrates a baseband unit (BBU) 112 in a wireless network. In at least one embodiment, multiple wireless devices 102, 104, 106 communicate using a fifth generation (5G) new radio standard, described herein, with an antenna connected to a radio unit (RU) 108. In at least one embodiment, an RU 108 communicates over a network 110, such as Ethernet, fiber optic, or another suitable wired or wireless networking medium, with at least one baseband unit (BBU) 112.

[0061] In at least one embodiment, a BBU 112 contains one or more computing devices to perform signal processing and other operations to process information in a 5G network. In at least one embodiment, a BBU 112 contains one or more parallel processing units (PPUs), described herein, to perform computing operations including those related to signal processing. In at least one embodiment, a BBU 112 is responsible for interpreting baseband frequencies in communication systems, including computer networks, internet, phone networks and radio broadcasting systems. In at least one embodiment, a BBU 112 switches communications in network data traffic between multiple locations. In at least one embodiment, a BBU 112 performs encoding and decoding for data encoded with error correcting codes. In at least one embodiment, a BBU 112 utilizes one or more PPUs to implement signal processing operations such as those implemented as part of a PHY or physical layer of a 5G communication scheme. In at least one embodiment, PPUs includes graphics processing units (GPUs). In at least one embodiment, a BBU 112 switches communications in network data traffic between multiple locations.

[0062] In at least one embodiment, a BBU 112 connects to a base station containing an antenna 108, which may also be referred to as a radio unit (RU), a remote radio unit (RRU), or a remote radio head (RRH). In at least one embodiment, an RU 108 contains processing or computing resources. In at least one embodiment, an RU 108 may contain one or more PPUs. In at least one embodiment, and RU 108 may contain one or more GPUs to facilitate computing of signal processing operations. In at least one embodiment, an RU 108 will contain an antenna used to facilitate wireless communication to one or more wireless devices 102, 104, 106.

[0063] In at least one embodiment, an RU 108 antenna may be a wire antenna, such as a short dipole antenna, dipole antenna, loop antenna, or monopole antenna. In at least one embodiment, an RU 108 antenna may be a log periodic antenna, such as a bow tie antenna, log periodic antenna, or log periodic dipole array. In at least one embodiment, an RU 108 antenna may be an aperture antenna, such as a slot antenna or a horn antenna. In at least one embodiment, an RU 108 antenna may be a microstrip antenna, such as a rectangular microstrip patch antenna or a quarter-wave patch antenna. In at least one embodiment, an RU 108 antenna may be a reflector antenna, such as a flat-plate reflector antenna, corner reflector antenna, or parabolic reflector antenna. In at least one embodiment, an RU 108 antenna may be a lens antenna. In at least one embodiment, an RU 108 antenna may be a travelling wave antenna, such as a long wire antenna, yagi-uda antenna, helical wire antenna, or spiral antenna. In at least one embodiment, an RU 108 antenna may be an array antenna, such as a two-element array antenna, a linear array antenna, or a phased array antenna. In at least one embodiment, an RU 108 antenna may be any type of antenna that facilitates long- or short-range wireless communications.

[0064] In at least one embodiment, wireless devices 102, 104, 106 send data across a noisy wireless channel to one or more RUs 108 containing one or more antennas, described herein. In at least one embodiment, wireless devices 102, 104, 106 encode and decode communication signals using techniques determined as part of a 5G wireless communication standard. In at least one embodiment, wireless devices 102, 104, 106 encode information sent to one or more RUs 108. In at least one embodiment, encoded information sent by wireless devices 102, 104, 106 to one or more RUs 108 is processed by a BBU 112, further described herein.

[0065] In at least one embodiment, wireless devices 102, 104, 106 include cellular telephones and other mobile telephonic devices. In at least one embodiment, wireless devices 102, 104, 106 are handheld tablets or other portable computing devices described herein. In at least one embodiment, wireless devices 102, 104, 106 are laptop computers. In at least one embodiment, wireless devices 102, 104, 106 is a desktop computing device connected wirelessly to a base station or RU 108. In at least one embodiment, wireless devices 102, 104, 106 include any computing device that transmits and receives data over a 5G new radio wireless communication scheme. In at least one embodiment, wireless devices 102, 104, 106 include any computing device that transmits and receives data over any other wireless communication scheme.

[0066] FIG. 2 illustrates a block diagram containing uplink 202 and downlink 204 signal processing components of a baseband unit (BBU). In at least one embodiment, uplink 202 and downlink 204 signal processing components of a baseband unit comprise a physical layer (PHY) in a fifth generation (5G) new radio wireless communication system. In at least one embodiment, a PHY is organized into physical channels, such as uplink 202 and downlink 204. In at least one embodiment, each channel performs functions for transmission 202 and reception 204 of data. In at least one embodiment, each channel performs functions for transmission 202 and reception 204 of control information, cell discovery, and initial access. In at least one embodiment, uplink 202 and downlink 204 signal processing components provide a signal processing pipeline consisting of signal processing blocks specific to each PHY channel. In at least one embodiment, for downlink 204 channels where a BBU is implementing transmitter communications, signal processing blocks are determined by a 3rd Generation Partnership Project (3GPP) NR standard specification. In at least one embodiment, for uplink 202 channels, where a BBU is implementing receiver communications, signal processing blocks are implementationspecific and not limited to those specified in FIG. 2.

[0067] In at least one embodiment, a PHY Controller 206 provides an interface between PHY layer signal processing operations, such as those contained in an uplink channel 202 and those contained in a downlink channel 204, to upper layers in a BBU. In at least one embodiment, a PHY Controller 206 acts as an interface between a PHY or physical layer, implementing signal processing operations, and upper layers of a 3rd Generation Partnership Project 3GPP protocol stack. In at least one embodiment, a PHY Controller 206 provides an application programming interface (API). In at least one embodiment, a PHY Controller 206 provides an API that is based on a standard, such as Small Cell Forum FAPI Interface. In at least one embodiment, a PHY Controller 206 provides an API that is proprietary.

[0068] In at least one embodiment, a PHY Controller 206 manages software run on any parallel processing units (PPUs). In at least one embodiment, a PHY Controller 206 manages software kernels, or segments of software instructions to perform one or more specific operations, implementing signal processing operations such as those implemented in a PHY layer of a 5G new radio wireless communication system, where said software kernels are executed by one or more graphics processing units (GPUs), as described below. In at least one embodiment, one or more GPUs may implement all functionality in a signal processing pipeline. In at least one embodiment, one or more GPUs may be used as accelerators for specific blocks of a signal processing pipeline. In at least one embodiment, a PHY Controller 206 provides software to manage GPU software calls. In at least one embodiment, a PHY Controller 206 supplies necessary parameters to software kernels being executed by one or more GPUs. In at least one embodiment, a PHY Controller 206 manages output from software kernels being executed by one or more GPUs.

[0069] In at least one embodiment, 5GNR PHY channels 202, 204 provide signal processing components for data transmission. In at least one embodiment, data transmission components include a physical uplink shared channel (PUSCH) 210. In at least one embodiment, PUSCH 210 in 5GNR is designated to carry multiplexed control information and user application data, as described further herein. In at least one embodiment, data transmission components include a physical downlink shared channel (PDSCH) 224. In at least one embodiment, PDSCH carries user data and higher-layer signaling, as described further herein.

[0070] In at least one embodiment, 5GNR PHY channels 202, 204 provide signal processing components for control information transmission. In at least one embodiment, control information transmission components include a physical downlink control channel (PDCCH) 226 and a physical uplink control channel (PUCCH) 212. In at least one embodiment, PDCCH 226 and PUCCH 212 carry information about a transport format and resource allocations related to PDSCH 224 and PUSCH 210 channels, as described further herein.

[0071] In at least one embodiment, control information transmission components include four main reference signals 214, 216, 230. In at least one embodiment, four main reference signals in PHY control information transmission components are demodulation reference signal (DMRS) 214, 230, phase-tracking reference signal (PTRS) 230, sounding reference signal (SRS) 216, and channel-state information reference signal (CSI-RS) 230. In at least one embodiment, DMRS 214, 230 is used to estimate a radio channel for demodulation, as described further herein. In at least one embodiment, PTRS 230 is utilized to enable compensation of oscillator phase noise, as described further herein. In at least one embodiment, SRS 216 and CSI-RS 230 are utilized to perform channel state information (CSI) measurements for scheduling and link adaptation, as further described herein.

[0072] In at least one embodiment, 5G NR PHY channels 202, 204 provide signal processing components for initial access and cell discovery. In at least one embodiment, cell discovery is facilitated by a physical random access channel (PRACH) 218 and physical broadcast channel (PBCH) 228, as further described herein. In at least one embodiment, a synchronization signal block (SS Block) 232 may be broadcast to select a serving cell, as further described herein.

[0073] In at least one embodiment, 5GNR PHY channels 202, 204 provide signal processing components for low-physical (Low PHY) functions, which perform fundamental operations on 5G NR signals, further described herein. In at least one embodiment, Low PHY functions include fast fourier transform (FFT) 222 and inverse fast fourier transform (IFFT) 236. In at least one embodiment, FFT 222 and IFFT 236 convert frequency-based signal information into time-based data for processing, and vice versa, further described herein. In at least one embodiment, Low PHY functions include cyclic prefix (CP) insertion 236 and removal 222. In at least one embodiment, CP insertion 236 and removal 222 facilitates performance of FFT 222 and IFFT 236 operations to perform convolution, further described herein. In at least one embodiment, Low PHY functions include transmission beamforming (Tx Beamforming) 234 and receive beamforming (Rx Beamforming) 220. In at least one embodiment, beamforming 220, 234 is a signal filtering technique used in 5G NR and other wireless networks, as further described herein. In at least one embodiment, one or more antennas 208 in one or more radio units will transmit and receive signal data.

[0074] FIG. 3 illustrates a split architecture for implementing signal processing components of a baseband unit (BBU) 304 and radio unit (RU) 302. In at least one embodiment, all physical channel (PHY) functionality is performed by either an RU 302 or BBU 304. In at least one embodiment, PHY functionality is segmented between an RU 302 and a BBU 304. In at least one embodiment, segmentation of PHY functionality is determined by standards such as 3rd Generation Partnership Project (3GPP) and / or Open Radio Access Networks (ORAN). In at least one embodiment, segmentation of PHY functionality may be determined by proprietary design requirements.

[0075] As an example, in at least one embodiment, Low PHY functions, described herein, are implemented on an RU 302, while remaining PHY functions are implemented on a BBU 304, which may contain one or more parallel processing units as described herein. In at least one embodiment, Low PHY functions include fast fourier transform (FFT) and inverse fast fourier transform (IFFT) 306, which perform a convolution operation to convert signal information into data that can be further processed by other PHY signal processing operations. In at least one embodiment, Low PHY functions include cyclic prefix (CP) addition and removal 306 to facilitate performance of convolutions operations such as FFT and IFFT 306. In at least one embodiment, beamforming operations 308, described herein, are performed as part of a segmentation of Low PHY functions to an RU 302

[0076] In at least one embodiment, when Low PHY operations 306, 308 are segmented to an RU 302, remaining PHY signal processing operations are implemented in a BBU 304, including one or more parallel processing units (PPUs) including graphics processing units (GPUs). In at least one embodiment, a PHY Controller 310 manages software run on any PPUs including GPUs. In at least one embodiment, a PHY Controller 310 manages software kernels, or segments of software instructions to perform one or more specific operations, implementing signal processing operations to perform PHY channel processing 312, where said software kernels are executed by one or more graphics processing units (GPUs), as described below. In at least one embodiment, a PHY Controller 310 provides software to manage GPU software calls to perform PHY channel processing 312. In at least one embodiment, a PHY Controller 310 supplies necessary parameters to software kernels being executed by one or more GPUs. In at least one embodiment, a PHY Controller 310 manages output from software kernels being executed by one or more GPUs. In at least one embodiment, a BBU 304 performs other PHY channel processing operations 312 using one or more central processing units (CPUs) and one or more GPUs, as described below. In at least one embodiment, some Low PHY operations that require more processing resources, such as beamforming weight calculations 314 are performed on a BBU 304 despite segmentation of Low PHY operations with an RU 302.

[0077] FIG. 4 illustrates a general baseband unit (BBU) 402 architecture containing one or more graphics processing units (GPUs) 408. In at least one embodiment, a BBU 402 or other system implementing fifth generation (5G) new radio (NR) physical layer or channels (PHY) contains hardware or software to perform signal processing operations as well as receive signal information. In at least one embodiment, signal information is received from a remote radio unit (RRU) or other radio unit (RU) over a wired network connection.

[0078] In at least one embodiment, a BBU 402 or other system implementing 5G NR PHY contains of one or more central processing units (CPUs) 406. In at least one embodiment, one or more CPUs 406 implement or execute software instructions that implement upper layers of 5G NR PHY. In at least one embodiment, one or more CPUs 406 implement or execute software instructions that implement some or all signal processing operations of 5GNR PHY, depending on how those operations are divided between a BBU 402 and one or more RUs, as described above. In at least one embodiment, one or more CPUs 406 implement or execute software instructions that implement some or all signal processing operations of 5GNR PHY, where specific signal processing operations executed are based on what operations have been designated for accelerated execution on one or more graphics processing units (GPUs) 408.

[0079] In at least one embodiment, a BBU 402 or other system implementing 5G NR PHY contains one or more GPUs 408. In at least one embodiment, one or more GPUs 408 implement or execute software instructions that implement full or partial 5G NR PHY. In at least one embodiment, one or more GPUs 408 implement or execute software instructions that implement some or all operations of 5G NR PHY, depending on which operations have been designated for implementation on or execution by one or more CPUs 406. In at least one embodiment, one or more GPUs 408 implement a full 5GNR PHY. In at least one embodiment, one or more GPUs 408 implement a partial 5G NR PHY, with remaining operations to be performed by one or more CPUs 406.

[0080] In at least one embodiment, a BBU 402 or other system implementing 5G NR PHY contains one or more network interface controllers (NICs) 404. In at least one embodiment, one or more NICs 404 transfer information received from one or more RUs or RRUs directly to one or more CPUs 406 and / or one or more GPUs 408 over a direct communication channel 410, such as a bus or other internal communication medium in a BBU 402 or other system implementing 5G NR PHY. In at least one embodiment, communication by one or more CPUs 406 and / or one or more GPUs 408 with one or more NICs 404 is bi-directional and used for transmission and receiving of data.

[0081] FIG. 5 illustrates a system for partial or full implementation of signal processing blocks in a fifth generation (5G) new radio (NR) physical layer or channel (PHY) on one or more parallel processing units (PPUs), such as one or more graphics processing units (GPUs) 504, in a baseband unit (BBU). In at least one embodiment, a BBU contains one or more central processing units (CPUs) 502 and one or more PPUs, such as GPUs 504, that process software instructions that implement signal processing components or operations of 5G NR PHY. In at least one embodiment, signal processing components or operations are implemented in one or more software blocks 514, 516. In at least one embodiment, software blocks 514, 516 perform, when executed or processed by one or more CPUs 502 and / or one or more GPUs 504, signal processing algorithms involved in reception and transmission of 5G NR signals. In at least one embodiment, software blocks 514, 516 implement low physical layer (Low PHY) operations such as a fast fourier transform (FFT), inverse fast fourier transform (IFFT), and beamforming, as described herein. In at least one embodiment, software blocks 514, 516 perform, when executed or processed by one or more CPUs 502 and / or one or more GPUs 504, some or all 5G NR PHY processing operations for one or more physical channels.

[0082] In at least one embodiment, software blocks 514, 516 perform, when executed or processed by one or more CPUs 502 and / or one or more GPUs 504, a signal processing pipeline for 5G NR PHY. In at least one embodiment, a signal processing pipeline consists of at least several signal processing blocks 514, 516. In at least one embodiment, signal processing blocks are specific to each 5G NR PHY channel, described herein. In at least one embodiment, a downlink channel where a BBU implements a transmitter contains signal processing blocks specified by 3rd Generation Partnership Project (3GPP). In at least one embodiment, an uplink channel where a BBU implements a receiver, signal processing blocks implemented are flexible. In at least one embodiment, one or more GPUs 504 implement all functionality in a signal processing pipeline as software signal processing blocks 516. In at least one embodiment, one or more GPUs 504 function as an accelerator for a specific subset of signal processing blocks 516 in 5G NR PHY.

[0083] In at least one embodiment, 5G NR PHY channel processing is fully or partially implemented as software instruction blocks 516 on one or more PPUs, such as GPUs 504. In at least one embodiment, PPU and / or GPU 504 acceleration is achieved by implementing individual signal processing blocks or kernels 516, which are called from a CPU 502 host. In at least one embodiment, data is directly transferred between one or more network interface controllers (NICs) 506 and memory associated with one or more CPUs 502. In at least one embodiment, data is directly transferred between one or more network interface controllers (NICs) 506 and shared memory associated with one or more PPUs such as GPUs 504.

[0084] In at least one embodiment, one or more CPUs 502 contain instructions that implement, when executed, upper layers 510 of 5GNR PHY. In at least one embodiment, upper layers 510 include software libraries and other operations specified in 3GPP. In at least one embodiment, one or more CPUs 502 implement a PHY Controller 512. In at least one embodiment, a PHY Controller 512 provides an interface between 5GNR PHY signal processing operation blocks 514, 516, and upper layers 510 in a BBU. In at least one embodiment, a PHY Controller 512 acts as an interface between 5G NR PHY signal processing operations 514, 516 and upper layers 510 of a 3GPP protocol stack. In at least one embodiment, a PHY Controller 512 provides an application programming interface (API). In at least one embodiment, a PHY Controller 512 provides an API to interface with software instruction blocks or kernels that, when performed by one or more CPUs 502 and / or one or more PPUs, such as GPUs 504, implement 5G NR PHY operations. In at least one embodiment, a PHY Controller 512 provides an API that is based on a standard, such as Small Cell Forum FAPI Interface. In at least one embodiment, a PHY Controller 512 provides an API that is proprietary.

[0085] In at least one embodiment, a PHY Controller 512 manages software instruction blocks or kernels implementing 5GNRPHY run on any parallel processing units (PPUs), such as GPUs 504. In at least one embodiment, a PHY Controller 512 manages software kernels, or segments of software instructions to perform one or more specific operations, implementing signal processing operations such as those implemented in a PHY layer of a 5G new radio wireless communication system, where said software kernels are executed by one or more PPUs, such as GPUs 504, as described herein. In at least one embodiment, one or more PPUs, such as GPUs 504, may implement all functionality in a signal processing pipeline. In at least one embodiment, one or more PPUs, such as GPUs 504, may be used as accelerators for specific blocks of a signal processing pipeline, such as specific signal processing operations in 5GNR PHY. In at least one embodiment, a PHY Controller 512 provides software to manage GPU 504 software calls. In at least one embodiment, a PHY Controller 512 supplies necessary parameters to software kernels being executed by one or more GPUs 504. In at least one embodiment, a PHY Controller 512 manages output from software kernels being executed by one or more GPUs 504.

[0086] In at least one embodiment, one or more PPUs 504 execute software instruction blocks 516 that implement one or more operations that perform portions of 5G NR PHY. In at least one embodiment, one or more PPUs are GPUs 504 that provide acceleration for software instruction blocks or kernels 516 that implement some or all functions of specific 5GNR PHY operations. In at least one embodiment, one or more CPUs 502 are responsible for managing and launching software kernels on one or more GPUs 504. In at least one embodiment, one or more CPUs 502 build an execution graph of 5G NR PHY pipeline signal processing kernels to minimize the number of GPU 504 software kernels launched from a CPU 502.

[0087] In at least one embodiment, a physical uplink shared channel (PUSCH) receiver is implemented on one or more PPUs, such as GPUs 504, in a 5G NR BBU. In at least one embodiment, PUSCH in 5G NR PHY is designated to carry multiplexed control information and user application data, as described further herein. In at least one embodiment, specific PUSCH operations implemented as software kernels for execution by one or more PPUs, such as GPUs 504, include demodulation reference signal (DMRS) processing and channel estimation, receive beamforming weight calculation, equalizer weight calculation, signal equalization, layer and resource element demapping, soft demapping, descrambling, de-rate-matching, de-interleaving, and cyclic redundancy check (CRC) decoding. In at least one embodiment, a specific GPU kernel implements PUSCH beamforming, which specifically performs processing blocks including at least beamforming weight calculation and beamforming weight application. In at least one embodiment, a specific GPU kernel implements a PUSCH front-end, which specifically performs processing blocks including at least DMRS processing and channel estimation, receive beamforming weight calculation, equalizer weight calculation, signal equalization, layer demapping, and soft demapping. In at least one embodiment, a specific GPU kernel implements PUSCH de-rate-matching, which specifically performs processing blocks including at least resource element demapping, descrambling, de-rate-matching, and de-interleaving. In at least one embodiment, a specific GPU kernel implements a PUSCH low density parity check (LDPC) decoder, which specifically performs processing blocks including at least LDPC decoding. In at least one embodiment, a specific GPU kernel implements a PUSCH CRC decoder, which specifically performs processing blocks including at least CRC decoding.

[0088] In at least one embodiment, a physical downlink shared channel (PDSCH) transmitter is implemented on one or more PPUs, such as GPUs 504, in a 5G NR BBU. In at least one embodiment, PDSCH carries user data and higher-layer signaling, as described further herein. In at least one embodiment, specific PUSCH operations implemented as software kernels for execution by one or more PPUs, such as GPUs 504, include transport block segmentation, CRC encoding for transport blocks and code blocks, LDPC encoding, rate matching, interleaving, scrambling, modulation, resource element and layer mapping, precoding, beamforming weight calculation, and beamforming weight application. In at least one embodiment, a specific GPU kernel implements a PDSCH CRC encoder, which specifically performs processing blocks including at least CRC encoding. In at least one embodiment, a specific GPU kernel implements a PDSCH LDPC encoder, which specifically performs processing blocks including at least LDPC encoding. In at least one embodiment, a specific GPU kernel implements a PDSCH rate matching, which specifically performs processing blocks including at least rate matching, interleaving, scrambling, and resource element mapping. In at least one embodiment, a specific GPU kernel implements a PDSCH beamforming, which specifically performs processing blocks including at least beamforming weight calculation and beamforming weight application. In at least one embodiment, a specific GPU kernel implements a PDSCH front end, which specifically performs processing blocks including at least DMRS processing and channel estimation, receive beamforming weight calculation, equalizer weight calculation, signal equalization, layer demapping, and soft demapping. In at least one embodiment, a specific GPU kernel implements a PDSCH de-rate-matching, which specifically performs processing blocks including at least resource element demapping, descrambling, de-rate-matching, and de-interleaving. In at least one embodiment, a specific GPU kernel implements a PDSCH LDPC decoder, which specifically performs processing blocks including at least LDPC decoding. In at least one embodiment, a specific GPU kernel implements a PDSCH CRC decoder, which specifically performs processing blocks including at least CRC decoding.

[0089] In at least one embodiment, a physical uplink control channel (PUCCH) transmitter and physical downlink control channel (PDCCH) receiver are implemented on one or more PPUs, such as GPUs 504, in a 5G NR BBU. In at least one embodiment, PUCCH and PDCCH carry information about a transport format and resource allocations related to PUSCH and PDSCH channels, as described further herein. In at least one embodiment, specific PUCCH operations implemented as software kernels for execution by one or more PPUs, such as GPUs 504, include a PUCCH format 0 receiver, a PUCCH format 1 receiver, a PUCCH format 2 receiver, a PUCCH format 3 receiver, a PUCCH format 4 receiver, a polar decoder, and a PUCCH decoder. In at least one embodiment, a specific GPU kernel implements a PUCCH polar decoding kernel, which specifically performs processing blocks including at least a polar decoder. In at least one embodiment, a specific GPU kernel implements a PUCCH format 0 receiver kernel, which specifically performs processing blocks including at least a PUCCH sequence detector and simplex decoder. In at least one embodiment, a specific GPU kernel implements a PUCCH format 1 receiver kernel, which specifically performs processing blocks including at least a PUCCH format 1 channel estimator, PUCCH format 1 equalization and demodulation, and a PUCCH format 1 decoder. In at least one embodiment, a specific GPU kernel implements a PUCCH format 2 receiver kernel, which specifically performs processing blocks including at least a PUCCH format 2 sequence generator, a PUCCH format 2 demultiplexer, PUCCH format 2 equalization and demodulation, and a PUCCH format 2 decoder. In at least one embodiment, a specific GPU kernel implements a PUCCH format 3 receiver kernel, which specifically performs processing blocks including at least a PUCCH format 3 sequence generator, a PUCCH format 3 demultiplexer, PUCCH format 3 equalization and demodulation, and a PUCCH format 3 decoder. In at least one embodiment, a specific GPU kernel implements a PUCCH format 4 receiver kernel, which specifically performs processing blocks including at least PUCCH format 4 channel estimation and PUCCH format 4 equalization and demodulation.

[0090] In at least one embodiment, components in support of a physical random access channel (PRACH) are implemented on one or more PPUs, such as GPUs 504, in a 5G NR BBU. In at least one embodiment, PRACH provides support for facilitating cell discovery, as described further herein. In at least one embodiment, specific PRACH operations implemented as software kernels for execution by one or more PPUs, such as GPUs 504, include PRACH sequence generation, PRACH correlator and threshold calculation, and a PRACH detector. In at least one embodiment, a specific GPU kernel implements a PRACH sequence generation kernel, which specifically performs processing blocks including at least PRACH sequence generation. In at least one embodiment, a specific GPU kernel implements a PRACH correlator and threshold calculation kernel, which specifically performs processing blocks including at least PRACH correlator and threshold calculation. In at least one embodiment, a specific GPU kernel implements a PRACH detector kernel, which specifically performs processing blocks including at least a PRACH detector.

[0091] In at least one embodiment, other 5G NR PHY components are implemented on one or more PPUs, such as GPUs 504, in a 5G NR BBU. In at least one embodiment, other components include Low PHY operations and control information transmission components including LDPC encoding and decoding, fast fourier transform (FFT), inverse fast fourier transform (IFFT), demodulation reference signal (DMRS), phase-tracking reference signal (PTRS), sounding reference signal (SRS) and channel state information reference signal (CSI- RS), and other operations to perform Low PHY and control information transmission, further described herein. In at least one embodiment, other components include signal processing components for initial access and cell discovery, including physical broadcast channel (PBCH) and one or more synchronization signal blocks (SS Blocks), further described herein. In at least one embodiment, other components include further Low PHY operations such as cyclic prefix (CP) insertion to facilitate convolution as well as transmission beamforming (Tx Beamforming) and receive beamforming (Rx Beamforming), further described herein. In at least one embodiment, other components related to Tx Beamforming and Rx Beamforming include beamforming weight application implemented as GPU 504 kernels.

[0092] In at least one embodiment, one or more remote radio units (RRUs) or radio units (RUs) 508 contain one or more antennas. In at least one embodiment, one or more RRUs or RUs 508 convert radio signals to data transferred to one or more network interface controllers 506, described herein. In at least one embodiment, one or more NICs 506 provide data samples to one or more CPUs 502 across a communication channel in a BBU, including a communication bus. In at least one embodiment, one or more NICS 506 provide data samples to shared memory for one or more PPUs, including GPUs 506 across a communication channel in a BBU, including a communication bus.

[0093] In at least one embodiment, a BBU using one or more PPUs, including GPUs 504, is configured to handle different carrier configurations. In at least one embodiment, parameters in a BBU are configurable, including carrier bandwidth, TDD or FDD operation, number of received layers and number of receiver antennas 508, number of transmitted layers and number of transmitter antennas 508, numerology, slot format, reference signal format, modulation and coding scheme, transport block size, and any other parameters specified as configurable, both dynamically, semi-statically, and statically, by 3GPP. In at least one embodiment, for dynamic, semi-static, and static configurations, a BBU using one or more PPUs, including GPUs 504, is configured by passing specific configuration parameters to each software kernel, described above, at kernel launch. In at least one embodiment, for dynamic, semi-static, and static configurations, a BBU using one or more PPUs, including GPUs 504, is configured by selecting appropriate software kernels, described above, to launch based on available configuration parameters. In at least one embodiment, for semi-static and static configurations, a BBU using one or more PPUs, including GPUs 504, is configured by selecting a hardware and / or virtualization profile for that configuration.

[0094] In at least one embodiment, a cell sector carrier is one 5G NR carrier transmitted on a given cell site and sector. In at least one embodiment, a BBU using one or more PPUs, including GPUs 504 supports multiple cell sector carriers. In at least one embodiment, all sector carriers corresponding to a given cell site are handled by a single BBU containing one or more PPUs, including GPUs 504. In at least one embodiment, cell sector carriers in distributed geographical locations are handled by a single BBU containing one or more PPUs, including GPUs 504. In at least one embodiment, cell sector carriers in different frequency bands and with different configurations, such as bandwidth, numerology, number of receive and transmit layers, and number of receive and transmit antennas are supported by a single BBU containing one or more PPUs, including GPUs 504. In at least one embodiment, multiple cell sector carrier optimizations include multiple PHY channel pipelines, each consisting of multiple PPU or GPU 516 software kernel launches, where each handles one cell sector carrier. In at least one embodiment, multiple cell sector carrier optimizations include a C++ programming language class encapsulating functionality of a PHY channel pipeline, where multiple C++ class objects are instantiated to handle multiple cell sector carriers. In at least one embodiment, multiple cell sector carrier optimizations include associating each PHY pipeline object in a C++ class with a CUDA stream to enable submission of workload to a PPU, including a GPU 504, by a CPU 502 independent of other PHY pipelines. In at least one embodiment, multiple cell sector carrier optimizations include handling multiple cell sector carriers by a single PHY channel pipeline by aggregating inputs. In at least one embodiment, multiple cell sector carrier optimizations include where received signals are stacked in memory and treated as a single pipeline with higher bandwidth, or equivalently, a higher number of PRBs, described herein.

[0095] FIG. 6 illustrates a process for performing fifth generation (5G) new radio (NR) baseband unit (BBU) physical layer (PHY) operations on one or more parallel processing units (PPUs), such as graphics processing units (GPUs). In at least one embodiment, a process for performing 5G NR BBU PHY operations starts 602 by determining if a signal is received or to be transmitted 604. In at least one embodiment, if a signal is to be transmitted 604, data for transmission is received from upper layers 606, as described herein. In at least one embodiment, if one or more PPUs, such as GPUs, are to be used for acceleration of 5G PHY operations 608, then data is copied to shared memory associated with one or more PPUs, such as GPUs 610. In at least one embodiment, if no acceleration is to be used 608, then data is copied to shared memory associated with one or more central processing units (CPUs) 618.

[0096] In at least one embodiment, if acceleration is being used for data transmission, a CPU invokes individual or groups of functions or kernels 612 on one or more PPUs, such as GPUs, as described above. In at least one embodiment, those functions or kernels perform 5G PHY signal processing operations 614 on one or more PPUs, such as GPUs, as described above. In at least one embodiment, once accelerated 5GPHY processing is complete, data is copied directly or indirectly from one or more PPUs, such as GPUs, to one or more network interface controllers (NICs) 616.

[0097] In at least one embodiment, if acceleration is not being used for data transmission, 5G PHY signal processing operations are performed on one or more CPUs 620. In at least one embodiment, once 5G PHY processing on one or more CPUs is complete, signal data is copied from memory associated with one or more CPUs, to memory associated with one or more NICs 622, for transmission.

[0098] In at least one embodiment, if a signal is received 604 and acceleration by one or more PPUs, such as GPUs, is being used 624, then signal data is copied from memory associated with one or more NICs to memory associated with one or more PPUs, such as GPUs 626. In at least one embodiment, one or more CPUs invoke functions or kernels implementing individual 5GPHY signal processing operations 628, as described above, to perform 5GPHY processing 630. In at least one embodiment, once 5G PHY processing on one or more PPUs, such as GPUs, is complete, data is copied directly or indirectly from memory associated with one or more PPUs, such as GPUs, to memory associated with one or more CPUs for propagation to upper layers 632, as described above.

[0099] In at least one embodiment, if a signal is received 604 and acceleration by one or more PPUs, such as GPUs, is not being used 624, then signal data is copied from memory associated with one or more NICs directly to memory associated with one or more CPUs 634. In at least one embodiment, one or more CPUs then perform 5GPHY signal processing 636, and data is propagated to upper layers 638. In at least one embodiment, once 5G PHY layer operations are complete, a process for performing 5G NR BBU PHY operations is finished 640. DATA CENTER

[00100] FIG. 7 illustrates an example data center 700, in which at least one embodiment may be used. In at least one embodiment, data center 700 includes a data center infrastructure layer 710, a framework layer 720, a software layer 730 and an application layer 740.

[00101] In at least one embodiment, as shown in FIG. 7, data center infrastructure layer 710 may include a resource orchestrator 712, grouped computing resources 714, and node computing resources (“node C.R.s”) 716(1)-716(N), where “N” represents any whole, positive integer. In at least one embodiment, node C.R.s 716(1)-716(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid state or disk drives), network input / output ("NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more node C.R.s from among node C.R.s 716(1)-716(N) may be a server having one or more of above-mentioned computing resources.

[00102] In at least one embodiment, grouped computing resources 714 may include separate groupings of node C.R.s housed within one or more racks (not shown), or many racks housed in data centers at various geographical locations (also not shown). Separate groupings of node C.R.s within grouped computing resources 714 may include grouped compute, network, memory or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node C.R.s including CPUs or processors may grouped within one or more racks to provide compute resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[00103] In at least one embodiment, resource orchestrator 712 may configure or otherwise control one or more node C.R.s 716(1)-716(N) and / or grouped computing resources 714. In at least one embodiment, resource orchestrator 712 may include a software design infrastructure (“SDI”) management entity for data center 700. In at least one embodiment, resource orchestrator may include hardware, software or some combination thereof.

[00104] In at least one embodiment, as shown in FIG. 7, framework layer 720 includes a job scheduler 732, a configuration manager 734, a resource manager 736 and a distributed file system 738. In at least one embodiment, framework layer 720 may include a framework to support software 732 of software layer 730 and / or one or more application(s) 742 of application layer 740. In at least one embodiment, software 732 or application(s) 742 may respectively include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud and Microsoft Azure. In at least one embodiment, framework layer 720 may be, but is not limited to, a type of free and open-source software web application framework such as Apache Spark™ (hereinafter “Spark”) that may utilize distributed file system 738 for large-scale data processing (e.g., "big data"). In at least one embodimentjob scheduler 732 may include a Spark driver to facilitate scheduling of workloads supported by various layers of data center 700. In at least one embodiment, configuration manager 734 may be capable of configuring different layers such as software layer 730 and framework layer 720 including Spark and distributed file system 738 for supporting large-scale data processing. In at least one embodiment, resource manager 736 may be capable of managing clustered or grouped computing resources mapped to or allocated for support of distributed file system 738 and job scheduler 732. In at least one embodiment, clustered or grouped computing resources may include grouped computing resource 714 at data center infrastructure layer 710. In at least one embodiment, resource manager 736 may coordinate with resource orchestrator 712 to manage these mapped or allocated computing resources.

[00105] In at least one embodiment, software 732 included in software layer 730 may include software used by at least portions of node C.R.s 716(1)-716(N), grouped computing resources 714, and / or distributed file system 738 of framework layer 720. One or more types of software may include, but are not limited to, Internet web page search software, e-mail virus scan software, database software, and streaming video content software.

[00106] In at least one embodiment, application(s) 742 included in application layer 740 may include one or more types of applications used by at least portions of node C.R.s 716(1)-716(N), grouped computing resources 714, and / or distributed file system 738 of framework layer 720. One or more types of applications may include, but are not limited to, any number of a genomics application, a cognitive compute, and a machine learning application, including training or inferencing software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.) or other machine learning applications used in conjunction with one or more embodiments.

[00107] In at least one embodiment, any of configuration manager 734, resource manager 736, and resource orchestrator 712 may implement any number and type of self-modifying actions based on any amount and type of data acquired in any technically feasible fashion. In at least one embodiment, self-modifying actions may relieve a data center operator of data center 700 from making possibly bad configuration decisions and possibly avoiding underutilized and / or poor performing portions of a data center.

[00108] In at least one embodiment, data center 700 may include tools, services, software or other resources to train one or more machine learning models or predict or infer information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weight parameters according to a neural network architecture using software and computing resources described above with respect to data center 700. In at least one embodiment, trained machine learning models corresponding to one or more neural networks may be used to infer or predict information using resources described above with respect to data center 700 by using weight parameters calculated through one or more training techniques described herein.

[00109] In at least one embodiment, data center may use CPUs, application-specific integrated circuits (ASICs), GPUs, FPGAs, or other hardware to perform training and / or inferencing using above-described resources. Moreover, one or more software and / or hardware resources described above may be configured as a service to allow users to train or performing inferencing of information, such as image recognition, speech recognition, or other artificial intelligence services. Autonomous Vehicle

[00110] FIG. 8 A illustrates an example of an autonomous vehicle 800, according to at least one embodiment. In at least one embodiment, autonomous vehicle 800 (alternatively referred to herein as “vehicle 800”) may be, without limitation, a passenger vehicle, such as a car, a truck, a bus, and / or another type of vehicle that accommodates one or more passengers. In at least one embodiment, vehicle 800 may be a semi-tractor-trailer truck used for hauling cargo. In at least one embodiment, vehicle 800 may be an airplane, robotic vehicle, or other kind of vehicle.

[00111] Autonomous vehicles may be described in terms of automation levels, defined by National Highway Traffic Safety Administration (“NHTSA”), a division of US Department of Transportation, and Society of Automotive Engineers (“SAE”) "Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016-201806, published on June 15, 2018, Standard No. J3016-201609, published on September 30, 2016, and previous and future versions of this standard). In one or more embodiments, vehicle 800 may be capable of functionality in accordance with one or more of level 1 - level 5 of autonomous driving levels. For example, in at least one embodiment, vehicle 800 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on embodiment.

[00112] In at least one embodiment, vehicle 800 may include, without limitation, components such as a chassis, a vehicle body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of a vehicle. In at least one embodiment, vehicle 800 may include, without limitation, a propulsion system 850, such as an internal combustion engine, hybrid electric power plant, an all-electric engine, and / or another propulsion system type. In at least one embodiment, propulsion system 850 may be connected to a drive train of vehicle 800, which may include, without limitation, a transmission, to enable propulsion of vehicle 800. In at least one embodiment, propulsion system 850 may be controlled in response to receiving signals from a throttle / accelerator(s) 852.

[00113] In at least one embodiment, a steering system 854, which may include, without limitation, a steering wheel, is used to steer a vehicle 800 (e.g., along a desired path or route) when a propulsion system 850 is operating (e.g., when vehicle is in motion). In at least one embodiment, a steering system 854 may receive signals from steering actuator(s) 856. Steering wheel may be optional for full automation (Level 5) functionality. In at least one embodiment, a brake sensor system 846 may be used to operate vehicle brakes in response to receiving signals from brake actuator(s) 848 and / or brake sensors.

[00114] In at least one embodiment, controller(s) 836, which may include, without limitation, one or more system on chips (“SoCs”) (not shown in FIG. 8A) and / or graphics processing unit(s) (“GPU(s)”), provide signals (e.g., representative of commands) to one or more components and / or systems of vehicle 800. For instance, in at least one embodiment, controller(s) 836 may send signals to operate vehicle brakes via brake actuators 848, to operate steering system 854 via steering actuator(s) 856, to operate propulsion system 850 via throttle / accelerator(s) 852. Controller 836 may include one or more onboard (e.g., integrated) computing devices (e.g., supercomputers) that process sensor signals, and output operation commands (e.g., signals representing commands) to enable autonomous driving and / or to assist a human driver in driving vehicle 800. In at least one embodiment, controller(s) 836 may include a first controller 836 for autonomous driving functions, a second controller 836 for functional safety functions, a third controller 836 for artificial intelligence functionality (e.g., computer vision), a fourth controller 836 for infotainment functionality, a fifth controller 836 for redundancy in emergency conditions, and / or other controllers. In at least one embodiment, a single controller 836 may handle two or more of above functionalities, two or more controllers 836 may handle a single functionality, and / or any combination thereof.

[00115] In at least one embodiment, controller(s) 836 provide signals for controlling one or more components and / or systems of vehicle 800 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, sensor data may be received from, for example and without limitation, global navigation satellite systems (“GNSS”) sensor(s) 858 (e.g., Global Positioning System sensor(s)), RADAR sensor(s) 860, ultrasonic sensor(s) 862, LIDAR sensor(s) 864, inertial measurement unit (“IMU”) sensor(s) 866 (e.g., accelerometer(s), gyroscope(s), magnetic compass(es), magnetometer(s), etc.), microphone(s) 896, stereo camera(s) 868, wide-view camera(s) 870 (e.g., fisheye cameras), infrared camera(s) 872, surround camera(s) 874 (e.g., 360 degree cameras), long-range cameras (not shown in Figure 8A), mid-range camera(s) (not shown in Figure 8A), speed sensor(s) 844 (e.g., for measuring speed of vehicle 800), vibration sensor(s) 842, steering sensor(s) 840, brake sensor(s) (e.g., as part of brake sensor system 846), and / or other sensor types.

[00116] In at least one embodiment, one or more of controller(s) 836 may receive inputs (e.g., represented by input data) from an instrument cluster 832 of vehicle 800 and provide outputs (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 834, an audible annunciator, a loudspeaker, and / or via other components of vehicle 800. In at least one embodiment, outputs may include information such as vehicle velocity, speed, time, map data (e.g., a High Definition map (not shown in FIG. 8A), location data (e.g., vehicle’s 800 location, such as on a map), direction, location of other vehicles (e.g., an occupancy grid), information about objects and status of objects as perceived by controller(s) 836, etc. For example, in at least one embodiment, HMI display 834 may display information about presence of one or more objects (e.g., a street sign, caution sign, traffic light changing, etc.), and / or information about driving maneuvers vehicle has made, is making, or will make (e.g., changing lanes now, taking exit 34B in two miles, etc.).

[00117] In at least one embodiment, vehicle 800 further includes a network interface 824 which may use wireless antenna(s) 826 and / or modem(s) to communicate over one or more networks. For example, in at least one embodiment, network interface 824 may be capable of communication over Long-Term Evolution (“LTE”), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile communication (“GSM”), IMT-CDMA Multi-Carrier (“CDMA2000”), etc. In at least one embodiment, wireless antenna(s) 826 may also enable communication between objects in environment (e.g., vehicles, mobile devices, etc.), using local area network(s), such as Bluetooth, Bluetooth Low Energy (“LE”), Z-Wave, ZigBee, etc., and / or low power wide-area network(s) (“LPWANs”), such as LoRaWAN, SigFox, etc.

[00118] FIG. 8B illustrates an example of camera locations and fields of view for autonomous vehicle 800 of FIG. 8 A, according to at least one embodiment. In at least one embodiment, cameras and respective fields of view are one example embodiment and are not intended to be limiting. For instance, in at least one embodiment, additional and / or alternative cameras may be included and / or cameras may be located at different locations on vehicle 800.

[00119] In at least one embodiment, camera types for cameras may include, but are not limited to, digital cameras that may be adapted for use with components and / or systems of vehicle 800. Camera may operate at automotive safety integrity level (“ASIL”) B and / or at another ASIL. In at least one embodiment, camera types may be capable of any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc., depending on embodiment. In at least one embodiment, cameras may be capable of using rolling shutters, global shutters, another type of shutter, or a combination thereof. In at least one embodiment, color filter array may include a red clear clear clear (“RCCC”) color filter array, a red clear clear blue (“RCCB”) color filter array, a red blue green clear (“RBGC”) color filter array, a Foveon X3 color filter array, a Bayer sensors (“RGGB”) color filter array, a monochrome sensor color filter array, and / or another type of color filter array. In at least one embodiment, clear pixel cameras, such as cameras with an RCCC, an RCCB, and / or an RBGC color filter array, may be used in an effort to increase light sensitivity.

[00120] In at least one embodiment, one or more of camera(s) may be used to perform advanced driver assistance systems (“ADAS”) functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a Multi-Function Mono Camera may be installed to provide functions including lane departure warning, traffic sign assist and intelligent headlamp control. In at least one embodiment, one or more of camera(s) (e.g., all of cameras) may record and provide image data (e.g., video) simultaneously.

[00121] In at least one embodiment, one or more of cameras may be mounted in a mounting assembly, such as a custom designed (three-dimensional (“3D”) printed) assembly, in order to cut out stray light and reflections from within car (e.g., reflections from dashboard reflected in windshield mirrors) which may interfere with camera’s image data capture abilities. With reference to wing-mirror mounting assemblies, in at least one embodiment, wing-mirror assemblies may be custom 3D printed so that camera mounting plate matches shape of wingmirror. In at least one embodiment, camera(s) may be integrated into wing-mirror. In at least one embodiment, for side-view cameras, camera(s) may also be integrated within four pillars at each corner of car.

[00122] In at least one embodiment, cameras with a field of view that include portions of environment in front of vehicle 800 (e.g., front-facing cameras) may be used for surround view, to help identify forward facing paths and obstacles, as well as aid in, with help of one or more of controllers 836 and / or control SoCs, providing information critical to generating an occupancy grid and / or determining preferred vehicle paths. In at least one embodiment, front-facing cameras may be used to perform many of same ADAS functions as LIDAR, including, without limitation, emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, front-facing cameras may also be used for ADAS functions and systems including, without limitation, Lane Departure Warnings (“LDW”), Autonomous Cruise Control (“ACC”), and / or other functions such as traffic sign recognition.

[00123] In at least one embodiment, a variety of cameras may be used in a front-facing configuration, including, for example, a monocular camera platform that includes a CMOS (“complementary metal oxide semiconductor”) color imager. In at least one embodiment, wide-view camera 870 may be used to perceive objects coming into view from periphery (e.g., pedestrians, crossing traffic or bicycles). Although only one wide-view camera 870 is illustrated in FIG. 8B, in other embodiments, there may be any number (including zero) of wide-view camera(s) 870 on vehicle 800. In at least one embodiment, any number of long-range camera(s) 898 (e.g., a long-view stereo camera pair) may be used for depth-based object detection, especially for objects for which a neural network has not yet been trained. In at least one embodiment, long-range camera(s) 898 may also be used for object detection and classification, as well as basic object tracking.

[00124] In at least one embodiment, any number of stereo camera(s) 868 may also be included in a front-facing configuration. In at least one embodiment, one or more of stereo camera(s) 868 may include an integrated control unit comprising a scalable processing unit, which may provide a programmable logic (“FPGA”) and a multi-core micro-processor with an integrated Controller Area Network (“CAN”) or Ethernet interface on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of environment of vehicle 800, including a distance estimate for all points in image. In at least one embodiment, one or more of stereo camera(s) 868 may include, without limitation, compact stereo vision sensor(s) that may include, without limitation, two camera lenses (one each on left and right) and an image processing chip that may measure distance from vehicle 800 to target object and use generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo camera(s) 868 may be used in addition to, or alternatively from, those described herein.

[00125] In at least one embodiment, cameras with a field of view that include portions of environment to side of vehicle 800 (e.g., side-view cameras) may be used for surround view, providing information used to create and update occupancy grid, as well as to generate side impact collision warnings. For example, in at least one embodiment, surround camera(s) 874 (e.g., four surround cameras 874 as illustrated in FIG. 8B) could be positioned on vehicle 800. Surround camera(s) 874 may include, without limitation, any number and combination of wide-view camera(s) 870, fisheye camera(s), 360 degree camera(s), and / or like. For instance, in at least one embodiment, four fisheye cameras may be positioned on front, rear, and sides of vehicle 800. In at least one embodiment, vehicle 800 may use three surround camera(s) 874 (e.g., left, right, and rear), and may leverage one or more other camera(s) (e.g., a forward-facing camera) as a fourth surround-view camera.

[00126] In at least one embodiment, cameras with a field of view that include portions of environment to rear of vehicle 800 (e.g., rear-view cameras) may be used for park assistance, surround view, rear collision warnings, and creating and updating occupancy grid. In at least one embodiment, a wide variety of cameras may be used including, but not limited to, cameras that are also suitable as a front-facing camera(s) (e.g., long-range cameras 898 and / or mid-range camera(s) 876, stereo camera(s) 868), infrared camera(s) 872, etc.), as described herein.

[00127] FIG. 8C is a block diagram illustrating an example system architecture for autonomous vehicle 800 of FIG. 8 A, according to at least one embodiment. In at least one embodiment, each of components, features, and systems of vehicle 800 in FIG. 8C are illustrated as being connected via a bus 802. In at least one embodiment, bus 802 may include, without limitation, a CAN data interface (alternatively referred to herein as a “CAN bus”). In at least one embodiment, a CAN may be a network inside vehicle 800 used to aid in control of various features and functionality of vehicle 800, such as actuation of brakes, acceleration, braking, steering, windshield wipers, etc. In at least one embodiment, bus 802 may be configured to have dozens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, bus 802 may be read to find steering wheel angle, ground speed, engine revolutions per minute (“RPMs”), button positions, and / or other vehicle status indicators. In at least one embodiment, bus 802 may be a CAN bus that is ASIL B compliant.

[00128] In at least one embodiment, in addition to, or alternatively from CAN, FlexRay and / or Ethernet may be used. In at least one embodiment, there may be any number of busses 802, which may include, without limitation, zero or more CAN busses, zero or more FlexRay busses, zero or more Ethernet busses, and / or zero or more other types of busses using a different protocol. In at least one embodiment, two or more busses 802 may be used to perform different functions, and / or may be used for redundancy. For example, a first bus 802 may be used for collision avoidance functionality and a second bus 802 may be used for actuation control. In at least one embodiment, each bus 802 may communicate with any of components of vehicle 800, and two or more busses 802 may communicate with same components. In at least one embodiment, each of any number of system(s) on chip(s) (“SoC(s)”) 804, each of controller(s) 836, and / or each computer within vehicle may have access to same input data (e.g., inputs from sensors of vehicle 800), and may be connected to a common bus, such CAN bus.

[00129] In at least one embodiment, vehicle 800 may include one or more controlled s) 836, such as those described herein with respect to FIG. 8 A. Controller 836 may be used for a variety of functions. In at least one embodiment, controlleds) 836 may be coupled to any of various other components and systems of vehicle 800, and may be used for control of vehicle 800, artificial intelligence of vehicle 800, infotainment for vehicle 800, and / or like.

[00130] In at least one embodiment, vehicle 800 may include any number of SoCs 804. Each of SoCs 804 may include, without limitation, central processing units (“CPU(s)”) 806, graphics processing units (“GPU(s)”) 808, processor(s) 810, cache(s) 812, accelerator(s) 814, data store(s) 816, and / or other components and features not illustrated. In at least one embodiment, SoC(s) 804 may be used to control vehicle 800 in a variety of platforms and systems. For example, in at least one embodiment, SoC(s) 804 may be combined in a system (e.g., system of vehicle 800) with a High Definition (“HD”) map 822 which may obtain map refreshes and / or updates via network interface 824 from one or more servers (not shown in Figure 8C).

[00131] In at least one embodiment, CPU(s) 806 may include a CPU cluster or CPU complex (alternatively referred to herein as a “CCPLEX”). In at least one embodiment, CPU(s) 806 may include multiple cores and / or level two (“L2”) caches. For instance, in at least one embodiment, CPU(s) 806 may include eight cores in a coherent multi-processor configuration. In at least one embodiment, CPU(s) 806 may include four dual-core clusters where each cluster has a dedicated L2 cache (e.g., a 2 MB L2 cache). In at least one embodiment, CPU(s) 806 (e.g., CCPLEX) may be configured to support simultaneous cluster operation enabling any combination of clusters of CPU(s) 806 to be active at any given time.

[00132] In at least one embodiment, one or more of CPU(s) 806 may implement power management capabilities that include, without limitation, one or more of following features: individual hardware blocks may be clock-gated automatically when idle to save dynamic power; each core clock may be gated when core is not actively executing instructions due to execution of Wait for Interrupt ("WFI”) / Wait for Event ("WFE”) instructions; each core may be independently power-gated; each core cluster may be independently clock-gated when all cores are clock-gated or power-gated; and / or each core cluster may be independently power-gated when all cores are power-gated. In at least one embodiment, CPU(s) 806 may further implement an enhanced algorithm for managing power states, where allowed power states and expected wakeup times are specified, and hard war e / microcode determines best power state to enter for core, cluster, and CCPLEX. In at least one embodiment, processing cores may support simplified power state entry sequences in software with work offloaded to microcode.

[00133] In at least one embodiment, GPU(s) 808 may include an integrated GPU (alternatively referred to herein as an “iGPU”). In at least one embodiment, GPU(s) 808 may be programmable and may be efficient for parallel workloads. In at least one embodiment, GPU(s) 808, in at least one embodiment, may use an enhanced tensor instruction set. In on embodiment, GPU(s) 808 may include one or more streaming microprocessors, where each streaming microprocessor may include a level one (“LI”) cache (e.g., an LI cache with at least 96KB storage capacity), and two or more of streaming microprocessors may share an L2 cache (e.g., an L2 cache with a 512 KB storage capacity). In at least one embodiment, GPU(s) 808 may include at least eight streaming microprocessors. In at least one embodiment, GPU(s) 808 may use compute application programming interface(s) (API(s)). In at least one embodiment, GPU(s) 808 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA’s CUD A).

[00134] In at least one embodiment, one or more of GPU(s) 808 may be power-optimized for best performance in automotive and embedded use cases. For example, in on embodiment, GPU(s) 808 could be fabricated on a Fin field-effect transistor ("FinFET”). In at least one embodiment, each streaming microprocessor may incorporate a number of mixed-precision processing cores partitioned into multiple blocks. For example, and without limitation, 64 PF32 cores and 32 PF64 cores could be partitioned into four processing blocks. In at least one embodiment, each processing block could be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA TENSOR COREs for deep learning matrix arithmetic, a level zero (“L0”) instruction cache, a warp scheduler, a dispatch unit, and / or a 64 KB register file. In at least one embodiment, streaming microprocessors may include independent parallel integer and floating-point data paths to provide for efficient execution of workloads with a mix of computation and addressing calculations. In at least one embodiment, streaming microprocessors may include independent thread scheduling capability to enable finer-grain synchronization and cooperation between parallel threads. In at least one embodiment, streaming microprocessors may include a combined LI data cache and shared memory unit in order to improve performance while simplifying programming.

[00135] In at least one embodiment, one or more of GPU(s) 808 may include a high bandwidth memory ("HBM) and / or a 16 GB HBM2 memory subsystem to provide, in some examples, about 900 GB / second peak memory bandwidth. In at least one embodiment, in addition to, or alternatively from, HBM memory, a synchronous graphics random-access memory ("SGRAM”) may be used, such as a graphics double data rate type five synchronous random-access memory ("GDDR5”).

[00136] In at least one embodiment, GPU(s) 808 may include unified memory technology. In at least one embodiment, address translation services (“ATS”) support may be used to allow GPU(s) 808 to access CPU(s) 806 page tables directly. In at least one embodiment, embodiment, when GPU(s) 808 memory management unit ("MMU”) experiences a miss, an address translation request may be transmitted to CPU(s) 806. In response, CPU(s) 806 may look in its page tables for virtual-to-physical mapping for address and transmits translation back to GPU(s) 808, in at least one embodiment. In at least one embodiment, unified memory technology may allow a single unified virtual address space for memory of both CPU(s) 806 and GPU(s) 808, thereby simplifying GPU(s) 808 programming and porting of applications to GPU(s) 808.

[00137] In at least one embodiment, GPU(s) 808 may include any number of access counters that may keep track of frequency of access of GPU(s) 808 to memory of other processors. In at least one embodiment, access counter(s) may help ensure that memory pages are moved to physical memory of processor that is accessing pages most frequently, thereby improving efficiency for memory ranges shared between processors.

[00138] In at least one embodiment, one or more of SoC(s) 804 may include any number of cache(s) 812, including those described herein. For example, in at least one embodiment, cache(s) 812 could include a level three (”L3”) cache that is available to both CPU(s) 806 and GPU(s) 808 (e.g., that is connected both CPU(s) 806 and GPU(s) 808). In at least one embodiment, cache(s) 812 may include a write-back cache that may keep track of states of lines, such as by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, L3 cache may include 4 MB or more, depending on embodiment, although smaller cache sizes may be used.

[00139] In at least one embodiment, one or more of SoC(s) 804 may include one or more accelerator(s) 814 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, SoC(s) 804 may include a hardware acceleration cluster that may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM), may enable hardware acceleration cluster to accelerate neural networks and other calculations. In at least one embodiment, hardware acceleration cluster may be used to complement GPU(s) 808 and to off-load some of tasks of GPU(s) 808 (e.g., to free up more cycles of GPU(s) 808 for performing other tasks). In at least one embodiment, accelerator s) 814 could be used for targeted workloads (e.g., perception, convolutional neural networks ("CNNs”), recurrent neural networks (“RNNs”), etc.) that are stable enough to be amenable to acceleration. In at least one embodiment, a CNN may include a region-based or regional convolutional neural networks ("RCNNs”) and Fast RCNNs (e.g., as used for object detection) or other type of CNN.

[00140] In at least one embodiment, accelerator(s) 814 (e.g., hardware acceleration cluster) may include a deep learning accelerator(s) ("DLA). DLA(s) may include, without limitation, one or more Tensor processing units ("TPUs) that may be configured to provide an additional ten trillion operations per second for deep learning applications and inferencing. In at least one embodiment, TPUs may be accelerators configured to, and optimized for, performing image processing functions (e.g., for CNNs, RCNNs, etc.). DLA(s) may further be optimized for a specific set of neural network types and floating point operations, as well as inferencing. In at least one embodiment, design of DLA(s) may provide more performance per millimeter than a typical general-purpose GPU, and typically vastly exceeds performance of a CPU. In at least one embodiment, TPU(s) may perform several functions, including a single-instance convolution function, supporting, for example, INT8, INTI6, and FP16 data types for both features and weights, as well as post-processor functions. In at least one embodiment, DLA(s) may quickly and efficiently execute neural networks, especially CNNs, on processed or unprocessed data for any of a variety of functions, including, for example and without limitation: a CNN for object identification and detection using data from camera sensors; a CNN for distance estimation using data from camera sensors; a CNN for emergency vehicle detection and identification and detection using data from microphones 896; a CNN for facial recognition and vehicle owner identification using data from camera sensors; and / or a CNN for security and / or safety related events.

[00141] In at least one embodiment, DLA(s) may perform any function of GPU(s) 808, and by using an inference accelerator, for example, a designer may target either DLA(s) or GPU(s) 808 for any function. For example, in at least one embodiment, designer may focus processing of CNNs and floating point operations on DLA(s) and leave other functions to GPU(s) 808 and / or other accelerator / s) 814.

[00142] In at least one embodiment, accelerator(s) 814 (e.g., hardware acceleration cluster) may include a programmable vision accelerator(s) ("PVA”), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, PVA(s) may be designed and configured to accelerate computer vision algorithms for advanced driver assistance system ("ADAS”) 838, autonomous driving, augmented reality ("AR”) applications, and / or virtual reality ("VR”) applications. PVA(s) may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA(s) may include, for example and without limitation, any number of reduced instruction set computer ("RISC”) cores, direct memory access ("DMA”), and / or any number of vector processors.

[00143] In at least one embodiment, RISC cores may interact with image sensors (e.g., image sensors of any of cameras described herein), image signal processor(s), and / or like. In at least one embodiment, each of RISC cores may include any amount of memory. In at least one embodiment, RISC cores may use any of a number of protocols, depending on embodiment. In at least one embodiment, RISC cores may execute a real-time operating system ("RTOS”). In at least one embodiment, RISC cores may be implemented using one or more integrated circuit devices, application specific integrated circuits ("ASICs”), and / or memory devices. For example, in at least one embodiment, RISC cores could include an instruction cache and / or a tightly coupled RAM.

[00144] In at least one embodiment, DMA may enable components of PVA(s) to access system memory independently of CPU(s) 806. In at least one embodiment, DMA may support any number of features used to provide optimization to PVA including, but not limited to, supporting multi-dimensional addressing and / or circular addressing. In at least one embodiment, DMA may support up to six or more dimensions of addressing, which may include, without limitation, block width, block height, block depth, horizontal block stepping, vertical block stepping, and / or depth stepping.

[00145] In at least one embodiment, vector processors may be programmable processors that may be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, PVA core may include a processor subsystem, DMA engine(s) (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, vector processing subsystem may operate as primary processing engine of PVA, and may include a vector processing unit ("VPU”), an instruction cache, and / or vector memory (e.g., “VMEM”). In at least one embodiment, VPU core may include a digital signal processor such as, for example, a single instruction, multiple data ("SIMD”), very long instruction word ("VLIW”) digital signal processor. In at least one embodiment, a combination of SIMD and VLIW may enhance throughput and speed.

[00146] In at least one embodiment, each of vector processors may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each of vector processors may be configured to execute independently of other vector processors. In at least one embodiment, vector processors that are included in a particular PVA may be configured to employ data parallelism. For instance, in at least one embodiment, plurality of vector processors included in a single PVA may execute same computer vision algorithm, but on different regions of an image. In at least one embodiment, vector processors included in a particular PVA may simultaneously execute different computer vision algorithms, on same image, or even execute different algorithms on sequential images or portions of an image. In at least one embodiment, among other things, any number of PVAs may be included in hardware acceleration cluster and any number of vector processors may be included in each of PVAs. In at least one embodiment, PVA(s) may include additional error correcting code ("ECC”) memory, to enhance overall system safety.

[00147] In at least one embodiment, accelerator(s) 814 (e.g., hardware acceleration cluster) may include a computer vision network on-chip and static random-access memory ("SRAM”), for providing a high-bandwidth, low latency SRAM for accelerator(s) 814. In at least one embodiment, on-chip memory may include at least 4MB SRAM, consisting of, for example and without limitation, eight field-configurable memory blocks, that may be accessible by both PVA and DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus ("APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, PVA and DLA may access memory via a backbone that provides PVA and DLA with high-speed access to memory. In at least one embodiment, backbone may include a computer vision network on-chip that interconnects PVA and DLA to memory (e.g., using APB).

[00148] In at least one embodiment, computer vision network on-chip may include an interface that determines, before transmission of any control signal / address / data, that both PVA and DLA provide ready and valid signals. In at least one embodiment, an interface may provide for separate phases and separate channels for transmitting control signals / addresses / data, as well as burst-type communications for continuous data transfer. In at least one embodiment, an interface may comply with International Organization for Standardization (“ISO”) 26262 or International Electrotechnical Commission (“IEC”) 61508 standards, although other standards and protocols may be used.

[00149] In at least one embodiment, one or more of SoC(s) 804 may include a real-time raytracing hardware accelerator. In at least one embodiment, real-time ray-tracing hardware accelerator may be used to quickly and efficiently determine positions and extents of objects (e.g., within a world model), to generate real-time visualization simulations, for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulation, for comparison to LIDAR data for purposes of localization and / or other functions, and / or for other uses.

[00150] In at least one embodiment, accelerator(s) 814 (e.g., hardware accelerator cluster) have a wide array of uses for autonomous driving. In at least one embodiment, PVA may be a programmable vision accelerator that may be used for key processing stages in ADAS and autonomous vehicles. In at least one embodiment, PVA’s capabilities are a good match for algorithmic domains needing predictable processing, at low power and low latency. In other words, PVA performs well on semi-dense or dense regular computation, even on small data sets, which need predictable run-times with low latency and low power. In at least one embodiment, autonomous vehicles, such as vehicle 800, PVAs are designed to run classic computer vision algorithms, as they are efficient at object detection and operating on integer math.

[00151] For example, according to at least one embodiment of technology, PVA is used to perform computer stereo vision. In at least one embodiment, semi-global matching-based algorithm may be used in some examples, although this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation / stereo matching on-the-fly (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, PVA may perform computer stereo vision function on inputs from two monocular cameras.

[00152] In at least one embodiment, PVA may be used to perform dense optical flow. For example, in at least one embodiment, PVA could process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, PVA is used for time of flight depth processing, by processing raw time of flight data to provide processed time of flight data, for example.

[00153] In at least one embodiment, DLA may be used to run any type of network to enhance control and driving safety, including for example and without limitation, a neural network that outputs a measure of confidence for each object detection. In at least one embodiment, confidence may be represented or interpreted as a probability, or as providing a relative “weight” of each detection compared to other detections. In at least one embodiment, confidence enables a system to make further decisions regarding which detections should be considered as true positive detections rather than false positive detections. For example, in at least one embodiment, a system may set a threshold value for confidence and consider only detections exceeding threshold value as true positive detections. In an embodiment in which an automatic emergency braking ("AEB”) system is used, false positive detections would cause vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, highly confident detections may be considered as triggers for AEB. In at least one embodiment, DLA may run a neural network for regressing confidence value. In at least one embodiment, neural network may take as its input at least some subset of parameters, such as bounding box dimensions, ground plane estimate obtained (e.g. from another subsystem), output from IMU sensor(s) 866 that correlates with vehicle 800 orientation, distance, 3D location estimates of object obtained from neural network and / or other sensors (e.g., LIDAR sensor(s) 864 or RADAR sensor(s) 860), among others.

[00154] In at least one embodiment, one or more of SoC(s) 804 may include data store(s) 816 (e.g., memory). In at least one embodiment, data store(s) 816 may be on-chip memory of SoC(s) 804, which may store neural networks to be executed on GPU(s) 808 and / or DLA. In at least one embodiment, data store(s) 816 may be large enough in capacity to store multiple instances of neural networks for redundancy and safety. In at least one embodiment, data store(s) 812 may comprise L2 or L3 cache(s). .

[00155] In at least one embodiment, one or more of SoC(s) 804 may include any number of processor(s) 810 (e.g., embedded processors). Processor 810 may include a boot and power management processor that may be a dedicated processor and subsystem to handle boot power and management functions and related security enforcement. In at least one embodiment, boot and power management processor may be a part of SoC(s) 804 boot sequence and may provide runtime power management services. In at least one embodiment, boot power and management processor may provide clock and voltage programming, assistance in system low power state transitions, management of SoC(s) 804 thermals and temperature sensors, and / or management of SoC(s) 804 power states. In at least one embodiment, each temperature sensor may be implemented as a ring-oscillator whose output frequency is proportional to temperature, and SoC(s) 804 may use ring-oscillators to detect temperatures of CPU(s) 806, GPU(s) 808, and / or accelerator(s) 814. In at least one embodiment, if temperatures are determined to exceed a threshold, then boot and power management processor may enter a temperature fault routine and put SoC(s) 804 into a lower power state and / or put vehicle 800 into a chauffeur to safe stop mode (e.g., bring vehicle 800 to a safe stop).

[00156] In at least one embodiment, processor(s) 810 may further include a set of embedded processors that may serve as an audio processing engine. In at least one embodiment, audio processing engine may be an audio subsystem that enables full hardware support for multichannel audio over multiple interfaces, and a broad and flexible range of audio I / O interfaces. In at least one embodiment, audio processing engine is a dedicated processor core with a digital signal processor with dedicated RAM.

[00157] In at least one embodiment, processor(s) 810 may further include an always on processor engine that may provide necessary hardware features to support low power sensor management and wake use cases. In at least one embodiment, always on processor engine may include, without limitation, a processor core, a tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[00158] In at least one embodiment, processor(s) 810 may further include a safety cluster engine that includes, without limitation, a dedicated processor subsystem to handle safety management for automotive applications. In at least one embodiment, safety cluster engine may include, without limitation, two or more processor cores, a tightly coupled RAM, support peripherals (e.g., timers, an interrupt controller, etc.), and / or routing logic. In a safety mode, two or more cores may operate, in at least one embodiment, in a lockstep mode and function as a single core with comparison logic to detect any differences between their operations. In at least one embodiment, processor(s) 810 may further include a real-time camera engine that may include, without limitation, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, processor(s) 810 may further include a high-dynamic range signal processor that may include, without limitation, an image signal processor that is a hardware engine that is part of camera processing pipeline.

[00159] In at least one embodiment, processor(s) 810 may include a video image compositor that may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions needed by a video playback application to produce final image for player window. In at least one embodiment, video image compositor may perform lens distortion correction on wide-view camera(s) 870, surround camera(s) 874, and / or on in-cabin monitoring camera sensor(s). In at least one embodiment, in-cabin monitoring camera sensor(s) are preferably monitored by a neural network running on another instance of SoC 804, configured to identify in cabin events and respond accordingly. In at least one embodiment, an in-cabin system may perform, without limitation, lip reading to activate cellular service and place a phone call, dictate emails, change vehicle’s destination, activate or change vehicle’s infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain functions are available to driver when vehicle is operating in an autonomous mode and are disabled otherwise.

[00160] In at least one embodiment, video image compositor may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, where motion occurs in a video, noise reduction weights spatial information appropriately, decreasing weight of information provided by adjacent frames. In at least one embodiment, where an image or portion of an image does not include motion, temporal noise reduction performed by video image compositor may use information from previous image to reduce noise in current image.

[00161] In at least one embodiment, video image compositor may also be configured to perform stereo rectification on input stereo lens frames. In at least one embodiment, video image compositor may further be used for user interface composition when operating system desktop is in use, and GPU(s) 808 are not required to continuously render new surfaces. In at least one embodiment, when GPU(s) 808 are powered on and active doing 3D rendering, video image compositor may be used to offload GPU(s) 808 to improve performance and responsiveness.

[00162] In at least one embodiment, one or more of SoC(s) 804 may further include a mobile industry processor interface (“MIPI”) camera serial interface for receiving video and input from cameras, a high-speed interface, and / or a video input block that may be used for camera and related pixel input functions. In at least one embodiment, one or more of SoC(s) 804 may further include an input / output controller(s) that may be controlled by software and may be used for receiving I / O signals that are uncommitted to a specific role.

[00163] In at least one embodiment, one or more of SoC(s) 804 may further include a broad range of peripheral interfaces to enable communication with peripherals, audio encoders / decoders (“codecs”), power management, and / or other devices. SoC(s) 804 may be used to process data from cameras (e.g., connected over Gigabit Multimedia Serial Link and Ethernet), sensors (e.g., LIDAR sensor(s) 864, RADAR sensor(s) 860, etc. that may be connected over Ethernet), data from bus 802 (e.g., speed of vehicle 800, steering wheel position, etc.), data from GNSS sensor(s) 858 (e.g., connected over Ethernet or CAN bus), etc. In at least one embodiment, one or more of SoC(s) 804 may further include dedicated high-performance mass storage controllers that may include their own DMA engines, and that may be used to free CPU(s) 806 from routine data management tasks.

[00164] In at least one embodiment, SoC(s) 804 may be an end-to-end platform with a flexible architecture that spans automation levels 3-5, thereby providing a comprehensive functional safety architecture that leverages and makes efficient use of computer vision and ADAS techniques for diversity and redundancy, provides a platform for a flexible, reliable driving software stack, along with deep learning tools. In at least one embodiment, SoC(s) 804 may be faster, more reliable, and even more energy-efficient and space-efficient than conventional systems. For example, in at least one embodiment, accelerator(s) 814, when combined with CPU(s) 806, GPU(s) 808, and data store(s) 816, may provide for a fast, efficient platform for level 3-5 autonomous vehicles.

[00165] In at least one embodiment, computer vision algorithms may be executed on CPUs, which may be configured using high-level programming language, such as C programming language, to execute a wide variety of processing algorithms across a wide variety of visual data. However, in at least one embodiment, CPUs are oftentimes unable to meet performance requirements of many computer vision applications, such as those related to execution time and power consumption, for example. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real-time, which is used in in-vehicle ADAS applications and in practical Level 3-5 autonomous vehicles.

[00166] Embodiments described herein allow for multiple neural networks to be performed simultaneously and / or sequentially, and for results to be combined together to enable Level 3-5 autonomous driving functionality. For example, in at least one embodiment, a CNN executing on DLA or discrete GPU (e.g., GPU(s) 820) may include text and word recognition, allowing supercomputer to read and understand traffic signs, including signs for which neural network has not been specifically trained. In at least one embodiment, DLA may further include a neural network that is able to identify, interpret, and provide semantic understanding of sign, and to pass that semantic understanding to path planning modules running on CPU Complex.

[00167] In at least one embodiment, multiple neural networks may be run simultaneously, as for Level 3, 4, or 5 driving. For example, in at least one embodiment, a warning sign consisting of “Caution: flashing lights indicate icy conditions,” along with an electric light, may be independently or collectively interpreted by several neural networks. In at least one embodiment, sign itself may be identified as a traffic sign by a first deployed neural network (e.g., a neural network that has been trained), text “flashing lights indicate icy conditions” may be interpreted by a second deployed neural network, which informs vehicle’s path planning software (preferably executing on CPU Complex) that when flashing lights are detected, icy conditions exist. In at least one embodiment, flashing light may be identified by operating a third deployed neural network over multiple frames, informing vehicle’s path-planning software of presence (or absence) of flashing lights. In at least one embodiment, all three neural networks may run simultaneously, such as within DLA and / or on GPU(s) 808.

[00168] In at least one embodiment, a CNN for facial recognition and vehicle owner identification may use data from camera sensors to identify presence of an authorized driver and / or owner of vehicle 800. In at least one embodiment, an always on sensor processing engine may be used to unlock vehicle when owner approaches driver door and turn on lights, and, in security mode, to disable vehicle when owner leaves vehicle. In this way, SoC(s) 804 provide for security against theft and / or carjacking.

[00169] In at least one embodiment, a CNN for emergency vehicle detection and identification may use data from microphones 896 to detect and identify emergency vehicle sirens. In at least one embodiment, SoC(s) 804 use CNN for classifying environmental and urban sounds, as well as classifying visual data. In at least one embodiment, CNN running on DLA is trained to identify relative closing speed of emergency vehicle (e.g., by using Doppler effect). In at least one embodiment, CNN may also be trained to identify emergency vehicles specific to local area in which vehicle is operating, as identified by GNSS sensor(s) 858. In at least one embodiment, when operating in Europe, CNN will seek to detect European sirens, and when in United States CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program may be used to execute an emergency vehicle safety routine, slowing vehicle, pulling over to side of road, parking vehicle, and / or idling vehicle, with assistance of ultrasonic sensor(s) 862, until emergency vehicle(s) passes.

[00170] In at least one embodiment, vehicle 800 may include CPU(s) 818 (e.g., discrete CPU(s), or dCPU(s)), that may be coupled to SoC(s) 804 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, CPU(s) 818 may include an X86 processor, for example. CPU(s) 818 may be used to perform any of a variety of functions, including arbitrating potentially inconsistent results between ADAS sensors and SoC(s) 804, and / or monitoring status and health of controller(s) 836 and / or an infotainment system on a chip (“infotainment SoC”) 830, for example.

[00171] In at least one embodiment, vehicle 800 may include GPU(s) 820 (e.g., discrete GPU(s), or dGPU(s)), that may be coupled to SoC(s) 804 via a high-speed interconnect (e.g., NVIDIA’s NVLINK). In at least one embodiment, GPU(s) 820 may provide additional artificial intelligence functionality, such as by executing redundant and / or different neural networks, and may be used to train and / or update neural networks based at least in part on input (e.g., sensor data) from sensors of vehicle 800.

[00172] In at least one embodiment, vehicle 800 may further include network interface 824 which may include, without limitation, wireless antenna(s) 826 (e.g., one or more wireless antennas 826 for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, network interface 824 may be used to enable wireless connectivity over Internet with cloud (e.g., with server(s) and / or other network devices), with other vehicles, and / or with computing devices (e.g., client devices of passengers). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 80 and other vehicle and / or an indirect link may be established (e.g., across networks and over Internet). In at least one embodiment, direct links may be provided using a vehicle-to-vehicle communication link. Vehicle-to-vehicle communication link may provide vehicle 800 information about vehicles in proximity to vehicle 800 (e.g., vehicles in front of, on side of, and / or behind vehicle 800). In at least one embodiment, aforementioned functionality may be part of a cooperative adaptive cruise control functionality of vehicle 800.

[00173] In at least one embodiment, network interface 824 may include an SoC that provides modulation and demodulation functionality and enables controlled s) 836 to communicate over wireless networks. In at least one embodiment, network interface 824 may include a radio frequency front-end for up-conversion from baseband to radio frequency, and down conversion from radio frequency to baseband. In at least one embodiment, frequency conversions may be performed in any technically feasible fashion. For example, frequency conversions could be performed through well-known processes, and / or using super-heterodyne processes. In at least one embodiment, radio frequency front end functionality may be provided by a separate chip. In at least one embodiment, network interface may include wireless functionality for communicating over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, WiFi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[00174] In at least one embodiment, vehicle 800 may further include data store(s) 828 which may include, without limitation, off-chip (e.g., off SoC(s) 804) storage. In at least one embodiment, data store(s) 828 may include, without limitation, one or more storage elements including RAM, SRAM, dynamic random-access memory (“DRAM”), video random-access memory (“VRAM”), Flash, hard disks, and / or other components and / or devices that may store at least one bit of data.

[00175] In at least one embodiment, vehicle 800 may further include GNSS sensor(s) 858 (e.g., GPS and / or assisted GPS sensors), to assist in mapping, perception, occupancy grid generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensor(s) 858 may be used, including, for example and without limitation, a GPS using a USB connector with an Ethernet to Serial (e.g., RS-232) bridge.

[00176] In at least one embodiment, vehicle 800 may further include RADAR sensor(s) 860. RADAR sensor(s) 860 may be used by vehicle 800 for long-range vehicle detection, even in darkness and / or severe weather conditions. In at least one embodiment, RADAR functional safety levels may be ASIL B. RADAR sensor(s) 860 may use CAN and / or bus 802 (e.g., to transmit data generated by RADAR sensor(s) 860) for control and to access object tracking data, with access to Ethernet to access raw data in some examples. In at least one embodiment, wide variety of RADAR sensor types may be used. For example, and without limitation, RADAR sensor(s) 860 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more of RADAR sensors(s) 860 are Pulse Doppler RADAR sensor(s).

[00177] In at least one embodiment, RADAR sensor(s) 860 may include different configurations, such as long-range with narrow field of view, short-range with wide field of view, short-range side coverage, etc. In at least one embodiment, long-range RADAR may be used for adaptive cruise control functionality. In at least one embodiment, long-range RADAR systems may provide a broad field of view realized by two or more independent scans, such as within a 250m range. In at least one embodiment, RADAR sensor(s) 860 may help in distinguishing between static and moving objects, and may be used by ADAS system 838 for emergency brake assist and forward collision warning. Sensors 860(s) included in a long-range RADAR system may include, without limitation, monostatic multimodal RADAR with multiple (e.g., six or more) fixed RADAR antennae and a high-speed CAN and FlexRay interface. In at least one embodiment, with six antennae, central four antennae may create a focused beam pattern, designed to record vehicle’s 800 surroundings at higher speeds with minimal interference from traffic in adjacent lanes. In at least one embodiment, other two antennae may expand field of view, making it possible to quickly detect vehicles entering or leaving vehicle’s 800 lane.

[00178] In at least one embodiment, mid-range RADAR systems may include, as an example, a range of up to 160m (front) or 80m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, short-range RADAR systems may include, without limitation, any number of RADAR sensor(s) 860 designed to be installed at both ends of rear bumper. When installed at both ends of rear bumper, in at least one embodiment, a RADAR sensor system may create two beams that constantly monitor blind spot in rear and next to vehicle. In at least one embodiment, short-range RADAR systems may be used in ADAS system 838 for blind spot detection and / or lane change assist.

[00179] In at least one embodiment, vehicle 800 may further include ultrasonic sensor(s) 862. Ultrasonic sensor(s) 862, which may be positioned at front, back, and / or sides of vehicle 800, may be used for park assist and / or to create and update an occupancy grid. In at least one embodiment, a wide variety of ultrasonic sensor(s) 862 may be used, and different ultrasonic sensor(s) 862 may be used for different ranges of detection (e.g., 2.5m, 4m). In at least one embodiment, ultrasonic sensor(s) 862 may operate at functional safety levels of ASIL B.

[00180] In at least one embodiment, vehicle 800 may include LIDAR sensor(s) 864. LIDAR sensor(s) 864 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, LIDAR sensor(s) 864 may be functional safety level ASIL B. In at least one embodiment, vehicle 800 may include multiple LIDAR sensors 864 (e.g., two, four, six, etc.) that may use Ethernet (e.g., to provide data to a Gigabit Ethernet switch).

[00181] In at least one embodiment, LIDAR sensor(s) 864 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available LIDAR sensor(s) 864 may have an advertised range of approximately 100m, with an accuracy of 2cm-3cm, and with support for a 100 Mbps Ethernet connection, for example. In at least one embodiment, one or more non-protruding LIDAR sensors 864 may be used. In such an embodiment, LIDAR sensor(s) 864 may be implemented as a small device that may be embedded into front, rear, sides, and / or comers of vehicle 800. In at least one embodiment, LIDAR sensor(s) 864, in such an embodiment, may provide up to a 120-degree horizontal and 35-degree vertical field-of-view, with a 200m range even for low-reflectivity objects. In at least one embodiment, front-mounted LIDAR sensor(s) 864 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

[00182] In at least one embodiment, LIDAR technologies, such as 3D flash LIDAR, may also be used. 3D Flash LIDAR uses a flash of a laser as a transmission source, to illuminate surroundings of vehicle 800 up to approximately 200m. In at least one embodiment, a flash LIDAR unit includes, without limitation, a receptor, which records laser pulse transit time and reflected light on each pixel, which in turn corresponds to range from vehicle 800 to objects. In at least one embodiment, flash LIDAR may allow for highly accurate and distortion-free images of surroundings to be generated with every laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, one at each side of vehicle 800. In at least one embodiment, 3D flash LIDAR systems include, without limitation, a solid-state 3D staring array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, flash LIDAR device may use a 5 nanosecond class I (eye-safe) laser pulse per frame and may capture reflected laser light in form of 3D range point clouds and co-registered intensity data.

[00183] In at least one embodiment, vehicle may further include IMU sensor(s) 866. In at least one embodiment, IMU sensor(s) 866 may be located at a center of rear axle of vehicle 800, in at least one embodiment. In at least one embodiment, IMU sensor(s) 866 may include, for example and without limitation, accelerometer(s), magnetometer(s), gyroscope(s), magnetic compass(es), and / or other sensor types. In at least one embodiment, such as in six-axis applications, IMU sensor(s) 866 may include, without limitation, accelerometers and gyroscopes. , In at least one embodiment, such as in nine-axis applications, IMU sensor(s) 866 may include, without limitation, accelerometers, gyroscopes, and magnetometers.

[00184] In at least one embodiment, IMU sensor(s) 866 may be implemented as a miniature, high performance GPS-Aided Inertial Navigation System ("GPS / INS”) that combines micro-electro-mechanical systems (“MEMS”) inertial sensors, a high-sensitivity GPS receiver, and advanced Kalman filtering algorithms to provide estimates of position, velocity, and attitude. In at least one embodiment, IMU sensor(s) 866 may enable vehicle 800 to estimate heading without requiring input from a magnetic sensor by directly observing and correlating changes in velocity from GPS to IMU sensor(s) 866. In at least one embodiment, IMU sensor(s) 866 and GNSS sensor(s) 858 may be combined in a single integrated unit.

[00185] In at least one embodiment, vehicle 800 may include microphone(s) 896 placed in and / or around vehicle 800. In at least one embodiment, microphone(s) 896 may be used for emergency vehicle detection and identification, among other things.

[00186] In at least one embodiment, vehicle 800 may further include any number of camera types, including stereo camera(s) 868, wide-view camera(s) 870, infrared camera(s) 872, surround camera(s) 874, long-range camera(s) 898, mid-range camera(s) 876, and / or other camera types. In at least one embodiment, cameras may be used to capture image data around an entire periphery of vehicle 800. In at least one embodiment, types of cameras used depends vehicle 800. In at least one embodiment, any combination of camera types may be used to provide necessary coverage around vehicle 800. In at least one embodiment, number of cameras may differ depending on embodiment. For example, in at least one embodiment, vehicle 800 could include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. Cameras may support, as an example and without limitation, Gigabit Multimedia Serial Link (“GMSL”) and / or Gigabit Ethernet. In at least one embodiment, each of camera(s) is described with more detail previously herein with respect to FIG. 8A and FIG. 8B.

[00187] In at least one embodiment, vehicle 800 may further include vibration sensor(s) 842. Vibration sensor(s) 842 may measure vibrations of components of vehicle 800, such as axle(s). For example, in at least one embodiment, changes in vibrations may indicate a change in road surfaces. In at least one embodiment, when two or more vibration sensors 842 are used, differences between vibrations may be used to determine friction or slippage of road surface (e.g., when difference in vibration is between a power-driven axle and a freely rotating axle).

[00188] In at least one embodiment, vehicle 800 may include ADAS system 838. ADAS system 838 may include, without limitation, an SoC, in some examples. In at least one embodiment, ADAS system 838 may include, without limitation, any number and combination of an autonomous / adaptive / automatic cruise control (“ACC”) system, a cooperative adaptive cruise control (“CACC”) system, a forward crash warning (“FCW”) system, an automatic emergency braking (“AEB”) system, a lane departure warning (“LDW)” system, a lane keep assist (“LKA”) system, a blind spot warning (“BSW”) system, a rear cross-traffic warning (“RCTW”) system, a collision warning (“CW”) system, a lane centering (“LC”) system, and / or other systems, features, and / or functionality.

[00189] In at least one embodiment, ACC system may use RADAR sensor(s) 860, LIDAR sensor(s) 864, and / or any number of camera(s). In at least one embodiment, ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, longitudinal ACC system monitors and controls distance to vehicle immediately ahead of vehicle 800 and automatically adjust speed of vehicle 800 to maintain a safe distance from vehicles ahead. In at least one embodiment, lateral ACC system performs distance keeping, and advises vehicle 800 to change lanes when necessary. In at least one embodiment, lateral ACC is related to other ADAS applications such as LC and CW.

[00190] In at least one embodiment, CACC system uses information from other vehicles that may be received via network interface 824 and / or wireless antenna(s) 826 from other vehicles via a wireless link, or indirectly, over a network connection (e.g., over Internet). In at least one embodiment, direct links may be provided by a vehicle-to-vehicle (“V2V”) communication link, while indirect links may be provided by an infrastructure-to-vehicle (“12V”) communication link. In general, V2V communication concept provides information about immediately preceding vehicles (e.g., vehicles immediately ahead of and in same lane as vehicle 800), while I2V communication concept provides information about traffic further ahead. In at least one embodiment, CACC system may include either or both I2V and V2V information sources. In at least one embodiment, given information of vehicles ahead of vehicle 800, CACC system may be more reliable and it has potential to improve traffic flow smoothness and reduce congestion on road.

[00191] In at least one embodiment, FCW system is designed to alert driver to a hazard, so that driver may take corrective action. In at least one embodiment, FCW system uses a frontfacing camera and / or RADAR sensor(s) 860, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, that is electrically coupled to driver feedback, such as a display, speaker, and / or vibrating component. In at least one embodiment, FCW system may provide a warning, such as in form of a sound, visual warning, vibration and / or a quick brake pulse.

[00192] In at least one embodiment, AEB system detects an impending forward collision with another vehicle or other object, and may automatically apply brakes if driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, AEB system may use front-facing camera(s) and / or RADAR sensor(s) 860, coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when AEB system detects a hazard, AEB system typically first alerts driver to take corrective action to avoid collision and, if driver does not take corrective action, AEB system may automatically apply brakes in an effort to prevent, or at least mitigate, impact of predicted collision. In at least one embodiment, AEB system, may include techniques such as dynamic brake support and / or crash imminent braking.

[00193] In at least one embodiment, LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to alert driver when vehicle 800 crosses lane markings. In at least one embodiment, LDW system does not activate when driver indicates an intentional lane departure, by activating a turn signal. In at least one embodiment, LDW system may use front-side facing cameras, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, that is electrically coupled to driver feedback, such as a display, speaker, and / or vibrating component. In at least one embodiment, LKA system is a variation of LDW system. LKA system provides steering input or braking to correct vehicle 800 if vehicle 800 starts to exit lane.

[00194] In at least one embodiment, BSW system detects and warns driver of vehicles in an automobile’s blind spot. In at least one embodiment, BSW system may provide a visual, audible, and / or tactile alert to indicate that merging or changing lanes is unsafe. In at least one embodiment, BSW system may provide an additional warning when driver uses a turn signal. In at least one embodiment, BSW system may use rear-side facing camera(s) and / or RADAR sensor(s) 860, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, that is electrically coupled to driver feedback, such as a display, speaker, and / or vibrating component.

[00195] In at least one embodiment, RCTW system may provide visual, audible, and / or tactile notification when an object is detected outside rear-camera range when vehicle 800 is backing up. In at least one embodiment, RCTW system includes AEB system to ensure that vehicle brakes are applied to avoid a crash. In at least one embodiment, RCTW system may use one or more rear-facing RADAR sensor(s) 860, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, that is electrically coupled to driver feedback, such as a display, speaker, and / or vibrating component.

[00196] In at least one embodiment, conventional ADAS systems may be prone to false positive results which may be annoying and distracting to a driver, but typically are not catastrophic, because conventional ADAS systems alert driver and allow driver to decide whether a safety condition truly exists and act accordingly. In at least one embodiment, vehicle 800 itself decides, in case of conflicting results, whether to heed result from a primary computer or a secondary computer (e.g., first controller 836 or second controller 836). For example, in at least one embodiment, ADAS system 838 may be a backup and / or secondary computer for providing perception information to a backup computer rationality module. In at least one embodiment, backup computer rationality monitor may run a redundant diverse software on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, outputs from ADAS system 838 may be provided to a supervisory MCU. In at least one embodiment, if outputs from primary computer and secondary computer conflict, supervisory MCU determines how to reconcile conflict to ensure safe operation.

[00197] In at least one embodiment, primary computer may be configured to provide supervisory MCU with a confidence score, indicating primary computer’s confidence in chosen result. In at least one embodiment, if confidence score exceeds a threshold, supervisory MCU may follow primary computer’s direction, regardless of whether secondary computer provides a conflicting or inconsistent result. In at least one embodiment, where confidence score does not meet threshold, and where primary and secondary computer indicate different results (e.g., a conflict), supervisory MCU may arbitrate between computers to determine appropriate outcome.

[00198] In at least one embodiment, supervisory MCU may be configured to run a neural network(s) that is trained and configured to determine, based at least in part on outputs from primary computer and secondary computer, conditions under which secondary computer provides false alarms. In at least one embodiment, neural network(s) in supervisory MCU may learn when secondary computer’s output may be trusted, and when it cannot. For example, in at least one embodiment, when secondary computer is a RADAR-based FCW system, a neural network(s) in supervisory MCU may learn when FCW system is identifying metallic objects that are not, in fact, hazards, such as a drainage grate or manhole cover that triggers an alarm. In at least one embodiment, when secondary computer is a camera-based LDW system, a neural network in supervisory MCU may learn to override LDW when bicyclists or pedestrians are present and a lane departure is, in fact, safest maneuver. In at least one embodiment, supervisory MCU may include at least one of a DLA or GPU suitable for running neural network(s) with associated memory. In at least one embodiment, supervisory MCU may comprise and / or be included as a component of SoC(s) 804.

[00199] In at least one embodiment, ADAS system 838 may include a secondary computer that performs ADAS functionality using traditional rules of computer vision. In at least one embodiment, secondary computer may use classic computer vision rules (if-then), and presence of a neural network(s) in supervisory MCU may improve reliability, safety and performance. For example, in at least one embodiment, diverse implementation and intentional non-identity makes overall system more fault-tolerant, especially to faults caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if there is a software bug or error in software running on primary computer, and non-identical software code running on secondary computer provides same overall result, then supervisory MCU may have greater confidence that overall result is correct, and bug in software or hardware on primary computer is not causing material error.

[00200] In at least one embodiment, output of ADAS system 838 may be fed into primary computer’s perception block and / or primary computer’s dynamic driving task block. For example, in at least one embodiment, if ADAS system 838 indicates a forward crash warning due to an object immediately ahead, perception block may use this information when identifying objects. In at least one embodiment, secondary computer may have its own neural network which is trained and thus reduces risk of false positives, as described herein.

[00201] In at least one embodiment, vehicle 800 may further include infotainment SoC 830 (e.g., an in-vehicle infotainment system (IVI)). Although illustrated and described as an SoC, infotainment system 830, in at least one embodiment, may not be an SoC, and may include, without limitation, two or more discrete components. In at least one embodiment, infotainment SoC 830 may include, without limitation, a combination of hardware and software that may be used to provide audio (e.g., music, a personal digital assistant, navigational instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g., navigation systems, rearparking assistance, a radio data system, vehicle related information such as fuel level, total distance covered, brake fuel level, oil level, door open / close, air filter information, etc.) to vehicle 800. For example, infotainment SoC 830 could include radios, disk players, navigation systems, video players, USB and Bluetooth connectivity, carputers, in-car entertainment, WiFi, steering wheel audio controls, hands free voice control, a heads-up display (“HUD”), HMI display 834, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, infotainment SoC 830 may further be used to provide information (e.g., visual and / or audible) to user(s) of vehicle, such as information from ADAS system 838, autonomous driving information such as planned vehicle maneuvers, trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[00202] In at least one embodiment, infotainment SoC 830 may include any amount and type of GPU functionality. In at least one embodiment, infotainment SoC 830 may communicate over bus 802 (e.g., CAN bus, Ethernet, etc.) with other devices, systems, and / or components of vehicle 800. In at least one embodiment, infotainment SoC 830 may be coupled to a supervisory MCU such that GPU of infotainment system may perform some self-driving functions in event that primary controller(s) 836 (e.g., primary and / or backup computers of vehicle 800) fail. In at least one embodiment, infotainment SoC 830 may put vehicle 800 into a chauffeur to safe stop mode, as described herein.

[00203] In at least one embodiment, vehicle 800 may further include instrument cluster 832 (e.g., a digital dash, an electronic instrument cluster, a digital instrument panel, etc.). Instrument cluster 832 may include, without limitation, a controller and / or supercomputer (e.g., a discrete controller or supercomputer). In at least one embodiment, instrument cluster 832 may include, without limitation, any number and combination of a set of instrumentation such as a speedometer, fuel level, oil pressure, tachometer, odometer, turn indicators, gearshift position indicator, seat belt warning light(s), parking-brake warning light(s), engine-malfunction light(s), supplemental restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared among infotainment SoC 830 and instrument cluster 832. In at least one embodiment, instrument cluster 832 may be included as part of infotainment SoC 830, or vice versa.

[00204] FIG. 8D is a diagram of a system 876 for communication between cloud-based server(s) and autonomous vehicle 800 of FIG. 8 A, according to at least one embodiment. In at least one embodiment, system 876 may include, without limitation, server(s) 878, network(s) 890, and any number and type of vehicles, including vehicle 800. server(s) 878 may include, without limitation, a plurality of GPUs 884(A)-884(H) (collectively referred to herein as GPUs 884), PCIe switches 882(A)-882(H) (collectively referred to herein as PCIe switches 882), and / or CPUs 880(A)-880(B) (collectively referred to herein as CPUs 880). GPUs 884, CPUs 880, and PCIe switches 882 may be interconnected with high-speed interconnects such as, for example and without limitation, NVLink interfaces 888 developed by NVIDIA and / or PCIe connections 886. In at least one embodiment, GPUs 884 are connected via an NVLink and / or NVSwitch SoC and GPUs 884 and PCIe switches 882 are connected via PCIe interconnects. In at least one embodiment, although eight GPUs 884, two CPUs 880, and four PCIe switches 882 are illustrated, this is not intended to be limiting. In at least one embodiment, each of server(s) 878 may include, without limitation, any number of GPUs 884, CPUs 880, and / or PCIe switches 882, in any combination. For example, in at least one embodiment, server(s) 878 could each include eight, sixteen, thirty-two, and / or more GPUs 884.

[00205] In at least one embodiment, server(s) 878 may receive, over network(s) 890 and from vehicles, image data representative of images showing unexpected or changed road conditions, such as recently commenced road-work. In at least one embodiment, server(s) 878 may transmit, over network(s) 890 and to vehicles, neural networks 892, updated neural networks 892, and / or map information 894, including, without limitation, information regarding traffic and road conditions. In at least one embodiment, updates to map information 894 may include, without limitation, updates for HD map 822, such as information regarding construction sites, potholes, detours, flooding, and / or other obstructions. In at least one embodiment, neural networks 892, updated neural networks 892, and / or map information 894 may have resulted from new training and / or experiences represented in data received from any number of vehicles in environment, and / or based at least in part on training performed at a data center (e.g., using server(s) 878 and / or other servers).

[00206] In at least one embodiment, server(s) 878 may be used to train machine learning models (e.g., neural networks) based at least in part on training data. Training data may be generated by vehicles, and / or may be generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is tagged (e.g., where associated neural network benefits from supervised learning) and / or undergoes other pre-processing. In at least one embodiment, any amount of training data is not tagged and / or pre-processed (e.g., where associated neural network does not require supervised learning). In at least one embodiment, once machine learning models are trained, machine learning models may be used by vehicles (e.g., transmitted to vehicles over network(s) 890, and / or machine learning models may be used by server(s) 878 to remotely monitor vehicles.

[00207] In at least one embodiment, server(s) 878 may receive data from vehicles and apply data to up-to-date real-time neural networks for real-time intelligent inferencing. In at least one embodiment, server(s) 878 may include deep-learning supercomputers and / or dedicated AI computers powered by GPU(s) 884, such as a DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, server(s) 878 may include deep learning infrastructure that use CPU-powered data centers.

[00208] In at least one embodiment, deep-learning infrastructure of server(s) 878 may be capable of fast, real-time inferencing, and may use that capability to evaluate and verify health of processors, software, and / or associated hardware in vehicle 800. For example, in at least one embodiment, deep-learning infrastructure may receive periodic updates from vehicle 800, such as a sequence of images and / or objects that vehicle 800 has located in that sequence of images (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, deep-learning infrastructure may run its own neural network to identify objects and compare them with objects identified by vehicle 800 and, if results do not match and deep-learning infrastructure concludes that AI in vehicle 800 is malfunctioning, then server(s) 878 may transmit a signal to vehicle 800 instructing a fail-safe computer of vehicle 800 to assume control, notify passengers, and complete a safe parking maneuver.

[00209] In at least one embodiment, server(s) 878 may include GPU(s) 884 and one or more programmable inference accelerators (e.g., NVIDIA’s TensorRT 3). In at least one embodiment, combination of GPU-powered servers and inference acceleration may make real-time responsiveness possible. In at least one embodiment, such as where performance is less critical, servers powered by CPUs, FPGAs, and other processors may be used for inferencing. In at least one embodiment, hardware structure(s) 715 are used to perform one or more embodiments. Details regarding hardware structure(x) 715 are provided herein in conjunction with FIGS. 7A and / or 7B. COMPUTER SYSTEMS

[00210] FIG. 9 is a block diagram illustrating an exemplary computer system, which may be a system with interconnected devices and components, a system-on-a-chip (SOC) or some combination thereof 900 formed with a processor that may include execution units to execute an instruction, according to at least one embodiment. In at least one embodiment, computer system 900 may include, without limitation, a component, such as a processor 902 to employ execution units including logic to perform algorithms for process data, in accordance with present disclosure, such as in embodiment described herein. In at least one embodiment, computer system 900 may include processors, such as PENTIUM® Processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including PCs having other microprocessors, engineering workstations, set-top boxes and like) may also be used. In at least one embodiment, computer system 900 may execute a version of WINDOWS’ operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (UNIX and Linux for example), embedded software, and / or graphical user interfaces, may also be used.

[00211] Embodiments may be used in other devices such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, embedded applications may include a microcontroller, a digital signal processor (“DSP”), system on a chip, network computers (“NetPCs”), set-top boxes, network hubs, wide area network (“WAN”) switches, or any other system that may perform one or more instructions in accordance with at least one embodiment.

[00212] In at least one embodiment, computer system 900 may include, without limitation, processor 902 that may include, without limitation, one or more execution units 908 to perform machine learning model training and / or inferencing according to techniques described herein. In at least one embodiment, system 9 is a single processor desktop or server system, but in another embodiment system 9 may be a multiprocessor system. In at least one embodiment, processor 902 may include, without limitation, a complex instruction set computer (“CISC”) microprocessor, a reduced instruction set computing (“RISC”) microprocessor, a very long instruction word (“VLIW”) microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor, for example. In at least one embodiment, processor 902 may be coupled to a processor bus 910 that may transmit data signals between processor 902 and other components in computer system 900.

[00213] In at least one embodiment, processor 902 may include, without limitation, a Level 1 (“LI”) internal cache memory (“cache”) 904. In at least one embodiment, processor 902 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may reside external to processor 902. Other embodiments may also include a combination of both internal and external caches depending on particular implementation and needs. In at least one embodiment, register file 906 may store different types of data in various registers including, without limitation, integer registers, floating point registers, status registers, and instruction pointer register.

[00214] In at least one embodiment, execution unit 908, including, without limitation, logic to perform integer and floating point operations, also resides in processor 902. Processor 902 may also include a microcode (“ucode”) read only memory (“ROM”) that stores microcode for certain macro instructions. In at least one embodiment, execution unit 908 may include logic to handle a packed instruction set 909. In at least one embodiment, by including packed instruction set 909 in instruction set of a general-purpose processor 902, along with associated circuitry to execute instructions, operations used by many multimedia applications may be performed using packed data in a general-purpose processor 902. In one or more embodiments, many multimedia applications may be accelerated and executed more efficiently by using full width of a processor's data bus for performing operations on packed data, which may eliminate need to transfer smaller units of data across processor's data bus to perform one or more operations one data element at a time.

[00215] In at least one embodiment, execution unit 908 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 900 may include, without limitation, a memory 920. In at least one embodiment, memory 920 may be implemented as a Dynamic Random Access Memory (“DRAM”) device, a Static Random Access Memory (“SRAM”) device, flash memory device, or other memory device. Memory 920 may store instruction(s) 919 and / or data 921 represented by data signals that may be executed by processor 902.

[00216] In at least one embodiment, system logic chip may be coupled to processor bus 910 and memory 920. In at least one embodiment, system logic chip may include, without limitation, a memory controller hub (“MCH”) 916, and processor 902 may communicate with MCH 916 via processor bus 910. In at least one embodiment, MCH 916 may provide a high bandwidth memory path 918 to memory 920 for instruction and data storage and for storage of graphics commands, data and textures. In at least one embodiment, MCH 916 may direct data signals between processor 902, memory 920, and other components in computer system 900 and to bridge data signals between processor bus 910, memory 920, and a system I / O 922. In at least one embodiment, system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 916 may be coupled to memory 920 through a high bandwidth memory path 918 and graphics / video card 912 may be coupled to MCH 916 through an Accelerated Graphics Port (“AGP”) interconnect 914.

[00217] In at least one embodiment, computer system 900 may use system I / O 922 that is a proprietary hub interface bus to couple MCH 916 to I / O controller hub (“ICH”) 930. In at least one embodiment, ICH 930 may provide direct connections to some I / O devices via a local I / O bus. In at least one embodiment, local I / O bus may include, without limitation, a high-speed I / O bus for connecting peripherals to memory 920, chipset, and processor 902. Examples may include, without limitation, an audio controller 929, a firmware hub (“flash BIOS”) 928, a wireless transceiver 926, a data storage 924, a legacy I / O controller 923 containing user input and keyboard interfaces, a serial expansion port 927, such as Universal Serial Bus (“USB”), and a network controller 934. Data storage 924 may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[00218] In at least one embodiment, FIG. 9 illustrates a system, which includes interconnected hardware devices or “chips”, whereas in other embodiments, FIG. 9 may illustrate an exemplary System on a Chip (“SoC”). In at least one embodiment, devices illustrated in FIG. cc may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe) or some combination thereof. In at least one embodiment, one or more components of system 900 are interconnected using compute express link (CXL) interconnects.

[00219] In at least one embodiment, FIG. 5 illustrates a system, which includes interconnected hardware devices or “chips”, whereas in other embodiments, FIG. 5 may illustrate an exemplary System on a Chip (“SoC”).

[00220] FIG. 10 is a block diagram illustrating an electronic device 1000 for utilizing a processor 1010, according to at least one embodiment. In at least one embodiment, electronic device 1000 may be, for example and without limitation, a notebook, a tower server, a rack server, a blade server, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[00221] In at least one embodiment, system 1000 may include, without limitation, processor 1010 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor 1010 coupled using a bus or interface, such as a 1 °C bus, a System Management Bus (“SMBus”), a Low Pin Count (LPC) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, a Universal Serial Bus (“USB”) (versions 1, 2, 3), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, FIG. 10 illustrates a system, which includes interconnected hardware devices or “chips”, whereas in other embodiments, FIG. 10 may illustrate an exemplary System on a Chip (“SoC”). In at least one embodiment, devices illustrated in FIG. 10 may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe) or some combination thereof. In at least one embodiment, one or more components of FIG. 10 are interconnected using compute express link (CXL) interconnects.

[00222] In at least one embodiment, FIG 10 may include a display 1024, a touch screen 1025, a touch pad 1030, a Near Field Communications unit (“NFC”) 1045, a sensor hub 1040, a thermal sensor 1046, an Express Chipset (“EC”) 1035, a Trusted Platform Module (“TPM”) 1038, BlOS / firmware / flash memory (“BIOS, FW Flash”) 1022, a DSP 1060, a drive “SSD or HDD”) 1020 such as a Solid State Disk (“SSD”) or a Hard Disk Drive (“HDD”), a wireless local area network unit (“WLAN”) 1050, a Bluetooth unit 1052, a Wireless Wide Area Network unit (“WWAN”) 1056, a Global Positioning System (GPS) 1055, a camera (“USB 3.0 camera”) 1054 such as a USB 3.0 camera, or a Low Power Double Data Rate (“LPDDR”) memory unit (“LPDDR3”) 1015 implemented in, for example, LPDDR3 standard. These components may each be implemented in any suitable manner.

[00223] In at least one embodiment, other components may be communicatively coupled to processor 1010 through components discussed above. In at least one embodiment, an accelerometer 1041, Ambient Light Sensor (“ALS”) 1042, compass 1043, and a gyroscope 1044 may be communicatively coupled to sensor hub 1040. In at least one embodiment, thermal sensor 1039, a fan 1037, a keyboard 1046, and a touch pad 1030 may be communicatively coupled to EC 1035. In at least one embodiment, speaker 1063, a headphones 1064, and a microphone (“mic”) 1065 may be communicatively coupled to an audio unit (“audio codec and class d amp”) 1064, which may in turn be communicatively coupled to DSP 1060. In at least one embodiment, audio unit 1064 may include, for example and without limitation, an audio coder / decoder (“codec”) and a class D amplifier. In at least one embodiment, SIM card (“SIM”) 1057 may be communicatively coupled to WWAN unit 1056. In at least one embodiment, components such as WLAN unit 1050 and Bluetooth unit 1052, as well as WWAN unit 1056 may be implemented in a Next Generation Form Factor (“NGFF”).

[00224] FIG. 11 illustrates a computer system 1100, according to at least one embodiment. In at least one embodiment, computer system 1100 is configured to implement various processes and methods described throughout this disclosure.

[00225] In at least one embodiment, computer system 1100 comprises, without limitation, at least one central processing unit (“CPU”) 1102 that is connected to a communication bus 1110 implemented using any suitable protocol, such as PCI (“Peripheral Component Interconnect”), peripheral component interconnect express (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol(s). In at least one embodiment, computer system 1100 includes, without limitation, a main memory 1104 and control logic (e.g., implemented as hardware, software, or a combination thereof) and data are stored in main memory 1104 which may take form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“network interface”) 1122 provides an interface to other computing devices and networks for receiving data from and transmitting data to other systems from computer system 1100.

[00226] In at least one embodiment, computer system 1100, in at least one embodiment, includes, without limitation, input devices 1108, parallel processing system 1112, and display devices 1106 which can be implemented using a conventional cathode ray tube (“CRT”), liquid crystal display (“LCD”), light emitting diode (“LED”), plasma display, or other suitable display technologies. In at least one embodiment, user input is received from input devices 1108 such as keyboard, mouse, touchpad, microphone, and more. In at least one embodiment, each of foregoing modules can be situated on a single semiconductor platform to form a processing system.

[00227] FIG. 12 illustrates a computer system 1200, according to at least one embodiment. In at least one embodiment, computer system 1200 includes, without limitation, a computer 1210 and a USB stick 1220. In at least one embodiment, computer 1210 may include, without limitation, any number and type of processor(s) (not shown) and a memory (not shown). In at least one embodiment, computer 1210 includes, without limitation, a server, a cloud instance, a laptop, and a desktop computer.

[00228] In at least one embodiment, USB stick 1220 includes, without limitation, a processing unit 1230, a USB interface 1240, and USB interface logic 1250. In at least one embodiment, processing unit 1230 may be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, processing unit 1230 may include, without limitation, any number and type of processing cores (not shown). In at least one embodiment, processing core 1230 comprises an application specific integrated circuit (“ASIC”) that is optimized to perform any amount and type of operations associated with machine learning. For instance, in at least one embodiment, processing core 1230 is a tensor processing unit (“TPC”) that is optimized to perform machine learning inference operations. In at least one embodiment, processing core 1230 is a vision processing unit (“VPU”) that is optimized to perform machine vision and machine learning inference operations.

[00229] In at least one embodiment, USB interface 1240 may be any type of USB connector or USB socket. For instance, in at least one embodiment, USB interface 1240 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, USB interface 1240 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1250 may include any amount and type of logic that enables processing unit 1230 to interface with or devices (e.g., computer 1210) via USB connector 1240.

[00230] FIG. 13A illustrates an exemplary architecture in which a plurality of GPUs 1310-1313 is communicatively coupled to a plurality of multi-core processors 1305-1306 over highspeed links 1340-1343 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, highspeed links 1340-1343 support a communication throughput of 4GB / s, 30GB / s, 80GB / s or higher. Various interconnect protocols may be used including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0.

[00231] In addition, and in one embodiment, two or more of GPUs 1310-1313 are interconnected over high-speed links 1329-1330, which may be implemented using same or different protocols / links than those used for high-speed links 1340-1343. Similarly, two or more of multi-core processors 1305-1306 may be connected over high speed link 1328 which may be symmetric multi-processor (SMP) buses operating at 20GB / s, 30GB / s, 120GB / s or higher. Alternatively, all communication between various system components shown in FIG. 13 A may be accomplished using same protocols / links (e.g., over a common interconnection fabric).

[00232] In one embodiment, each multi-core processor 1305-1306 is communicatively coupled to a processor memory 1301-1302, via memory interconnects 1326-1327, respectively, and each GPU 1310-1313 is communicatively coupled to GPU memory 1320-1323 over GPU memory interconnects 1350-1353, respectively. Memory interconnects 1326-1327 and 13SO-13 53 may utilize same or different memory access technologies. By way of example, and not limitation, processor memories 1301-1302 and GPU memories 1320-1323 may be volatile memories such as dynamic random access memories (DRAMs) (including stacked DRAMs), Graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or High Bandwidth Memory (HBM) and / or may be non-volatile memories such as 3D XPoint or Nano-Ram. In one embodiment, some portion of processor memories 1301-1302 may be volatile memory and another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[00233] As described herein, although various processors 1305-1306 and GPUs 1310-1313 may be physically coupled to a particular memory 1301-1302, 1320-1323, respectively, a unified memory architecture may be implemented in which a same virtual system address space (also referred to as “effective address” space) is distributed among various physical memories. For example, processor memories 1301-1302 may each comprise 64GB of system memory address space and GPU memories 1320-1323 may each comprise 32GB of system memory address space (resulting in a total of 256GB addressable memory in this example).

[00234] FIG. 13B illustrates additional details for an interconnection between a multi-core processor 1307 and a graphics acceleration module 1346 in accordance with one exemplary embodiment. Graphics acceleration module 1346 may include one or more GPU chips integrated on a line card which is coupled to processor 1307 via high-speed link 1340. Alternatively, graphics acceleration module 1346 may be integrated on a same package or chip as processor 1307.

[00235] In at least one embodiment, illustrated processor 1307 includes a plurality of cores 1360A-1360D, each with a translation lookaside buffer 1361A-1361D and one or more caches 1362A-1362D. In at least one embodiment, cores 1360A-1360D may include various other components for executing instructions and processing data which are not illustrated. Caches 1362A-1362D may comprise level 1 (LI) and level 2 (L2) caches. In addition, one or more shared caches 1356 may be included in caches 1362A-1362D and shared by sets of cores 1360A-1360D. For example, one embodiment of processor 1307 includes 24 cores, each with its own LI cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, one or more L2 and L3 caches are shared by two adjacent cores. Processor 1307 and graphics acceleration module 1346 connect with system memory 1314, which may include processor memories 1301-1302 of FIG. 13A.

[00236] Coherency is maintained for data and instructions stored in various caches 1362A-1362D, 1356 and system memory 1314 via inter-core communication over a coherence bus 1364. For example, each cache may have cache coherency logic / circuitry associated therewith to communicate to over coherence bus 1364 in response to detected reads or writes to particular cache lines. In one implementation, a cache snooping protocol is implemented over coherence bus 1364 to snoop cache accesses.

[00237] In one embodiment, a proxy circuit 1325 communicatively couples graphics acceleration module 1346 to coherence bus 1364, allowing graphics acceleration module 1346 to participate in a cache coherence protocol as a peer of cores 1360A-1360D. In particular, an interface 1335 provides connectivity to proxy circuit 1325 over high-speed link 1340 (e.g., a PCIe bus, NVLink, etc.) and an interface 1337 connects graphics acceleration module 1346 to link 1340.

[00238] In one implementation, an accelerator integration circuit 1336 provides cache management, memory access, context management, and interrupt management services on behalf of a plurality of graphics processing engines 1331, 1332, N of graphics acceleration module 1346. Graphics processing engines 1331, 1332, N may each comprise a separate graphics processing unit (GPU). Alternatively, graphics processing engines 1331, 1332, N may comprise different types of graphics processing engines within a GPU such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, graphics acceleration module 1346 may be a GPU with a plurality of graphics processing engines 1331-1332, N or graphics processing engines 1331-1332, N may be individual GPUs integrated on a common package, line card, or chip.

[00239] In one embodiment, accelerator integration circuit 1336 includes a memory management unit (MMU) 1339 for performing various memory management functions such as virtual-to-physical memory translations (also referred to as effective-to-real memory translations) and memory access protocols for accessing system memory 1314. MMU 1339 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective to physical / real address translations. In one implementation, a cache 1338 stores commands and data for efficient access by graphics processing engines 1331-1332, N. In one embodiment, data stored in cache 1338 and graphics memories 1333-1334, M is kept coherent with core caches 1362A-1362D, 1356 and system memory 1314. As mentioned, this may be accomplished via proxy circuit 1325 on behalf of cache 1338 and memories 1333-1334, M (e.g., sending updates to cache 1338 related to modifications / accesses of cache lines on processor caches 1362A-1362D, 1356 and receiving updates from cache 1338).

[00240] A set of registers 1345 store context data for threads executed by graphics processing engines 1331-1332, N and a context management circuit 1348 manages thread contexts. For example, context management circuit 1348 may perform save and restore operations to save and restore contexts of various threads during contexts switches (e.g., where a first thread is saved and a second thread is stored so that a second thread can be execute by a graphics processing engine). For example, on a context switch, context management circuit 1348 may store current register values to a designated region in memory (e.g., identified by a context pointer). It may then restore register values when returning to a context. In one embodiment, an interrupt management circuit 1347 receives and processes interrupts received from system devices.

[00241] In one implementation, virtual / effective addresses from a graphics processing engine 1331 are translated to real / physical addresses in system memory 1314 by MMU 1339. One embodiment of accelerator integration circuit 1336 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1346 and / or other accelerator devices. Graphics accelerator module 1346 may be dedicated to a single application executed on processor 1307 or may be shared between multiple applications. In one embodiment, a virtualized graphics execution environment is presented in which resources of graphics processing engines 1331-1332, N are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources may be subdivided into “slices” which are allocated to different VMs and / or applications based on processing requirements and priorities associated with VMs and / or applications.

[00242] In at least one embodiment, accelerator integration circuit 1336 performs as a bridge to a system for graphics acceleration module 1346 and provides address translation and system memory cache services. In addition, accelerator integration circuit 1336 may provide virtualization facilities for a host processor to manage virtualization of graphics processing engines 1331-1332, interrupts, and memory management.

[00243] Because hardware resources of graphics processing engines 1331-1332, N are mapped explicitly to a real address space seen by host processor 1307, any host processor can address these resources directly using an effective address value. One function of accelerator integration circuit 1336, in one embodiment, is physical separation of graphics processing engines 1331-1332, N so that they appear to a system as independent units.

[00244] In at least one embodiment, one or more graphics memories 1333-1334, M are coupled to each of graphics processing engines 1331-1332, N, respectively. Graphics memories 1333-1334, M store instructions and data being processed by each of graphics processing engines 1331-1332, N. Graphics memories 1333-1334, M may be volatile memories such as DRAMs (including stacked DRAMs), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memories such as 3D XPoint or Nano-Ram.

[00245] In one embodiment, to reduce data traffic over link 1340, biasing techniques are used to ensure that data stored in graphics memories 1333-1334, M is data which will be used most frequently by graphics processing engines 1331-1332, N and preferably not used by cores 1360A-1360D (at least not frequently). Similarly, a biasing mechanism attempts to keep data needed by cores (and preferably not graphics processing engines 1331-1332, N) within caches 1362A-1362D, 1356 of cores and system memory 1314.

[00246] FIG. 13C illustrates another exemplary embodiment in which accelerator integration circuit 1336 is integrated within processor 1307. In this embodiment, graphics processing engines 1331-1332, N communicate directly over high-speed link 1340 to accelerator integration circuit 1336 via interface 1337 and interface 1335 (which, again, may be utilize any form of bus or interface protocol). Accelerator integration circuit 1336 may perform same operations as those described with respect to FIG. 13B, but potentially at a higher throughput given its close proximity to coherence bus 1364 and caches 1362A-1362D, 1356. One embodiment supports different programming models including a dedicated-process programming model (no graphics acceleration module virtualization) and shared programming models (with virtualization), which may include programming models which are controlled by accelerator integration circuit 1336 and programming models which are controlled by graphics acceleration module 1346.

[00247] In at least one embodiment, graphics processing engines 1331-1332, N are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to graphics processing engines 1331-1332, N, providing virtualization within a VM / partition.

[00248] In at least one embodiment, graphics processing engines 1331-1332, N, may be shared by multiple VM / application partitions. In at least one embodiment, shared models may use a system hypervisor to virtualize graphics processing engines 1331-1332, N to allow access by each operating system. For single-partition systems without a hypervisor, graphics processing engines 1331-1332, N are owned by an operating system. In at least one embodiment, an operating system can virtualize graphics processing engines 1331-1332, N to provide access to each process or application.

[00249] In at least one embodiment, graphics acceleration module 1346 or an individual graphics processing engine 1331-1332, N selects a process element using a process handle. In one embodiment, process elements are stored in system memory 1314 and are addressable using an effective address to real address translation techniques described herein. In at least one embodiment, a process handle may be an implementation-specific value provided to a host process when registering its context with graphics processing engine 1331-1332, N (that is, calling system software to add a process element to a process element linked list). In at least one embodiment, a lower 16-bits of a process handle may be an offset of the process element within a process element linked list.

[00250] FIG. 13D illustrates an exemplary accelerator integration slice 1390. As used herein, a “slice” comprises a specified portion of processing resources of accelerator integration circuit 1336. Application effective address space 1382 within system memory 1314 stores process elements 1383. In one embodiment, process elements 1383 are stored in response to GPU invocations 1381 from applications 1380 executed on processor 1307. A process element 1383 contains process state for corresponding application 1380. A work descriptor (WD) 1384 contained in process element 1383 can be a single job requested by an application or may contain a pointer to a queue of jobs. In at least one embodiment, WD 1384 is a pointer to a job request queue in an application’s address space 1382.

[00251] Graphics acceleration module 1346 and / or individual graphics processing engines 1331-1332, N can be shared by all or a subset of processes in a system. In at least one embodiment, an infrastructure for setting up process state and sending a WD 1384 to a graphics acceleration module 1346 to start a job in a virtualized environment may be included.

[00252] In at least one embodiment, a dedicated-process programming model is implementation-specific. In this model, a single process owns graphics acceleration module 1346 or an individual graphics processing engine 1331. Because graphics acceleration module 1346 is owned by a single process, a hypervisor initializes accelerator integration circuit 1336 for an owning partition and an operating system initializes accelerator integration circuit 1336 for an owning process when graphics acceleration module 1346 is assigned.

[00253] In operation, a WD fetch unit 1391 in accelerator integration slice 1390 fetches next WD 1384 which includes an indication of work to be done by one or more graphics processing engines of graphics acceleration module 1346. Data from WD 1384 may be stored in registers 1345 and used by MMU 1339, interrupt management circuit 1347 and / or context management circuit 1348 as illustrated. For example, one embodiment of MMU 1339 includes segment / page walk circuitry for accessing segment / page tables 1386 within OS virtual address space 1385. Interrupt management circuit 1347 may process interrupt events 1392 received from graphics acceleration module 1346. When performing graphics operations, an effective address 1393 5 generated by a graphics processing engine 1331-1332, N is translated to a real address by MMU 1339.

[00254] In one embodiment, a same set of registers 1345 are duplicated for each graphics processing engine 1331-1332, N and / or graphics acceleration module 1346 and may be initialized by a hypervisor or operating system. Each of these duplicated registers may be 10 included in an accelerator integration slice 1390. Exemplary registers that may be initialized by a hypervisor are shown in Table 1. Table 1 -Hypervisor Initialized Registers 1 Slice Control Register 2 Real Address (RA) Scheduled Processes Area Pointer 3 Authority Mask Override Register 4 Interrupt Vector Table Entry Offset 5 Interrupt Vector Table Entry Limit 6 State Register 7 Logical Partition ID 8 Real address (RA) Hypervisor Accelerator Utilization Record Pointer 9 Storage Description Register

[00255] Exemplary registers that may be initialized by an operating system are shown in 15 Table 2. Table 2 -Operating System Initialized Registers 1 Process and Thread Identification 2 Effective Address (EA) Context Save / Restore Pointer 3 Virtual Address (VA) Accelerator Utilization Record Pointer 4 Virtual Address (VA) Storage Segment Table Pointer 5 Authority Mask 6 Work descriptor

[00256] In one embodiment, each WD 1384 is specific to a particular graphics acceleration module 1346 and / or graphics processing engines 1331-1332, N. It contains all information required by a graphics processing engine 1331-1332, N to do work or it can be a pointer to a memory location where an application has set up a command queue of work to be completed.

[00257] FIG. 13E illustrates additional details for one exemplary embodiment of a shared model. This embodiment includes a hypervisor real address space 1398 in which a process element list 1399 is stored. Hypervisor real address space 1398 is accessible via a hypervisor 1396 which virtualizes graphics acceleration module engines for operating system 1395.

[00258] In at least one embodiment, shared programming models allow for all or a subset of processes from all or a subset of partitions in a system to use a graphics acceleration module 1346. There are two programming models where graphics acceleration module 1346 is shared by multiple processes and partitions: time-sliced shared and graphics directed shared.

[00259] In this model, system hypervisor 1396 owns graphics acceleration module 1346 and makes its function available to all operating systems 1395. For a graphics acceleration module 1346 to support virtualization by system hypervisor 1396, graphics acceleration module 1346 may adhere to the following: 1) An application’s job request must be autonomous (that is, state does not need to be maintained between jobs), or graphics acceleration module 1346 must provide a context save and restore mechanism. 2) An application’s job request is guaranteed by graphics acceleration module 1346 to complete in a specified amount of time, including any translation faults, or graphics acceleration module 1346 provides an ability to preempt processing of a job. 3) Graphics acceleration module 1346 must be guaranteed fairness between processes when operating in a directed shared programming model.

[00260] In at least one embodiment, application 1380 is required to make an operating system 1395 system call with a graphics acceleration module 1346 type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore area pointer (CSRP). In at least one embodiment, graphics acceleration module 1346 type describes a targeted acceleration function for a system call. In at least one embodiment, graphics acceleration module 1346 type may be a system-specific value. In at least one embodiment, WD is formatted specifically for graphics acceleration module 1346 and can be in a form of a graphics acceleration module 1346 command, an effective address pointer to a user-defined structure, an effective address pointer to a queue of commands, or any other data structure to describe work to be done by graphics acceleration module 1346. In one embodiment, an AMR value is an AMR state to use for a current process. In at least one embodiment, a value passed to an operating system is similar to an application setting an AMR. If accelerator integration circuit 1336 and graphics acceleration module 1346 implementations do not support a User Authority Mask Override Register (UAMOR), an operating system may apply a current UAMOR value to an AMR value before passing an AMR in a hypervisor call. Hypervisor 1396 may optionally apply a current Authority Mask Override Register (AMOR) value before placing an AMR into process element 1383. In at least one embodiment, CSRP is one of registers 1345 containing an effective address of an area in an application’s address space 1382 for graphics acceleration module 1346 to save and restore context state. This pointer is optional if no state is required to be saved between jobs or when a job is preempted. In at least one embodiment, context save / restore area may be pinned system memory.

[00261] Upon receiving a system call, operating system 1395 may verify that application 1380 has registered and been given authority to use graphics acceleration module 1346. Operating system 1395 then calls hypervisor 1396 with information shown in Table 3. Table 3 -OS to Hypervisor Call Parameters 1 A work descriptor (WD) 2 An Authority Mask Register (AMR) value (potentially masked) 3 An effective address (EA) Context Save / Restore Area Pointer (CSRP) 4 A process ID (PID) and optional thread ID (TID) 5 A virtual address (VA) accelerator utilization record pointer (AURP) 6 Virtual address of storage segment table pointer (SSTP) 7 A logical interrupt service number (LISN)

[00262] Upon receiving a hypervisor call, hypervisor 1396 verifies that operating system 1395 has registered and been given authority to use graphics acceleration module 1346. Hypervisor 1396 then puts process element 1383 into a process element linked list for a corresponding graphics acceleration module 1346 type. A process element may include information shown in 10 Table 4. Table 4 -Process Element Information 1 A work descriptor (WD) 2 An Authority Mask Register (AMR) value (potentially masked). 3 An effective address (EA) Context Save / Restore Area Pointer (CSRP) 4 A process ID (PID) and optional thread ID (TID) 5 A virtual address (VA) accelerator utilization record pointer (AURP) 6 Virtual address of storage segment table pointer (SSTP) 7 A logical interrupt service number (LISN) 8 Interrupt vector table, derived from hypervisor call parameters 9 A state register (SR) value 10 A logical partition ID (LPID) 11 A real address (RA) hypervisor accelerator utilization record pointer 12 Storage Descriptor Register (SDR)

[00263] In at least one embodiment, hypervisor initializes a plurality of accelerator integration slice 1390 registers 1345.

[00264] As illustrated in FIG. 13F, in at least one embodiment, a unified memory is used, addressable via a common virtual memory address space used to access physical processor memories 1301-1302 and GPU memories 1320-1323. In this implementation, operations executed on GPUs 1310-1313 utilize a same virtual / effective memory address space to access processor memories 1301-1302 and vice versa, thereby simplifying programmability. In one embodiment, a first portion of a virtual / effective address space is allocated to processor memory 1301, a second portion to second processor memory 1302, a third portion to GPU memory 1320, and so on. In at least one embodiment, an entire virtual / effective memory space (sometimes referred to as an effective address space) is thereby distributed across each of processor memories 1301-1302 and GPU memories 1320-1323, allowing any processor or GPU to access any physical memory with a virtual address mapped to that memory.

[00265] In one embodiment, bias / coherence management circuitry 1394A-1394E within one or more of MMUs 1339A-1339E ensures cache coherence between caches of one or more host processors (e.g., 1305) and GPUs 1310-1313 and implements biasing techniques indicating physical memories in which certain types of data should be stored. While multiple instances of bias / coherence management circuitry 1394A-1394E are illustrated in FIG. 13F, bias / coherence circuitry may be implemented within an MMU of one or more host processors 1305 and / or within accelerator integration circuit 1336.

[00266] One embodiment allows GPU-attached memory 1320-1323 to be mapped as part of system memory, and accessed using shared virtual memory (SVM) technology, but without suffering performance drawbacks associated with full system cache coherence. In at least one embodiment, an ability for GPU-attached memory 1320-1323 to be accessed as system memory without onerous cache coherence overhead provides a beneficial operating environment for GPU offload. This arrangement allows host processor 1305 software to setup operands and access computation results, without overhead of tradition I / O DMA data copies. Such traditional copies involve driver calls, interrupts and memory mapped I / O (MMIO) accesses that are all inefficient relative to simple memory accesses. In at least one embodiment, an ability to access GPU attached memory 1320-1323 without cache coherence overheads can be critical to execution time of an offloaded computation. In cases with substantial streaming write memory traffic, for example, cache coherence overhead can significantly reduce an effective write bandwidth seen by a GPU 1310-1313. In at least one embodiment, efficiency of operand setup, efficiency of results access, and efficiency of GPU computation may play a role in determining effectiveness of a GPU offload.

[00267] In at least one embodiment, selection of GPU bias and host processor bias is driven by a bias tracker data structure. A bias table may be used, for example, which may be a page-granular structure (i.e„ controlled at a granularity of a memory page) that includes 1 or 2 bits per GPU-attached memory page. In at least one embodiment, a bias table may be implemented in a stolen memory range of one or more GPU-attached memories 1320-1323, with or without a bias cache in GPU 1310-1313 (e.g„ to cache frequently / recently used entries of a bias table). Alternatively, an entire bias table may be maintained within a GPU.

[00268] In at least one embodiment, a bias table entry associated with each access to GPU-attached memory 1320-1323 is accessed prior to actual access to a GPU memory, causing the following operations. First, local requests from GPU 1310-1313 that find their page in GPU bias are forwarded directly to a corresponding GPU memory 1320-1323. Local requests from a GPU that find their page in host bias are forwarded to processor 1305 (e.g„ over a high-speed link as discussed above). In one embodiment, requests from processor 1305 that find a requested page in host processor bias complete a request like a normal memory read. Alternatively, requests directed to a GPU-biased page may be forwarded to GPU 1310-1313. In at least one embodiment, a GPU may then transition a page to a host processor bias if it is not currently using a page. In at least one embodiment, bias state of a page can be changed either by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of cases, a purely hardware-based mechanism.

[00269] One mechanism for changing bias state employs an API call (e.g. OpenCL), which, in turn, calls a GPU’s device driver which, in turn, sends a message (or enqueues a command descriptor) to a GPU directing it to change a bias state and, for some transitions, perform a cache flushing operation in a host. In at least one embodiment, cache flushing operation is used for a transition from host processor 1305 bias to GPU bias, but is not for an opposite transition.

[00270] In one embodiment, cache coherency is maintained by temporarily rendering GPU-biased pages uncacheable by host processor 1305. To access these pages, processor 1305 may request access from GPU 1310 which may or may not grant access right away. Thus, to reduce communication between processor 1305 and GPU 1310 it is beneficial to ensure that GPU-biased pages are those which are required by a GPU but not host processor 1305 and vice versa.

[00271] Hardware structure(s) 715 are used to perform one or more embodiments. Details regarding the hardware structure(x) 715 are provided herein in conjunction with FIGS. 7A and / or 7B.

[00272] FIG. 14 illustrates exemplary integrated circuits and associated graphics processors that may be fabricated using one or more IP cores, according to various embodiments described herein. In addition to what is illustrated, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[00273] FIG. 14 is a block diagram illustrating an exemplary system on a chip integrated circuit 1400 that may be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, integrated circuit 1400 includes one or more application processor(s) 1405 (e.g., CPUs), at least one graphics processor 1410, and may additionally include an image processor 1415 and / or a video processor 1420, any of which may be a modular IP core. In at least one embodiment, integrated circuit 1400 includes peripheral or bus logic including a USB controller 1425, UART controller 1430, an SPI / SDIO controller 1435, and an I.sup.2S / I.sup.2C controller 1440. In at least one embodiment, integrated circuit 1400 can include a display device 1445 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1450 and a mobile industry processor interface (MIPI) display interface 1455. In at least one embodiment, storage may be provided by a flash memory subsystem 1460 including flash memory and a flash memory controller. In at least one embodiment, memory interface may be provided via a memory controller 1465 for access to SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits additionally include an embedded security engine 1470.

[00274] FIGS. 15A-15B illustrate exemplary integrated circuits and associated graphics processors that may be fabricated using one or more IP cores, according to various embodiments described herein. In addition to what is illustrated, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[00275] FIGS. 15A-15B are block diagrams illustrating exemplary graphics processors for use within an SoC, according to embodiments described herein. FIG. 15A illustrates an exemplary graphics processor 1510 of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to at least one embodiment. FIG. 15B illustrates an additional exemplary graphics processor 1540 of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, graphics processor 1510 of FIG. 15A is a low power graphics processor core. In at least one embodiment, graphics processor 1540 of FIG. 15B is a higher performance graphics processor core. In at least one embodiment, each of graphics processors 1510, 1540 can be variants of graphics processor 1410 of FIG. 14.

[00276] In at least one embodiment, graphics processor 1510 includes a vertex processor 1505 and one or more fragment processor(s) 1515A-1515N (e.g., 1515A, 1515B, 1515C, 1515D, through 1515N-1, and 1515N). In at least one embodiment, graphics processor 1510 can execute different shader programs via separate logic, such that vertex processor 1505 is optimized to execute operations for vertex shader programs, while one or more fragment processor(s) 15ISA- 1515N execute fragment (e.g„ pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, vertex processor 1505 performs a vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, fragment processor(s) 1515A-1515N use primitive and vertex data generated by vertex processor 1505 to produce a framebuffer that is displayed on a display device. In at least one embodiment, fragment processor(s) 1515A-1515N are optimized to execute fragment shader programs as provided for in an OpenGL API, which may be used to perform similar operations as a pixel shader program as provided for in a Direct 3D API.

[00277] In at least one embodiment, graphics processor 1510 additionally includes one or more memory management units (MMUs) 1520A-1520B, cache(s) 1525A-1525B, and circuit interconnect(s) 1530A-1530B. In at least one embodiment, one or more MMU(s) 1520A-1520B provide for virtual to physical address mapping for graphics processor 1510, including for vertex processor 1505 and / or fragment processor(s) 1515A-1515N, which may reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more cache(s) 1525A-1525B. In at least one embodiment, one or more MMU(s) 1520A-1520B may be synchronized with other MMUs within system, including one or more MMUs associated with one or more application processor(s) 1405, image processors 1415, and / or video processors 1420 of FIG. 14, such that each processor 1405-1420 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnect(s) 1530A-1530B enable graphics processor 1510 to interface with other IP cores within SoC, either via an internal bus of SoC or via a direct connection.

[00278] In at least one embodiment, graphics processor 1540 includes one or more MMU(s) 1520A-1520B, caches 1525A-1525B, and circuit interconnects 1530A-1530B of graphics processor 1510 of FIG. 15 A. In at least one embodiment, graphics processor 1540 includes one or more shader core(s) 1555A-1555N (e.g., 1555A, 1555B, 1555C, 1555D, 1555E, 1555F, through 1555N-1, and 1555N), which provides for a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, a number of shader cores can vary. In at least one embodiment, graphics processor 1540 includes an inter-core task manager 1545, which acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1555A-1555N and a tiling unit 1558 to accelerate tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in image space, for example to exploit local spatial coherence within a scene or to optimize use of internal caches.

[00279] FIGS. 16A-16B illustrate additional exemplary graphics processor logic according to embodiments described herein. FIG. 16A illustrates a graphics core 1600 that may be included within graphics processor 1410 of FIG. 14, in at least one embodiment, and may be a unified shader core 1555A-1555N as in FIG. 15B in at least one embodiment. FIG. 16B illustrates a highly-parallel general-purpose graphics processing unit 1630 suitable for deployment on a multi-chip module in at least one embodiment.

[00280] In at least one embodiment, graphics core 1600 includes a shared instruction cache 1602, a texture unit 1618, and a cache / shared memory 1620 that are common to execution resources within graphics core 1600. In at least one embodiment, graphics core 1600 can include multiple slices 1601 A-160 IN or partition for each core, and a graphics processor can include multiple instances of graphics core 1600. Slices 1601A-1601N can include support logic including a local instruction cache 1604A-1604N, a thread scheduler 1606A-1606N, a thread dispatcher 1608A-1608N, and a set of registers 1610A-1610N. In at least one embodiment, slices 1601A-1601N can include a set of additional function units (AFUs 1612A-1612N), floatingpoint units (FPU 1614A-1614N), integer arithmetic logic units (ALUs 1616-1616N), address computational units (ACU 1613A-1613N), double-precision floating-point units (DPFPU 1615A-1615N), and matrix processing units (MPU 1617A-1617N).

[00281] In at least one embodiment, FPUs 1614A-1614N can perform single-precision (32-bit) and half-precision (16-bit) floating point operations, while DPFPUs 1615A-1615N perform double precision (64-bit) floating point operations. In at least one embodiment, ALUs 1616A-1616N can perform variable precision integer operations at 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed precision operations. In at least one embodiment, MPUs 1617A-1617N can also be configured for mixed precision matrix operations, including half-precision floating point and 8-bit integer operations. In at least one embodiment, MPUs 1617-1617N can perform a variety of matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix to matrix multiplication (GEMM). In at least one embodiment, AFUs 1612A-1612N can perform additional logic operations not supported by floating-point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.).

[00282] FIG. 16B illustrates a general-purpose processing unit (GPGPU) 1630 that can be configured to enable highly-parallel compute operations to be performed by an array of graphics processing units, in at least one embodiment. In at least one embodiment, GPGPU 1630 can be linked directly to other instances of GPGPU 1630 to create a multi-GPU cluster to improve training speed for deep neural networks. In at least one embodiment, GPGPU 1630 includes a host interface 1632 to enable a connection with a host processor. In at least one embodiment, host interface 1632 is a PCI Express interface. In at least one embodiment, host interface 1632 can be a vendor specific communications interface or communications fabric. In at least one embodiment, GPGPU 1630 receives commands from a host processor and uses a global scheduler 1634 to distribute execution threads associated with those commands to a set of compute clusters 1636A-1636H. In at least one embodiment, compute clusters 1636A-1636H share a cache memory 1638. In at least one embodiment, cache memory 1638 can serve as a higher-level cache for cache memories within compute clusters 1636A-1636H.

[00283] In at least one embodiment, GPGPU 1630 includes memory 1644A-1644B coupled with compute clusters 1636A-1636H via a set of memory controllers 1642A-1642B. In at least one embodiment, memory 1644A-1644B can include various types of memory devices including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[00284] In at least one embodiment, compute clusters 1636A-1636H each include a set of graphics cores, such as graphics core 1600 of FIG. 16 A, which can include multiple types of integer and floating point logic units that can perform computational operations at a range of precisions including suited for machine learning computations. For example, in at least one embodiment, at least a subset of floating point units in each of compute clusters 1636A-1636H can be configured to perform 16-bit or 32-bit floating point operations, while a different subset of floating point units can be configured to perform 64-bit floating point operations.

[00285] In at least one embodiment, multiple instances of GPGPU 1630 can be configured to operate as a compute cluster. In at least one embodiment, communication used by compute clusters 1636A-1636H for synchronization and data exchange varies across embodiments. In at least one embodiment, multiple instances of GPGPU 1630 communicate over host interface 1632. In at least one embodiment, GPGPU 1630 includes an I / O hub 1639 that couples GPGPU 1630 with a GPU link 1640 that enables a direct connection to other instances of GPGPU 1630. In at least one embodiment, GPU link 1640 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1630. In at least one embodiment GPU link 1640 couples with a high speed interconnect to transmit and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1630 are located in separate data processing systems and communicate via a network device that is accessible via host interface 1632. In at least one embodiment GPU link 1640 can be configured to enable a connection to a host processor in addition to or as an alternative to host interface 1632.

[00286] In at least one embodiment, GPGPU 1630 can be configured to train neural networks. In at least one embodiment, GPGPU 1630 can be used within a inferencing platform. In at least one embodiment, in which GPGPU 1630 is used for inferencing, GPGPU may include fewer compute clusters 1636A-1636H relative to when GPGPU is used for training a neural network. In at least one embodiment, memory technology associated with memory 1644A-1644B may differ between inferencing and training configurations, with higher bandwidth memory technologies devoted to training configurations. In at least one embodiment, inferencing configuration of GPGPU 1630 can support inferencing specific instructions. For example, in at least one embodiment, an inferencing configuration can provide support for one or more 8-bit integer dot product instructions, which may be used during inferencing operations for deployed neural networks.

[00287] FIG. 17 is a block diagram illustrating a computing system 1700 according to at least one embodiment. In at least one embodiment, computing system 1700 includes a processing subsystem 1701 having one or more processor(s) 1702 and a system memory 1704 communicating via an interconnection path that may include a memory hub 1705. In at least one embodiment, memory hub 1705 may be a separate component within a chipset component or may be integrated within one or more processor(s) 1702. In at least one embodiment, memory hub 1705 couples with an I / O subsystem 1711 via a communication link 1706. In at least one embodiment, I / O subsystem 1711 includes an I / O hub 1707 that can enable computing system 1700 to receive input from one or more input device(s) 1708. In at least one embodiment, I / O hub 1707 can enable a display controller, which may be included in one or more processor(s) 1702, to provide outputs to one or more display device(s) 1710A. In at least one embodiment, one or more display device(s) 1710A coupled with I / O hub 1707 can include a local, internal, or embedded display device.

[00288] In at least one embodiment, processing subsystem 1701 includes one or more parallel processor(s) 1712 coupled to memory hub 1705 via a bus or other communication link 1713. In at least one embodiment, communication link 1713 may be one of any number of standards based communication link technologies or protocols, such as, but not limited to PCI Express, or may be a vendor specific communications interface or communications fabric. In at least one embodiment, one or more parallel processor(s) 1712 form a computationally focused parallel or vector processing system that can include a large number of processing cores and / or processing clusters, such as a many integrated core (MIC) processor. In at least one embodiment, one or more parallel processor(s) 1712 form a graphics processing subsystem that can output pixels to one of one or more display device(s) 1710A coupled via I / O Hub 1707. In at least one embodiment, one or more parallel processor(s) 1712 can also include a display controller and display interface (not shown) to enable a direct connection to one or more display device(s) 1710B.

[00289] In at least one embodiment, a system storage unit 1714 can connect to I / O hub 1707 to provide a storage mechanism for computing system 1700. In at least one embodiment, an I / O switch 1716 can be used to provide an interface mechanism to enable connections between I / O hub 1707 and other components, such as a network adapter 1718 and / or wireless network adapter 1719 that may be integrated into platform, and various other devices that can be added via one or more add-in device(s) 1720. In at least one embodiment, network adapter 1718 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 1719 can include one or more of a Wi-Fi, Bluetooth, near field communication (NFC), or other network device that includes one or more wireless radios.

[00290] In at least one embodiment, computing system 1700 can include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, and like, may also be connected to I / O hub 1707. In at least one embodiment, communication paths interconnecting various components in FIG. 17 may be implemented using any suitable protocols, such as PCI (Peripheral Component Interconnect) based protocols (e.g., PCI-Express), or other bus or point-to-point communication interfaces and / or protocol(s), such as NV-Link high-speed interconnect, or interconnect protocols.

[00291] In at least one embodiment, one or more parallel processor(s) 1712 incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitutes a graphics processing unit (GPU). In at least one embodiment, one or more parallel processor(s) 1712 incorporate circuitry optimized for general purpose processing. In at least embodiment, components of computing system 1700 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processor(s) 1712, memory hub 1705, processor(s) 1702, and I / O hub 1707 can be integrated into a system on chip (SoC) integrated circuit. In at least one embodiment, components of computing system 1700 can be integrated into a single package to form a system in package (SIP) configuration. In at least one embodiment, at least a portion of components of computing system 1700 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules into a modular computing system. PROCESSORS

[00292] FIG. 18A illustrates a parallel processor 1800 according to at least on embodiment. In at least one embodiment, various components of parallel processor 1800 may be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits (ASICs), or field programmable gate arrays (FPGA). In at least one embodiment, illustrated parallel processor 1800 is a variant of one or more parallel processor(s) 1712 shown in FIG. 17 according to an exemplary embodiment.

[00293] In at least one embodiment, parallel processor 1800 includes a parallel processing unit 1802. In at least one embodiment, parallel processing unit 1802 includes an I / O unit 1804 that enables communication with other devices, including other instances of parallel processing unit 1802. In at least one embodiment, I / O unit 1804 may be directly connected to other devices. In at least one embodiment, I / O unit 1804 connects with other devices via use of a hub or switch interface, such as memory hub 1705. In at least one embodiment, connections between memory hub 1705 and I / O unit 1804 form a communication link 1713. In at least one embodiment, I / O unit 1804 connects with a host interface 1806 and a memory crossbar 1816, where host interface 1806 receives commands directed to performing processing operations and memory crossbar 1816 receives commands directed to performing memory operations.

[00294] In at least one embodiment, when host interface 1806 receives a command buffer via I / O unit 1804, host interface 1806 can direct work operations to perform those commands to a front end 1808. In at least one embodiment, front end 1808 couples with a scheduler 1810, which is configured to distribute commands or other work items to a processing cluster array 1812. In at least one embodiment, scheduler 1810 ensures that processing cluster array 1812 is properly configured and in a valid state before tasks are distributed to processing cluster array 1812 of processing cluster array 1812. In at least one embodiment, scheduler 1810 is implemented via firmware logic executing on a microcontroller. In at least one embodiment, microcontroller implemented scheduler 1810 is configurable to perform complex scheduling and work distribution operations at coarse and fine granularity, enabling rapid preemption and context switching of threads executing on processing array 1812. In at least one embodiment, host software can prove workloads for scheduling on processing array 1812 via one of multiple graphics processing doorbells. In at least one embodiment, workloads can then be automatically distributed across processing array 1812 by scheduler 1810 logic within a microcontroller including scheduler 1810.

[00295] In at least one embodiment, processing cluster array 1812 can include up to “N” processing clusters (e.g., cluster 1814A, cluster 1814B, through cluster 1814N). In at least one embodiment, each cluster 1814A-1814N of processing cluster array 1812 can execute a large number of concurrent threads. In at least one embodiment, scheduler 1810 can allocate work to clusters 1814A-1814N of processing cluster array 1812 using various scheduling and / or work distribution algorithms, which may vary depending on workload arising for each type of program or computation. In at least one embodiment, scheduling can be handled dynamically by scheduler 1810, or can be assisted in part by compiler logic during compilation of program logic configured for execution by processing cluster array 1812. In at least one embodiment, different clusters 1814A-1814N of processing cluster array 1812 can be allocated for processing different types of programs or for performing different types of computations.

[00296] In at least one embodiment, processing cluster array 1812 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 1812 is configured to perform general-purpose parallel compute operations. For example, in at least one embodiment, processing cluster array 1812 can include logic to execute processing tasks including filtering of video and / or audio data, performing modeling operations, including physics operations, and performing data transformations.

[00297] In at least one embodiment, processing cluster array 1812 is configured to perform parallel graphics processing operations. In at least one embodiment, processing cluster array 1812 can include additional logic to support execution of such graphics processing operations, including, but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing cluster array 1812 can be configured to execute graphics processing related shader programs such as, but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing unit 1802 can transfer data from system memory via I / O unit 1804 for processing. In at least one embodiment, during processing, transferred data can be stored to on-chip memory (e.g., parallel processor memory 1822) during processing, then written back to system memory.

[00298] In at least one embodiment, when parallel processing unit 1802 is used to perform graphics processing, scheduler 1810 can be configured to divide a processing workload into approximately equal sized tasks, to better enable distribution of graphics processing operations to multiple clusters 1814A-1814N of processing cluster array 1812. In at least one embodiment, portions of processing cluster array 1812 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations, to produce a rendered image for display. In at least one embodiment, intermediate data produced by one or more of clusters 1814A-1814N may be stored in buffers to allow intermediate data to be transmitted between clusters 1814A-1814N for further processing.

[00299] In at least one embodiment, processing cluster array 1812 can receive processing tasks to be executed via scheduler 1810, which receives commands defining processing tasks from front end 1808. In at least one embodiment, processing tasks can include indices of data to be processed, e.g., surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how data is to be processed (e.g., what program is to be executed). In at least one embodiment, scheduler 1810 may be configured to fetch indices corresponding to tasks or may receive indices from front end 1808. In at least one embodiment, front end 1808 can be configured to ensure processing cluster array 1812 is configured to a valid state before a workload specified by incoming command buffers (e.g., batch-buffers, push buffers, etc.) is initiated.

[00300] In at least one embodiment, each of one or more instances of parallel processing unit 1802 can couple with parallel processor memory 1822. In at least one embodiment, parallel processor memory 1822 can be accessed via memory crossbar 1816, which can receive memory requests from processing cluster array 1812 as well as I / O unit 1804. In at least one embodiment, memory crossbar 1816 can access parallel processor memory 1822 via a memory interface 1818. In at least one embodiment, memory interface 1818 can include multiple partition units (e.g., partition unit 1820A, partition unit 1820B, through partition unit 1820N) that can each couple to a portion (e.g., memory unit) of parallel processor memory 1822. In at least one embodiment, a number of partition units 1820A-1820N is configured to be equal to a number of memory units, such that a first partition unit 1820A has a corresponding first memory unit 1824A, a second partition unit 1820B has a corresponding memory unit 1824B, and an Nth partition unit 1820N has a corresponding Nth memory unit 1824N. In at least one embodiment, a number of partition units 1820A-1820N may not be equal to a number of memory devices.

[00301] In at least one embodiment, memory units 1824A-1824N can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 1824A-1824N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, render targets, such as frame buffers or texture maps may be stored across memory units 1824A-1824N, allowing partition units 1820A-1820N to write portions of each render target in parallel to efficiently use available bandwidth of parallel processor memory 1822. In at least one embodiment, a local instance of parallel processor memory 1822 may be excluded in favor of a unified memory design that utilizes system memory in conjunction with local cache memory.

[00302] In at least one embodiment, any one of clusters 1814A-1814N of processing cluster array 1812 can process data that will be written to any of memory units 1824A-1824N within parallel processor memory 1822. In at least one embodiment, memory crossbar 1816 can be configured to transfer an output of each cluster 1814A-1814N to any partition unit 1820A-1820N or to another cluster 1814A-1814N, which can perform additional processing operations on an output. In at least one embodiment, each cluster 1814A-1814N can communicate with memory interface 1818 through memory crossbar 1816 to read from or write to various external memory devices. In at least one embodiment, memory crossbar 1816 has a connection to memory interface 1818 to communicate with I / O unit 1804, as well as a connection to a local instance of parallel processor memory 1822, enabling processing units within different processing clusters 1814A-1814N to communicate with system memory or other memory that is not local to parallel processing unit 1802. In at least one embodiment, memory crossbar 1816 can use virtual channels to separate traffic streams between clusters 1814A-1814N and partition units 1820A-1820N.

[00303] In at least one embodiment, multiple instances of parallel processing unit 1802 can be provided on a single add-in card, or multiple add-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 1802 can be configured to interoperate even if different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 1802 can include higher precision floating point units relative to other instances. In at least one embodiment, systems incorporating one or more instances of parallel processing unit 1802 or parallel processor 1800 can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[00304] FIG. 18B is a block diagram of a partition unit 1820 according to at least one embodiment. In at least one embodiment, partition unit 1820 is an instance of one of partition units 1820A-1820N of FIG. 18 A. In at least one embodiment, partition unit 1820 includes an L2 cache 1821, a frame buffer interface 1825, and a ROP 1826 (raster operations unit). L2 cache 1821 is a read / write cache that is configured to perform load and store operations received from memory crossbar 1816 and ROP 1826. In at least one embodiment, read misses and urgent writeback requests are output by L2 cache 1821 to frame buffer interface 1825 for processing. In at least one embodiment, updates can also be sent to a frame buffer via frame buffer interface 1825 for processing. In at least one embodiment, frame buffer interface 1825 interfaces with one of memory units in parallel processor memory, such as memory units 1824A-1824N of FIG. 18 (e.g., within parallel processor memory 1822).

[00305] In at least one embodiment, ROP 1826 is a processing unit that performs raster operations such as stencil, z test, blending, and like. In at least one embodiment, ROP 1826 then outputs processed graphics data that is stored in graphics memory. In at least one embodiment, ROP 1826 includes compression logic to compress depth or color data that is written to memory and decompress depth or color data that is read from memory. In at least one embodiment, compression logic can be lossless compression logic that makes use of one or more of multiple compression algorithms. Type of compression that is performed by ROP 1826 can vary based on statistical characteristics of data to be compressed. For example, in at least one embodiment, delta color compression is performed on depth and color data on a per-tile basis.

[00306] In In at least one embodiment, ROP 1826 is included within each processing cluster (e.g., cluster 1814A-1814N of FIG. 18) instead of within partition unit 1820. In at least one embodiment, read and write requests for pixel data are transmitted over memory crossbar 1816 instead of pixel fragment data. In at least one embodiment, processed graphics data may be displayed on a display device, such as one of one or more display device(s) 1710 of FIG. 17, routed for further processing by processor(s) 1702, or routed for further processing by one of processing entities within parallel processor 1800 of FIG. 18 A.

[00307] FIG. 18C is a block diagram of a processing cluster 1814 within a parallel processing unit according to at least one embodiment. In at least one embodiment, a processing cluster is an instance of one of processing clusters 1814A-1814N of FIG. 18. In at least one embodiment, processing cluster 1814 can be configured to execute many threads in parallel, where term “thread” refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, single-instruction, multiple-data (SIMD) instruction issue techniques are used to support parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single-instruction, multiple-thread (SIMT) techniques are used to support parallel execution of a large number of generally synchronized threads, using a common instruction unit configured to issue instructions to a set of processing engines within each one of processing clusters.

[00308] In at least one embodiment, operation of processing cluster 1814 can be controlled via a pipeline manager 1832 that distributes processing tasks to SIMT parallel processors. In at least one embodiment, pipeline manager 1832 receives instructions from scheduler 1810 of FIG. 18 and manages execution of those instructions via a graphics multiprocessor 1834 and / or a texture unit 1836. In at least one embodiment, graphics multiprocessor 1834 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of differing architectures may be included within processing cluster 1814. In at least one embodiment, one or more instances of graphics multiprocessor 1834 can be included within a processing cluster 1814. In at least one embodiment, graphics multiprocessor 1834 can process data and a data crossbar 1840 can be used to distribute processed data to one of multiple possible destinations, including other shader units. In at least one embodiment, pipeline manager 1832 can facilitate distribution of processed data by specifying destinations for processed data to be distributed via data crossbar 1840.

[00309] In at least one embodiment, each graphics multiprocessor 1834 within processing cluster 1814 can include an identical set of functional execution logic (e.g„ arithmetic logic units, load-store units, etc.). In at least one embodiment, functional execution logic can be configured in a pipelined manner in which new instructions can be issued before previous instructions are complete. In at least one embodiment, functional execution logic supports a variety of operations including integer and floating point arithmetic, comparison operations, Boolean operations, bit-shifting, and computation of various algebraic functions. In at least one embodiment, same functional-unit hardware can be leveraged to perform different operations and any combination of functional units may be present.

[00310] In at least one embodiment, instructions transmitted to processing cluster 1814 constitute a thread. In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, thread group executes a program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within a graphics multiprocessor 1834. In at least one embodiment, a thread group may include fewer threads than a number of processing engines within graphics multiprocessor 1834. In at least one embodiment, when a thread group includes fewer threads than a number of processing engines, one or more of processing engines may be idle during cycles in which that thread group is being processed. In at least one embodiment, a thread group may also include more threads than a number of processing engines within graphics multiprocessor 1834. In at least one embodiment, when a thread group includes more threads than number of processing engines within graphics multiprocessor 1834, processing can be performed over consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed concurrently on a graphics multiprocessor 1834.

[00311] In at least one embodiment, graphics multiprocessor 1834 includes an internal cache memory to perform load and store operations. In at least one embodiment, graphics multiprocessor 1834 can forego an internal cache and use a cache memory (e.g„ LI cache 1848) within processing cluster 1814. In at least one embodiment, each graphics multiprocessor 1834 also has access to L2 caches within partition units (e.g„ partition units 1820A-1820N of FIG. 18) that are shared among all processing clusters 1814 and may be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 1834 may also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 1802 may be used as global memory. In at least one embodiment, processing cluster 1814 includes multiple instances of graphics multiprocessor 1834 can share common instructions and data, which may be stored in LI cache 1848.

[00312] In at least one embodiment, each processing cluster 1814 may include an MMU 1845 (memory management unit) that is configured to map virtual addresses into physical addresses. In at least one embodiment, one or more instances of MMU 1845 may reside within memory interface 1818 of FIG. 18. In at least one embodiment, MMU 1845 includes a set of page table entries (PTEs) used to map a virtual address to a physical address of a tile (talk more about tiling) and optionally a cache line index. In at least one embodiment, MMU 1845 may include address translation lookaside buffers (TLB) or caches that may reside within graphics multiprocessor 1834 or LI cache or processing cluster 1814. In at least one embodiment, physical address is processed to distribute surface data access locality to allow efficient request interleaving among partition units. In at least one embodiment, cache line index may be used to determine whether a request for a cache line is a hit or miss.

[00313] In at least one embodiment, a processing cluster 1814 may be configured such that each graphics multiprocessor 1834 is coupled to a texture unit 1836 for performing texture mapping operations, e.g., determining texture sample positions, reading texture data, and filtering texture data. In at least one embodiment, texture data is read from an internal texture LI cache (not shown) or from an LI cache within graphics multiprocessor 1834 and is fetched from an L2 cache, local parallel processor memory, or system memory, as needed. In at least one embodiment, each graphics multiprocessor 1834 outputs processed tasks to data crossbar 1840 to provide processed task to another processing cluster 1814 for further processing or to store processed task in an L2 cache, local parallel processor memory, or system memory via memory crossbar 1816. In at least one embodiment, preROP 1842 (pre-raster operations unit) is configured to receive data from graphics multiprocessor 1834, direct data to ROP units, which may be located with partition units as described herein (e.g., partition units 1820A-1820N of FIG. 18). In at least one embodiment, PreROP 1842 unit can perform optimizations for color blending, organize pixel color data, and perform address translations.

[00314] In at least one embodiment, a processing cluster 1814 may be configured such that each graphics multiprocessor 1834 is coupled to a texture unit 1836 for performing baseband unit (BBU) operations implemented in FIG. 5.

[00315] FIG. 18D shows a graphics multiprocessor 1834 according to at least one embodiment. In at least one embodiment, graphics multiprocessor 1834 couples with pipeline manager 1832 of processing cluster 1814. In at least one embodiment, graphics multiprocessor 1834 has an execution pipeline including but not limited to an instruction cache 1852, an instruction unit 1854, an address mapping unit 1856, a register file 1858, one or more general purpose graphics processing unit (GPGPU) cores 1862, and one or more load / store units 1866. GPGPU cores 1862 and load / store units 1866 are coupled with cache memory 1872 and shared memory 1870 via a memory and cache interconnect 1868.

[00316] In at least one embodiment, instruction cache 1852 receives a stream of instructions to execute from pipeline manager 1832. In at least one embodiment, instructions are cached in instruction cache 1852 and dispatched for execution by instruction unit 1854. In at least one embodiment, instruction unit 1854 can dispatch instructions as thread groups (e.g„ warps), with each thread of thread group assigned to a different execution unit within GPGPU core 1862. In at least one embodiment, an instruction can access any of a local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, address mapping unit 1856 can be used to translate addresses in a unified address space into a distinct memory address that can be accessed by load / store units 1866.

[00317] In at least one embodiment, register file 1858 provides a set of registers for functional units of graphics multiprocessor 1834. In at least one embodiment, register file 1858 provides temporary storage for operands connected to data paths of functional units (e.g., GPGPU cores 1862, load / store units 1866) of graphics multiprocessor 1834. In at least one embodiment, register file 1858 is divided between each of functional units such that each functional unit is allocated a dedicated portion of register file 1858. In at least one embodiment, register file 1858 is divided between different warps being executed by graphics multiprocessor 1834.

[00318] In at least one embodiment, GPGPU cores 1862 can each include floating point units (FPUs) and / or integer arithmetic logic units (ALUs) that are used to execute instructions of graphics multiprocessor 1834. GPGPU cores 1862 can be similar in architecture or can differ in architecture. In at least one embodiment, a first portion of GPGPU cores 1862 include a single precision FPU and an integer ALU while a second portion of GPGPU cores include a double precision FPU. In at least one embodiment, FPUs can implement IEEE 754-2008 standard for floating point arithmetic or enable variable precision floating point arithmetic. In at least one embodiment, graphics multiprocessor 1834 can additionally include one or more fixed function or special function units to perform specific functions such as copy rectangle or pixel blending operations. In at least one embodiment one or more of GPGPU cores can also include fixed or special function logic.

[00319] In at least one embodiment, GPGPU cores 1862 include SIMD logic capable of performing a single instruction on multiple sets of data. In at least one embodiment GPGPU cores 1862 can physically execute SIMD4, SIMD8, and SIMD 16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for GPGPU cores can be generated at compile time by a shader compiler or automatically generated when executing programs written and compiled for single program multiple data (SPMD) or SIMT architectures. In at least one embodiment, multiple threads of a program configured for an SIMT execution model can executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads that perform same or similar operations can be executed in parallel via a single SIMD8 logic unit.

[00320] In at least one embodiment, memory and cache interconnect 1868 is an interconnect network that connects each functional unit of graphics multiprocessor 1834 to register file 1858 and to shared memory 1870. In at least one embodiment, memory and cache interconnect 1868 is a crossbar interconnect that allows load / store unit 1866 to implement load and store operations between shared memory 1870 and register file 1858. In at least one embodiment, register file 1858 can operate at a same frequency as GPGPU cores 1862, thus data transfer between GPGPU cores 1862 and register file 1858 is very low latency. In at least one embodiment, shared memory 1870 can be used to enable communication between threads that execute on functional units within graphics multiprocessor 1834. In at least one embodiment, cache memory 1872 can be used as a data cache for example, to cache texture data communicated between functional units and texture unit 1836. In at least one embodiment, shared memory 1870 can also be used as a program managed cached. In at least one embodiment, threads executing on GPGPU cores 1862 can programmatically store data within shared memory in addition to automatically cached data that is stored within cache memory 1872.

[00321] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to host / processor cores to accelerate graphics operations, machinelearning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. In at least one embodiment, GPU may be communicatively coupled to host processor / cores over a bus or other interconnect (e.g„ a high speed interconnect such as PCIe or NVLink). In at least one embodiment, GPU may be integrated on same package or chip as cores and communicatively coupled to cores over an internal processor bus / interconnect (i.e., internal to package or chip). In at least one embodiment, regardless of manner in which GPU is connected, processor cores may allocate work to GPU in form of sequences of commands / instructions contained in a work descriptor. In at least one embodiment, GPU then uses dedicated circuitry / logic for efficiently processing these commands / instructions.

[00322] FIG. 19 illustrates a multi-GPU computing system 1900, according to at least one embodiment. In at least one embodiment, multi-GPU computing system 1900 can include a processor 1902 coupled to multiple general purpose graphics processing units (GPGPUs) 1906A-D via a host interface switch 1904. In at least one embodiment, host interface switch 1904 is a PCI express switch device that couples processor 1902 to a PCI express bus over which processor 1902 can communicate with GPGPUs 1906A-D. GPGPUs 1906A-D can interconnect via a set of high-speed point to point GPU to GPU links 1916. In at least one embodiment, GPU to GPU links 1916 connect to each of GPGPUs 1906A-D via a dedicated GPU link. In at least one embodiment, P2P GPU links 1916 enable direct communication between each of GPGPUs 1906A-D without requiring communication over host interface bus 1904 to which processor 1902 is connected. In at least one embodiment, with GPU-to-GPU traffic directed to P2P GPU links 1916, host interface bus 1904 remains available for system memory access or to communicate with other instances of multi-GPU computing system 1900, for example, via one or more network devices. While in at least one embodiment GPGPUs 1906A-D connect to processor 1902 via host interface switch 1904, in at least one embodiment processor 1902 includes direct support for P2P GPU links 1916 and can connect directly to GPGPUs 1906A-D.

[00323] FIG. 20 is a block diagram of a graphics processor 2000, according to at least one embodiment. In at least one embodiment, graphics processor 2000 includes a ring interconnect 2002, a pipeline front-end 2004, a media engine 2037, and graphics cores 2080A-2080N. In at least one embodiment, ring interconnect 2002 couples graphics processor 2000 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 2000 is one of many processors integrated within a multi-core processing system.

[00324] In at least one embodiment, graphics processor 2000 receives batches of commands via ring interconnect 2002. In at least one embodiment, incoming commands are interpreted by a command streamer 2003 in pipeline front-end 2004. In at least one embodiment, graphics processor 2000 includes scalable execution logic to perform 3D geometry processing and media processing via graphics core(s) 2080A-2080N. In at least one embodiment, for 3D geometry processing commands, command streamer 2003 supplies commands to geometry pipeline 2036. In at least one embodiment, for at least some media processing commands, command streamer 2003 supplies commands to a video front end 2034, which couples with a media engine 2037. In at least one embodiment, media engine 2037 includes a Video Quality Engine (VQE) 2030 for video and image post-processing and a multi-format encode / decode (MFX) 2033 engine to provide hardware-accelerated media data encode and decode. In at least one embodiment, geometry pipeline 2036 and media engine 2037 each generate execution threads for thread execution resources provided by at least one graphics core 2080A.

[00325] In at least one embodiment, graphics processor 2000 includes scalable thread execution resources featuring modular cores 2080A-2080N (sometimes referred to as core slices), each having multiple sub-cores 2050A-550N, 2060A-2060N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor 2000 can have any number of graphics cores 2080A through 2080N. In at least one embodiment, graphics processor 2000 includes a graphics core 2080A having at least a first sub-core 2050A and a second sub-core 2060A. In at least one embodiment, graphics processor 2000 is a low power processor with a single sub-core (e.g., 2050A). In at least one embodiment, graphics processor 2000 includes multiple graphics cores 2080A-2080N, each including a set of first sub-cores 2050A-2050N and a set of second sub-cores 2060A-2060N. In at least one embodiment, each sub-core in first sub cores 2050A-2050N includes at least a first set of execution units 2052A-2052N and media / texture samplers 2054A-2054N. In at least one embodiment, each sub-core in second subcores 2060A-2060N includes at least a second set of execution units 2062A-2062N and samplers 2064A-2064N. In at least one embodiment, each sub-core 2050A-2050N, 2060A-2060N shares a set of shared resources 2070A-2070N. In at least one embodiment, shared resources include shared cache memory and pixel operation logic.

[00326] FIG. 21 is a block diagram illustrating micro-architecture for a processor 2100 that may include logic circuits to perform instructions, according to at least one embodiment. In at least one embodiment, processor 2100 may perform instructions, including x86 instructions, ARM instructions, specialized instructions for application-specific integrated circuits (ASICs), etc. In at least one embodiment, processor 2110 may include registers to store packed data, such as 64-bit wide MMX™ registers in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, Calif. In at least one embodiment, MMX registers, available in both integer and floating point forms, may operate with packed data elements that accompany single instruction, multiple data (“SIMD”) and streaming SIMD extensions (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers relating to SSE2, SSE3, SSE4, AVX, or beyond (referred to generically as “SSEx”) technology may hold such packed data operands. In at least one embodiment, processors 2110 may perform instructions to accelerate machine learning or deep learning algorithms, training, or inferencing.

[00327] In at least one embodiment, processor 2100 includes an in-order front end (“front end”) 2101 to fetch instructions to be executed and prepare instructions to be used later in processor pipeline. In at least one embodiment, front end 2101 may include several units. In at least one embodiment, an instruction prefetcher 2126 fetches instructions from memory and feeds instructions to an instruction decoder 2128 which in turn decodes or interprets instructions. For example, in at least one embodiment, instruction decoder 2128 decodes a received instruction into one or more operations called “micro-instructions” or “micro-operations” (also called “micro ops”or “uops”) that machine may execute. In at least one embodiment, instruction decoder 2128 parses instruction into an opcode and corresponding data and control fields that may be used by micro-architecture to perform operations in accordance with at least one embodiment. In at least one embodiment, a trace cache 2130 may assemble decoded uops into program ordered sequences or traces in a uop queue 2134 for execution. In at least one embodiment, when trace cache 2130 encounters a complex instruction, a microcode ROM 2132 provides uops needed to complete operation.

[00328] In at least one embodiment, some instructions may be converted into a single microop, whereas others need several micro-ops to complete full operation. In at least one embodiment, if more than four micro-ops are needed to complete an instruction, instruction decoder 2128 may access microcode ROM 2132 to perform instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-ops for processing at instruction decoder 2128. In at least one embodiment, an instruction may be stored within microcode ROM 2132 should a number of micro-ops be needed to accomplish operation. In at least one embodiment, trace cache 2130 refers to an entry point programmable logic array (“PLA”) to determine a correct micro-instruction pointer for reading microcode sequences to complete one or more instructions from microcode ROM 2132 in accordance with at least one embodiment. In at least one embodiment, after microcode ROM 2132 finishes sequencing micro-ops for an instruction, front end 2101 of machine may resume fetching micro-ops from trace cache 2130.

[00329] In at least one embodiment, out-of-order execution engine (“out of order engine”) 2103 may prepare instructions for execution. In at least one embodiment, out-of-order execution logic has a number of buffers to smooth out and re-order flow of instructions to optimize performance as they go down pipeline and get scheduled for execution, out-of-order execution engine 2103 includes, without limitation, an allocator / register renamer 2140, a memory uop queue 2142, an integer / floating point uop queue 2144, a memory scheduler 2146, a fast scheduler 2102, a slow / general floating point scheduler (“slow / general FP scheduler”) 2104, and a simple floating point scheduler (“simple FP scheduler”) 2106. In at least one embodiment, fast schedule 2102, slow / general floating point scheduler 2104, and simple floating point scheduler 2106 are also collectively referred to herein as “uop schedulers 2102, 2104, 2106.” Allocator / register renamer 2140 allocates machine buffers and resources that each uop needs in order to execute. In at least one embodiment, allocator / register renamer 2140 renames logic registers onto entries in a register file. In at least one embodiment, allocator / register renamer 2140 also allocates an entry for each uop in one of two uop queues, memory uop queue 2142 for memory operations and integer / floating point uop queue 2144 for non-memory operations, in front of memory scheduler 2146 and uop schedulers 2102, 2104, 2106. In at least one embodiment, uop schedulers 2102, 2104, 2106, determine when a uop is ready to execute based on readiness of their dependent input register operand sources and availability of execution resources uops need to complete their operation. In at least one embodiment, fast scheduler 2102 of at least one embodiment may schedule on each half of main clock cycle while slow / general floating point scheduler 2104 and simple floating point scheduler 2106 may schedule once per main processor clock cycle. In at least one embodiment, uop schedulers 2102, 2104, 2106 arbitrate for dispatch ports to schedule uops for execution.

[00330] In at least one embodiment, execution block bl 1 includes, without limitation, an integer register file / bypass network 2108, a floating point register file / bypass network (“FP register file / bypass network”) 2110, address generation units (“AGUs”) 2112 and 2114, fast Arithmetic Logic Units (ALUs) (“fast ALUs”) 2116 and 2118, a slow Arithmetic Logic Unit (“slow ALU”) 2120, a floating point ALU (“FP”) 2122, and a floating point move unit (“FP move”) 2124. In at least one embodiment, integer register file / bypass network 2108 and floating point register file / bypass network 2110 are also referred to herein as “register files 2108, 2110.” In at least one embodiment, AGUSs 2112 and 2114, fast ALUs 2116 and 2118, slow ALU 2120, floating point ALU 2122, and floating point move unit 2124 are also referred to herein as “execution units 2112, 2114, 2116, 2118, 2120, 2122, and 2124.” In at least one embodiment, execution block b 11 may include, without limitation, any number (including zero) and type of register files, bypass networks, address generation units, and execution units, in any combination.

[00331] In at least one embodiment, register files 2108, 2110 may be arranged between uop schedulers 2102, 2104, 2106, and execution units 2112, 2114, 2116, 2118, 2120, 2122, and 2124. In at least one embodiment, integer register file / bypass network 2108 performs integer operations. In at least one embodiment, floating point register file / bypass network 2110 performs floating point operations. In at least one embodiment, each of register files 2108, 2110 may include, without limitation, a bypass network that may bypass or forward just completed results that have not yet been written into register file to new dependent uops. In at least one embodiment, register files 2108, 2110 may communicate data with each other. In at least one embodiment, integer register file / bypass network 2108 may include, without limitation, two separate register files, one register file for low-order thirty-two bits of data and a second register file for high order thirty-two bits of data. In at least one embodiment, floating point register file / bypass network 2110 may include, without limitation, 128-bit wide entries because floating point instructions typically have operands from 64 to 128 bits in width.

[00332] In at least one embodiment, execution units 2112, 2114, 2116, 2118, 2120, 2122, 2124 may execute instructions. In at least one embodiment, register files 2108, 2110 store integer and floating point data operand values that micro-instructions need to execute. In at least one embodiment, processor 2100 may include, without limitation, any number and combination of execution units 2112, 2114, 2116, 2118, 2120, 2122, 2124. In at least one embodiment, floating point ALU 2122 and floating point move unit 2124, may execute floating point, MMX, SIMD, AVX and SSE, or other operations, including specialized machine learning instructions. In at least one embodiment, floating point ALU 2122 may include, without limitation, a 64-bit by 64-bit floating point divider to execute divide, square root, and remainder micro ops. In at least one embodiment, instructions involving a floating point value may be handled with floating point hardware. In at least one embodiment, ALU operations may be passed to fast ALUs 2116, 2118. In at least one embodiment, fast ALUS 2116, 2118 may execute fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations go to slow ALU 2120 as slow ALU 2120 may include, without limitation, integer execution hardware for long-latency type of operations, such as a multiplier, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations may be executed by AGUS 2112, 2114. In at least one embodiment, fast ALU 2116, fast ALU 2118, and slow ALU 2120 may perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2116, fast ALU 2118, and slow ALU 2120 may be implemented to support a variety of data bit sizes including sixteen, thirty-two, 128, 256, etc. In at least one embodiment, floating point ALU 2122 and floating point move unit 2124 may be implemented to support a range of operands having bits of various widths. In at least one embodiment, floating point ALU 2122 and floating point move unit 2124 may operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[00333] In at least one embodiment, uop schedulers 2102, 2104, 2106, dispatch dependent operations before parent load has finished executing. In at least one embodiment, as uops may be speculatively scheduled and executed in processor 2100, processor 2100 may also include logic to handle memory misses. In at least one embodiment, if a data load misses in data cache, there may be dependent operations in flight in pipeline that have left scheduler with temporarily incorrect data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, dependent operations might need to be replayed and independent ones may be allowed to complete. In at least one embodiment, schedulers and replay mechanism of at least one embodiment of a processor may also be designed to catch instruction sequences for text string comparison operations.

[00334] In at least one embodiment, term “registers” may refer to on-board processor storage locations that may be used as part of instructions to identify operands. In at least one embodiment, registers may be those that may be usable from outside of processor (from a programmer's perspective). In at least one embodiment, registers might not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform functions described herein. In at least one embodiment, registers described herein may be implemented by circuitry within a processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, integer registers store 32-bit integer data. A register file of at least one embodiment also contains eight multimedia SIMD registers for packed data.

[00335] FIG. 22 is a block diagram of a processing system, according to at least one embodiment. In at least one embodiment, system 2200 includes one or more processors 2202 and one or more graphics processors 2208, and may be a single processor desktop system, a multiprocessor workstation system, or a server system having a large number of processors 2202 or processor cores 2207. In at least one embodiment, system 2200 is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[00336] In at least one embodiment, system 2200 can include, or be incorporated within a server-based gaming platform, a game console, including a game and media console, a mobile gaming console, a handheld game console, or an online game console. In at least one embodiment, system 2200 is a mobile phone, smart phone, tablet computing device or mobile Internet device. In at least one embodiment, processing system 2200 can also include, couple with, or be integrated within a wearable device, such as a smart watch wearable device, smart eyewear device, augmented reality device, or virtual reality device. In at least one embodiment, processing system 2200 is a television or set top box device having one or more processors 2202 and a graphical interface generated by one or more graphics processors 2208.

[00337] In at least one embodiment, one or more processors 2202 each include one or more processor cores 2207 to process instructions which, when executed, perform operations for system and user software. In at least one embodiment, each of one or more processor cores 2207 is configured to process a specific instruction set 2209. In at least one embodiment, instruction set 2209 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computing via a Very Long Instruction Word (VLIW). In at least one embodiment, processor cores 2207 may each process a different instruction set 2209, which may include instructions to facilitate emulation of other instruction sets. In at least one embodiment, processor core 2207 may also include other processing devices, such a Digital Signal Processor (DSP).

[00338] In at least one embodiment, processor 2202 includes cache memory 2204. In at least one embodiment, processor 2202 can have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory is shared among various components of processor 2202. In at least one embodiment, processor 2202 also uses an external cache (e.g., a Level-3 (L3) cache or Last Level Cache (LLC)) (not shown), which may be shared among processor cores 2207 using known cache coherency techniques. In at least one embodiment, register file 2206 is additionally included in processor 2202 which may include different types of registers for storing different types of data (e.g., integer registers, floating point registers, status registers, and an instruction pointer register). In at least one embodiment, register file 2206 may include general-purpose registers or other registers.

[00339] In at least one embodiment, one or more processor(s) 2202 are coupled with one or more interface bus(es) 2210 to transmit communication signals such as address, data, or control signals between processor 2202 and other components in system 2200. In at least one embodiment interface bus 2210, in one embodiment, can be a processor bus, such as a version of a Direct Media Interface (DMI) bus. In at least one embodiment, interface 2210 is not limited to a DMI bus, and may include one or more Peripheral Component Interconnect buses (e.g., PCI, PCI Express), memory busses, or other types of interface busses. In at least one embodiment processor(s) 2202 include an integrated memory controller 2216 and a platform controller hub 2230. In at least one embodiment, memory controller 2216 facilitates communication between a memory device and other components of system 2200, while platform controller hub (PCH) 2230 provides connections to I / O devices via a local VO bus.

[00340] In at least one embodiment, memory device 2220 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, flash memory device, phase-change memory device, or some other memory device having suitable performance to serve as process memory. In at least one embodiment memory device 2220 can operate as system memory for system 2200, to store data 2222 and instructions 2221 for use when one or more processors 2202 executes an application or process. In at least one embodiment, memory controller 2216 also couples with an optional external graphics processor 2212, which may communicate with one or more graphics processors 2208 in processors 2202 to perform graphics and media operations. In at least one embodiment, a display device 2211 can connect to processor(s) 2202. In at least one embodiment display device 2211 can include one or more of an internal display device, as in a mobile electronic device or a laptop device or an external display device attached via a display interface (e.g., DisplayPort, etc.). In at least one embodiment, display device 2211 can include a head mounted display (HMD) such as a stereoscopic display device for use in virtual reality (VR) applications or augmented reality (AR) applications.

[00341] In at least one embodiment, platform controller hub 2230 enables peripherals to connect to memory device 2220 and processor 2202 via a high-speed VO bus. In at least one embodiment, I / O peripherals include, but are not limited to, an audio controller 2246, a network controller 2234, a firmware interface 2228, a wireless transceiver 2226, touch sensors 2225, a data storage device 2224 (e.g., hard disk drive, flash memory, etc.). In at least one embodiment, data storage device 2224 can connect via a storage interface (e.g„ SATA) or via a peripheral bus, such as a Peripheral Component Interconnect bus (e.g„ PCI, PCI Express). In at least one embodiment, touch sensors 2225 can include touch screen sensors, pressure sensors, or fingerprint sensors. In at least one embodiment, wireless transceiver 2226 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, firmware interface 2228 enables communication with system firmware, and can be, for example, a unified extensible firmware interface (UEFI). In at least one embodiment, network controller 2234 can enable a network connection to a wired network. In at least one embodiment, a high-performance network controller (not shown) couples with interface bus 2210. In at least one embodiment, audio controller 2246 is a multi-channel high definition audio controller. In at least one embodiment, system 2200 includes an optional legacy I / O controller 2240 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to system. In at least one embodiment, platform controller hub 2230 can also connect to one or more Universal Serial Bus (USB) controllers 2242 connect input devices, such as keyboard and mouse 2243 combinations, a camera 2244, or other USB input devices.

[00342] In at least one embodiment, an instance of memory controller 2216 and platform controller hub 2230 may be integrated into a discreet external graphics processor, such as external graphics processor 2212. In at least one embodiment, platform controller hub 2230 and / or memory controller 2216 may be external to one or more processor(s) 2202. For example, in at least one embodiment, system 2200 can include an external memory controller 2216 and platform controller hub 2230, which may be configured as a memory controller hub and peripheral controller hub within a system chipset that is in communication with processor(s) 2202.

[00343] FIG. 23 is a block diagram of a processor 2300 having one or more processor cores 2302A-2302N, an integrated memory controller 2314, and an integrated graphics processor 2308, according to at least one embodiment. In at least one embodiment, processor 2300 can include additional cores up to and including additional core 2302N represented by dashed lined boxes. In at least one embodiment, each of processor cores 2302A-2302N includes one or more internal cache units 2304A-2304N. In at least one embodiment, each processor core also has access to one or more shared cached units 2306.

[00344] In at least one embodiment, internal cache units 2304A-2304N and shared cache units 2306 represent a cache memory hierarchy within processor 2300. In at least one embodiment, cache memory units 2304A-2304N may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as a Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, where a highest level of cache before external memory is classified as an LLC. In at least one embodiment, cache coherency logic maintains coherency between various cache units 2306 and 2304A-2304N.

[00345] In at least one embodiment, processor 2300 may also include a set of one or more bus controller units 2316 and a system agent core 2310. In at least one embodiment, one or more bus controller units 2316 manage a set of peripheral buses, such as one or more PCI or PCI express busses. In at least one embodiment, system agent core 2310 provides management functionality for various processor components. In at least one embodiment, system agent core 2310 includes one or more integrated memory controllers 2314 to manage access to various external memory devices (not shown).

[00346] In at least one embodiment, one or more of processor cores 2302A-2302N include support for simultaneous multi-threading. In at least one embodiment, system agent core 2310 includes components for coordinating and operating cores 2302A-2302N during multi-threaded processing. In at least one embodiment, system agent core 2310 may additionally include a power control unit (PCU), which includes logic and components to regulate one or more power states of processor cores 2302A-2302N and graphics processor 2308.

[00347] In at least one embodiment, processor 2300 additionally includes graphics processor 2308 to execute graphics processing operations. In at least one embodiment, graphics processor 2308 couples with shared cache units 2306, and system agent core 2310, including one or more integrated memory controllers 2314. In at least one embodiment, system agent core 2310 also includes a display controller 2311 to drive graphics processor output to one or more coupled displays. In at least one embodiment, display controller 2311 may also be a separate module coupled with graphics processor 2308 via at least one interconnect, or may be integrated within graphics processor 2308.

[00348] In at least one embodiment, a ring based interconnect unit 2312 is used to couple internal components of processor 2300. In at least one embodiment, an alternative interconnect unit may be used, such as a point-to-point interconnect, a switched interconnect, or other techniques. In at least one embodiment, graphics processor 2308 couples with ring interconnect 2312 via an I / O link 2313.

[00349] In at least one embodiment, I / O link 2313 represents at least one of multiple varieties of I / O interconnects, including an on package I / O interconnect which facilitates communication between various processor components and a high-performance embedded memory module 2318, such as an eDRAM module. In at least one embodiment, each of processor cores 2302A-2302N and graphics processor 2308 use embedded memory modules 2318 as a shared Last Level Cache.

[00350] In at least one embodiment, processor cores 2302A-2302N are homogenous cores executing a common instruction set architecture. In at least one embodiment, processor cores 2302A-2302N are heterogeneous in terms of instruction set architecture (ISA), where one or more of processor cores 2302A-2302N execute a common instruction set, while one or more other cores of processor cores 2302A-23-02N executes a subset of a common instruction set or a different instruction set. In at least one embodiment, processor cores 2302A-2302N are heterogeneous in terms of microarchitecture, where one or more cores having a relatively higher power consumption couple with one or more power cores having a lower power consumption. In at least one embodiment, processor 2300 can be implemented on one or more chips or as an SoC integrated circuit.

[00351] FIG. 24 is a block diagram of a graphics processor 2400, which may be a discrete graphics processing unit, or may be a graphics processor integrated with a plurality of processing cores. In at least one embodiment, graphics processor 2400 communicates via a memory mapped I / O interface to registers on graphics processor 2400 and with commands placed into memory. In at least one embodiment, graphics processor 2400 includes a memory interface 2414 to access memory. In at least one embodiment, memory interface 2414 is an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[00352] In at least one embodiment, graphics processor 2400 also includes a display controller 2402 to drive display output data to a display device 2420. In at least one embodiment, display controller 2402 includes hardware for one or more overlay planes for display device 2420 and composition of multiple layers of video or user interface elements. In at least one embodiment, display device 2420 can be an internal or external display device. In at least one embodiment, display device 2420 is a head mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device. In at least one embodiment, graphics processor 2400 includes a video codec engine 2406 to encode, decode, or transcode media to, from, or between one or more media encoding formats, including, but not limited to Moving Picture Experts Group (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formats such as H.264 / MPEG-4 AVC, as well as the Society of Motion Picture &Television Engineers (SMPTE) 421M / VC-1, and Joint Photographic Experts Group (JPEG) formats such as JPEG, and Motion JPEG (MJPEG) formats.

[00353] In at least one embodiment, graphics processor 2400 includes a block image transfer (BLIT) engine 2404 to perform two-dimensional (2D) rasterizer operations including, for example, bit-boundary block transfers. However, in at least one embodiment, 2D graphics operations are performed using one or more components of graphics processing engine (GPE) 2410. In at least one embodiment, GPE 2410 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[00354] In at least one embodiment, GPE 2410 includes a 3D pipeline 2412 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that act upon 3D primitive shapes (e.g., rectangle, triangle, etc.). 3D pipeline 2412 includes programmable and fixed function elements that perform various tasks and / or spawn execution threads to a 3D / Media sub-system 2415. While 3D pipeline 2412 can be used to perform media operations, in at least one embodiment, GPE 2410 also includes a media pipeline 2416 that is used to perform media operations, such as video post-processing and image enhancement.

[00355] In at least one embodiment, media pipeline 2416 includes fixed function or programmable logic units to perform one or more specialized media operations, such as video decode acceleration, video de-interlacing, and video encode acceleration in place of, or on behalf of video codec engine 2406. In at least one embodiment, media pipeline 2416 additionally includes a thread spawning unit to spawn threads for execution on 3D / Media sub-system 2415. In at least one embodiment, spawned threads perform computations for media operations on one or more graphics execution units included in 3D / Media sub-system 2415.

[00356] In at least one embodiment, 3D / Media subsystem 2415 includes logic for executing threads spawned by 3D pipeline 2412 and media pipeline 2416. In at least one embodiment, 3D pipeline 2412 and media pipeline 2416 send thread execution requests to 3D / Media subsystem 2415, which includes thread dispatch logic for arbitrating and dispatching various requests to available thread execution resources. In at least one embodiment, execution resources include an array of graphics execution units to process 3D and media threads. In at least one embodiment, 3D / Media subsystem 2415 includes one or more internal caches for thread instructions and data. In at least one embodiment, subsystem 2415 also includes shared memory, including registers and addressable memory, to share data between threads and to store output data.

[00357] FIG. 25 is a block diagram of a graphics processing engine 2510 of a graphics processor in accordance with at least one embodiment. In at least one embodiment, graphics processing engine (GPE) 2510 is a version of GPE 2410 shown in FIG. 24. In at least one embodiment, media pipeline 2516 is optional and may not be explicitly included within GPE 2510. In at least one embodiment, a separate media and / or image processor is coupled to GPE 2510.

[00358] In at least one embodiment, GPE 2510 is coupled to or includes a command streamer 2503, which provides a command stream to 3D pipeline 2512 and / or media pipelines 2516. In at least one embodiment, command streamer 2503 is coupled to memory, which can be system memory, or one or more of internal cache memory and shared cache memory. In at least one embodiment, command streamer 2503 receives commands from memory and sends commands to 3D pipeline 2512 and / or media pipeline 2516. In at least one embodiment, commands are instructions, primitives, or micro-operations fetched from a ring buffer, which stores commands for 3D pipeline 2512 and media pipeline 2516. In at least one embodiment, a ring buffer can additionally include batch command buffers storing batches of multiple commands. In at least one embodiment, commands for 3D pipeline 2512 can also include references to data stored in memory, such as but not limited to vertex and geometry data for 3D pipeline 2512 and / or image data and memory objects for media pipeline 2516. In at least one embodiment, 3D pipeline 2512 and media pipeline 2516 process commands and data by performing operations or by dispatching one or more execution threads to a graphics core array 2514. In at least one embodiment graphics core array 2514 includes one or more blocks of graphics cores (e.g„ graphics core(s) 2515 A, graphics core(s) 2515B), each block including one or more graphics cores. In at least one embodiment, each graphics core includes a set of graphics execution resources that includes general-purpose and graphics specific execution logic to perform graphics and compute operations, as well as fixed function texture processing and / or machine learning and artificial intelligence acceleration logic.

[00359] In at least one embodiment, 3D pipeline 2512 includes fixed function and programmable logic to process one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to graphics core array 2514. In at least one embodiment, graphics core array 2514 provides a unified block of execution resources for use in processing shader programs. In at least one embodiment, multi-purpose execution logic (e.g., execution units) within graphics core(s) 2515A-2515B of graphic core array 2514 includes support for various 3D API shader languages and can execute multiple simultaneous execution threads associated with multiple shaders.

[00360] In at least one embodiment, graphics core array 2514 also includes execution logic to perform media functions, such as video and / or image processing. In at least one embodiment, execution units additionally include general-purpose logic that is programmable to perform parallel general-purpose computational operations, in addition to graphics processing operations.

[00361] In at least one embodiment, output data generated by threads executing on graphics core array 2514 can output data to memory in a unified return buffer (URB) 2518. URB 2518 can store data for multiple threads. In at least one embodiment, URB 2518 may be used to send data between different threads executing on graphics core array 2514. In at least one embodiment, URB 2518 may additionally be used for synchronization between threads on graphics core array 2514 and fixed function logic within shared function logic 2520.

[00362] In at least one embodiment, graphics core array 2514 is scalable, such that graphics core array 2514 includes a variable number of graphics cores, each having a variable number of execution units based on a target power and performance level of GPE 2510. In at least one embodiment, execution resources are dynamically scalable, such that execution resources may be enabled or disabled as needed.

[00363] In at least one embodiment, graphics core array 2514 is coupled to shared function logic 2520 that includes multiple resources that are shared between graphics cores in graphics core array 2514. In at least one embodiment, shared functions performed by shared function logic 2520 are embodied in hardware logic units that provide specialized supplemental functionality to graphics core array 2514. In at least one embodiment, shared function logic 2520 includes but is not limited to sampler 2521, math 2522, and inter-thread communication (ITC) 2523 logic. In at least one embodiment, one or more cache(s) 2525 are in included in or couple to share function logic 2520.

[00364] In at least one embodiment, a shared function is used if demand for a specialized function is insufficient for inclusion within graphics core array 2514. In at least one embodiment, a single instantiation of a specialized function is used in shared function logic 2520 and shared among other execution resources within graphics core array 2514. In at least one embodiment, specific shared functions within shared function logic 2520 that are used extensively by graphics core array 2514 may be included within shared function logic 2516 within graphics core array 2514. In at least one embodiment, shared function logic 2516 within graphics core array 2514 can include some or all logic within shared function logic 2520. In at least one embodiment, all logic elements within shared function logic 2520 may be duplicated within shared function logic 2516 of graphics core array 2514. In at least one embodiment, shared function logic 2520 is excluded in favor of shared function logic 2516 within graphics core array 2514.

[00365] FIG. 26 is a block diagram of hardware logic of a graphics processor core 2600, according to at least one embodiment described herein. In at least one embodiment, graphics processor core 2600 is included within a graphics core array. In at least one embodiment, graphics processor core 2600, sometimes referred to as a core slice, can be one or multiple graphics cores within a modular graphics processor. In at least one embodiment, graphics processor core 2600 is exemplary of one graphics core slice, and a graphics processor as described herein may include multiple graphics core slices based on target power and performance envelopes. In at least one embodiment, each graphics core 2600 can include a fixed function block 2630 coupled with multiple sub-cores 2601A-2601F, also referred to as subslices, that include modular blocks of general-purpose and fixed function logic.

[00366] In at least one embodiment, fixed function block 2630 includes a geometry / fixed function pipeline 2636 that can be shared by all sub-cores in graphics processor 2600, for example, in lower performance and / or lower power graphics processor implementations. In at least one embodiment, geometry / fixed function pipeline 2636 includes a 3D fixed function pipeline, a video front-end unit, a thread spawner and thread dispatcher, and a unified return buffer manager, which manages unified return buffers.

[00367] In at least one embodiment fixed function block 2630 also includes a graphics SoC interface 2637, a graphics microcontroller 2638, and a media pipeline 2639. Graphics SoC interface 2637 provides an interface between graphics core 2600 and other processor cores within a system on a chip integrated circuit. In at least one embodiment, graphics microcontroller 2638 is a programmable sub-processor that is configurable to manage various functions of graphics processor 2600, including thread dispatch, scheduling, and pre-emption. In at least one embodiment, media pipeline 2639 includes logic to facilitate decoding, encoding, pre-processing, and / or post-processing of multimedia data, including image and video data. In at least one embodiment, media pipeline 2639 implement media operations via requests to compute or sampling logic within sub-cores 2601-2601F.

[00368] In at least one embodiment, SoC interface 2637 enables graphics core 2600 to communicate with general-purpose application processor cores (e.g., CPUs) and / or other components within an SoC, including memory hierarchy elements such as a shared last level cache memory, system RAM, and / or embedded on-chip or on-package DRAM. In at least one embodiment, SoC interface 2637 can also enable communication with fixed function devices within an SoC, such as camera imaging pipelines, and enables use of and / or implements global memory atomics that may be shared between graphics core 2600 and CPUs within an SoC. In at least one embodiment, SoC interface 2637 can also implement power management controls for graphics core 2600 and enable an interface between a clock domain of graphic core 2600 and other clock domains within an SoC. In at least one embodiment, SoC interface 2637 enables receipt of command buffers from a command streamer and global thread dispatcher that are configured to provide commands and instructions to each of one or more graphics cores within a graphics processor. In at least one embodiment, commands and instructions can be dispatched to media pipeline 2639, when media operations are to be performed, or a geometry and fixed function pipeline (e.g., geometry and fixed function pipeline 2636, geometry and fixed function pipeline 2614) when graphics processing operations are to be performed.

[00369] In at least one embodiment, graphics microcontroller 2638 can be configured to perform various scheduling and management tasks for graphics core 2600. In at least one embodiment, graphics microcontroller 2638 can perform graphics and / or compute workload scheduling on various graphics parallel engines within execution unit (EU) arrays 2602A-2602F, 2604A-2604F within sub-cores 2601A-2601F. In at least one embodiment, host software executing on a CPU core of an SoC including graphics core 2600 can submit workloads one of multiple graphic processor doorbells, which invokes a scheduling operation on an appropriate graphics engine. In at least one embodiment, scheduling operations include determining which workload to run next, submitting a workload to a command streamer, pre-empting existing workloads running on an engine, monitoring progress of a workload, and notifying host software when a workload is complete. In at least one embodiment, graphics microcontroller 2638 can also facilitate low-power or idle states for graphics core 2600, providing graphics core 2600 with an ability to save and restore registers within graphics core 2600 across low-power state transitions independently from an operating system and / or graphics driver software on a system.

[00370] In at least one embodiment, graphics core 2600 may have greater than or fewer than illustrated sub-cores 2601A-2601F, up to N modular sub-cores. For each set of N sub-cores, in at least one embodiment, graphics core 2600 can also include shared function logic 2610, shared and / or cache memory 2612, a geometry / fixed function pipeline 2614, as well as additional fixed function logic 2616 to accelerate various graphics and compute processing operations. In at least one embodiment, shared function logic 2610 can include logic units (e.g., sampler, math, and / or inter-thread communication logic) that can be shared by each N sub-cores within graphics core 2600. Shared and / or cache memory 2612 can be a last-level cache for N sub-cores 2601A-2601F within graphics core 2600 and can also serve as shared memory that is accessible by multiple sub-cores. In at least one embodiment, geometry / fixed function pipeline 2614 can be included instead of geometry / fixed function pipeline 2636 within fixed function block 2630 and can include same or similar logic units.

[00371] In at least one embodiment, graphics core 2600 includes additional fixed function logic 2616 that can include various fixed function acceleration logic for use by graphics core 2600. In at least one embodiment, additional fixed function logic 2616 includes an additional geometry pipeline for use in position only shading. In position-only shading, at least two geometry pipelines exist, whereas in a full geometry pipeline within geometry / fixed function pipeline 2616, 2636, and a cull pipeline, which is an additional geometry pipeline which may be included within additional fixed function logic 2616. In at least one embodiment, cull pipeline is a trimmed down version of a full geometry pipeline. In at least one embodiment, a full pipeline and a cull pipeline can execute different instances of an application, each instance having a separate context. In at least one embodiment, position only shading can hide long cull runs of discarded triangles, enabling shading to be completed earlier in some instances. For example, in at least one embodiment, cull pipeline logic within additional fixed function logic 2616 can execute position shaders in parallel with a main application and generally generates critical results faster than a full pipeline, as cull pipeline fetches and shades position attribute of vertices, without performing rasterization and rendering of pixels to a frame buffer. In at least one embodiment, cull pipeline can use generated critical results to compute visibility information for all triangles without regard to whether those triangles are culled. In at least one embodiment, full pipeline (which in this instance may be referred to as a replay pipeline) can consume visibility information to skip culled triangles to shade only visible triangles that are finally passed to a rasterization phase.

[00372] In at least one embodiment, additional fixed function logic 2616 can also include machine-learning acceleration logic, such as fixed function matrix multiplication logic, for implementations including optimizations for machine learning training or inferencing.

[00373] In at least one embodiment, within each graphics sub-core 2601A-2601F includes a set of execution resources that may be used to perform graphics, media, and compute operations in response to requests by graphics pipeline, media pipeline, or shader programs. In at least one embodiment, graphics sub-cores 2601A-2601F include multiple EU arrays 2602A-2602F, 2604A-2604F, thread dispatch and inter-thread communication (TD / IC) logic 2603A-2603F, a 3D (e.g., texture) sampler 2605A-2605F, a media sampler 2606A-2606F, a shader processor 2607A-2607F, and shared local memory (SLM) 2608A-2608F. EU arrays 2602A-2602F, 2604A-2604F each include multiple execution units, which are general-purpose graphics processing units capable of performing floating-point and integer / fixed-point logic operations in service of a graphics, media, or compute operation, including graphics, media, or compute shader programs. In at least one embodiment, TD / IC logic 2603A-2603F performs local thread dispatch and thread control operations for execution units within a sub-core and facilitate communication between threads executing on execution units of a sub-core. In at least one embodiment, 3D sampler 2605A-2605F can read texture or other 3D graphics related data into memory. In at least one embodiment, 3D sampler can read texture data differently based on a configured sample state and texture format associated with a given texture. In at least one embodiment, media sampler 2606A-2606F can perform similar read operations based on a type and format associated with media data. In at least one embodiment, each graphics sub-core 2601A-2601F can alternately include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each of sub-cores 2601A-2601F can make use of shared local memory 2608A-2608F within each sub-core, to enable threads executing within a thread group to execute using a common pool of on-chip memory.

[00374] FIGS. 27A-27B illustrate thread execution logic 2700 including an array of processing elements of a graphics processor core according to at least one embodiment. FIG. 27A illustrates at least one embodiment, in which thread execution logic 2700 is used. FIG. 27B illustrates exemplary internal details of an execution unit, according to at least one embodiment.

[00375] As illustrated in FIG. 27A, in at least one embodiment, thread execution logic 2700 includes a shader processor 2702, a thread dispatcher 2704, instruction cache 2706, a scalable execution unit array including a plurality of execution units 2708A-2708N, a sampler 2710, a data cache 2712, and a data port 2714. In at least one embodiment a scalable execution unit array can dynamically scale by enabling or disabling one or more execution units (e.g., any of execution unit 2708A, 2708B, 2708C, 2708D, through 2708N-1 and 2708N) based on computational requirements of a workload, for example. In at least one embodiment, scalable execution units are interconnected via an interconnect fabric that links to each of execution unit. In at least one embodiment, thread execution logic 2700 includes one or more connections to memory, such as system memory or cache memory, through one or more of instruction cache 2706, data port 2714, sampler 2710, and execution units 2708A-2708N. In at least one embodiment, each execution unit (e.g„ 2708A) is a stand-alone programmable general-purpose computational unit that is capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In at least one embodiment, array of execution units 2708A-2708N is scalable to include any number individual execution units.

[00376] In at least one embodiment, execution units 2708A-2708N are primarily used to execute shader programs. In at least one embodiment, shader processor 2702 can process various shader programs and dispatch execution threads associated with shader programs via a thread dispatcher 2704. In at least one embodiment, thread dispatcher 2704 includes logic to arbitrate thread initiation requests from graphics and media pipelines and instantiate requested threads on one or more execution units in execution units 2708A-2708N. For example, in at least one embodiment, a geometry pipeline can dispatch vertex, tessellation, or geometry shaders to thread execution logic for processing. In at least one embodiment, thread dispatcher 2704 can also process runtime thread spawning requests from executing shader programs.

[00377] In at least one embodiment, execution units 2708A-2708N support an instruction set that includes native support for many standard 3D graphics shader instructions, such that shader programs from graphics libraries (e.g., Direct 3D and OpenGL) are executed with a minimal translation. In at least one embodiment, execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders) and general-purpose processing (e.g., compute and media shaders). In at least one embodiment, each of execution units 2708A-2708N, which include one or more arithmetic logic units (ALUs), is capable of multi-issue single instruction multiple data (SIMD) execution and multi-threaded operation enables an efficient execution environment despite higher latency memory accesses. In at least one embodiment, each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread-state. In at least one embodiment, execution is multi-issue per clock to pipelines capable of integer, single and double precision floating point operations, SIMD branch capability, logical operations, transcendental operations, and other miscellaneous operations. In at least one embodiment, while waiting for data from memory or one of shared functions, dependency logic within execution units 2708A-2708N causes a waiting thread to sleep until requested data has been returned. In at least one embodiment, while a waiting thread is sleeping, hardware resources may be devoted to processing other threads. For example, in at least one embodiment, during a delay associated with a vertex shader operation, an execution unit can perform operations for a pixel shader, fragment shader, or another type of shader program, including a different vertex shader.

[00378] In at least one embodiment, each execution unit in execution units 2708A-2708N operates on arrays of data elements. In at least one embodiment, a number of data elements is “execution size," or number of channels for an instruction. In at least one embodiment, an execution channel is a logical unit of execution for data element access, masking, and flow control within instructions. In at least one embodiment, a number of channels may be independent of a number of physical Arithmetic Logic Units (ALUs) or Floating Point Units (FPUs) for a particular graphics processor. In at least one embodiment, execution units 2708A-2708N support integer and floating-point data types.

[00379] In at least one embodiment, an execution unit instruction set includes SIMD instructions. In at least one embodiment, various data elements can be stored as a packed data type in a register and execution unit will process various elements based on data size of elements. For example, in at least one embodiment, when operating on a 256-bit wide vector, 256 bits of a vector are stored in a register and an execution unit operates on a vector as four separate 64-bit packed data elements (Quad-Word (QW) size data elements), eight separate 32-bit packed data elements (Double Word (DW) size data elements), sixteen separate 16-bit packed data elements (Word (W) size data elements), or thirty-two separate 8-bit data elements (byte (B) size data elements). However, in at least one embodiment, different vector widths and register sizes are possible.

[00380] In at least one embodiment, one or more execution units can be combined into a fused execution unit 2709A-2709N having thread control logic (2707A-2707N) that is common to fused EUs. In at least one embodiment, multiple EUs can be fused into an EU group. In at least one embodiment, each EU in fused EU group can be configured to execute a separate SIMD hardware thread. Number of EUs in a fused EU group can vary according to various embodiments. In at least one embodiment, various SIMD widths can be performed per-EU, including but not limited to SIMD8, SIMD 16, and SIMD32. In at least one embodiment, each fused graphics execution unit 2709A-2709N includes at least two execution units. For example, in at least one embodiment, fused execution unit 2709A includes a first EU 2708A, second EU 2708B, and thread control logic 2707A that is common to first EU 2708A and second EU 2708B. In at least one embodiment, thread control logic 2707A controls threads executed on fused graphics execution unit 2709A, allowing each EU within fused execution units 2709A-2709N to execute using a common instruction pointer register.

[00381] In at least one embodiment, one or more internal instruction caches (e.g„ 2706) are included in thread execution logic 2700 to cache thread instructions for execution units. In at least one embodiment, one or more data caches (e.g„ 2712) are included to cache thread data during thread execution. In at least one embodiment, a sampler 2710 is included to provide texture sampling for 3D operations and media sampling for media operations. In at least one embodiment, sampler 2710 includes specialized texture or media sampling functionality to process texture or media data during sampling process before providing sampled data to an execution unit.

[00382] During execution, in at least one embodiment, graphics and media pipelines send thread initiation requests to thread execution logic 2700 via thread spawning and dispatch logic. In at least one embodiment, once a group of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g„ pixel shader logic, fragment shader logic, etc.) within shader processor 2702 is invoked to further compute output information and cause results to be written to output surfaces (e.g„ color buffers, depth buffers, stencil buffers, etc.). In at least one embodiment, a pixel shader or fragment shader calculates values of various vertex attributes that are to be interpolated across a rasterized object. In at least one embodiment, pixel processor logic within shader processor 2702 then executes an application programming interface (API)-supplied pixel or fragment shader program. In at least one embodiment, to execute a shader program, shader processor 2702 dispatches threads to an execution unit (e.g., 2708A) via thread dispatcher 2704. In at least one embodiment, shader processor 2702 uses texture sampling logic in sampler 2710 to access texture data in texture maps stored in memory. In at least one embodiment, arithmetic operations on texture data and input geometry data compute pixel color data for each geometric fragment, or discards one or more pixels from further processing.

[00383] In at least one embodiment, data port 2714 provides a memory access mechanism for thread execution logic 2700 to output processed data to memory for further processing on a graphics processor output pipeline. In at least one embodiment, data port 2714 includes or couples to one or more cache memories (e.g., data cache 2712) to cache data for memory access via a data port.

[00384] As illustrated in FIG. 27B, in at least one embodiment, a graphics execution unit 2708 can include an instruction fetch unit 2737, a general register file array (GRF) 2724, an architectural register file array (ARF) 2726, a thread arbiter 2722, a send unit 2730, a branch unit 2732, a set of SIMD floating point units (FPUs) 2734, and In at least one embodiment a set of dedicated integer SIMD ALUs 2735. In at least one embodiment, GRF 2724 and ARF 2726 includes a set of general register files and architecture register files associated with each simultaneous hardware thread that may be active in graphics execution unit 2708. In at least one embodiment, per thread architectural state is maintained in ARF 2726, while data used during thread execution is stored in GRF 2724. In at least one embodiment, execution state of each thread, including instruction pointers for each thread, can be held in thread-specific registers in ARF 2726.

[00385] In at least one embodiment, graphics execution unit 2708 has an architecture that is a combination of Simultaneous Multi-Threading (SMT) and fine-grained Interleaved MultiThreading (IMT). In at least one embodiment, architecture has a modular configuration that can be fine-tuned at design time based on a target number of simultaneous threads and number of registers per execution unit, where execution unit resources are divided across logic used to execute multiple simultaneous threads.

[00386] In at least one embodiment, graphics execution unit 2708 can co-issue multiple instructions, which may each be different instructions. In at least one embodiment, thread arbiter 2722 of graphics execution unit thread 2708 can dispatch instructions to one of send unit 2730, branch unit 2742, or SIMD FPU(s) 2734 for execution. In at least one embodiment, each execution thread can access 128 general-purpose registers within GRF 2724, where each register can store 32 bytes, accessible as a SIMD 8-element vector of 32-bit data elements. In at least one embodiment, each execution unit thread has access to 4 Kbytes within GRF 2724, although embodiments are not so limited, and greater or fewer register resources may be provided in other embodiments. In at least one embodiment, up to seven threads can execute simultaneously, although a number of threads per execution unit can also vary according to embodiments. In at least one embodiment, in which seven threads may access 4 Kbytes, GRF 2724 can store a total of 28 Kbytes. In at least one embodiment, flexible addressing modes can permit registers to be addressed together to build effectively wider registers or to represent strided rectangular block data structures.

[00387] In at least one embodiment, memory operations, sampler operations, and other longer-latency system communications are dispatched via "send" instructions that are executed by message passing send unit 2730. In at least one embodiment, branch instructions are dispatched to a dedicated branch unit 2732 to facilitate SIMD divergence and eventual convergence.

[00388] In at least one embodiment graphics execution unit 2708 includes one or more SIMD floating point units (FPU(s)) 2734 to perform floating-point operations. In at least one embodiment, FPU(s) 2734 also support integer computation. In at least one embodiment FPU(s) 2734 can SIMD execute up to M number of 32-bit floating-point (or integer) operations, or SIMD execute up to 2M 16-bit integer or 16-bit floating-point operations. In at least one embodiment, at least one of FPU(s) provides extended math capability to support high-throughput transcendental math functions and double precision 64-bit floating-point. In at least one embodiment, a set of 8-bit integer SIMD ALUs 2735 are also present, and may be specifically optimized to perform operations associated with machine learning computations.

[00389] In at least one embodiment, arrays of multiple instances of graphics execution unit 2708 can be instantiated in a graphics sub-core grouping (e.g„ a sub-slice). In at least one embodiment execution unit 2708 can execute instructions across a plurality of execution channels. In at least one embodiment, each thread executed on graphics execution unit 2708 is executed on a different channel.

[00390] In at least one embodiment, arrays of multiple instances of graphics execution unit 2708 can be instantiated in a graphics sub-core grouping (e.g„ a sub-slice) 504 to perform signal processing operations.

[00391] FIG. 28 illustrates a parallel processing unit (“PPU”) 2800, according to at least one embodiment. In at least one embodiment, PPU 2800 is configured with machine-readable code that, if executed by PPU 2800, causes PPU 2800 to perform some or all of processes and techniques described throughout this disclosure. In at least one embodiment, PPU 2800 is a multi-threaded processor that is implemented on one or more integrated circuit devices and that utilizes multithreading as a latency-hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simply instructions) on multiple threads in parallel. In at least one embodiment, a thread refers to a thread of execution and is an instantiation of a set of instructions configured to be executed by PPU 2800. In at least one embodiment, PPU 2800 is a graphics processing unit (“GPU”) configured to implement a graphics rendering pipeline for processing three-dimensional (“3D”) graphics data in order to generate two-dimensional (“2D”) image data for display on a display device such as a liquid crystal display (“UCD”) device. In at least one embodiment, PPU 2800 is utilized to perform computations such as linear algebra operations and machine-learning operations. FIG. 28 illustrates an example parallel processor for illustrative purposes only and should be construed as a non-limiting example of processor architectures contemplated within scope of this disclosure and that any suitable processor may be employed to supplement and / or substitute for same.

[00392] In at least one embodiment, one or more PPUs 2800 are configured to accelerate High Performance Computing (“HPC”), data center, and machine learning applications. In at least one embodiment, PPU 2800 is configured to accelerate deep learning systems and applications including following non-limiting examples: autonomous vehicle platforms, deep learning, high- accuracy speech, image, text recognition systems, intelligent video analytics, molecular simulations, drug discovery, disease diagnosis, weather forecasting, big data analytics, astronomy, molecular dynamics simulation, financial modeling, robotics, factory automation, real-time language translation, online search optimizations, and personalized user recommendations, and more.

[00393] In at least one embodiment, PPU 2800 includes, without limitation, an Input / Output (“I / O”) unit 2806, a front-end unit 2810, a scheduler unit 2812, a work distribution unit 2814, a hub 2816, a crossbar (“Xbar”) 2820, one or more general processing clusters (“GPCs”) 2818, and one or more partition units (“memory partition units”) 2822. In at least one embodiment, PPU 2800 is connected to a host processor or other PPUs 2800 via one or more high-speed GPU interconnects (“GPU interconnects”) 2808. In at least one embodiment, PPU 2800 is connected to a host processor or other peripheral devices via an interconnect 2802. In at least one embodiment, PPU 2800 is connected to a local memory comprising one or more memory devices (“memory”) 2804. In at least one embodiment, memory devices 2804 include, without limitation, one or more dynamic random access memory (“DRAM”) devices. In at least one embodiment, one or more DRAM devices are configured and / or configurable as high-bandwidth memory (“HBM”) subsystems, with multiple DRAM dies stacked within each device.

[00394] In at least one embodiment, high-speed GPU interconnect 2808 may refer to a wirebased multi-lane communications link that is used by systems to scale and include one or more PPUs 2800 combined with one or more central processing units (“CPUs”), supports cache coherence between PPUs 2800 and CPUs, and CPU mastering. In at least one embodiment, data and / or commands are transmitted by high-speed GPU interconnect 2808 through hub 2816 to / from other units of PPU 2800 such as one or more copy engines, video encoders, video decoders, power management units, and other components which may not be explicitly illustrated in FIG. 28.

[00395] In at least one embodiment, I / O unit 2806 is configured to transmit and receive communications (e.g., commands, data) from a host processor (not illustrated in FIG. 28) over system bus 2802. In at least one embodiment, I / O unit 2806 communicates with host processor directly via system bus 2802 or through one or more intermediate devices such as a memory bridge. In at least one embodiment, I / O unit 2806 may communicate with one or more other processors, such as one or more of PPUs 2800 via system bus 2802. In at least one embodiment, I / O unit 2806 implements a Peripheral Component Interconnect Express (“PCIe”) interface for communications over a PCIe bus. In at least one embodiment, I / O unit 2806 implements interfaces for communicating with external devices.

[00396] In at least one embodiment, VO unit 2806 decodes packets received via system bus 2802. In at least one embodiment, at least some packets represent commands configured to cause PPU 2800 to perform various operations. In at least one embodiment, I / O unit 2806 transmits decoded commands to various other units of PPU 2800 as specified by commands. In at least one embodiment, commands are transmitted to front-end unit 2810 and / or transmitted to hub 2816 or other units of PPU 2800 such as one or more copy engines, a video encoder, a video decoder, a power management unit, etc. (not explicitly illustrated in FIG. 28). In at least one embodiment, I / O unit 2806 is configured to route communications between and among various logical units of PPU 2800.

[00397] In at least one embodiment, a program executed by host processor encodes a command stream in a buffer that provides workloads to PPU 2800 for processing. In at least one embodiment, a workload comprises instructions and data to be processed by those instructions. In at least one embodiment, buffer is a region in a memory that is accessible (e.g., read / write) by both host processor and PPU 2800 — a host interface unit may be configured to access buffer in a system memory connected to system bus 2802 via memory requests transmitted over system bus 2802 by I / O unit 2806. In at least one embodiment, host processor writes command stream to buffer and then transmits a pointer to start of command stream to PPU 2800 such that frontend unit 2810 receives pointers to one or more command streams and manages one or more command streams, reading commands from command streams and forwarding commands to various units of PPU 2800.

[00398] In at least one embodiment, front-end unit 2810 is coupled to scheduler unit 2812 that configures various GPCs 2818 to process tasks defined by one or more command streams. In at least one embodiment, scheduler unit 2812 is configured to track state information related to various tasks managed by scheduler unit 2812 where state information may indicate which of GPCs 2818 a task is assigned to, whether task is active or inactive, a priority level associated with task, and so forth. In at least one embodiment, scheduler unit 2812 manages execution of a plurality of tasks on one or more of GPCs 2818.

[00399] In at least one embodiment, scheduler unit 2812 is coupled to work distribution unit 2814 that is configured to dispatch tasks for execution on GPCs 2818. In at least one embodiment, work distribution unit 2814 tracks a number of scheduled tasks received from scheduler unit 2812 and work distribution unit 2814 manages a pending task pool and an active task pool for each of GPCs 2818. In at least one embodiment, pending task pool comprises a number of slots (e.g., 32 slots) that contain tasks assigned to be processed by a particular GPC 2818; active task pool may comprise a number of slots (e.g., 4 slots) for tasks that are actively being processed by GPCs 2818 such that as one of GPCs 2818 completes execution of a task, that task is evicted from active task pool for GPC 2818 and one of other tasks from pending task pool is selected and scheduled for execution on GPC 2818. In at least one embodiment, if an active task is idle on GPC 2818, such as while waiting for a data dependency to be resolved, then active task is evicted from GPC 2818 and returned to pending task pool while another task in pending task pool is selected and scheduled for execution on GPC 2818.

[00400] In at least one embodiment, work distribution unit 2814 communicates with one or more GPCs 2818 via XBar 2820. In at least one embodiment, XBar 2820 is an interconnect network that couples many of units of PPU 2800 to other units of PPU 2800 and can be configured to couple work distribution unit 2814 to a particular GPC 2818. In at least one embodiment, one or more other units of PPU 2800 may also be connected to XBar 2820 via hub 2816.

[00401] In at least one embodiment, tasks are managed by scheduler unit 2812 and dispatched to one of GPCs 2818 by work distribution unit 2814. GPC 2818 is configured to process task and generate results. In at least one embodiment, results may be consumed by other tasks within GPC 2818, routed to a different GPC 2818 via XBar 2820, or stored in me...

Claims

What is ciainied is:

1. A processor comprising:one or more circuits to encode or decode fifth generation (5G) new radio signals based, at least in part, on two or more kernels to be performed in parallel, wherein the processor is10 configured to send the 5G new radio signals directly to one or more network interface controllers, and wherein the processor is configured to receive the 5G new radio signals directly from one or more network interface controllers,2. The processor of claim 1, wherein the one or more circuits are to encode or decode the 5G new' radio signals by performing one or more physical layer steps, where the one or more15 physical layer steps are partially performed by one or more parallel processing units and partially performed by a central processing unit.

3. The processor of claim 1, wherein encoding the 5G new radio signals comprises launching the two or more kernels to perform one or more signal processing blocks.

4. The processor of claim 3, wherein the one or more signal processing blocks are physical20 uplink shared channel (PUSCH) signal processing blocks.

5. The processor of claim 3, wherein the one or more signal processing blocks are physical downlink shared channel (PDSCH) signal processing blocks.

6. The processor of claim 1, wherein the two or more kernels are performed on graphics processing units.25 7. A system comprising:one or more processors to encode or decode fifth generation (5G) new radio signals based, at least in part, on two or more kernels per processor to be performed in parallel, wherein the one or more processors are configured to send the 5G new' radio signals directly to one or more network interface controllers, and wherein the one or more processors are configured to30 receive the 5G new radio signals directly from one or more network interface controllers.22 07 2522 07 258. The system of claim 7, wherein encoding or decoding 5<3 signals comprises performing physical layer operations using software instructions executed partially by one or more parallel processing units.

9. The system of claim 8, wherein the software instructions executed by the one or more 35 parallel processing units are controlled by additional instructions being executed by a central processing unit.

10. The system of claim 8, wherein the physical layer operations are performed by launching parallel processing unit functions from a CPU host.

11. The system of claim 7, wherein the encoding or decoding of 5(3 signals are of a 5G 40 physical layer and performed in response to an application programming call from a different layer than the physical layer.

12. The system of claim 7, wherein the one or more processors include one or more graphics processing units.

13. A machine-readable medium having stored thereon a set of instructions, which if45 performed by one or more processors, cause the one or more processors to at least:encode or decode fifth generation (5G) new radio signals based, at least in part, on two or more kernels per processor to be performed in parallel, wherein the one or more processors are configured to send 5G new radio signals directly to one or more network interface controllers, and wherein the one or more processors are configured to receive 5G new radio signals directly50 from one or more network interface controllers.

14. The machine-readable medium of claim 13, wherein the instructions, if performed, further cause the one or more processors to perform one or more physical layer steps to encode or decode the 5G new' radio signals, where the one or more physical layer steps are partially performed by one or more parallel processing units and partially performed by a central55 processing unit.22 07 2515. The machine-readable medium of claim 13, wherein encoding or decoding the 5Gnew radio signals comprises launching the two or more kernels to perform one or more signal processing blocks on one or more parallel processing units.

16. The machine-readable medium of claim 15, wherein the one or more signal processing 60 blocks are physical uplink shared channel (PUSCH) signal processing blocks.

17. The machine-readable medium of claim 15, wherein the one or more signal processing blocks are physical downlink shared channel (PDSCH) signal processing blocks.

18. The machine-readable medium of claim 13, wherein encoding the 5G new radio signals is performed by launching at least one of: a physical uplink shared channel (PUSCH) beamforming 65 kernel, a PUSCH front-end kernel, a PUSCH de-rate-matching kernel, a PUSCH low densityparity check (LDPC) kernel, or a cyclic redundancy check (CRC) kernel.

19. The machine-readable medium of claim 13, wherein decoding the 5G new radio signals is performed by launching at least one of: a physical downlink shared channel (PDSCH) beamforming kernel, a PDSCH rate matching kernel, a PDSCH low density parity check (LDPC) 70 kernel, or a cyclic redundancy check (CRC) kernel.

20. A method, comprising:performing encoding or decoding of fifth generation (5G) new radio signals based, at least in part, on two or more kernels to be performed in parallel by one or more circuits on a processor, wherein one or more signals for 5G signal processing are received by the processor75 directly from one or more network interface controllers, and wherein the processor is configured to send the one or more signals for 5G signal processing directly to one or more network interface controllers.

21. The method of claim 20, where the encoding or decoding of 5G signals further compriseperforming physical layer operations using software functions executed by one or more parallel 80 processing units.

22. The method of claim 21, wherein the software functions executed by the one or more parallel processing units are controlled by a central processing unit.

23. The method of claim 21, wherein the software functions implement one or more signal processing operation of the physical layer.85 24. The method of claim 23, wherein the one or more encoding operations are physicaluplink shared channel (PUSCH) signal processing operations.

25. The method of claim 23, wherein the one or more decoding operations are physical downlink shared channel (PDSCH) signal processing operations.

26. The method of claim 20, wherein the two or more kernels are performed on graphics 90 processing units.22 07 25

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