Charged particle trap apparatus

Abstract

A charged particle trap apparatus comprises: a set of electrodes 6 for generating electric fields for manipulating charged particles; a voltage source 44 having an output; and a demultiplexer 132 havi

Description

Field The present invention relates to a charged particle trap apparatus, such as a trapped 5 charged particle quantum computer. Background Trapped-ion qubits are one of the most promising approaches to quantum computing. One of the advantages of using trapped-ion qubits is flexible connectivity. Specifically, io qubit routing (that is, changing which qubit is coupled to which other qubits) can be accomplished by physically moving ions in space. This ability, combined with excellent coherence times, allows qubit routing with negligible errors even at large scales. Flexible qubit routing is the basis of the quantum charge-coupled device (QCCD) architecture, and is one of the reasons why trapped-ion systems allow for high quantum 15 volumes. Reference is made to D. Kielpinski, C. Monroe, and D. J. Wineland, Nature 417, 709 (2002), number: 6890. Flexible connectivity, however, comes at a cost. Fast, low-heating ion transport uses precise dynamical control of voltages on many electrodes. 20 Figure 1 illustrates an approach to electrical wiring of trapped-ion quantum computers, for example, as described in J. M. Pino, J. M. Dreiling, C. Figgatt, J. P. Gaebler, S. A. Moses, M. S. Allman, C. H. Baldwin, M. Foss-Feig, D. Hayes, K. Mayer, C. Ryan-Anderson, and B. Neyenhuis, Nature 592, 209 (2021), arXiv:2OO3.01293 [quantph] and 25 V. Kaushal, B. Lekitsch, A. Stahl, J. Hilder, D. Pijn, C. Schmiegelow, A. Bermudez, M. Muller, F. Schmidt-Kaier, and U. Poschinger, “Shuttling-Based Trapped-Ion Quantum Information Processing,” (2019), arXiv: 1912.04712 [quant-ph]. This approach uses about ten electrodes per ion or qubit, each wired to a separate DAC outside of the vacuum system. This approach is not scalable with system size. For example, a 1,000-30 qubit chip would require approximately 10,000 analog input lines. Developing a reliable DAC-to-chip interface at this scale would be a major challenge in itself. One solution that has been proposed and experimentally investigated is to form an integrated quantum processing unit (QPU), which combines an ion trap chip with 35 digital to analogue converters (DACs) and reference is made to N. D. Guise, S. D. Fallek, H. Hayden, C.-S. Pai, C. Volin, K. R. Brown, J. T. Merrill, A. W. Harter, J. M. Amini, L. 06 05 25 M. Lust, K. Muldoon, D. Carlson, and J. Budach, Review of Scientific Instruments 85, 063101 (2014), arXiv: 1403.3662 [physics, physics :quant-ph]. Integration can be either monolithic, or achieved by packaging together several independently fabricated chips, for example, as described in R. Mahajan, Z. Qian, R. S. Viswanath, S. Srinivasan, K. 5 Aygiin, W.-L. Jen, S. Sharan, and A. Dhall, “Embedded Multidie Interconnect Bridge -A Localized, High-Density Multichip Packaging Interconnect” IEEE Transactions on Components, Packaging and Manufacturing Technology 9,1952 (2019), conference Name: IEEE Transactions on Components, Packaging and Manufacturing Technology. 10 DAC integration, however, comes with several major challenges. The first is power dissipation. Compact cryogenic DACs have been developed with power consumption of 30 mW per channel, or 300 W power for 1,000 qubits. While this can be optimised, DAC power dissipation presents significant challenges on the 15 cryogenic system and thermal interfaces. Second, DAC control requires streaming large volumes of data to the QPU. For example, in V. Kaushal ibid., each DAC require 5 MB / s of data input. For a 1000-qubit QPU, this corresponds to about 50 GB / s of data flow between the DAC and the 20 controller. Designing an appropriate interface would not be trivial, and in practice would require integration of further electronics, for example, for waveform, compression, or the controller itself. Thirdly, an integrated DAC typically occupies a much larger chip area than the 25 electrode itself. For example, J. Stuart, R. Panock, C. D. Bruzewicz, J. A. Sedlacek, R. McConnell, I. L. Chuang, J. M. Sage, and J. Chiaverini, Physical Review Applied 11, 024010 (2019), arXiv: 1810.07152 [physics, physics:quant-ph] describes a single, unfiltered DAC block with an area of 130 pm x 270 pm. A lower noise controller is likely to have an even larger footprint, especially to accommodate integrated filters. 30 Developing low-noise voltage sources areas comparable to top layer electrodes (for example, around 50 pm x 50 pm) is a challenge in itself. 06 05 25 Summary According to a first aspect of the present invention there is provided apparatus comprising a charged particle trap. The charged particle trap includes a set of electrodes for generating electric fields for manipulating charged particles. The 5 apparatus comprises a voltage source having an output and a demultiplexer having an input and a plurality of outputs, wherein the output of the voltage source is coupled to the input of the demultiplexer, and each of the plurality of outputs of the demultiplexer are coupled to a respective one of the set of electrodes. The demultiplexer is configured, in a first phase, to charge the electrodes by sequentially connecting each io electrode to the voltage source and, in a second phase, to disconnect the voltage source from the electrodes for a given time for providing a lower noise environment in which operations can be performed on the charge particles. Using a demultiplexer can allow significantly fewer voltage sources to be used, while 15 arranging for the demultiplexer to be disconnected can help to reduce or even avoid introducing noise resulting from using the demultiplexer. The electrodes in the set of electrodes can be used to compensate for local stray fields. The apparatus may further comprise at least one further electrode coupled to the 20 demultiplexer, wherein the demultiplexer is configured, in the second phase, to connect the at least one further electrode to the voltage source. The apparatus may further comprise a set of capacitors, wherein each electrode in the set of electrodes is provided with a respective capacitor arranged between the electrode 25 and ground. The apparatus may comprise a charged particle trap chip, supporting the charged particle trap, wherein the capacitors are monolithically integrated on the charged particle trap chip. The apparatus may comprise a charged particle trap chip, 30 supporting the charged particle trap and at least one further chip stacked on the charged particle trap chip, wherein the capacitors are integrated into the at least one further chip. The voltage source may be integrated on the charged particle trap chip or the at least one further chip. 35 The given time may be sufficient to perform a series of at least one quantum gates. Thus, the given time may be between i ps and i s. 06 05 25 The given time may be sufficient to transport at least one charged particle from a first arrangement of charged particles to a second, different arrangement of charged particles. Thus, the given time may be between i ms and 500 ms (for example, in the 5 case where charged particles are transported between quantum gates) or between 1 ps ms and 1,800 s (for example, in cases where the apparatus is not used for quantum gates). The given time may be between 60 s and 1,000 s. Each electrode may be layer-like having a thickness, and wherein each electrode may 10 have at least one dimension perpendicular to the thickness between 10 pm and 2,000 pm. The apparatus may further comprise a shim controller, wherein the shim controller is configured to cause charging of the electrodes in the set of electrodes. The shim 15 controller may be configured to cause charging of the electrodes in the set of electrodes to respective levels appropriate to compensate for stay electric fields. The shim controller may be a classical computer system, such as a desktop computer, comprising at least one processor and memory. 20 The apparatus may be a quantum computer. The apparatus may be an atomic clock. According to a second aspect of the present invention there is provided a system comprising the apparatus and a cryogenic system for cooling at least the charged particle trap. 25 According to a third aspect of the present invention there is provided a method of operating the apparatus the method comprising, causing, in a first phase, the demultiplexer to charge the electrodes by sequentially connecting each electrode to the voltage source and causing, in a second phase, demultiplexer to disconnect the voltage 30 source from the electrodes for a given time for providing a lower noise environment in which operations can be performed on the charge particles. 06 05 25 Brief Description of the Drawings Certain embodiments of the present invention will now be described, by way of example, with reference to Figures 2 to 19 of the accompanying drawings, in which: Figure 1 schematically illustrates electrical wiring of trapped-ion quantum computers; 5 Figure 2 schematically illustrates electrical wiring of a trapped-ion quantum computer employing a switch network and a demultiplexing network and using dynamic electrodes and shim electrodes; Figure 3 schematically illustrates an array of electrodes which can be configured to provide electrodes of different shapes and / or for different purposes; 10 Figure 4 schematically illustrates a charged particle above an electrode; Figure 5A schematically illustrates a first, simple parallel control arrangement; Figure 5B schematically illustrates a second, simple parallel control arrangement; Figure 5C schematically illustrates a third, more complex parallel control arrangement; Figure 5D schematically illustrates a fourth, more complex parallel control 15 arrangement; Figure 5E schematically illustrates a fifth, more complex parallel control arrangement; Figure 6A schematically illustrates before and after a so-called “switchable swap” involving two qubits in neighbouring zones; Figure 6B schematically illustrates a parallel odd swap in a linear one-dimensional 20 qubit array in which qubits in six of the eight zones undergo swap operations, while qubits in two zones remain stationary; Figure 7 schematically illustrates two-dimensional ion swaps in a 4x4 ion trap; Figure 8A schematically illustrates one-dimensional physical swap for two neighbouring qubits in a one-dimensional trap or in a two-dimensional trap segment 25 without junctions between the qubits; Figure 8B schematically illustrates a two-dimensional physical swap for two neighbouring qubits sharing a junction; Figure 9 schematically illustrates an extended 1D swap waveform; Figure 10 schematically illustrates single-switch implementation of parallel digital 30 control; Figure 11A schematically illustrates a switch system for controlling a dynamic electrode; Figure 11B is a circuit schematic showings implementation of an SPDT switch in eth system shown in Figure 8A using two transistors in a pass configuration; Figure 11C is a circuit schematic showings implementation of an SPDT switch in eth 35 system shown in Figure 8A using two transmission gates; Figure 12 schematically illustrates multi-switch implementation of parallel dynamic control; Figure 13 schematically illustrates two-dimensional trap with four qubits per junction; Figures 14A and 14B shows plots of reconfiguration time and number of time steps and 5 of associated memory error, in a worst-case scenario, for reconfiguring a two-dimensional trap array of qubits in a so-called “optimal configuration” assuming swap time of t0 = too ps; Figure 15 schematically illustrates an example of an architecture of shim demultiplexing in which shim electrodes are connected one-by-one to voltage sources 10 via demultiplexers; Figure 16 schematically illustrates an analog shim demultiplexer based on a multi-stage network of switches; Figure ^schematically illustrates a hybrid shim demultiplexer implementation; Figures 18A to 18E schematically illustrate different methods of implementing single-15 qubit and multi-qubit quantum gates; and Figure 19 schematically illustrates an example of electrical wiring of a 1,000-qubit chip in which a quantum processing unit requires only about 200 electrical inputs to control 1,000 qubits. 06 05 25 Detailed Description of Certain Embodiments I. Introduction Embodiments of ion trap wiring approaches are herein described which allow fast and arbitrary qubit routing with low number of control lines. As an example, a 1000-qubit 5 chip is demonstrated which can be controlled with about 200 input lines and minimal on-chip power dissipation. In a quantum charge-coupled device (QCCD), electrodes can serve two different purposes. The first is dynamic, namely to deliver time-varying waveforms which 10 execute the desired transport primitives, such as shuttling, merging, splitting or crystal rotations. The second is quasi-static, namely to compensate stray electric fields, generated for example by local charges. Typically, each electrode serves both purposes. In the approach herein described, each electrode is explicitly assigned to be either dynamic or quasi-static. 15 Two techniques are employed, namely (1) dynamic electrode parallelisation wherein dynamic electrodes are co-wired to a fixed number of voltage sources assigned potentially through integrated switches, and (2) quasi-static electrode demultiplexing wherein quasi-static electrodes (herein referred to as “shim electrodes”) are controlled 20 through a small number of voltage sources through integrated demultiplexers. The voltage sources may include or take the form of digital-to-analog converters (DACs). In the approaches herein described, instead of voltage source integration, switch integration is used. Unlike voltage sources, switches and demultiplexers require very 25 small data input rates, and can be operated with negligible power dissipation. Furthermore, switches and demultiplexers are relatively simple structures, made of a small number of transistors and inverters. Thus, they can be readily fabricated in a CMOS process, and can be cryogenically compatible. 30 In the approaches herein described, dynamic operations are massively parallelised across the processor. This decreases operation flexibility, but significantly eases the control requirements. As will be explained hereinafter, instead of needing about 10 voltage sources per qubit, about too of these voltage sources suffice regardless of the processor size. Shim electrodes require local voltage tuning, so they cannot be driven in 35 parallel. However, since they do not require dynamic tuning, an electrode can be set to the target voltage and then disconnected from the voltage source. This allows one 06 05 25 voltage source to serve multiple shim electrodes. As will be explained in more detail hereinafter, one voltage source should suffice to serve in the region of too to 1000 electrodes. Thus, at 2 to io shim electrodes per qubit, the approach allows for about io to 500 qubits per voltage source. 5 Referring to Figure 2, a quantum computing system 1 is shown which incorporates a chip wiring architecture. The quantum computing system 1 comprises a QPU 2 which includes an A^-qubit ion io trap 3 comprising dynamic electrodes 4 (or “dynamic electrodes”), rf electrodes 5 and quasi-static electrodes 6 (or “shim electrodes”) for controlling charged particles 7 which in this case take the form of ions, such as 43Ca+ ions. The charged particles may, however, take the form of atoms or molecules, each with a net electric charge, electrons or positrons. 15 The electrodes 4,5, 6 are generally supported on a principal surface 8 of a substrate 9. However, at least some of the electrodes maybe buried and, as will be explained in more detail later, components such as capacitors, switches (formed by transistors), and interconnects may be buried. 20 In this example, the dynamic electrodes 4 run in pairs in rows 10 along central axis 11 and singly in columns 12 crossing the rows 10. The rf electrodes 5 run along outer edges of the rows 8 and the quasi-static electrodes 6 run along the outer edges of the rf electrodes 6. 25 The electrodes 4,5, 6 may have other different configurations. For example, the dynamic electrodes 4 need not be formed between the rf electrodes 5 and the quasi-static electrodes 6. The electrodes 4,5, 6 need not be rectangular and need not be the same shape. 30 Referring to Figure 3, the electrodes 4,5, 6 may be provided by an array 13 of blank electrodes 14 and the function of each electrode 14 is defined or programmed by control electronics. 35 Referring also to Figure 4, the trap 3 is configured to hold charged particles 7 at a height h above the surface 15 of the trap 3. Electrodes 4 used for the transporting 06 05 25 charged particles 7 (such as the dynamic electrodes 4) may have a lateral dimension di, d2 (such as width or length) which is approximately the same as the height h. The height h may be, for example, between 5 pm to 2 mm, or between 10 pm and 200 pm. Thus, the electrodes 4 may have a width di of between 5 pm to 2 mm, or between 10 pm 5 and 200 pm. Referring again to Figure 2, the QPU 3 includes a switch / demultiplexing network 21 comprising a switch network 22 which comprises a plurality of switches 23 and switch lines 24, and a demultiplexing network 25 which comprises a plurality of demultiplexes 10 26 and demux lines 27. A transport controller 31, in the form of a computer system, receives qubit permutation and outputs transport control signals to transport voltage sources 34, for example, comprising digital-to-analog converters (DACs), which generate signals which are 15 provided to first transport control lines 36. The first transport control lines 36 are provided with corresponding filters 37 and filtered signals are provided to second transport control lines 38 which are coupled to the switch network 22. A shim controller 41, in the form of a computer system, receives calibration data and 20 outputs control signals to shim voltage sources 44, for example, comprising DACs 44, which generate signals which are provided to shim control lines 46. In this example, for transport control, there are about iOjV which lines (where N is the number of qubits, in this case, about 1,000), 100 transport DACs 34, about 100 first 25 transport control lines 36, about 100 filters 37, about 100 second transport lines 39, and for shim control, there are between 3^ and IOjV demux lines 27, between (A7300) and (A710) shim DACs 44 and between (A7300) and (A710) shim control lines 46. The trap 3 and optionally some other parts of the system 1 may be housed in a 30 cryogenic refrigerator (not shown) for cooling the trap 3 to a suitably low temperature T (e.g., below 77 K or 4.2 K). The trap 3 may be housed in a vacuum chamber (not shown), which provides an ultra-high vacuum environment allowing individual charged particles to be isolated. 35 Herein, the term “qubits” tends to be used rather than “ions”. Thus, when referring to a physically movement of a qubit, for example, “a qubit is moved around”, this physically 06 05 25 corresponds to shuttling one or more ions that encode that qubit, as well as potentially ancilla ions that serve to re-cool it. The chip wiring architecture will now be described in more detail. 5 First, parallelising dynamic control will be described including examples of how parallel dynamic control is used and qubit routing methods compatible with parallel control. Then, demultiplexed shim operation will be described including an example implementation. io II. Parallel dynamic control Referring to Figure 5A, a first parallel control arrangement for a group 15 of transport electrodes 4 is shown. 15 Each dynamic electrode 4 is provided with a respective switch 23 (either as a singlepole, single-throw switch or a single-pole, double-throw switch) which is configured to selectably connect the electrode 4 to the output of a transport voltage source 34 (for example, a DAC). In this case, each electrode 4 is provided with a respective transport voltage source 34. More than one electrode 4 may, however, share the same voltage 20 source 34. The electrodes 4 and the switches 23 are located on chip. The voltage source 34 is preferably located off chip, although it maybe locatedon-chip. For a group 15 of dynamic electrodes 4, switches 23 are configured to operate together, in other words, to close together (and thus connect all the electrodes 4 in the same 25 group to voltage source 34) and to open together (and thus, all the electrodes 4 in the group are disconnected from voltage source 34). Expressed differently, the switches 23 can be seen to operate together as a multiple-pole, single-throw switch or a multiplepole, double-throw switch. 30 The switches 23 can be controlled using one control signal for example by a single control bit, s. For example, when s = 1, each switch 23 is closed and, thus, each electrode 4 is connected to the output of a voltage source 34, and when s = o, the switch is open and, thus, each electrode 4 is unconnected to the output of a voltage source 34 or vice versa. Referring to Figure 5B, a second parallel control arrangement is shown. 06 05 25 The second parallel control arrangement is the same as the first parallel control arrangement shown in Figure 5A, except that it includes a second set of transport voltage sources 34 and each switch is a multi-throw switch with one terminal connected 5 to a first transport voltage source 34 and another terminal connected to a second transport voltage source 34. In this case, each electrode 4 is provided with two respective transport voltage sources 34. More than one electrode 4 may, however, share the same voltage source 34. 10 The switches 23 can be controlled by a single control bit, s. For example, when s = 1, an electrode 4 is connected to one voltage source 34, and when s = o, the electrode 4 is connected to a another, different voltage source 34. In some cases, the switches may have a third terminal allowing an electrode 4 to be 15 connected to one of two voltage sources 34, or be unconnected. More complex parallel control arrangements can be used. Referring to Figure 5C, a third parallel control arrangement is shown. 20 The third parallel control arrangement is similar to the first parallel control arrangement shown in Figure 5A, except that there are first and second groups 151,152 of electrodes 4 which share the same set of transport voltage sources 34. For example, a first electrode 4 in the first group 151 and a second electrode 4 in the second group 152 25 may share the same voltage source 34. Although electrodes 4 in one group 151,152 can be switched together, each group 151,152 of electrodes can be switched independently of the other group 151,152. There may be more than two groups 15 of electrodes 4, and the output of a voltage 30 source 34 can be shared between more than group 15. Furthermore, the output of a voltage source 34 can be shared between more than one electrode 4 in one group 15. The output of a voltage source 34 may not be shared between all groups 15. Referring to Figure 5D, a fourth parallel control arrangement is shown. 06 05 25 The fourth parallel control arrangement is similar to the second parallel control arrangement shown in Figure 5B, except that there are first and second groups 151,152 of electrodes 4 which share the same set of transport voltage sources 34. For example, a first electrode 4 in the first group 151 and a second electrode 4 in the second group 152 5 may share the same voltage source 34, while a second electrode 4 in the first group 151 and a first electrode 4 in the second group 152 may share another voltage source 34. As in the third parallel control arrangement, electrodes 4 in one group 151,152 can be switched together, while each group 151,152 of electrodes can be switched 10 independently of the other group 151,152. Also as in the third parallel control arrangement, there may be more than two groups 15 of electrodes 4, and the output of a voltage source 34 can be shared between more than group 15. Furthermore, the output of a voltage source 34 can be shared between more 15 than one electrode 4 in one group 15. The output of a voltage source 34 may not be shared between all groups 15. Referring to Figure 5E, a fifth parallel control arrangement is shown. 20 This arrangement shows that the output of one voltage source can shared between electrodes 4 between different groups 15 (or “zones”), while inside one group 15 (“zone”), each electrode 4 is connected to a different voltage source 34. In this arrangement (which is simplified for ease of understanding), there are four electrodes per zone 15. There may, however, be more electrodes 4 per zone. 25 In this arrangement, electrodes 4 are labelled using the notation (electrode index, zone type, zone index). Figure 5E illustrates how the same voltage source can be shared between different 30 electrodes in different zones, while electrodes in the same zone can be controlled in parallel. For example, voltage source labelled “V1>1>3” is shared between the third electrode in zone 1 (the electrode labelled (3,1,1)), the third electrode in zone 5 (the electrode labelled (3,1,5)) and the third electrode in zone 7 (the electrode labelled (3,1,7)) and so on. 06 05 25 A simple of example of how parallel dynamic control is used will first be described to help provide a better understanding of parallel dynamic control. Referring to Figure 6A, two qubits (1,2) (labelled 71, 72) are in neighbouring trap zones 5 1, 2 (also labelled 5I1,522). Qubit swap can be accomplished by connecting all electrodes to a set of voltage sources 34 (Figure 2) that execute a swap waveform. If a swap is not needed (that is, if the qubits are to be kept stationary), then one approach is simply to modify the voltage 10 source waveforms. Instead, however, according to the approach in accordance with the invention, the swap waveform continues to be played from (or “generated by”) the voltage sources, but a set of switches 23 (Figure 2) in the QPU 2 is used to select whether or not the ions 7 move. Specifically, action in zone i is controlled by a digital line Si. If Si = 1, the qubit in zone i experiences the swap waveform, while if Si = o, then 15 the qubit stays stationary. Thus, in a two-zone trap, qubits are swapped if (si, s2) = (1, 1), and remain in the same order if (si, s2) = (o, 0). It should be noted that in this case, (o, 1) and (1, 0) are not valid instructions. Referring to Figure 6B, the processor may be scaled up to be a linear repeating array 20 with zones i = 1, 2,..., N, in this case, with N = 6. Every second zone is connected to the same fixed set of voltage sources, that is, if s, = Si+2, then every dynamic electrode in zone 1+2 executes the same waveform as the corresponding dynamic electrode in zone i. Thus, by applying the same swap waveform as above, and sending an TV-bit word s = (si, s2,..., sn) to the QPU, it is possible to select whether or not to swap qubits (i, i + 1) for 25 every odd i in parallel. This step is referred to an “odd swap”. Similarly, an “even swap”, where it is selected whether or not to swap qubits (i, i + 1) for every even i in parallel, can be accomplished by playing a modified swap waveform and sending another TV-bit word s. 30 Thus, arbitrary parallel qubit swaps can be achieved in one dimension (1D) with a fixed number of voltage sources 34 and an TV-bit digital signal. In 1D, two types of zones 51odd, 51even are used, namely odd and even zones 41odd, 41even, and two sets of voltage sources 34odd, 34even are employed, namely one for odd zones, and one for even zones. 35 Referring to Figure 7, if every zone is connected via a transport path to its four neighbours to provide a cross-shaped junction, this approach can be extended to a two- 06 05 25 dimensional (2D) array. In such a 2D array, an “odd horizontal swap” and an “even horizontal swap” can be executed in the same way as described earlier for a 1D array. Vertical swaps can be executed by first tilting the view 90 degrees. In Section IID below, how these primitives allow for efficient arbitrary qubit reconfiguration will be shown. 5 A 2D processor maybe more complex. For example, it maybe beneficial to separate gate zones from junction zones, or create specialised readout zones or storage zones. Nonetheless, parallel dynamic control can also be applied. For example, as will be described hereinafter in Section IID, traps with separate junction and gate zones can 10 be controlled by using eight sets of voltage sources instead of four, hereinbefore described. All in all, parallel dynamic control is compatible with a complex processor and specialised zones, as long they consist of a repeating pattern of nominally identical unit cells. Likewise, the approach can be extended beyond swaps onto a larger set of parallel primitive actions by using more voltage source sets and more switch settings 15 per zone. A. Swap waveforms While the logical primitive of the architecture is a qubit swap, this is not necessarily the physical primitive. There are several ways that qubit swap can be implemented 20 physically. Referring to Figure 8A, a 1D physical swap sequence is illustrated. Two qubits 7 in separate wells 61 are brought together by shuttling and merged into a single crystal 62. Next, the crystal undergoes rotation that swaps the qubit order. Reference is made to 25 H. Kaufmann, T. Ruster, C. T. Schmieglow, M. A. Luda, V. Kaushal, J. Schulz, D. von Lindenfels, F. Schmidt-Kaier, and U. G. Poschinger, Physical Review A 95, 052319 (2017). Finally, the crystal is split, and the qubits are shuttled away from each other. Referring to Figure 8B, a 2D physical swap sequence is illustrated which can be used 30 when a junction 53 is present. By using a junction, two qubits 7 can be reordered in several steps of shuttling, without the need for crystal rotations (steps S8.1 to S8.3). This can be advantageous in terms of speed and heating. Finally, logical swaps can be implemented through quantum gates. This can lead to additional errors, but may allow for faster reconfiguration, especially in longer chains. 06 05 25 First and second qubits 7a, 7b are located in adjacent first and second channels 63ul, 63ur which lie across from third and fourth channels 63lr, 63ll, respectively, joined by a common central channel 63c. The second qubit 6b can be shuttled to the fourth channel 63lr lying opposite (step S8.1). The first qubit 7b is shuttled to the second 5 channel 63ur to take its place (step S8.2). The second qubit 7b can be shuttled to the first channel 63ul to take the place of the first qubit (step S8.3). While the swap waveforms above assume all qubits start in separate zones, this need not be the case. For example, consider an initial configuration where N qubits are 10 arranged in chains of length 2c, where c is a positive, non-zero integer. Before the routing begins, a sequence of c splitting waveforms is applied in every pair of zones until every qubit is placed in a separate zone. The procedure is repeated in reverse after the routing to bring the qubits together and apply the next layer of gates. More complex procedures can be used to control other chain lengths. The algorithm is also flexible 15 with regards to ancilla handling. For example, every qubit could represent a pair of ions, namely one qubit ion and one ancilla ion. In that case, primitive operations could involve 4-ion crystal rotations or 2-ion junction shuttling. Transport waveforms are determined using an electrostatic model of the charged 20 particle trap. A path for a charged particle from an initial position Xi to an end position xN is provided (e.g., from a routing module) and is divided into intermediate positions Xi, x2,..., xn. The electrostatic model of the trap is used to compute the electrostatic potential generated by putting a fixed voltage, for example, 1V on each electrode individually. Then, for each i (i.e., i = 1, 2,...., N), an optimisation algorithm is run that 25 computes a linear combination of electrode voltages that generates a potential that holds an ion at location x;. Finally, the obtained voltage (i.e., computed linear combination of electrode) are interpolated to generate a smooth waveform. An example of determining waveforms and examples of waveforms obtained in this way can be found in L. E. de Clercq: “Transport Quantum Logic Gates for Trapped Ions” 30 (2015) https: / / www.research-collection.ethz.ch / handle / 2o.5oo.1185o / 111463 (see for example, Figures 6.4, 6.5 and 6.6) which is incorporated herein by reference. Another method can be found, for example, in J. D. Sterk et al. “Closed-loop optimization of fast trapped-ion shuttling with sub-quanta excitation”, npj Quantum Information (2022) 8:68 https: / / www.nature.com / articles / s41534-022-00579-3.pdf B. Single-switch implementation 06 05 25 Referring to Figure 9, an extension of the 1D swap waveform between zones (1, 2) is shown. First qubits 71 undergo a swap and second qubits 72 remain stationary. Referring to Figure 10, an alternative way to use this waveform is as follows. 5 Suppose that there are only two qubits 71, 72, namely one in a first zone 5I1 (“zone 1”), and another in a second zone 522 (“zone 2”). A switchable push field can be used to push qubits 71, 72, in each zone 5I1,512 either left or right. Specifically, if s, = 1, the qubit in zone i is pushed into a first respective location 71^ while if s, = o, it is pushed 10 into a second respective location 7i2. After the switch is set, the waveform is executed. Thus, if (si, s2) = (1,1), the qubits undergo a swap, while if (si, s2) = (o, o), they remain in the original order. This swap waveform can be physically implemented as follows. 15 The fixed voltage sources are used to execute the extended swap waveform in every zone in parallel. At the same time, in each zone, whether the ion 71, 72 is pushed into the second or first well 622, 621 at t = 0 can be selected by (a) creating a double-well potential while (step Sio.ia) (b) applying either positive voltage +V or negative voltage 20 -V to one or more electrodes (step Sio.ib). This allows one to locally and digitally select if the ion undergoes a swap or not. Thus, one switch per zone suffices to implement parallel dynamic control. The same method can be used to condition the execution of a 2D swap waveform. Steps Sio.ia and Sio.ib can be carried out sequentially or simultaneously. 25 Referring to Figure 11A, an example of a switch system 81 is shown. The select bit word s = (si,..., sn) is loaded into a serial-to-parallel register 82, and is used to select whether zone i is connected to the + rail 83+ or - rail 84 using a selection swich 85. 30 Referring also to Figures 11B and 11C, the selection switch 85 can be physically implemented using a pair of pass transistors 86, or as two transmission gates 87, each implemented using an NMOS / PMOS transistor pair 88, 89 and an inverter. In one embodiment, the ± rails 83, 84 connect to separate voltage sources 34 (Figure 2) 35 and are initially set to the same voltage Vo. Once each electrode 4 is connected to one rail 83, 84, the voltage on the + rail 83 is increased to Vo + V, and the voltage on the - 06 05 25 rail 84 is reduced to Vo - V. This ramping can be done smoothly to avoid undesired motional excitation, with voltage source outputs filtered off-chip. After all electrodes 4 are set to either Vo + V or Vo -V, the swap waveform is played, and the rails 83, 84 return to Vo. This implements one cycle of parallel swaps. 5 Alternatively, parallel switching can be implemented by purely digital means. In this method, the ± rails 83, 84 are permanently set to VO±V. This can considerably simplify circuit design, and make it compatible with standard digital CMOS. However, digital implementation may require capacitors after the switches 85 to smooth out the 10 switching impulses. Alternatively, qubits can be displaced with minimum motional excitation and without filtering by a sequence of switching events using bang-bang methods. In relation to capacitive shunting of the electrodes to ground, while technologies exist 15 to manufacture low-loss switches with R <toil resistance, transistor switches with R too £2 are more typical. The larger the resistance R, the larger the RF pickup on the dynamic electrodes. Referring still to Figure 11A, this pickup can be mitigated by placing a shunt capacitor 20 90 between the switch 85 and the electrode 4. However, significantly reducing the RF impedance to ground requires large capacitors, for example, example, at £2rf = 271 x 50 MHz, an impedance Z <toil requires capacitance C >300 pF. Implementing such large capacitors on the chip likely requires significant footprint and vertical capacitor technology (as explained in Section III A). Furthermore, such on-chip filtering also 25 means the total capacitive load of each voltage source may vary significantly sequence-to-sequence, leading to waveform distortions. Thus, it is preferable overall to filter signals off-chip, and reduce the transmission gate resistance if necessary. C. Multi-switch implementation 30 In the multi-switch implementation, multiple or all dynamic electrodes 4 (Figure 2) in every zone are connected to a switch. Figure 12 illustrates a possible multi-switch implementation of a single parallel odd swap in 1D described earlier with reference to Figure 6B. 06 05 25 Referring to Figure 12, a zone i (labelled 52) is called odd (52odd) if i is odd, and even (52even) otherwise. Every dynamic electrode 4 in zone i is controlled by the same switch Si. Specifically, dynamic electrodes 4 in zone i are connected to the voltage source set Vi(mod2),Si. Thus, the illustrated implementation requires four sets of voltage sources 34 5 and at 6 dynamic electrodes 4 per zone, and so 24 voltage sources 34 in total are used. More generally for N zones, t zone types, e switchable dynamic electrodes per zone, each connected to a switch with k settings, multi-switch implementation requires txexk voltage sources and N x e on-chip switches. Each electrode 4 is individually wired as in 10 the single-switch implementation. The multi-switch implementation allows for maximum flexibility in the waveform design, as every action can have a completely separate custom waveform. As all the switches in zone i are controlled by the same digital line Si, the length of the bit select 15 word s is still N. D. Routing algorithm As explained earlier, parallel dynamic control allows implementation parallel “odd swaps” and parallel “even swaps” in a 1D array. In a 2D array, those can be performed 20 either on all rows in parallel (“horizontal odd / even swap”) or on all columns in parallel (“vertical odd / even swap”). In this section, how this capability allows for arbitrary qubit routing in a complex trap will be explained. As the simplest case, consider a 1D trap described with reference to Figure 6B. In this 25 case, arbitrary qubit permutation can be optimally generated by an algorithm known as “odd-even sort”. Denote the current qubit configuration as x = (x1; x2,..., xN), and the target configuration as tt(x) = (71(^), 7t(x2), , ^(^n))- In the first time step, qubits Xi and Xi+i swapped if 71(¾) >X^i+i) for every odd i. These swaps are performed in parallel across the processor. In the second time step, qubits Xi and Xi+1 swapped if %(xi) 30 >?r(xi+1) for every even i. These steps are repeated until x = n(x). The odd-even sort is the time-optimal method of sorting qubits in 1D, with worst-case run time of N time-steps (in the case where two qubits at the opposite ends need to be swapped). 06 05 25 Next, the method can be extended onto a 2D architecture described with reference to Figure 8B. Reference is made to N. Alon, F. R. K. Chung, and R. L. Graham, SIAM Journal on Discrete Mathematics 7, 513 (1994), A. M. Childs, E. Schoute, and C. M. Unsal,, 24 pages (2019), arXiv: 1902.09102 [quant-ph] and A. Banerjee, X. Liang, and 5 R. Tohid, “Locality-aware Qubit Routing for the Grid Architecture,” (2022), arXiv:22O3.H333 [quant-ph]. Consider a grid of m x n qubits arranged in a 2D array, and enumerate zones as where i = 1,2,..., m and J = 1,2,..., n. A zone is considered “odd” if i +j is odd, and 10 “even” otherwise. In this way, every odd zone only neighbours even zones, and vice versa. Qubit reconfiguration as follows. First, rearrange the qubits in every row in parallel such that, for every column, the target row of every qubit is different. This is possible by repeated application of Hall’s 15 marriage theorem. This rearrangement proceeds by horizontal odd even swap as outlined above, and thus takes at most m time-steps. Afterwards, rearrange the qubits in every column in parallel such as every qubit is in the target row. This is executed by vertical odd-even swap, and takes at most n time steps. Finally, proceed with the final row-wise rearrangement, which takes at most n time steps. Thus, the architecture 20 allows for arbitrary permutation of N = m x n qubits in 2D in at most 2m+n swap steps and two types of zones. Changing the permutation order to column-row-column allows for arbitrary permutation in at most 2n + m steps, which may be more efficient The considerations above assume every qubit can be swapped with any of its four 25 neighbours, that is, one junction per qubit. However, junctions take up real estate, and high-performance quantum processors may benefit from higher qubit density. Thus, it maybe beneficial to operate with multiple qubits per junction. Referring to Figure 13, a trap 3 is shown which illustrates one possible solution. The 30 chip of linear segments 101, each holding k qubits. Between every k qubits, there is an X-junction 102. Arbitrary routing in such a processor can be achieved by extending the methods hereinbefore described. Unlike previous examples with two types of zones, there are 35 four types of zones, namely junction odd, junction even, inner odd, and inner even. 06 05 25 In the first step, the qubits are arranged in each row in parallel as before. Additional zone types are required, as the physical waveform necessary to control qubits is different depending on whether it is in a junction zone 102 or an inner zone 101. Second, qubits are sorted vertically in every junction zone in parallel. Afterwards, the 5 qubit is swapped in each junction zone with its immediate neighbour to the right, and repeat the vertical sorting. This procedure is repeated k times, until all columns have been sorted. Thus, the only difference with the fully-connected 2D case is that the “vertical sort” step takes approximately k x m steps, rather than m steps as before. Finally, the horizontal sort is repeated as before. In total, arbitrary permutation of an io array with m x n qubits takes approximately 2m + krt steps, using four types of zones. Given any given (N, k) it is easy to verify that the reconfiguration time is minimised when m = yjKN / 2 and n = ^2N / k. In that case, arbitrary reconfiguration of an N-qubit array requires approximately fBkN swap steps. This solution is referred to as the 15 “optimal configuration”, and is discussed in more detail below. E. Performance and timing The total duration of qubit permutation depends on the time it takes to execute a single step of parallel swaps. This, in turn, depends on the duration of other primitives, such 20 as ion splitting, merging, rotation, linear shuttling (in case of a 1D swap) or junction shuttling (in case of a 2D swap). As an order of magnitude, a qubit swap duration of to = too ps is used, which is realistic given typical performance of existing systems. Referring to Figure 14A, the time necessary to perform arbitrary qubit routing in an 25 optimal 2D array is shown (using that assumption). With k = 6, an arbitraiy reconfiguration of a 1000-qubit array is achieved in 22 ms, while 10,000 qubits takes 70 ms. Referring to Figure 14B, is plot showing associated memoiy errors, assuming the error 30 model measured for 43Ca+ clock qubits in M. A. Sepiol, A. C. Hughes, J. E. Tarlton, D. P. Nadlinger, T. G. Ballance, C. J. Ballance, T. P. Harty, A. M. Steane, J. F. Goodwin, and D. M. Lucas, Physical Review Letters 123,110503 (2019), arXiv:i9O5.06878 [quant-ph]. With k = 6, a memory error (per qubit per reconfiguration) of 2e-5 for a 1000-qubit array is expected, and ie-4 for a 10,000-qubit system. This demonstrates that, 06 05 25 despite limited freedom of operation, parallel dynamic control is compatible with fast, high-fidelity reconfiguration at scale. In the analysis above, only the worst-case reconfiguration time is calculated. It is 5 reasonable to ask whether a typical reconfiguration time will be substantially different. Numerical analysis indicates that, for a random qubit permutation matrix, the average reconfiguration time is very close to the worst-case reconfiguration time. This is particularly true for large 2D arrays, as the time necessary to perform parallel horizontal / vertical sort is given by the time necessary to sort the slowest row / column. io Thus, significantly reducing the reconfiguration time requires considerable amount of structure in the permutation matrix, that is careful qubit mapping in the algorithm. III. Demultiplexed shim operation Referring to Figure 15, the principle underlying demultiplexed shim operation is that 15 multiple shim electrodes 6 can be set by a single voltage source 44. In particular, one voltage source 44 is connected through a demultiplexer 26 to multiple shim electrodes 6. Naive demultiplexing, however, risks degrading the performance of quantum operations due to noise injection. The risk can be mitigated 20 or ameliorated by operating by (1) charging the electrodes 6 one-by-one, (2) turning off the demultiplexer 26 and (3) executing quantum operations. Thus, during reconfiguration, the shim voltage is maintained not by the voltage source 44, but by on-chip capacitors 20, which also serve to shunt RF pickup to ground. These capacitors 20 may be unnecessary if the ion trap is ac Penning trap, rather than an RF trap. 25 A. Shim capacitors and RFpickup Suppose that zth shim electrode 6 is set to V. There may be residual RF voltage on the shim electrode, which can be particularly significant when the electrode 6 is disconnected from the voltage source 44. Suppose that shim electrodes 6 are shunted to 30 ground through capacitance C. When the switch is open, the voltage on the shim electrode is V + VRF x Ci / C cos(£2t), where £2 is the RF frequency VRF is the voltage on the RF electrode, and Ci is a parasitic capacitance between the RF and the DC electrode. This leads to additional micromotion, especially if there are variations of G / Cbetween electrodes. From this perspective, it is desirable to keep C very large. 06 05 25 As every shim electrode 6 has its own capacitor 20, these are integrated into the QPU 2 (for example, on-chip or co-packaged in a stacked structure) to avoid interconnect count. Once the capacitors 2oare integrated, the maximum value of Cmaybe limited by chip footprint constraints. As an example, consider a device with ion height h and zone 5 area Az = loh x io / i. Each zone contains Ns shim electrodes, each connected to a capacitor of area Ac. As long as Ns x Ac <Az, the capacitors 15 do not represent a significant bottleneck on the device size. Thin-film planar capacitors allow for C / A ~ 3 fF / pm2. Thus, a capacitor C with dimensions Ac = too pm x 100 pm provides a capacitance of C ~ 30 pF. Assuming h = 30 pm, it is possible to connect Ns = 10 shims 10 per zone to such capacitors without bottlenecking the device footprint. Given a typical parasitic capacitance between the RF and the shim electrode of ~ 1 fF, this reduces the RF pickup by a factor of ~ 3 x io-5. This should allow for good operations, especially that the pickup will be largely uniform across the chip. Nonetheless, parasitic capacitances can also be managed. 15 If necessary, RF pickup can be further reduced by using larger values of C. There are several ways this can be accomplished on-chip. First, larger planar capacitors can be used. For example, achieving C ~ 300 pF with Ns = 10 requires an area of ~ 1mm2 per zone. This means that a chip with N = 10, 000 qubits would have to be attached to a 10 20 cm x 10 cm capacitor die. More practically, multiple planar capacitors can be placed on different layers of the same chip. For example, using a 10-layer process, the effective C / A can be increased to ~ 30 fF / pm2, allowing for shim capacitance of C ~ 300 pF without increasing the footprint. Finally, vertical fabrication of trench capacitors allows for C / A ~ 10 fF / pm2 or even C / A ~ too fF / pm2. 25 B. Demultiplexer implementation Referring to Figure 16, a shim demultiplexer 26 can be implemented as a multistage switch network 131. The network 131 comprises a set of individual switches 132 arranged in pairs between the voltage source 44 and a respective electrode 6. A switch 30 132 connects the input 133 to the output 134 when s = 1, and leave them disconnected otherwise. The individual switches 132 can be implemented, for example, as transmission gates (similar to those hereinbefore described). In this configuration, a digital word s = (Si, s2,..., Sk) of length k controls which one of 35 2.k electrodes is connected to the voltage source voltage V. The word s can be sent to the 06 05 25 chip either through a parallel interface, in other words, k cables, a serial interface 19 (Figure 2), or generated on-chip using a flip-flop circuit that cycles through the switch settings in a fixed order. 5 Referring to Figure 17, as an alternative, hybrid implementation, the switch can be separated into digital and analog parts. First, a word s is sent to a digital demultiplexer 135. This selects which one of the 2k lines Xi, x2,..., x2Jt is pulled up, while the rest are set to ground. Second, for each i = 1, 2, 10 .., 2k, electrode i is connected to the shim voltage source 44 via a single switch 136 controlled by Xi. Thus, the demultiplexer 135 serves to connect one and only one of the shim electrodes to V. There are two advantages of the hybrid implementation. First, the digital demultiplexer 15 135 is straightforward to design and fabricate. Second, the analog signal V need only to pass through a single switch 136, regardless of how many electrodes are connected to the same source. This helps reduce potential time-dependent issues associated with transmission gates, such as due to resistive load or charge injection. 20 C. Electrode charging Before reconfiguration, electrodes 6 are charged to the correct voltage. While switching speed is fundamentally limited by the filter function of the switch resistance and the load capacitance, in practice it might be desirable to reduce the switching rate to reduce noise and ion motional excitation. 25 A transmission gate may have a resistance of R = too El and an on-chip capacitor may have a capacitance of C = 30 pF. Thus, on-chip components act as a low-pass filter with cut-off frequency / c = 53 MHz, which is large compared to typical motional frequencies of trapped ions (f= 1-10 MHz). Thus, charging the electrodes 5 using smooth 30 waveforms for several microseconds can help to avoid significant motional excitations, while simultaneously avoiding bandwidth limitations imposed by the on-chip load. In the following, it is assumed that a charging sequence takes t = 3 ps per electrode. Using k = 7, it is possible to charge M x 2k = M x 128 electrodes using M voltage 35 sources in 2k x t = 380 ps. Thus, the time necessary to charge shim electrodes 6 is comparable to the time necessary to execute three to four swaps. Therefore, if needed, 06 05 25 the electrodes 6 can be recharged between every reconfiguration layer, without significantly affecting the runtime. As will explained later, recharging shim electrodes 6 between every reconfiguration layer can be used to implement parallel gate operations. If it is not necessary to do so, it might be sufficient to recharge shim electrodes 5 much 5 less frequently, for example, once per quantum circuit shot. In that case, it should be possible to serve many more electrodes 6 from a single voltage source 44. One challenge of demultiplexed operation is charge injection. Once the electrode 6 is charged to voltage V, when the switch 132,136 is open, the residual charge on the 10 switch is injected into the electrode 6. In a simple model, each transistor switch stores charge Q = Ct (Vg - Vth - V), where Ct is the transistor gate-source capacitance, Vg is the gate control voltage, and Vth is the transistor threshold voltage. This charge is equally redistributed between the source and drain, hence the electrode voltage increases by AV = Q / C= (yg - Vth -V) x Ct / C after the source is disconnected. Assuming Vg - Vth - V~ 15 V, the resulting voltage is systematically offset by ~ VxCt / C. In this model, charge injection is a local systematic offset that is expected to be stable shot-to-shot, and thus can be calibrated out, even in the presence of variations between channels. Nonetheless, since no physical process is perfectly stable, it is desirable to 20 minimise the systematic shift in the first place. The primary way of reducing charge injection systematic is by decreasing switch capacitance. Single-transistor switches having a transistor gate-source capacitance Ct ~ 20 fF and even as low as ~ 1 fF are possible. 25 D. Electrode discharging While voltage V would ideally stay constant after the switch is disconnected, it actually decays over time. The main loss channels are due to current flow through the capacitor and the transistor. The former is dominant and decay through the capacitor is characterised by a time constant of t = RC, where R is the insulation resistance for the 30 capacitor. For a parallel plate capacitor of area A, dielectric gap t, dielectric constant ere0 and dielectric resistivity p, C = ereoA / 1 and R = pt / A. Thus, in this simple model, the time constant t = e,eop is independent of the capacitance. Naturally, this is just an approximation, as p can be affected by fabrication imperfections, which can depend on capacitor size. Still, given typical dielectric resistivities at room temperature, time 35 constants exceeding minutes can be expected, t ~ 270 s have been measured for thin- 06 05 25 film capacitors in alumina, and this number in further analysis, and reference is made to Y. Xu, F. K. Unseld, A. Corna, A. M. J. Zwerver, A. Sammak, D. Brousse, N. Samkharadze, S. V. Amitonov, M. Veldhorst, G. Scappucci, R. Ishihara, and L. M. K. Vandersypen, Applied Physics Letters 117,144002 (2020). 5 Assuming t = 270 s, the duration that the electrode can remain disconnected before it needs to be recharged can be determined. The most stringent target relates not to transport, but to entangling gates: electrode voltage changes lead to stray field changes lead to motional frequency changes due to trap anharmonicities. This is particularly 10 severe for radial modes and mixed-species crystals in surface-electrode Paul traps. As an order-of-magnitude A / ~ 1 kHz per V / m is used. For entangling gates, A / should be significantly below the sideband Rabi frequency £2’. As an order of magnitude, A / ^ 100 Hz, thus a stray-field error of E 0.1 V / m is 15 required. In principle, much bigger stray field changes can be tolerated, as long as they are known and accounted for in the gate drive settings. For transport, ion splitting is the most sensitive operation, and an axial stray field error of E 5 V / m is required for the operation to be executed successfully. However, larger 20 stray-field drifts can be tolerated as long they are radial. Finally, errors in stray fields can lead to heating and even ion loss during transport operations such as crystal rotations or junction transport. However, these can typically tolerate errors as large as E ~ too V / m. 25 Measurements from surface traps indicate that stray fields generally fluctuate by E ~ too V / m along the trap axis, although the presence of unshielded structures can produce variations an order of magnitude larger. Furthermore, the offsets are predominately in the out-of-plane direction. Suppose that the shim electrode is used to compensate a stray field range E = 200 V / m. Thus, (a) high-fidelity gates require a 30 voltage error below AV / V 0.1 / 200 = 5 x 10-4, (b) splitting AV / V 0.1 / 200 = 2.5 x 10-2, and (c) other transport AV / V 100 / 200 = 0.5. These numbers are rough, and the actual requirements can be significantly less stringent, depending on the trap anharmonicity, gate mode choice, sideband Rabi frequency, and whether the decay is uniform across the processor. 06 05 25 Nonetheless, these numbers are a useful starting point for discussing discharging timescales. Assuming t = 270 s as above, it is found that shim electrodes might require recharging every (a) 135 ms for gates (b) 7 s for splitting, (c) 3 min for transport. Thus, given the typical qubit reconfiguration timescales herein before described, unless the 5 sideband drive can be adjusted to keep track of shifting mode frequencies, shim electrodes will likely require recharging mid-circuit, for example, between subsequent reconfigurations. On the other hand, if the gate drive can compensate for local offsets, it might be sufficient to recharge the shim electrodes between circuits only. 10 IV. Quantum operations The approaches hereinbefore described can also help with improving qubit internal state control. In fault-tolerant quantum computing, the problem of implementing arbitrary unitaries 15 is reduced onto a problem of implementing a fixed set of primitive gates, for example single-qubit and two-qubit gates. Typically, quantum gates on N qubits are performed by applying O(N) signals from O(N) qubit drives (such as lasers or microwaves). Instead, however, parallel dynamic control and shim multiplexing methods can be used to implement primitive gates with only a small number of qubit drives. 20 The term “qubit drive” is intended, loosely, to refer to a signal source that couples to the qubit state. For example, when a laser is split into N paths, each modulated by a separate acoustic-optical modulator (AOM) and focused onto a different qubit, it can be said that there are “N individual qubit drives”. On the other hand, if a laser is 25 modulated by a single AOM and focused onto N qubits, it can be said that there is only a single, global qubit drive. Typical qubit drives include laser light near-resonant with a qubit quadrupole transition, a pair of laser beams near-resonant with a qubit Raman transition and microwave / RF B-fields near-resonant with the qubit transition. On the other hand, DC or AC electric fields from trap electrodes typically cannot be used as 30 qubit drives, as they only couple to the motion, not to the internal state of the ion. Referring to Figures 18A to 18E, quantum gate operation can be illustrated using an example 1D linear trap 3 with a microwave conductor 19 running along the trap axis. The conductor 19 acts as a global qubit drive, creating the same B-field and B-field 35 gradient, near-resonant with the qubit frequency, in every zone in parallel. This leads to qubit coupling with Rabi frequency Q(r) ~ + Q’r, where r is the distance from the 06 05 25 trap axis. Furthermore, for simplicity of illustration, it is assumed that £20 o, which can be achieved using multiple conductors, or by “partial nulling”, where the B-field generated is polarised in a way that avoids qubit coupling. 5 A. Quantum gates via parallel dynamic control Referring to Figure 18A, a method of single-qubit control is illustrated. Using parallel dynamic control, the ion 7 can be moved in every zone into one of two locations. If s = 1, the ion 7 is moved to a location rt = r, while if s = o, the ion 7 is moved into location r0 = 0. The locations are selected such that, once the qubit drive is switched on, ions in 10 location 1 experience a Rabi frequency £2 ~ £20 + £2’r, while ions in location 0 experience Rabi frequency £20 0. If the drive is resonant with the qubit frequency, this generates a Hamiltonian = £ , where 0$ = cosher* + sm^Oy, and 0 and £2 can be tuned by adjusting the global drive phase and amplitude, respectively. If the drive is detuned from the qubits by 8 » £2, we instead obtain a Hamiltonian H = 15 SiS;Uzn2 / (2<5). Using this toolbox, any single-qubit rotation can be implemented on any subset of qubits in parallel. For example, a Hadamard gate on qubits (1,3, 4) can be implemented by setting Si = s3 = s4 = 1 and applying for time t = 7i / (2£2), with 0 = 20 -n / ^. Due to unavoidable experimental imperfections, it is impossible to ensure £20 = o, and the qubits in location 0 will always experience some residual Rabi frequency £20 = s x £2. This, if uncorrected, results in ~ e2 infidelity per qubit per gate. There are several 25 ways to mitigate this error. First, if e is known, it is possible to undo the undesired rotation with an additional layer of pulses. Second, whether or not e is known, composite pulse schemes such as SKi or CORPSE can be used to cancel out any systematic imperfections, and reference is made to J. T. Merrill and K. R. Brown, “Progress in compensating pulse sequences for quantum computation,” (2012), 30 arXiv:i2O3.6392 [quant-ph]. Referring to Figure 18B, in a similar way, multi-qubit gates can be implemented using parallel dynamic control. There, pairs at the intersection of zones, and dynamic electrodes are used to tune the motional frequencies. If (si, Si+i) = (1,1), the motional 35 frequency of qubit pair (i, z + i) H - V - 06 05 25 while if (si, Si+i) = (o, o), the motional frequency is tuned to co0. The global drive parameters are tuned to coi, that is, they generate an effective interaction when w = Wi, while leaving ions at motional frequency Wi untouched. Thus, a Hamiltonian is generated. As in the single-qubit case, composite pulses can be used to suppress 5 infidelity associated with undesired spin-motion couplings in zones where s = o. In Figure 18B, tuning the motional frequency is illustrated by qubit displacement from the trap axis. It is, however, possible to tune the motional frequency by adjusting shim curvatures, leaving qubit locations intact. io B. Quantum gates via shim demultiplexing The methods described above allow one to implement single- and multi-qubit gates in parallel, but the angle and phase of the gate are set globally. This is sufficient in the fault-tolerant regime, but in the NISQ regime, it is strongly desirable to implement 15 parallel control where the gate parameters are locally adjustable. Figures 18C and 18D demonstrate how shim multiplexing can be used for that purpose. Referring first to Figure 18C, using shim multiplexing, the shim voltage in every zone is set to Vi, resulting in a locally ion displacement ri oc Vi. This displacement can be 20 directly translated into Rabi frequency as £2; VLr oc Vi. Thus, shim multiplexing a Hamiltonian = to be implemented, where is locally adjustable. This Hamiltonian allows implementation of single-qubit parallel rotations with locally adjustable angles across the processor, while using only a single qubit drive. 25 Referring first to Figure 18D, likewise parallel multi-qubit gates with locally adjustable pulse angle can be implemented by locally tuning motional frequencies and orientations, implementing H = Yt where Q,\ is locally adjustable. Lack of local phase control, however, constrains the use of composite pulses to reduce unknown coherent errors in these schemes. 30 C. Quantum gates via modulator multiplexing Parallel local amplitude and phase single-qubit control can be achieved by multiplexing on-chip signal modulators. Previously, emphasis has been placed on developing on-chip qubit drive modulators, such as laser amplitude modulators. Instead, qubit drives 06 05 25 can be kept global, but locally adjust the Rabi frequency and phase using local multiplexed low-frequency voltage sources. Referring to Figure 18E, a possible architecture is shown, where single-qubit control is 5 achieved by a global qubit drive in combination with local low-frequency (for example, i-io MHz) electric fields, generated by locally adjustable IQ mixers 150. The mixer inputs A,..., In, Qi,...,Qn can be controlled by multiplexing a small number of voltage sources. This can be used to implement H = Xi where £2; can be adjusted by tuning the amplitude of the AC electric field, and <pi can be adjusted by tuning the phase 10 of the AC electric field. This Hamiltonian allows for fully parallel single-qubit control, and the resulting phase control allows for the use of composite pulses to suppress systematic calibration errors. D. Summary 15 Table I below summarises the available the single- and two-qubit control Hamiltonians for different parallelisation methods. Scheme i-q Hamiltonian 2-q Hamiltonian Method Global angle, local phase Li=1s^ ^.= 1S2i-in' Parallel dynamic control Local angle, global phase X"., ° Shim multiplexing Local angle, local phase Li=1s^ - IQ mixer multiplexing Table I 20 Summary and comparison of qubit control Hamiltonians available with different gate schemes While the examples presented above demonstrate parallel single- and two-qubit control in traps with global microwave gradients, these methods are equally applicable to laser-25 based gates. In that case, trap voltages are used to translate ions within laser beams, modifying the resulting laser intensity and thus the Rabi frequency of light-ion interactions. Furthermore, the methods can be extended to multi-qubit gates beyond two qubits. 30 V. Wiring a 1000-qubit chip 06 05 25 Referring to Figure 19, an electrical wiring arrangement for an IV-qubit chip 160 is shown. In this case, N = 1,000. However, Nmaybe between 100 and 1,000, or between 1,000 and 10,000 or more. 5 In this example, there are 10 dynamic electrodes 4 and 10 shim electrodes 6 per qubit 7 resulting in a total of 20 electrodes per qubit 7. In this case, the ion-electrode height h is about 50 pm, and a 2D layout with k = 6 qubits per junction is used. In the so-called “optimal configuration”, this requires an array of m x n zones with (m, n) = (54,19). Assuming zone size of toh x toh (as explained in Section IIIA above), this requires a 10 footprint of at least 27 mm x 10 mm. Dynamic operations are executed using four different zone types in a 2D architecture, each executing one of two possible actions. This requires a total of 80 off-chip voltage sources 34 (Figure 2). The action selection is performed by sending an action select 15 word s = (Si, s2,..., Sv) through a 4-wire SPI interface (not shown). Assuming SPI data streaming rate of / = 50 Mb / s, the select word s can be updated in 20 ps. This is faster than the typical transport operation timescale (to = 100 ps for a single swap), thus the SPI interface does not bottleneck the dynamic performance. 20 Multiplexed operations are executed by connecting each shim voltage source 44 to 128 shim electrodes 6. Thus, 10,000 / 128 78 shim voltage sources 34. Each shim electrode 6 is connected to a C = 30 pF on-chip capacitor 20 (Figure 15), and all capacitors 20 can be placed on a single layer without increasing device footprint. Digital shim multiplexers 26 switch every 3 ps, controlled by an on-chip shift register (not 25 shown). Thus, shim switching only requires two external inputs, namely a 333 kHz clock (not shown) and an enable line (not shown). This is a cautious approach and the number of shim voltage sources 34 can be significantly reduced by decreasing the number of shim electrodes 6 per qubit 7 and increasing the number of shim electrodes 5 per voltage source 44. 30 The core of the QPU 2 is a surface layer trap 3 which may take the form of a multi-layer surface trap. 06 05 25 On a top layer 161 of the trap 3, approximately 20,000 electrodes 4, 5, 6 serve to trap and transport 1,000 qubits provided by 2,000 (i.e., half encoding qubits and half used as ancillas for mid-circuit readout). 5 One or more buried ion trap layers 162 can be used to (a) route and deliver voltages to the top-layer electrodes, (b) route currents and deliver qubit drive B-fields and B-field gradients to the ions, (c) route lasers to the ions via integrated photonics, (d) collect and / or readout ion fluorescence. The electrode voltages are delivered via ~ 20, 000 vias 163 from the bottom layers 162 of the chip which implement the switch network 10 22. Alternatively, the switch network can be implemented on a separate chip 164, connected to the ion trap chip 3 via a high-density IC interconnect with ~ 20, 000 bumps (not shown). The separate chip 164 may additionally or alternatively house other circuits (not shown) providing, for example, signal conditioning, and may include DC filters, RF resonators, and microwave impedance matching circuits. 15 A first buried layer 1621 (or “capacitor layer”) may include around 10, 000 thin-film planar capacitors 20 (Figure 15), one per shim electrode 6. A second buried layer 1622 (or “switch layer”) may provide, for example, (a) around 20 10,000 dynamic electrode switches 26 (Figure 2), for example, each made of out two transmission gates 87 (Figure 11C), (b) around 10,000 shim electrode switches 136 (Figure 17), for example, each made of one transmission gate, (c) a digital serial-to-parallel converter 82 (Figure 11A) for dynamic electrode control, and (d) a digital demultiplexer 135 (Figure 17) for shim control. 25 The separation of the QPU into layers of specific function, as well as the precise ordering of these layers and the stack-up, may differ from the one presented above. Table II below summarises the electrical connections to the 1,000-qubit chip. In total, 30 167 wirebonds 165 suffice to perform arbitrary qubit reconfiguration in a 1,000-qubit chip. In addition to the transport voltage lines, additional electrical connections might be required to perform quantum gates. To perform laser-free quantum gates, one would additionally connect a small number (1 toio) of current lines that generate magnetic field gradients in multiple zones across the chip at once. Furthermore, Paul traps 35 require a small number of high-voltage inputs to generate the trapping potentials. Thus, under 200 electrical input connections suffice to control a 1000-qubit trapped ion quantum computer. Source I / O count Transport voltage sources 80 Dynamic SPI 4 Digital logic power 3 Shim voltage sources 78 Multiplexer control 2 Total 167 Table II 5 Electrical connects to QPU for DC electrode control in a 1,000-qubit chip. Additional electrical connections can be used to connect the trapping RG and on-chip current lines. 06 05 25 Additional optical control can be used to perform dissipative operations such as state 10 preparation, ion cooling, and qubit measurement. In this architecture, these operations can be executed globally, with light delivery accomplished by connecting a small number of optical fibres to the chip, and then splitting them passively between zones. Furthermore, qubit readout can be executed by integrating multiplexed photodetectors into the QPU. 15 Modifications It will be appreciated that various modifications may be made to the embodiments hereinbefore described. Such modifications may involve equivalent and other features which are already known in the design, manufacture and use of charged particle trap 20 apparatus and component parts thereof and which may be used instead of or in addition to features already described herein. Features of one embodiment maybe replaced or supplemented by features of another embodiment. The charged particle trap apparatus need not necessarily be a quantum information 25 processing (or “qubit” processing) apparatus such as a quantum computer, but can be, for example, an atomic clock. 06 05 25

Claims

1. Apparatus, comprising:• a charged particle trap (3) comprising:5 - a set of trap electrodes (4,5, 6) including a set of electrodes (6) forgenerating electric fields for manipulating charged particles;• a voltage source (44) having an output; and• a demultiplexer (26) having an input and a plurality of outputs, wherein the output of the voltage source is coupled to the input of the demultiplexer, and each of10 the plurality of outputs of the demultiplexer are coupled to a respective one of the set of electrodes;wherein the demultiplexer is configured, in a first phase, to charge the electrodes by sequentially connecting each electrode to the voltage source and, in a second phase, to disconnect the voltage source from the electrodes for a given time for providing a15 lower noise environment in which operations can be performed on the charge particles.

2. The apparatus of claim 1, further comprising:• at least one further electrode coupled to the demultiplexer (26), wherein the demultiplexer is configured, in the second phase, to connect the at least20 one further electrode to the voltage source.

3. The apparatus of claim 1 or 2, further comprising:• a set of capacitors (20), wherein each electrode (6) in the set of electrodes is provided with a respective capacitor arranged between the electrode and ground.

254. The apparatus of any one of claims 1 to 3, comprising:• a charged particle trap chip (9) supporting the charged particle trap;wherein the capacitors (20) are integrated on the charged particle trap chip.30 5. The apparatus of any one of claims 1 to 3, comprising:• a charged particle trap chip (9); and• at least one further chip stacked on the charged particle trap chip;wherein the capacitors (20) are integrated into the at least one further chip.3506 05 256. The apparatus of claim 4, wherein the voltage sources (44) are integrated on the charged particle trap chip or the at least one further chip.

7. The apparatus of any one of claims 1 to 6, wherein the given time is sufficient to5 perform a series of at least one quantum gates.

8. The apparatus of any one of claims 1 to 6 or 7, wherein the given time is between 1 ps and 1 s.10 9. The apparatus of any one of claims 1 to 6, wherein the given time is sufficient totransport at least one charged particle from a first arrangement of charged particles to a second, different arrangement of charged particles.

10. The apparatus of any one of claims 1 to 6 or 9, wherein the given time is between 1 15 ms and 500 ms.

11. The apparatus of any one of claims 1 to 6 or 9, wherein the given time is between 1 ps ms and 1,800 s.20 12. The apparatus of claim 11, wherein the given time is between 60 s and 1,000 s.

13. The apparatus of any one of claims 1 to 12, wherein each electrode (6) is layer-like having a thickness, and wherein each electrode has at least one dimension (di, d2) perpendicular to the thickness between 10 pm and 2,000 pm.2514. The apparatus of any one of claims 1 to 13 further comprising:• a shim controller (41);wherein the shim controller is configured to cause charging of the electrodes (6) in the set of electrodes.3015. The apparatus of claim 14, wherein the shim controller (41) is configured to cause charging of the electrodes (6) in the set of electrodes to respective levels appropriate to compensate for stay electric fields.35 16. The apparatus of any one of claims 1 to 15, configured to be a quantum computer.17- A system comprising:• the apparatus of any one of claims 1 to 16; and• a cryogenic system for cooling at least the charged particle trap (3).5 18. A method of operating the apparatus of any one of claims 1 to 16 or the system ofclaim 17, the method comprising:causing, in a first phase, the demultiplexer to charge the electrodes by sequentially connecting each electrode to the voltage source and:causing, in a second phase, demultiplexer to disconnect the voltage source from10 the electrodes for a given time for providing a lower noise environment in which operations can be performed on the charge particles.

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