A quantum computation chip and a method of fabricating a quantum computation chip

Abstract

A method of making a quantum computer chip by forming one or more qubits on a first face of a sapphire substrate; after forming the qubits, forming an aperture in the substrate, the aperture extending

Description

FIELD Embodiments described herein relate to a quantum computation chip and a method for fabricating a quantum computation chip. BACKGROUND A quantum computer is a computer that stores and processes information in the form of quantum bits (or “qubits”). A quantum computer can take advantage of quantum mechanical phenomena to perform computational processes that are not possible on a classical computer, including performing encoding and processing of information in quantum states to achieve faster processing times than may be possible in a classical computer. To achieve a practical quantum computer, high-coherence qubits with long lifetimes are desirable. Qubits may be manufactured on a high resistivity substrate, for example silicon or sapphire. As the number of qubits in a quantum computing chip is increased, the physical size of the quantum processing unit typically increases which can give rise to unwanted modes with frequencies similar to that of the qubit frequencies. These unwanted modes can lead to leakage and a general reduction in the performance of the quantum processing unit. Methods to avoid unwanted modes include airbridges or through-substrate-vias (TSVs) through the chip’s substrate. However, the fabrication of such structures is complex. High-coherence qubits have been manufactured on silicon substrates, with observed lifetimes in the region 200 to 300 ps (depending on whether a capping film is used, and the composition of the capping film). Alternatively, sapphire can be used as a substrate. High coherence qubits have been manufactured on sapphire substrates with observed lifetimes in the region of 300 to 400 ps using titanium nitride films or tantalum films. Measurements of sapphire dielectric loss have also typically been lower than comparable measurements for silicon substrates, with observed losses of 1.8 x 10'8 on sapphire compared to 2.7 x 10-6 on silicon. Sapphire therefore offers a low-loss platform for high coherence qubits. However, due to its high hardness, relatively low feature toughness, and chemical inertness, sapphire is 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 challenging to process. For example, when silicon is used as a substrate structures can be formed therein using high aspect ratio chemical etch process such as deep reactive ion etching (DRIE), but such fabrication methods are not possible with sapphire due to its chemical inertness. Laser drilling can be used to process sapphire. However, laser drilling imparts significant energy in the form of heat onto the substrate. Such heating can be damaging to quantum circuits, for example the heat can significantly change the parameters of Josephson junctions. Heat imparted by the laser typically leads to cross-linking of the material in resists, making them difficult to remove without residue. Residue generally degrades performance in quantum circuits. As such, it is generally not desirable to use laser drilling in processing sapphire for use in quantum circuits. BRIEF DESCRIPTION OF THE DRAWINGS Embodiments will now be described by way of example with reference to the accompanying drawings. Fig. 1 schematically illustrates a quantum computing chip; Fig. 2 schematically depicts a cross-section of the chip of Fig. 1; Fig. 3 illustrates a method of fabricating a portion of a chip using a sapphire substrate; Fig. 4A and 4B depict optical micrographs showing resist inhomogeneity surrounding an aperture in a substrate; Fig. 5A and 5B are results illustrating the performance of a plurality of qubits fabricated in accordance with an embodiment; and Fig. 6 is a photograph of a via in a quantum computing chip, where the via has been formed prior to the formation of the Josephson Junctions. SUMMARY OF INVENTION In an embodiment, a method of fabricating a quantum computing chip is provided, comprising: forming one or more qubits on a first face of a sapphire substrate; after forming the one or more qubits, forming an aperture in the substrate, the aperture extending between the first face of the substrate and a second opposing face of the substrate. Forming the aperture or via after forming the qubit can beneficially improve the quality and hence performance of the qubits compared to chips where apertures are formed prior to formation of the qubits. Vias are of particular use when there are multiple qubits. Therefore, in an embodiment, the method may include forming multiple qubits on the first of the substrate. The method may also comprise forming multiple apertures in the substrate. The multiple apertures may be positioned between the multiple qubits. Forming the aperture in the sapphire substrate may comprise drilling the aperture using micromachining. Micromachining is particularly suited to the formation of an aperture or via chip comprising a sapphire substrate, because many other fabrication methods commonly used in the fabrication of chips are unsuitable for use with sapphire, for example due to its high hardness, relatively low feature toughness, and chemical inertness. Other fabrication methods, for example laser drilling, can cause negative effects even if performed prior to the provision of the qubits. For example, laser drilling imparts significant thermal energy and so additional protective layers are typically used to reduce damage. However, these additional protective layers are changed by the heat damage from the laser and so are difficult to remove without residue. The resultant residue negatively affects the performance of the chips (e.g. by affecting the resistance of the qubits). Forming the aperture in the sapphire substrate may comprise: drilling a first portion of the aperture extending from the first face of the substrate towards, but not extending through, the second face of the substrate; drilling a second portion of the aperture extending from the second face of the towards the first portion of the aperture, so as to form a single continuous aperture. In an embodiment, the first and second portion will be drilled parallel and in alignment (e.g. the centre of the first portion will be aligned with the centre of the second portion). The first and second portion may each be drilled generally perpendicular to the plane of the first and second face of the substrate, respectively. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Drilling the aperture in two portions, one from each face of the substrate, reduces the severity of blowout experienced. Blowout can negatively affect the yield of a chip. The micromachining may use a helical tool path. Forming one or more qubits on the first face of the substrate may comprise: depositing a layer of superconducting material on the first face of the substrate; selectively removing one or more portions of the superconducting material so as to form a pattern of superconducting features which cooperatively form the one or more qubit electrodes. The removal of superconducting material may be performed by etching or via a lift-off process. For example, selectively removing one or more portions of the superconducting material may comprise: providing a resist layer on top of the layer of superconducting material; exposing a patterned portion of the resist layer to radiation; developing the resist layer to form a patterned resist layer; and removing any superconducting material not covered by the resist layer. In a further embodiment, depositing a layer of superconducting material on the first face of the substrate and selectively removing one or more portions of the superconducting material may comprise: providing a resist layer; exposing a patterned portion of the resist layer to radiation; developing the resist layer to form a patterned resist layer; depositing superconducting material on the patterned resist layer; and performing a lift-off process to selectively removing one or more portions of the superconducting material. The resist layer may be a photoresist layer or an e-beam resist layer. Exposing a patterned region of the photoresist layer to radiation may include exposing the photoresist layer to light containing the pattern. Exposing a patterned region of the photoresist layer to light may include covering the photoresist layer with a mask (e.g. the mask having the pattern) to form a masked photoresist layer and then exposing the masked photoresist layer to light. The light may be UV light. The photoresist may be positive or negative. With a positive resist, the patterned portion (i.e. the portion exposed to light) is removed. With a negative resist, any areas of the photoresist layer which do not correspond to the patterned portion (i.e. any areas which were not exposed to light) are removed. In further embodiments, an e-beam resist is used which is patterned by exposing the e-beam resist to an electron beam, for example in a SEM or the like. E-beam methods are used to pattern features with a higher resolution than that obtainable by photolithographic techniques, for example, e-beam can be used to pattern the Josephson junctions. The patterned portion or portions not corresponding to the patterned portion may be removed using a chemical agent, for example a solvent. The removal of superconducting material may be performed by etching. The method may further comprise removing the remaining photoresist after removal of the superconducting material. The remaining photoresist may be removed using solvents. The method may further comprise, after forming the aperture, providing a layer of metal on the walls of the aperture. This process may be referred to as metallisation. The layer may be thin, for example of the order of hundreds of nanometers. The layer may have a thickness of less than 500 nm, for example. The layer may have a thickness of less than 100 nm. The metal may comprise aluminium. Rather than a metal, a metallic material (i.e. a material comprising metal) may be used. The method may further comprise, before forming the aperture, forming one or more resonators on the second face of the substrate, each resonator corresponding to and aligned with a corresponding one of the one or more qubits. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 In an embodiment, aligned with may mean coaxial with (i.e. their centres are aligned). In a second aspect, a method of fabricating a quantum computing chip is provided, the method, comprising: forming an aperture in the substrate, the aperture extending between the first face of the substrate and a second opposing face of the substrate. wherein forming the aperture in the sapphire substrate comprises: drilling a first portion of the aperture via micromachining extending from the first face of the substrate towards, but not extending through, the second face of the substrate; drilling a second portion of the aperture via micromachining extending from the second face of the towards the first portion of the aperture, so as to form a single continuous aperture, the method further comprising forming one or more qubits on the first face of a sapphire substrate. The one or more qubits on the first face of a sapphire substrate may be performed before or after the micromachining of the vias. In a further embodiment, a quantum computation chip is provided comprising: a sapphire substrate; one or more qubits on a first face of the substrate; one or more resonators on a second face of the substrate, the second face opposing the first face, each resonator corresponding to and aligned with a corresponding one of the one or more qubits; and one or more apertures, each aperture extending between the first and second faces of the substrate; wherein there are substantially no bodies of unwanted material protruding from the first and / or second face of the substrate in a region proximal to the aperture. The chip may be formed, for example, using any of the methods of the first aspect or second aspects. Unwanted material may comprise irregular shaped metallisation which is formed around the aperture. For example, irregular shaped material may be streaks or shards of material which are not provided in a regular repeating pattern. The unwanted material is material that is not intended to be provided around the aperture and can be identified as it will not have the same pattern as that of the photolithographic mask used to define metallisation patterns or e-beam patterns. Also, the unwanted material may not have a regular repeating pattern. Substantially no bodies of unwanted material may mean substantially no bodies of material comprising unwanted superconducting material. Substantially no bodies of unwanted material may mean substantially no bodies of material with a diameter length smaller than an aperture diameter of the aperture. The length may be measured parallel to the first and / or second face of the substrate. The length may be, for example, less than 100 nm, 50 nm, 10 nm. DETAILED DESCRIPTION Fig. 1 schematically illustrates a quantum computing chip 10. The chip 10 has multiple qubits 12 arranged on a substrate 11. Each qubit 12 is configured to store a quantum state. Each qubit 12 comprises a first and second superconducting electrode 12a, 12b with a Josephson junction 12c between the electrodes 12a, 12b. The electrodes 12a, 12b may be made from, for example, aluminium, niobium, tantalum, titanium nitride, aluminium nitride or niobium nitride. In an embodiment, a plurality of chips will be provided on a wafer and the wafer will be processed. The chips are then cut from the wafer after processing. In other embodiments, chips are cut from the wafer prior to or part way through processing. The qubits 12 are coupled together with a coupling 14. The coupling 14 in Fig. 1 is illustrated as a capacitive coupling, but other forms of coupling may also be implemented (for example a resonant coupling comprising an inductor and a capacitor). In Fig. 1, the qubits 12 are displayed in a hexagonal array, however a hexagonal array is only one example and other arrangements of qubits are possible including grid-like arrays, circular arrays or other planar arrangements. The chip 10 depicted in Fig. 1 may be a portion of a larger computing chip. For example, the portion of substrate 11 shown in Fig. 1 may be only a portion of a larger substrate, with further qubits arranged elsewhere on the substrate. Additionally, or alternatively, the chip 10 depicted in Fig. 1 may be (or form part of) a ‘chiplet’, wherein multiple smaller chips form modular blocks of a larger overall chip. The chip 10 depicted in Fig. 1 also includes a through-substrate via 15. The via 15 extends from a first face of the substrate 11 (on which the qubits are arranged) to a rear face of the substrate 11, as can be seen in Fig. 2. Vias may be provided to reduce unwanted modes in the chip. The via 15 takes the form of an aperture through the substrate 11. The via 15 is therefore a void or hole within the substrate 11. The via 11 may contain air, or be held at a vacuum, depending on the environment in which the chip is provided in. In this arrangement, the via 15 is positioned generally centrally to the hexagonal array of qubits 12. However, it should be understood that other arrangements are possible. For example, more than one via 15 may be positioned in the central region of the hexagonal array or the via may be positioned off-centre. Additionally, with other qubit arrangements vias may be arranged differently. With a grid-like array of qubits, a corresponding gridlike array of vias may be provided, wherein the via array is offset from the qubit array such that each via is positioned within the space between four adjacent qubits, for example. Fig. 2 schematically depicts a cross-section of the chip 10 of Fig. 1. The qubits 12 are arranged on a first face 11a of the substrate. On a second face 11b of the substrate, opposing the first face 11a, are arranged a set of resonators 22. The resonators 22 are arranged in a hexagonal array, corresponding to the arrangement of the array of cubits 12, such that each cubit 12 has a corresponding resonator 22. Each pair of qubit 12 and resonator 22 are coaxially aligned. The resonators 22 may be, for example, lumped inductive capacitive (LC) spiral resonators. Fig. 2 also depicts a control mechanism 24 and readout mechanism 26. The control mechanism 24 and readout mechanism 26 are coaxially aligned with a qubit 12 and resonator 22. The control mechanism 24 and readout mechanism 26 are coupled to a processor (not shown) configured to control the control mechanism 24 and readout mechanism 26 to perform quantum information processing. The qubits 12 are used to store quantum information and to be addressed in order to transition the qubit between quantum states. To prepare the qubit in a logical state or to transition the qubit between states, the qubit 12 is addressed via a control mechanism 24. The control mechanism is capacitively coupled to the qubit to provide control pulses to transition the qubit between quantum states. The readout mechanism 26 and resonator 22 together form a readout element. The coaxial arrangement described above is a chip that is compact in-plane, allowing for higher scalability of the quantum information system to include many qubits without minimal control wiring on the substrate. However, it will be appreciated that the coaxial arrangement described is an example only, and alternative control line and readout line arrangements are possible, including those in plane with the qubit. The via can be seen in Fig. 2 as a void or aperture extending through the substrate 11 from the first face 11a to the second face 11 b. It should be understood that Fig. 2 depicts only a cut-through of a portion of a chip. A quantum computation chip will generally house multiple qubits and multiple vias positioned therebetween. Fig. 3 illustrates a method of fabricating a portion of a chip using a sapphire substrate. The method includes the formation of a via using drilling, for example micro-machining. In a first step 102, qubits 12 are formed on a first face 11a of the substrate 11. The substrate 11 is a sapphire substrate. The qubits 12 are formed on the substrate 11 via a process of photolithography, where one side (e.g. the first face 11a) of the substrate is patterned with a superconducting material (e.g. aluminium or tantalum) to form the superconducting electrodes 12a, 12b. Photolithography techniques may be used. In an embodiment, the process of forming qubits 12 includes providing the substrate 11, depositing the superconducting material over the substrate 11 (e.g. a face 11 a thereof), followed by covering the substrate 11 with a photoresist. The photoresist is typically provided using spin coating. A mask is used over the photoresist layer followed by exposure of the photoresist to radiation (e.g. light, for example UV light). The exposed section of photoresist is then removed (e.g. using a chemical agent) to leave a pattern on the substrate 11. The superconducting material is then etched away revealing a pattern on the substrate 11 of the superconducting electrodes 12a, 12b defining the qubits 12. Remaining photoresist is removed by solvents. In this example, the photoresist is a positive resist. In another example, a negative resist may be used. With a negative resist, any portions of the resist which are not exposed are removed. In summary, a patterned portion of the photoresist layer is exposed to light and then either the patterned portion (in the case of a positive resist) or the non-patterned portion (in the case of a negative resist) is removed. Optionally, the first step 102 may also comprise forming resonators (not shown) on the second face 11 b of the substrate 11. The fabrication of resonators may be performed via a process of photolithography similar to that described above. Josephson junctions are formed via a combination of electron-beam lithography and metal deposition. The qubit side of the substrate is covered in an electron-beam resist. The pattern is defined via electron-beam lithography prior to chemical development to remove resist from the regions exposed by the electron beam. In an embodiment, a double-angle deposition is performed whereby a first layer of superconducting material (e.g., aluminium) is deposited prior to oxidation to form the Josephson Junctions oxide barrier. Then, a second metal evaporation at a different angle is performed. The Josephson junction is formed where an oxide barrier separates the superconducting material from the first and second depositions of superconducting material. The remainder of the electron-beam resist, is then removed in a lift-off process to remove the metal which overlies the p electron-beam resist. In a second step 104, a first portion 15a of an aperture (i.e. a via) is drilled into the substrate 11. The drilling is performed from the first face 11a of the substrate 11, i.e. the surface on which the qubits 12 are formed. In the second step 104 of Fig. 3, the direction of drilling is shown by a first direction arrow X. The drilling is performed using micromachining, for example using a micro-milling system. The micro-milling system may use a micrograin tool comprising diamond. In an example, a micrograin tool with a 600 pm diamond grinding pin is used following a helical tool path, so as to form an aperture with a 1mm diameter. The drilling can process can be optimized using active cooling during drilling. The substrate 11 and grinding pin can be actively cooled, for example using deionized water. Such cooling keeps the grinding pin cool, thereby avoiding heat damage to the substrate 11 or components formed thereon (e.g. the qubits 12). Prior to the second step 104 (e.g., prior to drilling), the substrate 11 can be provided with one or more protective coatings. Protective coatings can include one or more charge mitigation layers and / or one or more photoresist layers. The protective layers can protect the substrate 11 and the resultant fabricated chips from electrostatic damage and manufacturing debris. Active cooling can additionally reduce or avoid heating of these protective coatings, thereby further reducing damage. In a third step 106, a second portion 15b of the aperture is drilled into the substrate. The drilling during the third step 106 is performed from the second face 11b of the substrate 11, opposite to the first face 11a. That is, when resonators have been formed on the opposite face compared to the qubits 12, the drilling in the third step 106 is performed from the same face of the substrate 11 which the resonators are formed on. In the third step 106 of Fig. 3, the direction of drilling is shown by a second direction arrow Y. Drilling from the opposite side can be performed by, between the second and third steps 104, 106, rotating the substrate 11 by 180 degrees (i.e. flipping it). The substrate 11 is re-aligned with the grinding pin before drilling the second portion 15b of the aperture. In this way, the first and second portions 15a, 15b of the aperture form one continuous aperture 15 through the substrate 11. It should be understood that the first and second direction arrows X and Y are indicative of a direction with respect to the faces 11a, 11 b of the substrate 11. The direction of the arrows X, Y may therefore change as the orientation of the substrate 11 is changed. For example, if rotating the substrate 11 by 180 degrees between the second and third steps 104, 106, the drill need not be moved and so the first and second direction X, Y will be the same in free space (e.g. from the point of the observer) while still providing drilling in opposing directions with respect to the faces 11a, 11 b of the substrate 11. The drilling in the third step 106 may use substantially the same drilling parameters compared to the second step 104. For example, where a micrograin tool with a 600 pm diamond grinding pin following a helical tool path is used in the second step 104, the same 600 pm diamond grinding pin following a helical tool path can be used in the third step 106. Beneficially, this can ensure consistency of both portions 15a, 15b of the aperture. Consistency may include consistency of wall roughness, angle of incidence, alignment, diameter etc. In an alternative implementation, the second step 104 may comprise drilling from the second face 11b and the third step 106 may comprise drilling from the first face 11a. In implementations where two drilling steps are performed, it is beneficial to perform each drilling step from an opposite face of the substrate 11 but the first face 11a need not be drilled first. Performing drilling from both sides (i.e. faces 11a, 11b) of the substrate 11 is particularly beneficial when machining sapphire due to its high hardness and relatively low fracture toughness. Typically, when drilling through a sapphire substrate in a single direction, the sapphire is prone to severe breakout on the rear face (i.e. the face which is opposite to the face in which drilling begins from) as breakout occurs as the grinding pin exits the rear face of the substrate. Drilling from both sides of the substrate (e.g. drilling a first portion 15a of the aperture 15 from a first face 11a and a second portion 15b of the aperture 15 from a second, opposing face 11b significantly reduces the appearance and severity of breakout. Breakout refers to irregularities in structure (or deviations from a desired structure) around the aperture, for example damage or departure from the desired aperture. With an aperture with no breakout, a substantially 90 degree angle may be formed between the face (e.g. 11a, 11 b) of the substrate 11 and the walls of the aperture 15. With an aperture with breakout, there may instead be portions of nonperpendicularity between the substrate face and the walls of the aperture, for example a staggered profile where the aperture begins with a wider aperture than desired which gradually tapers to the desired aperture. The depth of drilling performed in the second and third steps 104, 106 may be chosen depending on, for example, the thickness of the substrate 11. In an example, the second step 104 may include drilling to a depth of 40% of the thickness of the substrate 11 and the third step 106 may include drilling to a depth of 60% of the thickness of the substrate 11. That is, the ratio of drilling on the first side to the second side is 40:60. In other examples, other ratios may be used, for example 20:80, 30:70, 50:50, 60:40, 70:30, 80:20 or any other ratio not specifically mentioned herein. In a specific example where the substrate thickness is 500 pm, the second step 104 can include drilling the first portion 15a of the aperture to a depth of 225 pm and the third step 106 includes drilling the second portion 15b of the aperture to a depth of 275 pm. As such, the ratio used in the example is 45:55. It should be understood that, while this two-stage drilling process for the formation of vias is particularly beneficial, for example for reducing breakout, it is optional. In alternative implementations, the aperture can be drilled in a single step from a single face of the substrate. That is, in some implementations the second step 104 may include drilling the entire aperture from the first face 11a of the substrate 11 and the third step may be obviated. In yet another example, rather than drilling (e.g. using micromachining), the aperture may be formed using laser drilling, or any other means for providing an aperture in the substrate. In these other examples, the aperture is formed after formation of the qubits, for example in place of the second and / or third steps 104, 106. In general, the inventors have realised that it is useful to fabricate the vias after the qubits have been fabricated. It has previously been through that fabricating the qubits (and optionally resonators) as a final step in the fabrication process flow beneficially reduces the risk of damage to the qubits (and resonators), for example because accelerated aging (e.g. by heating) or electrostatic damage can occur in subsequent processing steps. The inventors have surprisingly found that forming the vias after qubit formation does not negatively affect the quality and / or performance of the qubits. Rather, the inventors have found that forming the vias after qubit formation can improve the quality and / or performance of the qubits, compared to qubits which were formed after via formation. The reason for the improved quality and performance is as follows. When fabricating qubits and / or resonators subsequently, the fabrication process includes the deposition of a resist such as a photoresist or an e-beam resist. Typically, the resist is “spun-on”. In this process, resist is deposited on the chip and then the chip is spun to uniformly deposit the resist. When an aperture (e.g. a via) is formed in a substrate, the aperture causes flow issues for the resist during spinning, leading to inhomogeneity or uneveness in the resist. Inhomogeneity in the resist leads to inhomogeneity in the layer which is patterned using the resist. For example, if the resist is uneven, then it is difficult to evenly expose and develop the resist to pattern the resist. This means that during patterning of the resist, parts of the resist which are to be removed may not be evenly removed and parts of the resist which are to remain may also be uneven. Thus, a subsequent metal deposition and lift off process might result in either unwanted metal being left on the chip and / or metal being not present where required on the chip. Similarly, if a resist is patterned to be used as an etch mask, then the uneven patterning of the resist can result in some metal which is to be removed by the etch not being removed and some metal which is not be removed, being removed. Thus, the presence of the vias during the spinning process can affect the subsequent processing steps, for example the application of and removal of the superconducting material for formation of the qubits / resonators. Figs. 4A and 4B depict optical micrographs showing resist inhomogeneity surrounding an aperture 15 in a substrate 11. Fig. 4A shows the area immediately surrounding the aperture 15 on a microscale. Variation in the form of striations can be seen in the photoresist, indicative of inhomogeneity. Also seen in Fig. 4A are small particles 40 surrounding the aperture. These particles 40 represent contamination following the formation of the aperture. Fig. 4B shows a chip comprising qubits on a substrate and a through-substrate aperture, at a distance of 1.5 mm from the aperture. Variations in the form of striations can be seen in the photoresist, indicating that inhomogeneity is still seen on a macroscale. The inhomogeneity caused by aperture formation, illustrated in Figs. 4A and 4B, are such that it is difficult to consistently form high quality qubits (and resonators) on the substrate. The inhomogeneity in the photoresist can cause inhomogeneity in the applied superconducting material and / or cause material to be deposited or removed in undesired locations. In general, while some of the qubits and resonators formed may be of high quality, there is generally a large variation in the properties. Using the methods described herein, wherein the vias are formed after the qubits and / or resonators, qubits and resonators with a lower variation in quality (e.g. feature size, lifetime etc.) can be formed compared to when vias are formed before the qubits and / or resonators. As mentioned above, inhomogeneity and unevenness in the resist can result in unwanted material around the aperture. Such unwanted material being metallisation due to uneven or inhomogeneous resist. As such, a quantum computation chip fabricated using the methods described herein may be characterized by a lack of unwanted material on the face of the substrate proximal to the via(s) formed therein. There may be substantially zero unwanted material surrounding the vias. Unwanted material may comprise any material which is not the substrate and / or any irregular or non-repeating shapes. For example, unwanted material may comprise material which was intended to be deposited at areas of the chip which are away from the via. A desired material may be, for example, a protective film provided to the substrate. The unwanted material may be irregular in shape and not provided in a repeating pattern. The unwanted material may have a size that is substantially smaller than the diameter of the aperture. The unwanted materialmay have a size smaller than 100 nm, smaller than 50 nm, or smaller than 10 nm, for example. The unwanted material may protrude (e.g. extend at least partially perpendicularly) from the surface (i.e. the first and / or second face 11a, 11 b) of the substrate 11. Returning to Fig. 3, the method depicted in Fig. 3 can optionally include an additional step associated with metallising the via. The additional step 108 may be referred to as a metallisation step. The metallisation step 108 is performed after the third step 106. In the metallisation step 105, the via 15 is metallised. Metallisation can include providing a thin layer 30 (e.g. on the order of hundreds of nanometers) of metal through the aperture. The metal can be provided using a deposition tool, for example electron-beam deposition, although other methods may also be used (e.g. sputtering, cold metal injection). In an example, a layer of approximately 300 nm is provided. In an example, the metal is aluminium, although other metals can be used, for example Nb, Ta, TiN.. The metallisation step 105 can include two metal deposition sub-steps with a milling step between the first and second metal deposition sub-steps. The sub-steps may comprise e-beam deposition. For example, metal can be deposited in a first sub-step on a first face in an e-beam evaporator. Following this first sub-step, the wafer is turned over. The wafer may need to be removed from the evaporator to be turned so that evaporation will occur from towards the second face of the wafer. The aperture is milled to be provide a better surface for deposition in the via. Then, more metal deposited in a second substep. The intermediate milling can improve ohmic contact. The substrate can be rotated during the deposition of metal to ensure full coverage of the aperture walls. A quantum computation chip fabricated using the methods described herein and with a metallisation layer 30 applied to the aperture may be characterized by a lack of bodies of additional material (e.g. metal) on the face of the substrate proximal to the via(s) formed therein. However, the metallisation layer 30 will be seen immediately adjacent the aperture, and most likely not protruding from the surface of the substrate. The bodies of additional material may protrude from the surface of the substrate. The bodies of additional material may have a size that is substantially smaller than the thickness of the metallisation layer 30, e.g. smaller than 300 nm. The bodies may have a size smaller than 100 nm, smaller than 50 nm, or smaller than 10 nm, for example. Figs. 5A and 5B illustrate the performance of a plurality of qubits before and after drilling a via in an experimental example. Fig. 5A depicts an example layout of fifty six 12 surrounding an aperture 15 (i.e. a via). In this example, ten of these formations were fabricated on a single substrate. The resulting chip therefore comprised a substrate with ten apertures 15, each surrounded by fifth six qubits 12, each in the form of a Josephson junction. In a first step (corresponding to the first step 102 of the above described method), the qubits 12 were fabricated on the substrate. Following this, the performance of the qubits 12 was tested. In a second step (corresponding to the second and third steps 104, 106 of the above described method), an aperture 15 was drilled in the centre of each formation of qubits 12. Following this, the performance of the qubits 12 was tested again. Fig. 5B depicts the variation in resistance of the plurality of qubits 12 both before 50 and after 52 the apertures were drilled. The spread in resistance of the qubits 12 prior to drilling was 2.35%. Following drilling, the spread in resistance of the qubits 12 increased slightly to 2.58%. Furthermore, the performance of the qubits 12 was measured before and after aperture formation. It was found that the number of working qubits 12 (e.g. not open-circuit or short-circuit) prior to aperture formation was 98.93%. Following drilling, of the working qubits 12 prior to drilling, 99.28% of the qubits 12 were still functional. As such, the formation of apertures following qubit formation maintained an almost 100% aperture formation success rate. It can be seen in Fig. 5B that the average resistance of the qubits 12 increased after aperture formation. The resulting chip comprising qubits and apertures was further processed into a 32 qubit quantum processing unit (QPU). The performance of the qubits was subsequently tested. The variation in resistance increased slightly to 3.12%. The increase in spread may again be due to aging and / or further processing processes (e.g. cutting of the substrate to form the final chip). This process was repeated three times to prepare three quantum 32 qubit QPUs. The resulting QPUs had toshiko 1 values of 66.4, 69.2 and 69.4 ps. The resulting QPUs had Toshiko 2e values of 88.6, 105.2 and 102.6 ps. As such, the resulting QPUs are demonstrated to be compatible with the manufacture of high coherence qubits and QPUs. In the above description, sometimes QPUs are sometimes referred to more simply as chips. Qubits may be of a Josephson junction type, or any other type, for example Dolan bridge, Manhattan style etc. Fig. 6 is a photograph of a via in a quantum computation chip 101 where a via 103 was formed prior to the Josephson Junctions. Metallisation 105 is seen around the edge of the via 101. The metallisation is due to the via 103 causing non-uniformity in the resist which is spun on after the formation of the vias. During the subsequent fabrication of the Josephson junctions, variations in the thickness of the resist around the edge of the via make it difficult to properly expose the resist and therefore metal from the step of forming the Josephson junctions can be left. Whilst certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel devices, and methods described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in 1 the form of the devices, methods and products described herein may be made without 2 departing from the spirit of the inventions. The accompanying claims and their 3 equivalents are intended to cover such forms or modifications as would fall within the 4 scope and spirit of the inventions.

Claims

1. A method of fabricating a quantum computing chip, comprising:forming one or more qubits on a first face of a sapphire substrate;after forming the one or more qubits, forming an aperture in the substrate, the aperture extending between the first face of the substrate and a second opposing face of the substrate.

2. The method of claim 1, wherein forming the aperture in the sapphire substrate comprises drilling the aperture using micromachining.

3. The method of claim 1 or 2, wherein forming the aperture in the sapphire substrate comprises:drilling a first portion of the aperture extending from the first face of the substrate towards, but not extending through, the second face of the substrate;drilling a second portion of the aperture extending from the second face of the towards the first portion of the aperture, so as to form a single continuous aperture.

4. The method of claim 2 or 3, wherein the micromachining uses a helical tool path.

5. The method of any preceding claim, wherein forming one or more qubits on thefirst face of the substrate comprises:depositing a layer of superconducting material on the first face of the substrate;selectively removing one or more portions of the superconducting material so as to form a pattern of superconducting features which cooperatively form the one or more qubits.

6. The method of claim 5, wherein selectively removing one or more portions of the superconducting material comprises:providing a resist layer on top of the layer of superconducting material;exposing a patterned portion of the resist layer to radiation;developing the resist layer to form a patterned resist layer; andremoving any superconducting material not covered by the resist layer.12345678910111213141516171819202122232425262728293031323334357. The method of claim 5, wherein depositing a layer of superconducting material on the first face of the substrate and selectively removing one or more portions of the superconducting material comprises:providing a resist layer;exposing a patterned portion of the resist layer to radiation;developing the resist layer to form a patterned resist layer;depositing superconducting material on the patterned resist layer; and performing a lift-off process to selectively removing one or more portions of the superconducting material.

8. The method of any preceding claim further comprising, after forming the aperture, providing a layer of metal on the walls of the aperture.

9. The method of any preceding claim further comprising, before forming the aperture, forming one or more resonators on the second face of the substrate, each resonator corresponding to and aligned with a corresponding one of the one or more qubits.

10. A method of fabricating a quantum computing chip, comprising:forming an aperture in the substrate, the aperture extending between the first face of the substrate and a second opposing face of the substrate.wherein forming the aperture in the sapphire substrate comprises:drilling a first portion of the aperture via micromachining extending from the first face of the substrate towards, but not extending through, the second face of the substrate;drilling a second portion of the aperture via micromachining extending from the second face of the towards the first portion of the aperture, so as to form a single continuous aperture,the method further comprising forming one or more qubits on the first face of a sapphire substrate.

11. A method according to claim 10, wherein the drilling of the first portion and the drilling of the second portion is performed after forming one or more qubits on the first face of a sapphire substrate.

12. A quantum computation chip comprising:a sapphire substrate;one or more qubits on a first face of the substrate;one or more resonators on a second face of the substrate, the second face opposing the first face, each resonator corresponding to and aligned with a corresponding one of the one or more qubits; andone or more apertures, each aperture extending between the first and second faces of the substrate;wherein there are substantially no bodies of unwanted material on the first and / or second face of the substrate in a region proximal to the aperture.

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