Clock tree

Abstract

A clock tree 900 comprises a first clock buffer 906 electrically connected to a second clock buffer 910. The first clock buffer comprises a first transistor 972, a second transistor 974, a first resis

Description

Technical Field

[0001] The present invention relates to a clock tree, an integrated circuit (IC) comprising a clock tree, a device comprising the clock circuit or IC, and a method of manufacturing the clock tree, IC or device. Background

[0002] For an IC to function it is often required that components of the IC are temporally synchronised or substantially temporally synchronised. A clock generator is commonly used to generate a reference clock signal for synchronising the components. A clock tree is used as a distribution network to deliver a clock signal based on the reference clock signal to components of the IC. Each component ideally receives its respective clock signal synchronously or substantially synchronously. This enables the components to operate synchronously or substantially synchronously. If the timing of a clock signal received by a component differs from that of the reference clock signal (is ‘skewed’), e.g., due to the clock tree, it can have a negative impact on performance of the component that receives the clock signal and on performance of the IC. Similarly, if a high period ora low period of a clock signal is lost or significantly reduced, it can have a negative impact on performance of the component that receives the clock signal. It is desirable to provide clock trees that provide a clock signal to components with reduced or minimal skew without loss or significant reduction in the high period or the low period. Clock trees often include clock buffers to maintain the timing, high periods and low periods of the clock signal which facilitate the components receiving a clock signal that enables normal functioning of the component.

[0003] A clock buffer typically comprises a complementary metal oxide semiconductor (CMOS) push-pull transistor pair. Such a CMOS push-pull transistor pair includes: a p-channel metal oxide semiconductor (PMOS) transistor and an n-channel metal oxide semiconductor (NMOS) transistor. The complementary operation of the PMOS and NMOS transistors when the CMOS push-pull transistor pair is in use ensures that for any binary state input (e.g., on or off) into the CMOS push-pull transistor pair, there is no (or substantially no) leakage path to a voltage supply and / or a ground. If a clock buffer is manufactured with only NMOS or only PMOS transistors there will be a leakage path to a voltage supply and / or ground for at least one input into the clock buffer. This leakage can be reduced by including a resistor in the clock buffer; however, this can cause an imbalance in the rise and fall times of a signal output by the clock buffer. So, when several said clock buffers are combined in series, they can cause skew and / or loss of a high period or a low period.

[0004] Some semiconductor materials, e.g., indium gallium zinc oxide (InGaZnO or IGZO), are mono-type, so can usually only be used to manufacture monopolar transistors all with the same polarity, e.g., either only NMOS transistors or only PMOS transistors. So, such mono-type semiconductors alone cannot be used to manufacture a CMOS push-pull transistor pair. Previously this limitation has been overcome using heterogeneous integration of two different semiconductors (e.g., combining IGZO NMOS transistors with organic semiconductor PMOS transistors); however, such heterogeneous integration can be associated with decreased performance and increased complexity and / or cost of manufacture. So, it is desirable to provide a clock tree design wherein all the transistors are a common polarity, e.g., NMOS only or PMOS only. Further, it is desirable to provide clock buffers with transistors of a common polarity which can be connected in series without inducing skew or loss of a high period or a low period.

[0005] The present disclosure seeks to mitigate the above-mentioned problems. Alternatively, or additionally, the present disclosure seeks to provide at least one of an improved: clock tree, IC, device, or, method of manufacturing a clock tree, IC, or device. Summary

[0006] The present disclosure provides, according to a first aspect, a clock tree comprising: a first clock buffer comprising a first transistor, a second transistor, a first resistor, and a second resistor; and a second clock buffer comprising a third transistor, a fourth transistor, a fifth transistor, and a third resistor, wherein: an output of the first clock buffer is electrically connected to the second resistor and the second transistor; an output of the second clock buffer is electrically connected to a drain terminal of the fourth transistor and a source terminal of the fifth transistor; the first clock buffer is electrically connected to the second clock buffer; and each of the first, second, third, fourth, and fifth transistors are a common polarity.

[0007] It was found that, when the first clock buffer is in use, an output of the first clock buffer has a reduced length high period compared to an input of the first clock buffer (detailed below in relation to Figure 2). It was also found that an output of the second clock buffer has an increased length high period compared to an input of the first clock buffer (detailed below in relation to Figure 2). So, electrically connecting the first clock buffer and the second clock buffer may facilitate the clock tree to output a clock signal to a component of an IC, the clock signal having a balanced high period and low period and / or a clock signal provided to a component of an IC by the clock tree having a mark-space ratio similar to that of a reference clock signal input into the clock tree.

[0008] It was found that if too many first clock buffers are provided in series in a clock tree without a second clock buffer, the high period is lost. Contrastingly, if too many second clock buffers are provided in series in a clock tree without a first clock buffer, the low period is lost. So, the claimed combination of a first clock buffer and a second clock buffer may facilitate functional clock trees comprising a greater number of clock buffers than is possible with either a plurality of first clock buffers only or a plurality of second clock buffers only.

[0009] Each of the first, second, third, fourth, and fifth transistors being the common polarity may allow the manufacture of the clock tree with a mono-type semiconductor (e.g., IGZO) without the need for heterogeneous integration or another method of providing complementary transistors.

[0010] In some examples, the second clock buffer is a pseudo-CMOS buffer (PCMOS). This, in combination with the transistors of the second clock buffer having the common polarity, may facilitate the second clock buffer having properties similar to those of a CMOS buffer and being manufactured with a mono-type semiconductor material.

[0011] The present disclosure provides, according to a second aspect, a clock tree comprising: a first clock buffer comprising a first transistor and a first resistor; and a second clock buffer comprising a second transistor, a third transistor, a fourth transistor, and a second resistor, wherein: an output of the first clock buffer is electrically connected to the first resistor and the first transistor; an output of the second clock buffer is electrically connected to a drain terminal of the third transistor and a source terminal of the fourth transistor; the first clock buffer is electrically connected to the second clock buffer; and each of the first, second, third, and fourth transistors are a common polarity.

[0012] The present disclosure provides, according to a third aspect, an IC comprising the clock tree of the first or second aspect. This may facilitate incorporation of the clock tree with the IC

[0013] The present disclosure provides, according to a fourth aspect, a device comprising the clock tree of the first or second aspect or the IC of the third aspect. This may facilitate incorporation of the clock tree with the device.

[0014] The present disclosure provides, according to a fifth aspect, a method of manufacturing the clock tree of the first or second aspect.

[0015] The present disclosure provides, according to a sixth aspect, a method of manufacturing the IC of the third aspect.

[0016] The present disclosure provides, according to a seventh aspect, a method of manufacturing the device of the fourth aspect.

[0017] It will of course be appreciated that features described herein in relation to one aspect of the present disclosure may be incorporated into other aspects of the present disclosure. For example, the method of the disclosure may incorporate any of the features described with reference to the clock tree of the disclosure and vice versa. Brief Description of the Drawings Figure 1 shows schematically, in accordance with a first example, an IC comprising a clock tree of examples; Figure 2 shows schematically, example signals output by a clock signal generator, a first clock buffer, and a second clock buffer of examples; Figures 3 to 8 show schematic circuit diagrams of example clock buffers of the clock tree of the first example; Figures 9 and 10 show schematically, ICs in accordance with second and third examples respectively; Figures 11 and 12 show schematically, devices in accordance with fourth and fifth examples respectively; and Figure 13 shows a flow diagram of a method of manufacturing a clock tree in accordance with a sixth example. Detailed Description

[0018] Examples are now described with reference to the Figures. A description of some terms and features used when describing the examples is given at the end of the detailed description.

[0019] A first example of a clock tree 100 and IC 192 are now described with reference to Figure 1. The IC 192 includes the clock tree 100, a clock signal generator 102, and a component 114. The clock tree 100 includes a first clock buffer 106 and a second clock buffer 110. The first clock buffer 106 is electrically connected to the second clock buffer 110. In some examples, such as that of Figure 1, the first clock buffer 106 is directly electrically connected to the second clock buffer 110 without a component between. In other examples, the first clock buffer is indirectly electrically connected to the second clock buffer, e.g., with a component of the IC or the clock tree between. The clock tree 100 is electrically connected to a clock signal generator 102 and the component 114 of the IC 192. An input of the first clock buffer 106 is electrically connected to a clock signal generator 102 by a first wire 104. An output of the first clock buffer 106 is electrically connected to an input of the second clock buffer 110 by a second wire 108. The second clock buffer 110 is electrically connected to the component 114 by a third wire 112. In other examples the input of the first clock buffer is electrically connected to the output of the second clock buffer. Further, in other examples, neither the first clock buffer nor the second clock buffer is directly electrically connected to the clock signal generator or the component; it is envisaged that in other examples components of the clock tree are between the clock buffers and the clock signal generator and / or the component. In other examples, the clock tree includes a plurality of first clock buffers and / or a plurality of second clock buffers, e.g., between the clock signal generator and the first clock buffer and / or between the second clock buffer and the component.

[0020] The clock signal generator 102, when in use, outputs a reference clock signal to the first clock buffer 106 by the first wire 104, the reference clock signal having a high period and a low period. The clock signal generator 102 is not comprised by the clock tree 100; in other examples the clock signal generator is comprised by the clock tree. In other examples, the clock signal generator is not electrically connected to the clock tree nor comprised by the IC, e.g., the clock signal generator may be comprised by a further IC and the reference clock signal may be communicated to the IC, e.g., by an optical or radio communication system.

[0021] The first clock buffer 106 includes a first transistor, a second transistor, a first resistor, and a second resistor (e.g., as shown in Figures 3 and 4). The output of the first clock buffer 106 is electrically connected to the second resistor and the second transistor. Several configurations of the first clock buffer are envisaged, two example configurations are given in Figures 3 and 4. The first buffer is either an NMOS clock buffer wherein the first transistor and the second transistor are NMOS transistors, or a PMOS clock buffer wherein the first transistor and the second transistor are PMOS transistors.

[0022] In other examples (such as some examples of the second aspect), the first clock buffer includes a first transistor, and a first resistor. The output of the first clock buffer is electrically connected to the first resistor and the first transistor. Several configurations of the first clock buffer are envisaged. The first buffer is either an NMOS clock buffer wherein the first transistor is an NMOS transistor, or a PMOS clock buffer wherein the first transistor is a PMOS transistor. In some such examples the first clock buffer does not comprise a second transistor and / or a second resistor. For clock buffers comprising a first clock buffer of these examples, the third, fourth, fifth, and / or sixth transistors described herein may be referred to as second, third, fourth, and / or fifth transistors respectively. Similarly, for clock buffers comprising a first clock buffer of these examples, the third and / or fourth resistors herein may be referred to as second and / or third resistors respectively.

[0023] The second clock buffer 110 includes a third transistor, a fourth transistor, a fifth transistor, and a third resistor (e.g., as shown in Figures 5 to 8). An output of the second clock buffer is electrically connected to a drain terminal of the fourth transistor and a source terminal of the fifth transistor. Several configurations of the second clock buffer are envisaged, example configurations are given in Figures 5 to 8. The second clock buffer is a PCMOS clock buffer.

[0024] In some examples, the first clock buffer and the second clock buffer are each combinational circuits, comprising elements such as a buffer or an inverter. In some such examples the first clock buffer and / or the second clock buffer do not include a sequential circuit, such as a flip-flop.

[0025] Each of the first, second, third, fourth, and fifth transistors (of the first clock buffer 106 and the second clock buffer 110) are a common polarity, e.g. NMOS or PMOS. In some examples, such as those of Figure 1, all the transistors of the IC 192 are the common polarity. In other examples, the IC comprises a transistor not of the common polarity, e.g., due to heterogeneous integration of the transistor not of the common polarity into the IC. In this example and in some other examples, respective channels of the first, second, third, fourth, and fifth transistors are comprised by a semiconductor layer. This may facilitate simplified and / or cheaper manufacture of the channels of the first, second, third, fourth, and fifth transistors. In other examples, the transistors are comprised by different layers, e.g., the first and second transistors comprised by a first semiconductor layer, and the third, fourth, and fifth transistors comprised by a second semiconductor layer.

[0026] The component 114 is an electrical component. In other examples the component is any component of the IC requiring a clock signal.

[0027] The first 104, second 108, and third 112 wires are formed of electrically conductive material. Other electrical connections between the components of the first example are envisaged, e.g., traces, tracking, vias etc.

[0028] Example signals output by the signal generator, the first clock buffer, and the second clock buffer, e.g. those of the first example, are now described with reference to Figure 2. The signals are voltages (indicated with a y-axis 242), against time (indicated with an x-axis 240).

[0029] A first signal 216 is an example reference clock signal output by a clock signal generator of some examples. The first signal 216 has high periods 218 and low periods 220. A rise time of the first signal 216 (a time period of the transitions from the low periods 220 to the high periods 218) is significantly less than a length of time of one of the high periods 218 and a length of time of one of the low periods 220. A mark-space ratio of the first signal 216 is 1:1; a duty cycle of the first signal 216 is 50%. Other mark-space ratios and duty cycles are envisaged, e.g., mark-space ratios from 1:9 to 9:1 and / or duty cycles from 10% to 90%. The first signal 216 is a square wave function, other functions are envisaged such as substantially a square wave function or a square wave function convoluted with a sinusoidal function.

[0030] A second signal 222 is an example clock signal output by a first clock buffer of some examples when the first signal 216 is input into the first clock buffer. The second signal 222 has high periods 224 and low periods 226. The first clock buffer causes a rise time of the second signal 222 to be greater than the rise time of the first signal 216, and a length of a high period of the high periods 224 to be less than that of the first signal 216. A mark-space ratio of the second signal 222 is 1:3, and a duty cycle of the second signal 222 is 15%. It was found that (in examples not claimed) if several first clock buffers are electrically connected in series without a second clock buffer: the high periods are lost, the high periods are substantially lost, the duty cycle becomes no more than 10%, the duty cycle becomes 0% and / or the mark-space ratio becomes 0:1.

[0031] A third signal 228 is an example clock signal output by a second clock buffer of some examples when the first signal 216 is input into the second clock buffer. The third signal 228 has high periods 230 and low periods 232. The second clock buffer causes a rise time of the third signal 228 to be greater than the rise time of the first signal 216 and the second signal 222, and a length of a high period of the high periods 224 to be greater than that of the first signal 216 and the second signal 222. A mark-space ratio of the third signal 228 is 3:1, and a duty cycle of the third signal 228 is 70%. It was found that (in examples not claimed) if several second clock buffers are electrically connected in series without a first clock buffer: the low periods are lost, the low periods are substantially lost, the duty cycle becomes no less than 90%, the duty cycle becomes 100%, and / or the mark-space ratio becomes 1:0.

[0032] A fourth signal 234 is an example clock signal output by a clock tree of some examples when the first signal 216 is input into the clock tree. The fourth signal 234 has high periods 236 and low periods 238. The clock tree causes a rise time of the fourth signal 234 to be less than the rise time of the second signal 222 and the third signal 228, and a length of a high period of the high periods 236 to be greater than that of the second signal 224 and less than that of the third signal 228. A mark-space ratio of the fourth signal 234 is 1:1, and a duty cycle of the fourth signal 234 is 45%. It was found that (in some examples herein) if several second clock trees and / or combinations of first clock buffers and second clock buffers are electrically connected in series: the mark-space ratio of the fourth signal is from 1:9 to 9:1 and the duty cycles from 10% to 90%. So, in some examples herein, a mark-space ratio of a clock signal received by a component of the integrated circuit from the clock tree is from 1:9 to 9:1 and / or the duty cycles from 10% to 90%. This may facilitate reliable functioning of the component when the clock tree and the component are in use.

[0033] Examples of the first clock buffer 106 of Figure 1 are now described with reference to Figures 3 and 4.

[0034] An example first clock buffer 300 of the clock tree 100 of the first example is now described with reference to Figure 3. The first clock buffer 300 is an NMOS clock buffer. The first clock buffer 300 includes the first transistor 372, the second transistor 374, the first resistor 368, the second resistor 370, an input 348, and an output 350. In some examples, including that of Figure 3, the first transistor 372 and the second transistor 374 are NMOS transistors. For said examples, the third, fourth, and fifth transistors (of the second clock buffer of the clock tree, not shown in Figure 3, e.g., those of Figure 5 or 7) are also each NMOS transistors. This may facilitate the clock tree being provided by an NMOS-only semiconductor material, such as IGZO. In some such examples, including that of Figure 3, the clock tree does not comprise a PMOS transistor. This may further facilitate the clock tree being provided by an NMOS-only semiconductor material, such as IGZO, without the need for heterogeneous integration. The first clock buffer 300 is electrically connected to a first voltage supply 344 and a second voltage supply 346. The first voltage supply 344 is a source voltage supply. The second voltage supply 346 is a drain voltage supply. The input 348 is for the reference clock signal from the clock signal generator 102 by the first wire 104. In other examples the input is for an output of a further first clock buffer or an output of a second clock buffer. The output 350 is for a clock signal to the second clock buffer 110 by the second wire 108. In other examples, the output is for a clock signal to a further first clock buffer or the component of the IC.

[0035] A gate terminal of the first transistor 372 is electrically connected to the input 348. A source terminal of the first transistor 372 is electrically connected to the first voltage supply 344. A drain terminal of the first transistor 372 is electrically connected to a first end of the first resistor 368 and to a gate terminal of the second transistor 374. A second end of the first resistor 368 is electrically connected to the second voltage supply 346. A source terminal of the second transistor 374 is electrically connected to the first voltage supply 344. A drain terminal of the second transistor 374 is electrically connected to the output 350 and to a first end of the second resistor 370. A second end of the second resistor 370 is electrically connected to the second voltage supply 346. This configuration of the first clock buffer may facilitate the first buffer being an NMOS-only clock buffer with reduced and / or minimal leakage to the first voltage supply and / or the second voltage supply.

[0036] A further example first clock buffer 400 of the clock tree 100 of the first example is now described with reference to Figure 4. The first clock buffer 400 is a PMOS clock buffer. The first clock buffer 400 includes the first transistor 472, the second transistor 474, the first resistor 468, the second resistor 470, an input 448, and an output 450. In some examples, including that of Figure 4, the first transistor 472 and the second transistor 474 are PMOS transistors. For said examples, the third, fourth, and fifth transistors (of the second clock buffer of the clock tree, not shown in Figure 4, e.g., those of Figure 6 or 8) are also each PMOS transistors. This may facilitate the clock tree being provided by a PMOS-only semiconductor material, such as an organic or silicon semiconductor material. In some examples, the clock tree comprising the first clock buffer does not comprise an NMOS transistor. This may further facilitate the clock tree being provided by a PMOS-only semiconductor material, such as an organic or silicon semiconductor material without the need for heterogeneous integration. The first clock buffer 400 is electrically connected to a first voltage supply 444 and a second voltage supply 446. The first voltage supply 444 is a source voltage supply. The second voltage supply 446 is a drain voltage supply. The input 448 is for the reference clock signal from the clock signal generator 102 by the first wire 104. In other examples the input is for an output of a further first clock buffer or an output of a second clock buffer. The output 450 is for a clock signal to the second clock buffer 110 by the second wire 108. In other examples, the output is for a clock signal to a further first clock buffer or the component of the IC.

[0037] A gate terminal of the first transistor 472 is electrically connected to the input 448. A source terminal of the first transistor 472 is electrically connected to a first end of the first resistor 468 and to a gate terminal of the second transistor 474. A drain terminal of the first transistor 472 is electrically connected to the second voltage supply 446. A second end of the first resistor 468 is electrically connected to the first voltage supply 444. A source terminal of the second transistor 474 is electrically connected to the output 450 and to a first end of the second resistor 470. A drain terminal of the second transistor 474 is electrically connected to the second voltage supply 446. A second end of the second resistor 470 is electrically connected to the first voltage supply 444. This configuration of the first clock buffer may facilitate the first clock buffer being a PMOS-only clock buffer with reduced and / or minimal leakage to the first voltage supply and / or the second voltage supply.

[0038] A further example first clock buffer of the clock tree 100 of the first example is now described. The further example first clock buffer is of the second aspect. The first clock buffer is an NMOS clock buffer and includes the first transistor, the first resistor, an input, and an output. In some examples, the first transistor is an NMOS transistor. For said examples, the third, fourth, and fifth transistors (as described below, which may be referred to as the second, third, and fourth transistors respectively for clock trees comprising the first clock buffer of this example) are also each NMOS transistors. In some such examples, the clock tree does not comprise a PMOS transistor. For a clock tree comprising a first clock buffer of this example, the third and / or fourth resistors herein may be referred to as second and / or third resistors respectively. The first clock buffer is electrically connected to a first voltage supply and a second voltage supply. The first voltage supply is a source voltage supply. The second voltage supply is a drain voltage supply. The input is for the reference clock signal from the clock signal generator by the first wire. In other examples the input is for an output of a further first clock buffer or an output of a second clock buffer. The output is for a clock signal to the second clock buffer by the second wire 108. In other examples, the output is for a clock signal to a further first clock buffer or the component of the IC. A gate terminal of the first transistor is electrically connected to the input. A source terminal of the first transistor is electrically connected to the first voltage supply. A drain terminal of the first transistor is electrically connected to a first end of the first resistor and to the output. A second end of the first resistor is electrically connected to the second voltage supply. This configuration of the first clock buffer may facilitate the first buffer being an NMOS-only clock buffer with reduced and / or minimal leakage to the first voltage supply and / or the second voltage supply.

[0039] A further example first clock buffer of the clock tree 100 of the first example is now described. The further example first clock buffer is of the second aspect. The first clock buffer is a PMOS clock buffer and includes the first transistor, the first resistor, an input, and an output. In some examples, the first transistor is a PMOS transistor. For said examples, the third, fourth, and fifth transistors (as described below, which may be referred to as the second, third, and fourth transistors respectively for clock trees comprising the first clock buffer of this example) are also each PMOS transistors. In some such examples, the clock tree does not comprise an NMOS transistor. For a clock tree comprising a first clock buffer of this example, the third and / or fourth resistors herein may be referred to as second and / or third resistors respectively. The first clock buffer is electrically connected to a first voltage supply and a second voltage supply. The first voltage supply is a source voltage supply. The second voltage supply is a drain voltage supply. The input is for the reference clock signal from the clock signal generator by the first wire. In other examples the input is for an output of a further first clock buffer or an output of a second clock buffer. The output is for a clock signal to the second clock buffer by the second wire 108. In other examples, the output is for a clock signal to a further first clock buffer or the component of the IC. A gate terminal of the first transistor is electrically connected to the input. A drain terminal of the first transistor is electrically connected to the second voltage supply. A source terminal of the first transistor is electrically connected to a first end of the first resistor and to the output. A second end of the first resistor is electrically connected to the first voltage supply. This configuration of the first clock buffer may facilitate the first buffer being a PMOS-only clock buffer with reduced and / or minimal leakage to the first voltage supply and / or the second voltage supply.

[0040] Examples of the second clock buffer 110 of Figure 1 are now described with reference to Figures 5 to 8.

[0041] An example second clock buffer 500 of the clock tree 100 of the first example is now described with reference to Figure 5. The second clock buffer 500 is a PCMOS clock buffer. The second clock buffer 500 includes the third transistor 580, the fourth transistor 582, the fifth transistor 584, the third resistor 576, an input 548, and an output 550. The third transistor 580, the fourth transistor 582, and the fifth transistor 584 are NMOS transistors. For example, clock trees wherein the second clock buffer 500 is that of Figure 5, the first and second transistors (of the first clock buffer of the clock tree, not shown in Figure 5, e.g., that of Figure 3) are also each NMOS transistors. In some examples, the clock tree 100 comprising the second clock buffer 500 does not comprise a PMOS transistor. The second clock buffer 500 is electrically connected to a first voltage supply 544 and to a second voltage supply 546. The first voltage supply 544 is a source voltage supply. The second voltage supply 546 is a drain voltage supply. The input 548 is for a clock signal from the first clock buffer 106 by the second wire 108. In other examples the input 548 is for a reference clock signal from the clock signal generator or an output of a further second clock buffer. The output 550 is for a clock signal to the component 114 of the IC by the third wire 112. In other examples, the output is for a clock signal to a further first clock buffer or a further second clock buffer.

[0042] A gate terminal of the third transistor 580 is electrically connected to the input 548 and to a gate terminal of the fourth transistor 582. A source terminal of the third transistor 5 is electrically connected to the first voltage supply 544. A drain terminal of the third transistor 580 is electrically connected to a first end of the third resistor 576 and to a gate terminal of the fifth transistor 584. A second end of the third resistor 576 is electrically connected to the second voltage supply 546. A source terminal of the fourth transistor 582 is electrically connected to the first voltage supply 544. A drain terminal of the fourth transistor 582 is electrically connected to the output 550 and to a source terminal of the fifth transistor 584. A drain terminal of the fifth transistor 584 is electrically connected to the second voltage supply 546. This configuration of the second clock buffer may facilitate the second clock buffer being an NMOS-transistor-only PCMOS clock buffer. Further, this configuration of the second clock buffer may facilitate the second clock buffer including an inverter.

[0043] A further example second clock buffer 600 of the clock tree 100 of the first example is now described with reference to Figure 6. The second clock buffer 600 is a PCMOS clock buffer. The second clock buffer 600 includes the third transistor 680, the fourth transistor 682, the fifth transistor 684, the third resistor 676, an input 648, and an output 650. The third transistor 680, the fourth transistor 682, and the fifth transistor 684 are PMOS transistors. For example, clock trees wherein the second clock buffer 600 is that of Figure 6, the first and second transistors (of the first clock buffer of the clock tree, not shown in Figure 6, e.g., that of Figure 4) are also each PMOS transistors. In some examples, the clock tree comprising the second clock buffer does not comprise an NMOS transistor. The second clock buffer 600 is electrically connected to a first voltage supply 644 and a second voltage supply 646. The first voltage supply 644 is a source voltage supply. The second voltage supply 646 is a drain voltage supply. The input 648 is for a clock signal from the first clock buffer 106 by the second wire 108. In other examples the input 648 is for a reference clock signal from the clock signal generator 102 or an output of a further second clock buffer. The output 650 is for a clock signal to the component 114 of the IC by the third wire 112. In other examples, the output is for a clock signal to a further first clock buffer or a further second clock buffer.

[0044] A gate terminal of the third transistor 680 is electrically connected to the input 648 and to a gate terminal of the fourth transistor 682. A drain terminal of the third transistor 680 is electrically connected to the second voltage supply 646. A source terminal of the third transistor 680 is electrically connected to a first end of the third resistor 676 and to a gate terminal of the fifth transistor 684. A second end of the third resistor 676 is electrically connected to the first voltage supply 644. A drain terminal of the fourth transistor 682 is electrically connected to the second voltage supply 646. A source terminal of the fourth transistor 682 is electrically connected to the output 650 and to a drain terminal of the fifth transistor 684. A source terminal of the fifth transistor 684 is electrically connected to the first voltage supply 644. This configuration of the second clock buffer may facilitate the second clock buffer being an PMOS-transistor-only PCMOS clock buffer. Further, this configuration of the second clock buffer may facilitate the second clock buffer including an inverter.

[0045] A further example second clock buffer 700 of the clock tree 100 of the first example is now described with reference to Figure 7. The second clock buffer 700 is an PCMOS clock buffer. The second clock buffer 700 includes the third transistor 780, the fourth transistor 782, the fifth transistor 784, a sixth transistor 786, the third resistor 776, a fourth resistor 778, an input 748, and an output 750. The third transistor 780, the fourth transistor 782, the fifth transistor 784, and the sixth transistor 786 are NMOS transistors. In some examples, such as that of Figure 7, each of the first, second, third, fourth, fifth, and sixth transistors are a common polarity (NMOS). For example, clock trees wherein the second clock buffer 700 is that of Figure 7, the first and second transistors (of the first clock buffer of the clock tree, not shown in Figure 7, e.g., that of Figure 3) are also each NMOS transistors. In some examples, the clock tree comprising the second clock buffer does not comprise a PMOS transistor. The second clock buffer 700 is electrically connected to a first voltage supply 744 and a second voltage supply 746. The first voltage supply 744 is a source voltage supply. The second voltage supply 746 is a drain voltage supply. The input 748 is for a clock signal from the first clock buffer 106 by the second wire 108. In other examples the input 748 is for a reference clock signal from the clock signal generator 102 or an output of a further second clock buffer. The output 750 is for a clock signal to the component 114 of the IC by the third wire 112. In other examples, the output is for a clock signal to a further first clock buffer or a further second clock buffer.

[0046] A gate terminal of the third transistor 780 is electrically connected to the input 748. A drain terminal of the third transistor 780 is electrically connected to a first end of the third resistor 776, to a gate terminal of the fourth transistor 782, and to a gate terminal of the sixth transistor 786. A source terminal of the third transistor 780 is electrically connected to the first voltage supply 744. A second end of the third resistor 776 is electrically connected to the second voltage supply 746. A source terminal of the sixth transistor 786 is electrically connected to the first voltage supply 744. A drain terminal of the sixth transistor is electrically connected to a first end of the fourth resistor 778 and to a gate terminal of the fifth transistor 784. A second end of the fourth resistor 778 is electrically connected to the second voltage supply 746. A drain terminal of the fifth transistor 784 is electrically connected to the second voltage supply 746. A source terminal of the fourth transistor 782 is electrically connected to the first voltage supply 744. A drain terminal of the fourth transistor 782 is electrically connected to a source terminal of the fifth transistor 784 and to the output 750. This configuration of the second clock buffer may facilitate the second clock buffer being an NMOS-transistor-only PCMOS clock buffer.

[0047] A further example second clock buffer 800 of the clock tree 100 of the first example is now described with reference to Figure 8. The second clock buffer 800 is a PCMOS clock buffer. The second clock buffer 800 includes the third transistor 880, the fourth transistor 882, the fifth transistor 884, a sixth transistor 886, the third resistor 876, a fourth resistor 878, an input 848, and an output 850. The third transistor 880, the fourth transistor 882, the fifth transistor 884, and the sixth transistor 886 are PMOS transistors. For example clock trees wherein the second clock buffer 800 is that of Figure 8, the first and second transistors (of the first clock buffer of the clock tree, not shown in Figure 8, e.g., that of Figure 4) are also each PMOS transistors. In some examples, the clock tree comprising the second clock buffer does not comprise an NMOS transistor. The second clock buffer 800 is electrically connected to a first voltage supply 844 and to a second voltage supply 846. The first voltage supply 844 is a source voltage supply. The second voltage supply 846 is a drain voltage supply. The input 848 is for a clock signal from the first clock buffer 106 by the second wire 108. In other examples the input 848 is for a reference clock signal from the clock signal generator 102 or an output of a further second clock buffer. The output 850 is for a clock signal to the component 114 of the IC by the third wire 112. In other examples, the output is for a clock signal to a further first clock buffer or a further second clock buffer.

[0048] A gate terminal of the third transistor 880 is electrically connected to the input 848. A source terminal of the third transistor 880 is electrically connected to a first end of the third resistor 876, to a gate terminal of the fourth transistor 882, and to a gate terminal of the sixth transistor 886. A second end of the third resistor 876 is electrically connected to the first voltage supply 844. A source terminal of the sixth transistor 886 is electrically connected to a first end of the fourth resistor 878 and to a gate terminal of the fifth transistor 844. A second end of the fourth resistor 878 is electrically connected to the first voltage supply 844. A source terminal of the fifth transistor 884 is electrically connected to the first voltage supply 844. A drain terminal of the fourth transistor 882 is electrically connected to the second voltage supply 846. A source terminal of the fourth transistor 882 is electrically connected to a drain terminal of the fifth transistor 884 and to the output 850. This configuration of the second clock buffer may facilitate the second clock buffer being a PMOS-transistor-only PCMOS clock buffer.

[0049] A clock tree 900 in accordance with a second example is now described with reference to Figure 9. The clock tree 900 includes a clock signal generator 902, a first clock buffer 906, a second clock buffer 910, and a component 914.

[0050] The first clock buffer 906 is similar to the first clock buffer 300 described above in relation to Figure 3. The first clock buffer 906 is an NMOS clock buffer. The first clock buffer 300 includes a first transistor 972, a second transistor 974, a first resistor 968, a second resistor 970. The first transistor 972 and the second transistor 974 are NMOS transistors. The first clock buffer 906 does not comprise a PMOS transistor. The first clock buffer 906 is electrically connected to a first voltage supply 944 and to a second voltage supply 946. The first voltage supply 944 is a source voltage supply. The second voltage supply 946 is a drain voltage supply. The first clock buffer 906 is configured to receive a reference clock signal from the clock signal generator 902 by a first wire 904. The first clock buffer 906 is configured to output a first clock signal to the second clock buffer 910 by a second wire 908.

[0051] A gate terminal of the first transistor 972 is electrically connected to the clock signal generator 902 by the first wire 904. A source terminal of the first transistor 972 is electrically connected to the first voltage supply 944. A drain terminal of the first transistor 972 is electrically connected to a first end of the first resistor 968 and to a gate terminal of the second transistor 974. A second end of the first resistor 968 is electrically connected to the second voltage supply 946. A source terminal of the second transistor 974 is electrically connected to the first voltage supply 944. A drain terminal of the second transistor 974 is electrically connected to the second clock buffer 910 by the second wire 908, and to a first end of the second resistor 970. A second end of the second resistor 970 is electrically connected to the second voltage supply 946.

[0052] The second clock buffer 910 is similar to the second clock buffer 700 described above in relation to figure 7. The second clock buffer 910 is a PCMOS clock buffer. The second clock buffer 910 includes a third transistor 980, a fourth transistor 982, a fifth transistor 984, a sixth transistor 986, a third resistor 976, and a fourth resistor 978. The third transistor 980, the fourth transistor 982, the fifth transistor 984, and the sixth transistor 986 are NMOS transistors. The second clock 910 buffer does not comprise a PMOS transistor. The second clock buffer 910 is electrically connected to the first voltage supply 944 and to the second voltage supply 946. The second clock buffer 910 is configured to receive the first clock signal from the first clock buffer 906 by the second wire 908. The second clock buffer 910 is configured to output a second clock signal to the component 914 by a third wire 912.

[0053] A gate terminal of the third transistor 980 is electrically connected to the first clock buffer 906 by the second wire 908. A drain terminal of the third transistor 980 is electrically connected to a first end of the third resistor 976, to a gate terminal of the fourth transistor 982, and to a gate terminal of the sixth transistor 986. A source terminal of the third transistor 980 is electrically connected to the first voltage supply 944. A second end of the third resistor 976 is electrically connected to the second voltage supply 946. A source terminal of the sixth transistor 986 is electrically connected to the first voltage supply 944. A drain terminal of the sixth transistor 986 is electrically connected to a first end of the fourth resistor 978 and to a gate terminal of the fifth transistor 984. A second end of the fourth resistor 978 is electrically connected to the second voltage supply 946. A drain terminal of the fifth transistor 984 is electrically connected to the second voltage supply 946. A source terminal of the fourth transistor 982 is electrically connected to the first voltage supply 944. A drain terminal of the fourth transistor 982 is electrically connected to a source terminal of the fifth transistor 984 and to the component 914 by the third wire 912.

[0054] An IC 1000 in accordance with a third example is now described with reference to Figure 10. The IC 100 includes a clock tree 1000, components 1014A, 1014B, 1014C, 1014D, 1014E, 1014F, 1014G, 1014H, 1014J, a logic circuit 1090, a first frequency domain 1089, a second frequency domain 1091, a clock signal generator 1002, and a frequency divider 1088.

[0055] The clock tree includes a clock signal generator 1002, a plurality of first clock buffers 1006A, 1006B, 1006C, 1006D, 1006E, 1006F, 1006G, and a plurality of second clock buffers 1010A, 101 OB, 101OC, 101OD. A ratio of a number of first clock buffers 1006A, 1006B, 1006C, 1006D, 1006E, 1006F, 1006G to a number of second clock buffers 101OA, 101 OB, 1010C, 1010D is 7:4 In other examples the ratio is from 20:1 to 1:20, from 10:1 to 1:10, or from 5:1 to 1:5. In a further example, the ratio is from 1:20 to 1:10. In a further example, the ratio is from 1:5 to 1:1. This may facilitate the mark-space ratio of a clock signal received by the components 1014A, 1014B, 1014C, 1014D, 1014E, 1014F, 1014G, 1014H, 1014J to be from 1:9 to 9:1. The clock tree has two branches, a first branch in the first frequency domain 1089, and a second branch in the second frequency domain 1091. The second branch splits into two sub-branches which each split into two further sub-sub-branches. Various other clock tree and branch configurations are envisaged.

[0056] The clock signal generator 1002 is similar to the clock signal generator 102 described in relation to Figure 1. When in use, the clock signal generator 1002 outputs a reference clock signal to the branches of the clock tree.

[0057] The components 1014A, 1014B, 1014C, 1014D, 1014E, 1014F, 1014G, 1014H, 1014J are each an electrical component requiring a clock signal to function.

[0058] The logic circuit 1090 is electrically connected to a first component 1014J and to a second component 1014H. The first component 1014J and the second component 1014H are of the components 1014A, 1014B, 1014C, 1014D, 1014E, 1014F, 1014G, 1014H, 1014J. The first component 1014J is of the first frequency domain 1089. The second component 1014H is of the second frequency domain 1091.

[0059] The first frequency domain 1089 has a frequency of 1.0 Megahertz (MHz). Each component of the first frequency domain 1089 is configured for signals of 1.0 MHz frequency or substantially 1.0 MHz frequency. The second frequency domain 1091 has a frequency of 0.5 MHz. Each component of the second frequency domain 1091 is configured for signals of 0.5 MHz frequency or substantially 0.5 MHz frequency. The frequency divider 1088 is for converting a 1.0 MHz frequency input from the first frequency domain 1089 to a 0.5 MHz frequency output into the second frequency domain 1091.

[0060] A device 1100 in accordance with a fourth example is now described with reference to Figure 11. The device 1100 includes an IC 1192 comprising a clock tree of examples herein, such as the clock tree of Figure 9 or 10. The device is a radiofrequency identification (RFID) device.

[0061] Other devices comprising a clock tree or IC described herein are envisaged, for example: a medical device, smart glasses, an augmented reality device, a virtual reality device, a sensing device, an audio device, a communication device, a display device, or a packaging device. Some examples herein relate to a device including a processor and / or a microprocessor comprising a clock tree or IC described herein. In some such examples, the processor and / or microprocessor is a reduced instruction set computer (RISC) processor. Further devices comprising a clock tree and / or IC described herein are envisaged, for example: an application-specific integrated circuit (ASIC), a neural network IC, a machine learning IC, an artificial intelligence IC, readonly memory (ROM), programmable ROM (PROM), memory, random-access memory (RAM), dynamic random-access memory (DRAM), static random-access memory (SRAM), and / or non-volatile memory (NVM).

[0062] A device 1200 in accordance with a fifth example is now described with reference to Figure 12. The device 1200 comprises a flexible interconnect 1294 comprising an IC as described herein. A first part 1296 of the device 1200 is flexibly connected to a second part 1298 of the device 1200.

[0063] A method 1300 of manufacturing a clock tree in accordance with a sixth example is now described with reference to Figure 13. Firstly, the method 1300 includes providing 1301 a substrate. In some examples, the substrate is provided on a carrier wafer, such as a glass or silicon wafer, to support the substrate. This may facilitate the substrate being flexible. The method 1300 then includes forming 1303 first, second, third, fourth, and fifth transistors on the substrate. Each of the first, second, third, fourth, and fifth transistors has a common polarity. Forming 1303 may comprise forming respective first, second, third, fourth, and fifth channels of the transistors. In some examples, the channels are comprised by a semiconductor layer on the substrate. The semiconductor layer is formed on the substrate. This may facilitate simplified manufacture of the channels. In some examples the semiconductor layer is directly on the substrate without anything between. In other examples, the semiconductor layer is indirectly on the substrate, e.g., with a further layer between the substrate and the semiconductor layer. The method 1300 then includes forming 1305 first, second, and third resistors. Next, the method 1300 includes forming 1307 electrical connections to provide a first clock buffer and a second clock buffer. The first clock buffer comprises the first transistor, the second transistor, the first resistor, and the second resistor. The second clock buffer comprises the third, fourth, and fifth transistors, and a third resistor. An output of the first clock buffer is electrically connected to the second resistor and the second transistor. An output of the second clock buffer is electrically connected to a drain terminal of the fourth transistor and a source terminal of the fifth transistor. The first clock buffer is electrically connected to the second clock buffer. In some examples the substrate is supported by a carrier wafer during the forming the clock circuit. This may facilitate the substrate being flexible. In other examples, the parts of the method of Figure 13 are in a different order and / or additional parts are included in the method. Further, other methods of manufacture of the clock trees, ICs, and / or devices described herein are envisaged.

[0064] A description of some terms and features used herein is now given, to elaborate on features of examples described herein.

[0065] A clock tree herein is, e.g., for part of an IC, an IC, or a device. Further, a clock tree when in use receives a reference clock signal and outputs a clock signal based on the reference clock signal to a component or components of an IC. In some examples all the components receive the same clock signal. In other examples the components each receive respective different clock signals each based on the reference clock signal.

[0066] A clock buffer herein is configured to receive an input clock signal (such as a reference clock signal or an output of a further clock buffer) and output a clock signal that is a copy or a derivative of the input clock signal, e.g., to correct skew or invert a signal. An output of a clock buffer typically mimics one or more properties of an input into the clock buffer. In some examples a clock buffer is non-inverting; in other examples a clock buffer is inverting (in which case the output of the clock buffer is an inversion or substantial inversion of the input of the clock buffer. In some examples, a clock buffer applies a gain factor or converts between voltage levels (for example, converting from 1,2V logic to 3.3V logic) between the input and the output.

[0067] A polarity of a transistor herein relates to a charge carrier of the semiconductor of the transistor that provides electrical conductivity, e.g., electrons for NMOS, or electron-holes for PMOS. For example, two NMOS transistors have a common polarity; contrastingly a NMOS transistor and a PMOS transistor do not have a common polarity. In some examples herein the transistors are monopolar (otherwise referred to as unipolar and in contrast to bipolar or ambipolar). This may facilitate the clock tree to be manufactured with a mono-type semiconductor (a semiconductor that can substantially only support one type of charge carrier: electrons or electron-holes). In some examples, the clock tree does not comprise a bipolar transistor. In some examples the clock tree does not comprise an ambipolar transistor.

[0068] In some examples, the first, second, third, fourth, and fifth transistors are monopolar. In some examples herein a channel of the first, second, third, fourth, fifth, and / or sixth transistors herein is a mono-type semiconductor. This may facilitate the transistor(s) to be manufactured with a mono-type semiconductor. In some examples, at least one of the first, second, third, fourth, or fifth transistors is a thin film transistor. This may facilitate the transistor(s), clock tree and / or IC being flexible and / or bendable, and / or manufacturable with low environmental impact and in a short time.

[0069] A PCMOS buffer herein is a buffer only including transistors with a common polarity (e.g., NMOS or PMOS) and having substantially a least some of the characteristics of a CMOS buffer and / or comparable performance to a CMOS buffer. For example, this may include a high drive strength, a substantially rail-to-rail output voltage, and / or a high fan-out capability.

[0070] An electrical connection herein may be direct (with no components in between the electrically connected parts) or indirect (with a component between the electrically connected parts). An electrical connection may be provided by a line of electrically-conductive material, a via, and / or a wire; other forms of electrical connection are envisaged.

[0071] A first voltage supply herein is a source voltage supply. In some examples, the first voltage supply is configured to provide a negative voltage, a zero voltage, a substantially zero voltage, and / or an electrical ground. Electrical ground may refer to a reference voltage in an IC and is not limited to a connection to the Earth. A second voltage supply herein is a drain voltage supply. In some examples, the second voltage supply is configured to provide a positive voltage.

[0072] A signal herein is an electrical signal. In some examples the signal is a voltagetime signal, other electrical signals are envisaged.

[0073] A mark-space ratio herein is a ratio of a length of time of a high period of a signal to a length of time of a low period of the signal. Alternatively, a mark-space ratio herein may be a ratio of an average length of time of the high periods of the signal to an average length of time of the low periods of the signal. A duty cycle herein is a percentage of one period of a signal wherein the signal is in the high period.

[0074] An IC herein is an integration of a plurality of electronic functionalities onto a single substrate, and may be referred to as a chip, or a microchip. ICs comprise components (which may be referred to as cells) for performing said electronic functions. Example components of an IC include: processors, memory, input interfaces, output interfaces, antenna, power management units, transistors, capacitors, clock circuits, modulators, and demodulators. Other components are envisaged. Components of an IC may be electrically connected.

[0075] In some examples, the IC herein is a flexible IC and / or a bendable IC. Herein, a flexible IC (otherwise referred to as a flexIC, natively flexible IC, bendable IC, or bend IC) is an IC that is designed to be flexible and conformable, allowing it to bend, twist, and conform to non-flat or irregular surfaces. Unlike traditional rigid ICs, which are typically made on silicon wafers and are inflexible, flexible IC are manufactured on flexible substrates using appropriate materials and thin-film processes.

[0076] A combinational circuit herein is a circuit wherein the circuit’s output does not depend on previous inputs, e.g., a circuit that does not include a memory element and / or cannot store a state or retain a previous input. Example combination circuits are: buffers, inverters, and logic gates such as AND, OR, NOT, NAND, and NOR. In some examples, the clock tree is a combination circuit.

[0077] A sequential circuit herein is a circuit wherein the circuit’s output may depend on previous inputs, e.g., a circuit that includes a memory element and / or can store a state or retain a previous input. Example sequential circuits are: flip-flops, counters, registers, and memories.

[0078] A frequency domain herein is a part of an IC wherein the components have a common clock frequency, such as 1 MHz, or 1 Gigahertz (GHz).

[0079] A substrate herein may be referred to as a wafer or a layer. In some examples, the first clock buffer and the second clock buffer are supported by a substrate (this may be referred to as the same substrate). This may facilitate simplified manufacture of the first clock buffer and the second clock buffer at the same time. In other examples, the first buffer and the second buffer are on the substrate and / or over the substrate. In some examples, the substrate is a disc of least one of: a glass, a dielectric, a polymer, silicon, gallium, germanium, lithium niobate, carbon, indium, an alloy of at least one of the foregoing, or a compound comprising at least one of the foregoing. This may facilitate known manufacturing techniques being used for the methods described herein. In some examples, the substrate is at least one of: a 25 millimetre, 51 millimetre, 76 millimetre, 100 millimetre, 200 millimetre, or 300 millimetre disc.

[0080] In some examples, the substrate is a polymer substrate. This may facilitate the substrate being flexible and / or bendable. Further, this may facilitate the substrate being manufactured using known techniques. A polymer herein may comprise one or more polymers selected from: polyethylene naphthalates, polyethylene terephthalates; polymethyl methacrylates; polycarbonates, polyvinyl alcohols, polyvinyl acetates, polyvinyl pyrrolidones, polyvinyl phenols, polyvinyl chlorides, polystyrenes, polyimides, polyamides (e.g. nylon); poly(hydroxy ethers), polyurethanes, polycarbonates, polysulfones, parylenes, polyarylates, polyether ether ketones (PEEKs); acrylonitrile butadiene styrene (ABS), 1 methoxy 2 propyl acetates, benzocyclobutenes (BCB), polylactic acid (PLA), polyhydroxyalkanoates (PHAs), polybutylene succinate (PBS), polybutylene adipate terephthalate (PBAT), cellulose polymers, or any other suitable polymer material.

[0081] In some examples, the substrate is from 0.5 micrometres to 40 micrometres thick, from 0.5 micrometres to 20 micrometres thick, from 1 micrometre to 10 micrometres thick, or about 5 micrometres thick. This may facilitate the substrate being flexible and / or bendable. In some examples, the IC and / or the device has a thickness of no more than 40 micrometres, about 37 micrometres, or no more than 30 micrometres.

[0082] A substrate herein may be a flexible substrate and / or a bendable substrate. The substrate may be formed of a flexible material such as an appropriate flexible polymer material, the flexible substrate may be formed from any other materials that provide suitable electrical, chemical, and / or structural properties. The flexible substrate may be formed from a single common material, may be formed from a plurality of different materials, or may be formed from a plurality of different types of the same material. A flexible substrate may, for example, comprise one or more materials selected from the following list of materials: flexible glass, polymer materials, metal oxide materials, resin materials, resist materials, foil materials, paper, insulator coated metals, or any other suitable material.

[0083] A material herein refers to an atomic composition of a channel of a transistor, a substrate, an electrical connection, a component etc. The atomic composition relates to the types of atoms included in the material in question and also to the relative quantities of those types of atoms. For example, zinc oxide (ZnO) is a particular material, while indium gallium zinc oxide (InGaZnO, also referred to as IGZO) is referred to as a different material because it also comprises indium and gallium atoms making the composition different. In some examples herein, a first IGZO with an ln:Ga:Zn stoichiometry of 1:1:1 is a different material to a second IGZO with an ln:Ga:Zn stoichiometry of 1:3:1 because the relative quantities of the types of atoms are different. In other examples, two alloys or compounds that comprise the same elements and have different stoichiometries (e.g., two stoichiometries of IGZO) are the same material.

[0084] A channel of a transistor herein is a semiconductor region within the transistor configured to allow a flow of current between the source and drain terminals when the transistor is in use. In some examples, respective channels of the at least one of the first, second, third, fourth, or fifth transistors comprises IGZO. This may facilitate the transistor(s), clock tree, and / or IC being flexible and / or bendable.

[0085] A semiconductor herein has a Fermi level within an electronic bandgap between its electronic valence and conduction bands. An energy of the electronic bandgap may be low enough for the conduction band to be thermally populated by electrons or electron holes, e.g., at 298 Kelvin. An electrical conductivity of a semiconductor may increase with temperature. An n-type semiconductor herein is a semiconductor that has been doped with an electron donor. A p-type semiconductor herein is a semiconductor that has been doped with an electron hole donor.

[0086] A semiconductor, e.g., a semiconductor of a channel of a transistor herein may be selected from one or more of: compound semiconductors, metal oxides, metal oxynitrides, inorganic semiconductors, organic semiconductors, polymer semiconductors, 2D semiconductor materials, chalcogenides, perovskites, or any other semiconductor material. For example, semiconductor materials may be selected from one or more of: GaAs, GaN, InP, CdSe, InGaAs, InGaAsSb, ZnO, SnO2, NiO, SnO, Cu2O, ln2O3, LiZnO, ZnSnO, InSnO (ITO), InZnO (IZO), HflnZnO (HIZO), InGaZnO (IGZO) ZnxOyNz amorphous, microcrystalline or nanocrystalline Si, copper(ll) phthalocyanine (CuPc), pentacene, perylenetetracarboxylic dianhydride (PTCDA), methylene blue, Orange G, rubrene; PEDOT:PSS, poly(3-octylthiophene) (POT), poly(3-octylthiophene-2,5-diyl) (P3OT), poly(3-hexylthiophene) (P3HT), polyaniline, polycarbazole, graphene, MoS2, GeSbTeSrTiOs, CHsNHsPbCh, H2NCHNH2PbCl3, CsSnh, or any other suitable semiconductor material.

[0087] Providing herein may comprise forming, as described below, or other methods of providing such as by a different method or purchase from a supplier.

[0088] Forming herein may comprise a manufacturing process, e.g., using known techniques such as lithography, photolithography, etching, heating, deposition, or spin coating.

[0089] A carrier wafer herein may be substantially planar or planar. Further, a carrier wafer herein may be a disc of crystalline semiconductor, glass, or dielectric, e.g., a 25 millimetre, 51 millimetre, 76 millimetre, 100 millimetre, 200 millimetre, or 300 millimetre disc for use in a semiconductor manufacture plant.

[0090] First, second, third, fourth, fifth, and sixth as used herein do not imply the presence of each other. For example, a third transistor herein does not limit a claim or example herein to including a second transistor. Similarly, for example, a third resistor herein does not limit the claim or example herein to including a second resistor. For example, a first clock buffer of the second aspect herein and not comprising a second transistor and / or a second resistor may be combined with a second clock buffer of any example herein also not having a second transistor and / or a second resistor and having a third resistor and a third transistor etc. without the limitation of the clock tree to including a second transistor and / or a second resistor. Further, first, second, third, fourth, fifth, and sixth as used herein do not imply an order or chronology unless explicitly stated. Further, features of the examples in the detailed description without an ordinal number (e.g. “first”) such may relate to a claim feature with an ordinal 5 number of the claims. Similarly, the ordinal number use for a feature in the examples of the detailed description may relate to a claim feature with a different ordinal number.

[0091] It is to be understood that any feature described in relation to any one example may be used alone, or in combination with other features described, and may also be used in combination with one or more features of any other of the example, or any 1 o combination of any other of the examples. Furthermore, equivalents and modifications not described above may also be employed without departing from the scope of the accompanying claims.

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