Fast checkpointing of neural network training

Abstract

The performing of fast checkpointing of training states during training of a neural network 500. In this, one or more pinned shared memory buffers are allocated to one or more neural network accelera

Description

FIELD

[0001] At least one embodiment pertains to processing resources to perform fast checkpointing during training of a neural network on a computer system that uses graphics processing unit (GPU) acceleration device(s). For example, at least one embodiment pertains implementation of a checkpoint operation that performs a memory-to-memory copy of training state information from a GPU memory to a pinned shared region of central processing unit (CPU) memory, which avoids a double copying of this information in process memory of a training process on said CPU. BACKGROUND

[0002] Training systems for training large AI models use checkpointing to reduce recovery time after failures. In systems that use GPU acceleration devices, saving a checkpoint involves transferring training state information, such as model weights, from a GPU memory' to a host memory' designated for storing said checkpoint. This transfer must be performed efficiently in applications that checkpoint very large models or take checkpoints very frequently. However, such transfer operations can be fairly' timeconsuming due to various factors, such as high error rates associated with copying data from high bandwidth memory' (HBM) used to implement GPU memory'. Small time penalties added by individual transfer operations can accumulate over time to create a significant lengthening of overall training time. SUMMARY

[0003] The invention is defined by the claims. In order to illustrate the invention, aspects and embodiments which may or may not fall within the scope of the claims are described herein.

[0004] Disclosed are apparatuses, systems, and techniques to perform fast checkpointing of training states during training of a neural network. In at least one embodiment, a checkpoint is created using a memory-to-memory copy operation that copies training state information from a graphics processing unit (GPU) memory' to a pinned shared region of a central processing unit (CPU) memory, without creating an additional copy' of this information in a process memory' allocated to a training process. The disclosure extends to any novel aspects or features described and / or illustrated herein.

[0005] Further features of the disclosure are characterized by the independent and dependent claims. [00061 Any feature in one aspect of the disclosure may be applied to other aspects of the disclosure, in any' appropriate combination. In particular, method aspects may' be applied to apparatus or system aspects, and vice versa. [00071 Furthermore, features implemented in hardware may be implemented in software, and vice versa. Any reference to software and hardware features herein should be construed accordingly.

[0008] Any system or apparatus feature as described herein may also be provided as a method feature, and vice versa. System and / or apparatus aspects described functionally (including means plus function features) may be expressed alternatively in terms of their corresponding structure, such as a suitably programmed processor and associated memory'.

[0009] It should also be appreciated that particular combinations of the various features described and defined in any aspects of the disclosure can be implemented and / or supplied and / or used independently. [09101 The disclosure also provides computer programs and computer program products comprising software code adapted, when executed on a data processing apparatus, to perform any of the methods and / or for embodying any of the apparatus and system features described herein, including any or all of the component steps of any method. [0011 j The disclosure also provides a computer or computing system (including networked or distributed systems) having an operating system which supports a computer program for carrying out any of the methods described herein and / or for embodying any of the apparatus or system features described herein.

[0012] The disclosure also provides a computer readable media having stored thereon any one or more of the computer programs aforesaid. [00131 The disclosure also provides a signal carrying any one or more of the computer programs aforesaid.

[0014] The disclosure extends to methods and / or apparatus and / or systems as herein described with reference to the accompanying drawings.

[0015] Aspects and embodiments of the disclosure will now be described purely' by' way of example, with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS [00161 FIG. 1 illustrates an example neural network training system that implements fast checkpoint creation during model training, according to at least one embodiment; [00171 FIG. 2 illustrates an example checkpoint operation that uses a memory copy API provided by an operating system, according to at least one embodiment;

[0018] FIG. 3 illustrates an example model training system that uses a supervisor process to supervise recovery* from worker node failures using checkpoints, according to at least one embodiment;

[0019] FIG. 4 illustrates an example training process that does not wait for checkpoint completion to proceed to a next training step, according to at least one embodiment; [00201 FIG. 5A illustrates an example process of a checkpoint creation during model training, according to at least one embodiment; [00211 FIG. 5B illustrates an example process performed by a supervisor process during model training, according to at least one embodiment; [00221 FIG. 6A illustrates logic, according to at least one embodiment; [00231 FIG. 6B illustrates logic, according to at least one embodiment;

[0024] FIG. 7 illustrates training and deployment of a neural network, according to at least one embodiment; [00251 FIG. 8 illustrates an example data center system, according to at least one embodiment;

[0026] FIG. 9A illustrates an example of an autonomous vehicle, according to at least one embodiment; [00271 FIG. 9B illustrates an example of camera locations and fields of view for the autonomous vehicle of FIG. 9A, according to at least one embodiment;

[0028] FIG. 9C is a block diagram illustrating an example system architecture for the autonomous vehicle of FIG. 9A, according to at least one embodiment;

[0029] FIG. 9D is a diagram illustrating a system for communication between cloud-based server(s) and the autonomous vehicle of FIG. 9A, according to at least one embodiment;

[0030] FIG. 10 is a block diagram illustrating a computer system, according to at least one embodiment; [0031 j FIG. 11 is a block diagram illustrating a computer system, according to at least one embodiment;

[0032] FIG. 12 illustrates a computer system, according to at least one embodiment;

[0033] FIG. 13 illustrates a computer system, according to at least one embodiment;

[0034] FIG. 14A illustrates a computer system, according to at least one embodiment;

[0035] FIG. I4B illustrates a computer system, according to at least one embodiment;

[0036] FIG. 14C illustrates a computer system, according to at least one embodiment; [00371 FIG. I4D illustrates a computer system, according to at least one embodiment;

[0038] FIG. 14E and I4F illustrate a shared programming model, according to at least one embodiment;

[0039] FIG. 15 illustrates exemplary integrated circuits and associated graphics processors, according to at least one embodiment;

[0040] FIGS. I6A-16B illustrate exemplary' integrated circuits and associated graphics processors, according to at least one embodiment;

[0041] FIGS. 17A-17B illustrate additional exemplary graphics processor logic according to at least one embodiment;

[0042] FIG. 18 illustrates a computer system, according to at least one embodiment;

[0043] FIG. 19A illustrates a parallel processor, according to at least one embodiment; [00441 FIG. I9B illustrates a partition unit, according to at least one embodiment; [00451 FIG. 19C illustrates a processing cluster, according to at least one embodiment;

[0046] FIG. 19D illustrates a graphics multiprocessor, according to at least one embodiment;

[0047] FIG. 20 illustrates a multi-graphics processing unit (GPU) system, according to at least one embodiment;

[0048] FIG. 21 illustrates a graphics processor, according to at least one embodiment; [00491 FIG. 22 is a block diagram illustrating a processor micro-architecture for a processor, according to at least one embodiment; [00501 FIG. 23 illustrates a deep learning application processor, according to at least one embodiment;

[0051] FIG. 24 is a block diagram illustrating an example neuromorphic processor, according to at least one embodiment; [00521 FIG. 25 illustrates at least portions of a graphics processor, according to one or more embodiments;

[0053] FIG. 26 illustrates at least portions of a graphics processor, according to one or more embodiments;

[0054] FIG. 27 illustrates at least portions of a graphics processor, according to one or more embodiments;

[0055] FIG. 28 is a block diagram of a graphics processing engine of a graphics processor in accordance with at least one embodiment;

[0056] FIG. 29 is a block diagram of at least portions of a graphics processor core, according to at least one embodiment; [00571 FIGS. 30A-30B illustrate thread execution logic including an array of processing elements of a graphics processor core according to at least one embodiment;

[0058] FIG. 31 illustrates a parallel processing unit (“PPU”), according to at least one embodiment; [09591 FIG. 32 illustrates a general processing cluster (“GPC”), according to at least one embodiment;

[0060] FIG. 33 illustrates a memory partition unit of a parallel processing unit (“PPU”), according to at least one embodiment;

[0061] FIG. 34 illustrates a streaming multi-processor, according to at least one embodiment;

[0062] FIG. 35 is an example data flow diagram for an advanced computing pipeline, in accordance with at least one embodiment;

[0063] FIG. 36 is a system diagram for an example system for training, adapting, instantiating and deploying machine learning models in an advanced computing pipeline, in accordance with at least one embodiment;

[0064] FIG. 37 includes an example illustration of an advanced computing pipeline 3610A for processing imaging data, in accordance with at least one embodiment; [00651 FIG. 38A includes an example dataflow diagram of a virtual instrument supporting an ultrasound device, in accordance with at least one embodiment;

[0066] FIG. 38B includes an example data How diagram of a virtual instrument supporting an CT scanner, in accordance with at least one embodiment;

[0067] FIG. 39A illustrates a data flow diagram for a process to train a machine learning model, in accordance with at least one embodiment;

[0068] FIG. 39B is an example illustration of a client-server architecture to enhance annotation tools with pre-trained annotation models, in accordance with at least one embodiment; and [00691 FIG. 40 illustrates components of a system to access a large language model, according to at least one embodiment. DETAILED DESCRIPTION

[0070] FIG. 1 illustrates an example neural network training system 100 that implements fast checkpoint creation during model training, according to at least one embodiment. In at least one embodiment, neural network training system 100 is used to execute a training process 150 to perform training iterations 152 on one or more neural networks. Training state data 180 may be maintained in a GPU memory 170 provided by hardware memory7 resources 142 associated with one or more GPUs 140. In at least one embodiment, training process 150 is allocated a process memory 158, which is provided by CPU memory resources 132 associated with one or more CPUs 130. In at least one embodiment, said training process 150 is able to invoke or execute a checkpoint operation 154 to copy 156 training state data 180 from said GPU memory7 170 to an area of pinned shared memory 160 to create a checkpoint 190. In at least one embodiment, said checkpoint 190 includes neural network weights that are changed by said training process, and these neural network weight checkpoints are defined by a user before training starts at various intervals in the training process. In at least one embodiment, checkpoint creation is accomplished using software that can be embodied in an API, specialized instruction, or software program that allocates a page locked (or “pinned”) shared memory’ buffer large enough to contain all of checkpointing neural network w’eight information that will be used in said checkpointing process, rather than iteratively allocating pinned shared memory each time a checkpoint is invoked and copying said checkpointed neural network weight data from host to shared data each time checkpointing is used. In at least one embodiment, training process 150, GPU memory 170, and pinned shared memory’ 160 are implemented as part of a software execution environment 110 of said neural network training system 100. In at least one embodiment, CPUs 130, CPU memory’ resources 132, GPUs 140, and GPU memory resources 142 comprise hardware resources 120 of said neural network training system 100. Training system 100 may' be implemented using a single computer or a group of multiple training computers. [00711 In at least one embodiment, training system 100 executes an operating system (OS) call to provide said execution environment 110 for training process 150. In at least one embodiment, said OS allocates process memory 158 to said training process 150. In at least one embodiment, pinned shared memory buffer 160 is a continuous region of memory' allocated by said OS, but said memory7 buffer 160 is allocated outside of and separate from any OS processes. In at least one embodiment, allocated shared memory' 160 is not deallocated after termination of training process 150, so that if training processes 150 terminates unexpectedly during training, checkpoints 190 generated by said process are not lost with said process. In at least one embodiment, GPU memory' 170 is a region of memory allocated on GPU memory resources 142. GPU memory resources 142 may be directly controlled by GPU(s) 140 but are writeable by OS processes such as training process 150 through GPU drivers executing on said CPU(s) 130. [00721 In at least one embodiment, said shared memory' buffer 160 is configured as a pinned or page-locked region of memory', so that said OS is prevented from swapping pages in said shared memory 160 out to secondary storage, for example persistent disk storage. Some ty pes of OSs may perform such page swapping in order to expand allocated volatile memory into a larger virtual memory. An OS may' dynamically swap out memory' pages that are not recently accessed and swap in pages that are needed for processing so that a portion of contents of said memory' is maintained on secondary storage. However, when page swapping is used, accesses to said memory area are slowed due to checks of whether a desired page is resident in memory' or not. This checking (and potential fetching of a page from secondary' storage) drastically reduces access performance of said memory. Tims, in at least one embodiment, said shared memory 160 is pinned or page-locked to avoid such penalties on said memory so that checkpoints 190 can be written as quickly as possible. In at least one embodiment, said shared memory buffer 160 is pre-allocated as a continuous region of memory, sized with capacity' to store a large number of checkpoints generated during model training. In at least one embodiment, this continuous region of memory' is set as pinned memory’ via a single operating system call, so that said entire region is pinned by said single system call as opposed to being pinned for each checkpoint as it is allocated. This former approach works best for shared memories that are potentially shared by multiple training processes, enabling faster checkpoint writing and promoting efficient memory usage (for example avoiding many small fragments of pinned memory). [09731 Although said shared memory' 160 is depicted in this example to be provided by CPU memory resources 132, in at least one embodiment, memory used to store checkpoints 190 may be provided by memory resources other than host memory 132 used to execute training process 150. For example, in at least one embodiment, checkpoints 190 may be written to a separate memory' device that is optimized for write speed. In at least one embodiment, checkpoints 190 may be written to a memory’ device that is near to GPU memory' resources 142. [00741 As shown, in at least one embodiment, to create a checkpoint 190, training process 150 executes a checkpoint operation 154. Training process 150 may create checkpoints 190 as needed during training, for example, after each training iteration, every N number of iterations, or after a significant computation or training phase is completed. In at least one embodiment, checkpoint operation 154 involves a direct memory- copy 156 of training state data 180 in said GPU memory' 170 to said shared memory' 160. Training state data 180 may include data that is changed by training iterations 152 of training process 150, such as model weights, variable precision parameters, iteration or epoch metadata, among other types of information. In at least one embodiment, said memory copy 156 is performed directly from GPU memory 170 to shared memory 160, so that no additional intermediate copy of training state data 180 is created in process memory' 158. Avoidance of this “double copy” reduces memory consumption of training process 150 and allows checkpointing operation 154 to be completed much more quickly.

[0075] In at least one embodiment, copy 156 may be performed using a direct memory' copy API, which performs a direct copy of a block of data from one memory region to another memory region. In at least one embodiment, shared memory 160 and GPU memory 170 may' be mapped into process memory 158, but without creating an additional copy of contents of these memories 160 and 170 in said process memory. In at least one embodiment, checkpoint operation 154 may be implemented by a library module loaded by-said training process 150, so that client code in said training process 150 does not have to interface directly with low level system call(s) to perform said copy 156. For example, in at least one embodiment, checkpoint operation 154 may be implemented as a library' call provided by a machine learning framework such as PYTORCH or TENSORFLOW. [00761 In at least one embodiment, hardware resources 120 of training sy stem 100 may include a central processing unit (CPU), a video image compositor (VIC), a graphics processing unit (GPU), a data processing unit (DPU) or other hardware, such as a field programmable gate array (FPGA) or application-specific integrated circuit (ASIC) to perform ML model training or inferencing. In at least one embodiment, components of training system 100 may- include any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide said functionality described herein. In at least one embodiment, software running on training system 100 may be implemented a software package, code and / or instruction set or instructions that, as a result of being executed by one or more processors, including a central processing unit (CPU), a video image compositor (VIC), a graphics processing unit (GPU), a data processing unit (DPU) or other hardware, such as a field programmable gate array (FPGA) or application-specific integrated circuit (ASIC), cause system 100 to perform one or more ML operations, and “hardware,” as used in any implementation described herein, includes, for example, alone or in any combination, hardwired circuitry, programmable circuitry', state machine circuitry', fixed function circuitry', execution unit circuitry, and / or firmware that stores instructions executed by programmable circuitry to perform one or more ML operations. In at least one embodiment, said components are collectively or individually embodied as circuitty that forms part of a larger sy stem, for example, an integrated circuit (IC), system on-chip (SoC), mid so forth.

[0077] Embodiments of neural network training system 100 are capable of implementing a fast checkpoint operation 154 that addresses numerous challenges associated with checkpointing in current ML training systems. Use of a pinned shared memory 160 improves checkpointing speed. Moreover, use of a direct memory copy 156 eliminates a double copying of checkpoint information in training process memory, which reduces memory consumption and avoids use of other types of less efficient memory write APIs. In at least one embodiment, said checkpoint operation 154 may be performed asynchronously from said training process 150, so that training process 150 does not need to pause to wait for a checkpoint 190 to be completed before proceeding with further computations. These advantages significantly improve end-to-end training performance of ML training sy stems that write checkpoints, especially those systems that train very large models or checkpoint at very high frequencies. In at least one embodiment, such a training system may use generated checkpoints 190 to enable automatic recovery' from a failure of training process 150. Such a recovery' process may be initiated and / or performed by said training process 150 or some other recovery process, possibly executing on said GPU 140. In either case, said recovery process will be able to use a last checkpoint 190 stored in said shared memory buffer 160 to resume training from that last checkpoint.

[0078] FIG. 2 illustrates an example checkpoint operation that uses a memory copy API 220 provided by an operating system 210, according to at least one embodiment. As shown, FIG. 2 depicts two different paths for copying data from GPU memory 170 to shared memory 160, using two different APIs 220 and 240 provided by an operating system 210.

[0079] As shown, in a first path, training state data 180 is first read 230 from GPU memory 170 and then written 234 to shared memory' 160 via a file access API 240. In at least one embodiment, operating system 210 allows shared memory’ 160 to be written as a pseudo-file via file access API 240. However, this type of file access API 240 is not an efficient API for memory copy operations 156 because it uses translational steps to translate file write requests to memory write instructions. Moreover, a file access API 240 typically requires a caller to directly' supply write data as an argument to a write operation 234, w'hich requires a double copy 232 of said data to be created in caller memory.

[0080] In contrast, a second path of performing said copy' is shown in FIG. 2, which uses a direct memory copy operation 156 provided by a memory copy' API 220. In at least one embodiment, said memory copy API 220 enables a direct copy of a specified number of contiguous bytes from one memory' address to another memory address. In at least one embodiment, such an direct copy operation may' employ a call interface similar to a memcpy() call used on LINUX systems, w'hich does not create a double copy 232 in a process memory of calling process 150. Moreover, because said memory copy API 220 does not treat its copy destination as a higher-level abstraction such as a file, a copy operation 156 performed using this API 220 is simpler and more efficient than file write operation 234 performed through file access API 240. In at least one embodiment, checkpoint operations 154 performed using direct memory copy 156 can achieve much higher write speeds as compared to file writes 234. [00811 FIG. 3 illustrates an example model training system that uses a supervisor process 320 to supervise recovery from worker node failures using checkpoints, according to at least one embodiment. As shown, in at least one embodiment, training system 100 is implemented using a pool 310 of worker nodes 312a-d that are performing training iterations 152 concurrently on a neural network. In at least one embodiment, each worker node 150 may include a separate framing process that is updating a local portion of a neural network.

[0082] As shown, in at least one embodiment, individual worker nodes 312a-d may execute training processes 150 that perform checkpoint operations 154 to write local checkpoints to shared memory 160. As discussed, in at least one embodiment, said shared memory 160 is allocated outside of these training processes 150 and is pinned in memory so that page swapping does not occur for said memory’ 160. In at least one embodiment, shared memory’ buffer 160 may be allocated in the host processor memory (for example CPU memory), but allocated to a particular neural network accelerator device (for example a GPU device), so that the training state generated by said GPU device are always copied to the shared memory’ buffer for that GPU device. Worker nodes 312 may write checkpoints to the shared memory' buffer 160 as needed, for example, once every’ iteration or every’ few iterations of said training process.

[0083] In at least one embodiment, these local checkpoints may’ be aggregated as a global checkpoint, for example at a persistent storage device. As shown, in at least one embodiment, shared memory 160 is allocated with sufficient size to store at least two checkpoints, a working a checkpoint 360 and a completed checkpoint 370. In at least one embodiment, said complete checkpoint 370 may be used to restart a training process 150a that has terminated unexpectedly or failed due to some error. In at least one embodiment, completed copy 370 may be eventually written out to a persistent storage, and when that is done, memory’ space occupied by said complete copy' 370 is freed to write a next checkpoint.

[0084] As shown, in at least one embodiment, operations of a worker node 312 is supervised by a supervisor process 320, which may be implemented as a separate process from training processes 150. In at least one embodiment, supervisor process 320 is responsible for initially allocating 330 said shared memory' 160 and having it in pinned. In at least one embodiment, supervisor process 320 may start individual training processes 150 in said worker node 312, and enable each training process 150 to have access to said shared memory 160. [0()851 In at least one embodiment, supervisor process 320 performs a monitoring function to monitor said training processes 150 for indications of error, failure, performance problems, unexpected termination, or other types of unhealthy conditions. In at least one embodiment, said monitoring relies on individual training processes 150 sending heartbeat messages to supervisor process 320 to report their health conditions. In at least one embodiment, supervisor process 320 may periodically ping individual training processes 150 to request reports from said training processes.

[0086] In at least one embodiment, when an error condition is detected 340 on a training process 1.50a, supervisor process 320 may determine that said afflicted training process 150a will be terminated and restarted. In that event, if afflicted process 150a is not already terminated by said error, it is terminated by supervisor process 320. Then, supervisor process 320 may perform a recovery operation 350, which will cause a new training process 150b to be launched to replace said terminated process 150a. In at least one embodiment, replacement process 1.50b will resume training execution of its predecessor 150a based on a last local checkpoint generated by its predecessor. That is, said replacement process 150b will begin training execution from a GPU state indicated by said last checkpoint. In at least one embodiment, supervisor process 320 may provide a correct local checkpoint of a terminated process 150a its replacement process 150b.

[0087] In this manner, embodiments of training system 100 can implement an auto-recovery mechanism to automatically recover from failed training processes. In training systems 100 that employ a massive number of training processes 150, individual process failures can occur fairly frequently. Said checkpointing operation 154 enables fast and efficient creation of local checkpoints in such systems without causing significant impacts on overall training execution.

[0088] FIG. 4 illustrates an example training process 150 that does not wait 444 for checkpoint completion 442 to proceed to a next training step 410, according to at least one embodiment. As shown, in at least one embodiment, checkpoint operation 154 may be performed asynchronously 430 from training process 150, for example, by a separate checkpointing process or thread. In at least one embodiment, execution of checkpoint operation 154 asynchronously from training process 150 further reduces impacts ofcheckpointing on training execution, for example, by allowing training execution and checkpoint creation to overlap to an extent so that they can be executed at least partly in parallel.

[0089] In at least one embodiment, checkpoint process 430 may be implemented as a separate process from training process 150. For example, in at least one embodiment, a supervisor process 320 as discussed in connection with FIG. 3 may be used to perform checkpoint operation 154 on behalf of training process 150. In at least one embodiment, checkpointing process 430 may operate as a separate thread within training process 150, for example, as part of a multi-threading library loaded by training process 150. In at least one embodiment, checkpointing process 430 may be executed on a GPU device 140 controlling said GPU memory 170. In at least one embodiment, checkpointing process 430 may take advantage of a double buffering technique implemented by said GPU device, where a first memory buffer holds a version of training state 180 being modified by training process 150 and a second memory' buffer holds another version being copied to host memory as part of checkpoint creation. [00901 As shown, in at least one embodiment, training process 150 may be divided into training steps 410a and 410b. Flach training step 410 may include one or more training iterations. Each training iteration may involve executing and / or modifying said neural network based on one or more training data samples. As shown, in at least one embodiment, a training step 410 may' be further divided into an update phase 420a and a no-update phase 420b. For example, a no-update phase 420b may occur during a forward pass of a training iteration where said neural network is used to generate inference results but not changed. Then, an update phase 420a is performed when model parameters and weights are adjusted in a backpropagation pass. [00911 In at least one embodiment, training process 150 is not permitted to modify' training state 180 in GPU memory’ before said training state has been checkpointed. However, in at least one embodiment, training process 150 can parallelize or overlap checkpoint operation 154 with said no-update phase 420b, because training state 180 in GPU memory' is not updated during this phase. Thus, training process 150 can request 440 a checkpoint at an end of an update phase 420a, and as long as said checkpoint operation 154 completes 442 during a next no-update phase 420b, a checkpoint 190 will be correctly created in said shared memory’ 160. Training process 150 does not need to pause to wait 444 for completion of checkpoint operation 154 before proceeding with further execution, and this overlap of execution further reduces impact of checkpointing on said training process 150. In at least one embodiment, a boundary between update phase 420a and no-update phase 420b is defined based on a scope of said checkpoints. For example, in at least one embodiment, training state 180 may include a variety’ of changing metadata that are modified during a forward pass of training process 150 (for example performance metadata or training hyperparameters that are being dynamically adjusted), and such metadata is not strictly necessary to recover from a training error and not included in said checkpoint scope. In that case, said update phase 420a can be understood to include only a short period when critical training state data needed for recovery' (for example model weights) are updated, so that better parallelization can be achieved between said processes 150 and 430. [00921 As shown, in at least one embodiment, an asynchronous completion event 442 of checkpoint operation 154, which indicates completion of said copy' operation 156, will be reported back to training process 150. In at least one embodiment, training process 150 may' wait for said asynchronous completion event 442 before proceeding o a next update phase 420a. In this manner, said two asynchronous processes 150 and 430 may implement a type of synchronization protocol to ensure that a checkpoint is successfully taken before said training state is overwritten by further training. In at least one embodiment, such a completion event 442 may not be explicitly reported to said training process 150, but simply be observed by said training process 150 based on contents of sard shared memory buffer 160.

[0093] FIG. 5A illustrates an example process 500 of a checkpoint creation during model training, according to at least one embodiment. Although example process 500 is depicted as a series of steps or operations, it will be appreciated that embodiments of process 500 include altered or reordered steps or operations, or omits certain steps or operations, except where explicitly noted or logically required, such as when an output of one step or operation is used as input for another. In at least one embodiment, each block of process 500, described herein, is performed in a system described in conjunction with FIG. 1. In at least one embodiment, each block of process 500 is performed using any combination of hardware, firmware, and / or software. For example, in at least one embodiment, various functions are carried out by a processor executing instructions stored in memory . In at least one embodiment, said methods are also embodied as computer-usable instructions stored on computer storage media or provided by a standalone application, a sendee or hosted sendee (standalone or in combination with another hosted service).

[0094] At operation 510, in at least one embodiment, a training process 150 is executed by a neural network training system 100. In at least one embodiment, training process 150 performs training of aneural network in training iterations 152 to repeatedly update a training state 180 stored at least in part on a GPU memory 170. Sard training state data 180 may include information such as model parameters or weights, iteration or epoch metadata, precision metadata or statistics, and / or other types of variables that are changed by said training process 150. In at least one embodiment, said GPU memory 170 is backed by GPU memory' resources 142 controlled by GPU(s) 140, which are used as AI acceleration devices or a training host. In at least one embodiment, said training process 150 executes on host CPU(s) 130 and aprocess memory 158 of said training process 150 is allocated using CPU memory' resources 132 controlled by said CPU(s) 130.

[0095] At operation 520, in at least one embodiment, a determination is made to create a checkpoint of said training state 180 of said training process 150. In at least one embodiment, this determination may be a decision of said training process 150 itself, for example, to checkpoint after every' training iteration, training step, or some number of training iterations or steps. In at least one embodiment, a checkpoint may be taken after an important phase of training has been completed, for example, after a certain training criterion has been met. In at least one embodiment, a checkpoint may occur in response to an instruction received by training process 150, for example, issued by a supervisor process 320. [00961 At operation 530, in at least one embodiment, training process 150 creates a checkpoint 190 using a direct memory-to-memory copy 156 to copy said training state 180 from said GPU memory 170 to a pinned shared memory' 160. In at least one embodiment said shared memory 160 is allocated by an operating system 210 on a host system, where said shared memory7 is allocated separate from and external to processes executing on said operating system. In at least one embodiment, said shared memory 160 is pinned or page-locked so that said operating system does not swap out memory pages in said shared memory 160 to secondary7 storage. In at least one embodiment, said copy 156 is performed using a memory7 copy API 220, and does not use a file access API 240. In at least one embodiment, said copy 156 is performed without making an additional copy- of said training state 180 in a process memory7 158 of said training process. As shown, such checkpoints 190 may be created repeatedly during said training process 150, for example, once every7 few training iterations or steps 410. [00971 As shown, in at least some embodiment, training system 110 implements a recovery7 process 540 using checkpoints 190 created by said fast checkpoint operation 154. At operation 542, in at least some embodiment, training system 100 detects an error that has terminated or requires termination of said training process 542. For example, in at least one embodiment, another process such as a supervisor process 320 may7 execute to monitor said training process 150 for unexpected termination, errors, or unhealthy conditions. If such a condition is detected, at operation 544, in at least some embodiment, said recovery7 process 540 starts another training process (for example process 150e in FIG. 3) to replace said training process afflicted with said error. In at least one embodiment, said replacement process will resume work of its predecessor from a last checkpoint generated by said predecessor. In at least one embodiment, said last checkpoint may be provided to said replacement process by an external supervisor process 320 that is responsible for launching said replacement process.

[0098] FIG. 5B illustrates an example process performed by a supervisor process 320 during model training, according to at least one embodiment. As shown, said example process may be performed as part of process 500 discussed in connection with FIG. 5A.

[0099] At operation 550, in at least one embodiment, supervisor process 320 allocates a pinned shared memory 160 to store checkpoints for model training. In at least one embodiment, a single supervisor process 320 may be configured to manage a large number of training processes 150 running on a pool 310 of worker nodes 132. As discussed, in some embodiments, said shared memory 160 is allocated separately from these training processes 150, for example, as a separately kernel memory region whose lifetime is not tied to any of said training processes 150. In at least one embodiment, said training processes 150 may write local checkpoints 190 to respective shared memory 160. In at least one embodiment, said shared memory 160 is sized so that it has sufficient space to hold at least two checkpoints of said training state 180, including a working checkpoint 360 that is not yet completed, and a complete checkpoint 370 that can be used to perform a recovery, for example when a restart of a training process is needed.

[0100] At operation 560, in at least one embodiment, supervisor process 320 initiates training processes 150 to train one or more neural networks. As discussed, these framing processes 150 are configured to perform training iterations on said neural network(s), whose training state I80 is held at least in part in GPU memory 170. In at least one embodiment, when said training processes are started, supervisor process 320 provides each training process access to said shared memory 160 so that each training process can create its own checkpoints 190 in said shared memory'. In at least one embodiment, said shared memory' 160 and said GPU memory 170 are mapped into a process memory' 158 of individual training processes 150, but without making an additional copy' of these memories 160 and 170.

[0101] At operation 570, in at least one embodiment, supervisor process 320 monitors said training processes 150 for errors such as unexpected termination, performance issues, or other types of unhealthy conditions. If any such conditions are detected for a failing or failed training process 150, supervisor process 320 will automatically recover from said failed training process. In at least one embodiment, said recovery process may be implemented as discussed in connection with operation 540 of FIG. 5A. In at least one embodiment, supervisor process 32.0 may' perform this operation 570 continuously during model training to implement an auto-recovery mechanism for individual failing training nodes. [01021 At operation 580, in at least one embodiment, supervisor process 320 creates a global checkpoint of said training state 180 from a last set of worker node (or local) checkpoints. In at least one embodiment, individual worker nodes 132. may asynchronously create local checkpoints at their own pace, and when all worker nodes have written their local checkpoints for a particular synchronization point during said model training (for example after processing a batch of training records), supervisor process 320 may aggregate these local checkpoints into a global checkpoint. In at least one embodiment, once a completed global checkpoint 370 is created, it may be written out from shared memory 160 to more persistent storage such as a persistent storage device attached to said training system. In at least one embodiment, supervisor process 320 may' create global checkpoints repeatedly in this fashion to save successive global checkpoints during model training. LOGIC

[0103] FIG. 6A illustrates logic 615 which, as described elsewhere herein, can be used in one or more devices to perform operations such as those discussed herein in accordance with at least one embodiment. In at least one embodiment, logic 615 is used to perform inferencing and / or training operations associated with one or more embodiments. In at least one embodiment, logic 615 is inference and / or training logic. Details regarding logic 615 are provided below in conjunction with FIGS. 6A and / or 6B. In at least one embodiment, logic refers to any' combination of software logic, hardware logic, and / or firmware logic to provide functionality or operations described herein, wherein logic may be, collectively or individually, embodied as circuitry' that forms part of a larger system, for example, an integrated circuit (IC), system-on-chip (SoC), or one or processors (e.g., CPU, GPU). [01041 In at least one embodiment, logic 615 may include, without limitation, code and / or data storage 601 to store forward and / or output weight and / or input / output data, and / or other parameters to configure neurons or layers of a neural network trained and / or used for inferencing in aspects of one or more embodiments. In at least one embodiment, logic 615 may include, or be coupled to code and / or data storage 601 to store graph code or other software to control timing and / or order, in which weight and / or other parameter information is to be loaded to configure, logic, including integer and / or floating point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code, such as graph code, loads weight or other parameter information into processor ALUs based on an architecture of a neural network to which such code corresponds. In at least one embodiment, code and / or data storage 601 stores weight parameters and / or input / output data of each layer of a neural network trained or used in conjunction with one or more embodiments during forward propagation of mput / output data and / or weight parameters during training and / or inferencing using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 601 may be included with other on-chip or off-chip data storage, including a processor’s LI, L2, or L3 cache or system memory-. [01051 In at least one embodiment, any portion of code and / or data storage 601 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or code and / or data storage 601 may be cache memory, dynamic randomly addressable memory (“DRAM”), static randomly addressable memory (“SRAM”), non-volatile memory- (e.g., flash memory-), or other storage. In at least one embodiment, a choice of whether code and / or code and / or data storage 601 is interna] or external to a processor, for example, or comprising DRAM, SRAM, flash or some other storage type may depend on available storage on-chip versus off-chip, latency requirements of training and / or inferencing functions being performed, batch size of data used in inferencing and / or training of a neural network, or some combination of these factors. [01061 In at least one embodiment, logic 615 may include, without limitation, a code and / or data storage 605 to store back-ward and / or output w-eight and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inferencing in aspects of one or more embodiments. In at least one embodiment, code and / or data storage 605 stores -weight parameters and / or input / output data of each layer of a neural network trained or used in conjunction with one or more embodiments during backward propagation of input / output data and / or w-eight parameters during training and / or inferencing using aspects of one or more embodiments. In at least one embodiment, logic 615 may include, or be coupled to code and / or data storage 605 to store graph code or other software to control timing and / or order, in which weight and / or other parameter information is to be loaded to configure, logic, including integer and / or floating point units (collectively, arithmetic logic units (ALUs)). [01071 In at least one embodiment, code, such as graph code, causes the loading of weight or other parameter information into processor ALUs based on an architecture of a neural network to which such code corresponds. In at least one embodiment, any portion of code and / or data storage 605 may be included with other on-chip or off-chip data storage, including a processor’s Li, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 605 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 605 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, a choice of whether code and / or data storage 605 is internal or external to a processor, for example, or comprising DRAM, SRAM, flash memory or some other storage typo may depend on available storage on-chip versus off-chip, latency- requirements of training and / or inferencing functions being performed, batch size of data used in inferencing and / or Raining of a neural network, or some combination of these factors.

[0108] In at least one embodiment, code and / or data storage 601 and code and / or data storage 605 may be separate storage structures. In at least one embodiment, code and / or data storage 601 and code and / or data storage 605 may be a combined storage structure. In at least one embodiment, code and / or data storage 601 and code and / or data storage 605 may be partially combined and partially separate. In at least one embodiment, any portion of code and / or data storage 601 and code and / or data storage 605 may be included with other on-chip or off-chip data storage, including a processor’s LI, L2, or L3 cache or system memory. [01091 In at least one embodiment, logic 615 may include, without limitation, one or more arithmetic logic unit(s) C‘ALU(s)”) 610, including integer and / or floating point units, to perform logical and / or mathematical operations based, at least in part on, or indicated by, training and / or inference code (e.g., graph code), a result of which may produce activations (e.g., output values from layers or neurons within a neural network) stored in an activation storage 620 that are functions of input / output and / or weight parameter data stored in code and / or data storage 601 and / or code and / or data storage 605. In at least one embodiment, activations stored m activation storage 620 are generated according to linear algebraic and or matrix-based mathematics performed by ALU(s) 610 in response to performing instructions or other code, wherein weight values stored in code and / or data storage 605 and / or data storage 601 are used as operands along with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 605 or code and / or data storage 601 or another storage on or off-chip. [01101 In at least one embodiment, ALU(s) 610 are included within one or more processors or other hardware logic devices or circuits, -whereas in another embodiment, ALU(s) 610 may be external to a processor or other hardware logic device or circuit that uses them (e.g., a co-processor). In at least one embodiment, ALUs 610 may be included within a processor’s execution units or otherwise within a bank of ALUs accessible by a processor’s execution units either within same processor or distributed between different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and / or data storage 601, code and / or data storage 605, and activation storage 620 may share a processor or other hardware logic device or circuit, whereas in another embodiment, they may be in different processors or other hardware logic devices or circuits, or some combination of same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 620 may be included with other on-chip or off-chip data storage, including a processor’s LI, L2, or L3 cache or system memory. Furthermore, inferencing and / or training code may be stored with other code accessible to a processor or other hardware logic or circuit and fetched and / or processed using a processor’s fetch, decode, scheduling, execution, retirement and / or other logical circuits. [0111 j In at least one embodiment, activation storage 620 may be cache memory, DRAM, SRAM, nonvolatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 620 may be completely or partially within or external to one or more processors or other logical circuits. In at least one embodiment, a choice of whether activation storage 620 is internal or external to a processor, for example, or comprising DRAM, SRAM, flash memory or some other storage type may depend on available storage on-chip versus off-chip, latency requirements of training and / or inferencing functions being performed, batch size of data used in inferencing and / or training of a neural network, or some combination of these factors.

[0112] In at least one embodiment, logic 615 illustrated in FIG. 6A may be used in conjunction with an application-specific integrated circuit (’‘ASIC”), such as a TensorFlow® Processing Unit from Google, an inference processing unit (1PU) from Graphcore™, or aNervana® (e.g., "‘Lake Crest”) processor from Intel Corp. In at least one embodiment, logic 615 illustrated in FIG. 6A may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware or other hardware, such as field programmable gate arrays (“FPGAs”).

[0113] FIG. 6B illustrates logic 615, according to at least one embodiment. In at least one embodiment, logic 615 is inference and / or training logic. In at least one embodiment, logic 615 may include, without limitation, hardware logic in which computational resources are dedicated or otherwise exclusively used in conjunction with weight values or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, logic 615 illustrated in FIG. 6B may be used in conjunction with an application-specific integrated circuit (ASIC), such as TensorFlow® Processing Unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., “Lake Crest”) processor from Intel Corp. In at least one embodiment, logic 615 illustrated in FIG. 6B may be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware or other hardware, such as field programmable gate arrays (FPGAs). In at least one embodiment, logic 615 includes, without limitation, code and / or data storage 601 and code and / or data storage 605, which may be used to store code (e.g., graph code), weight values and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. In at least one embodiment illustrated in FIG. 6B, each of code and / or data storage 601 and code and / or data storage 605 is associated with a dedicated computational resource, such as computational hardware 602 and computational hardware 606, respectively. In at least one embodiment, each of computational hardware 602 and computational hardware 606 comprises one or more ALUs that perform mathematical functions, such as linear algebraic functions, only on information stored in code and / or data storage 601 and code and / or data storage 605, respectively, result of which is stored in activation storage 620. [01141 In at least one embodiment, each of code and / or data storage 601 and 605 and corresponding computational hardware 602 and 606, respectively, correspond to different layers of a neural network, such that resulting activation from one storage / computational pair 601 / 602 of code and / or data storage 601 and computational hardware 602 is provided as an input to a next storage / computational pair 605 / 606 of code and / or data storage 605 and computational hardware 606, in order to mirror a conceptual organization of a neural network. In at least one embodiment, each of storage / computational pairs 601 / 602 and 605 / 606 may correspond to more than one neural network layer. In at least one embodiment, additional storage / computation pairs (not shown) subsequent to or in parallel with storage / computation pairs 601 / 602 and 605 / 606 may be included in logic 615. NEURAL NETWORK. TRAINING AND DEPLOYMENT [01151 FIG. 7 illustrates training and deployment of a deep neural network, according to at least one embodiment. In at least one embodiment, untrained neural network 706 is trained using a training dataset 702. In at least one embodiment, training framework 704 is a PyTorch framework, whereas in other embodiments, training framework 704 is a TensorFIow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deepleaming4i, or other training frame-work. In at least one embodiment, training framework 704 trains an untrained neural network 706 and enables it to be trained using processing resources described herein to generate a trained neural network 708. In at least one embodiment, weights may be chosen randomly or by pre-training using a deep belief network. In at least one embodiment, training may be performed in either a supervised, partially supervised, or unsupervised manner.

[0116] In at least one embodiment, untrained neural network 706 is trained using supervised learning, wherein training dataset 702 includes an input paired with a desired output for an input, or where training dataset 702 includes input having a knowm output and an output of neural network 706 is manually graded. In at least one embodiment, untrained neural network 706 is trained in a supervised manner and processes inputs from training dataset 702 and compares resulting outputs against a set of expected or desired outputs. In at least one embodiment, errors are then propagated back through untrained neural network 706. In at least one embodiment, training framework 704 adjusts weights that control untrained neural network 706. In at least one embodiment, training framework 704 includes tools to monitor how well untrained neural network 706 is converging towards a model, such as trained neural network 708, suitable to generating correct answers, such as in result 714, based on input data such as a new dataset 712. In at least one embodiment, training framework 704 trains untrained neural network 706 repeatedly wdiile adjusting weights to refine an output of untrained neural network 706 using a loss function and adjustment algorithm, such as stochastic gradient descent. In at least one embodiment, training framework 704 trains untrained neural network 706 until untrained neural network 706 achieves a desired accuracy. In at least one embodiment, trained neural network 708 can then be deployed to implement any number of machine learning operations.

[0117] In at least one embodiment, untrained neural network 706 is trained using unsupervised learning, wherein untrained neural network 706 attempts to train itself using unlabeled data. In at least one embodiment, unsupervised learning training dataset 702 will include input data without any associated output data or "‘ground truth” data. In at least one embodiment, untrained neural network 706 can learn groupings within training dataset 702 and can determine how individual inputs are related to untrained dataset 702. In at least one embodiment, unsupervised training can be used to generate a self-organizing map in trained neural network 708 capable of performing operations useful in reducing dimensionality of new dataset 712. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows identification of data points in new dataset 712 that deviate from normal patterns of new dataset 712. [01181 In at least one embodiment, semi-supervised learning may be used, which is a technique in which in training dataset 702 includes a mix of labeled and unlabeled data. In at least one embodiment, training framework 704 may be used to perform incremental learning, such as through transferred learning techniques. In at least one embodiment, incremental learning enables trained neural network 708 to adapt to new dataset 712 without forgetting knowledge instilled within trained neural network 708 during initial training.

[0119] In at least one embodiment, training framework 704 is a framework processed in connection with a software development toolkit such as an OpenVINO (Open Visual Inference and Neural network Optimization) toolkit. In at least one embodiment, an OpenVINO toolkit is a toolkit such as those developed by Intel Corporation of Santa Clara, CA. In at least one embodiment, OpenVINO comprises logic 615 or uses logic 615 to perform operations described herein. In at least one embodiment, an SoC, integrated circuit, or processor uses OpenVINO to perform operations described herein. [01201 In at least one embodiment, Open VINO is a toolkit for facilitating development of applications, specifically neural network applications, for various tasks and operations, such as human vision emulation, speech recognition, natural language processing, recommendation systems, and / or variations thereof. In at least one embodiment, OpenVINO supports neural networks such as convolutional neural networks (CNNs), recurrent and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries such as OpenCV, OpenCL, and / or variations thereof. [0121 j In at least one embodiment, OpenVINO supports neural network models for various tasks and operations, such as classification, segmentation, object detection, face recognition, speech recognition, pose estimation (e.g., humans and / or objects), monocular depth estimation, image inpainting, style transfer, action recognition, colorization, and / or variations thereof.

[0122] In at least one embodiment, OpenVINO comprises one or more software tools and / or modules for model optimization, also referred to as a model optimizer. In at least one embodiment, a model optimizer is a command line tool that facilitates transitions between training and deployment of neural network models. In at least one embodiment, a model optimizer optimizes neural network models for execution on various devices and / or processing units, such as a GPU, CPU, PPU, GPGPU, and / or variations thereof. In at least one embodiment, a model optimizer generates an internal representation of a model, and optimizes said model to generate an intermediate representation. In at least one embodiment, a model optimizer reduces a number of layers of a model. In at least one embodiment, a model optimizer removes layers of a model that are utilized for training. In at least one embodiment, a model optimizer performs various neural network operations, such as modifying inputs to a model (e.g., resizing inputs to a model), modifying a size of inputs of a model (e.g., modifying a batch size of a model), modifying a model structure (e.g., modifying layers of a model), normalization, standardization, quantization (e.g., converting weights of a model from a first representation, such as floating point, to a second representation, such as integer), and / or variations thereof [0123I In at least one embodiment, OpenVINO comprises one or more software libraries for mferencing, also referred to as an inference engine. In at least one embodiment, an inference engine is a C++ library, or any suitable programming language library'. In at least one embodiment, an inference engine is utilized to infer input data. In at least one embodiment, an inference engine implements various classes to infer input data and generate one or snore results. In at least one embodiment, an inference engine implements one or more API functions to process an intermediate representation, set input and / or output formats, and / or execute a model on one or more devices.

[0124] In at least one embodiment, OpenVINO provides various abilities for heterogeneous execution of one or more neural network models. In at least one embodiment, heterogeneous execution, or heterogeneous computing, refers to one or more computing processes and / or systems that utilize one or more types of processors and / or cores. In at least one embodiment. Open VINO provides various software functions to execute a program on one or more devices. In at least one embodiment, Open VINO provides various software functions to execute a program and / or portions of a program on different devices. In at least one embodiment, OpenVINO provides various software functions to, for example, run a first portion of code on a CPU and a second portion of code on a GPU and / or FPGA. In at least one embodiment, OpenVINO provides various software functions to execute one or more layers of a neural network on one or more devices (e.g., a first set of layers on a first device, such as a GPU, and a second set of layers on a second device, such as a CPU).

[0125] In at least one embodiment, OpenVINO includes various functionality’ similar to functionalities associated with a CUBA programming model, such as various neural network model operations associated with frameworks such as TensorFlow, PyTorch, and / or variations thereof. In at least one embodiment, one or more CUDA programming model operations are performed using OpenVINO. In at least one embodiment, various systems, methods, and / or techniques described herein arc implemented using OpenVINO. DATA CENTER

[0126] FIG. 8 illustrates an example data center 800, in which at least one embodiment may be used. In at least one embodiment, data center 800 includes a data center infrastructure layer 810, a framework layer 820, a software layer 830 and an application layer 840.

[0127] In at least one embodiment, as shown in FIG. 8, data center infrastructure layer 810 may’ include a resource orchestrator 812, grouped computing resources 814, and node computing resources (“node C.R.s”) 816(1)-816(N), where “N” represents a positive integer (which may be a different integer “N” than used in other figures). In at least one embodiment, node C.R.s 816(1)-816(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 818(F)-818(N) (e.g., dynamic read-only memory, solid state storage or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more node C.R.s from among node C.R.s 816(I)-816(N) may be a server having one or more of above-mentioned computing resources.

[0128] In at least one embodiment, grouped computing resources 814 may include separate groupings of node C.R.S housed within one or more racks (not shown), or many racks housed in data centers at various geographical locations (also not shown). In at least one embodiment, separate groupings of node C.R.s within grouped computing resources 814 may include grouped compute, network, memory' or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node C.R.s including CPUs or processors may be grouped within one or more racks to provide compute resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0129] In at least one embodiment, resource orchestrator 812 may configure or otherwise control one or more node C.R.s 816(I)-816(N) and / or grouped computing resources 814. In at least one embodiment, resource orchestrator 812 may include a software design infrastructure (“SDI”) management entity for data center 800. In at least one embodiment, resource orchestrator 612 may include hardware, software or some combination thereof.

[0130] In at least one embodiment, as shown in FIG. 8, framework layer 820 includes a job scheduler 822, a configuration manager 824, a resource manager 826 and a distributed file system 828. In at least one embodiment, framework layer 820 may include a framework to support software 832 of software layer 830 and / or one or more application(s) 842 of application layer 840. In at least one embodiment, software 832 or application^) 842 may respectively include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud and Microsoft Azure. In at least one embodiment, framework layer 82.0 may be, but is not limited to, a type of free and open-source software web application framework such as Apache Spark™ (hereinafter “Spark”) that may utilize distributed file system 828 for large-scale data processing (e.g., “big data”). In at least one embodiment, job scheduler 822 may include a Spark driver to facilitate scheduling of workloads supported by various layers of data center 800. In at least one embodiment, configuration manager 824 may be capable of configuring different layers such as software layer 830 and framework layer 820 including Spark and distributed file system 828 for supporting large-scale data processing. In at least one embodiment, resource manager 826 may be capable of managing clustered or grouped computing resources mapped to or allocated for support of distributed file system 828 and job scheduler 822. In at least one embodiment, clustered or grouped computing resources may include grouped computing resources 814 at data center infrastructure layer 810. In at least one embodiment, resource manager 826 may coordinate with resource orchestrator 812 to manage these mapped or allocated computing resources.

[0131] In at least one embodiment, software 832 included in software layer 830 may include software used by at least portions of node C.R.s 816(1)-816(N), grouped computing resources 814, and / or distributed file sy stem 828 of framework layer 820. In at least one embodiment, one or more types of software may include, but are not limited to, Internet web page search software, e-mail virus scan software, database software, and streaming video content software.

[0132] In at least one embodiment, application(s) 842 included in application layer 840 may include one or more types of applications used by at least portions of node C.R.s 816(1)-816(N), grouped computing resources 814, and / or distributed file system 828 of framework layer 820. In at least one embodiment, one or more types of applications may include, but are not limited to, any number of a genomics application, a cognitive compute, application and a machine learning application, including training or inferencing software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.) or other machine learning applications used in conjunction with one or more embodiments. [01331 In at least one embodiment, any of configuration manager 824, resource manager 826, and resource orchestrator 812 may implement any number and type of self-modifying actions based on any amount and type of data acquired in any technically feasible fashion. In at least one embodiment, selfmodifying actions may relieve a data center operator of data center 800 from making possibly bad configuration decisions and possibly avoiding underutilized and / or poor performing portions of a data center.

[0134] In at least one embodiment, data center 800 may include tools, services, software or other resources to train one or more machine learning models or predict or infer information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weight parameters according to a neural network architecture using software and computing resources described above with respect to data center 800. In at least one embodiment, trained machine learning models corresponding to one or more neural networks may be used to infer or predict information using resources described above with respect to data center 800 by using weight parameters calculated through one or more training techniques described herein.

[0135] In at least one embodiment, data center may use CPUs, application-specific integrated circuits (ASICs), GPUs, FPGAs, or other hardware to perform training and / or inferencing using above-described resources. Moreover, one or more software and / or hardware resources described above may be configured as a sendee to allow users to train or performing inferencing of information, such as image recognition, speech recognition, or other artificial intelligence sendees.

[0136] Logic 615 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding logic 615 are provided herein in conjunction with FIGS. 6A and / or 6B. In at least one embodiment, logic 615 may be used in data center 800 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0137] In at least one embodiment, an embodiment consistent with said figures includes one or more processors, circuitry', or systems to cause one or more pinned shared memory' buffers to be allocated to one or more neural network accelerators, wherein the one or more pinned shared memory' buffers are to store a plurality’ of neural network training checkpoints to be used by the one or more neural network accelerators to recover from one or more errors detected during training of one or more neural networks, such as described with respect to any of FIGS. 1-5B. AUTONOMOUS VEHICLE [01381 FIG. 9A illustrates an example of an autonomous vehicle 900, according to at least one embodiment. In at least one embodiment, autonomous vehicle 900 (alternatively referred to herein as "vehicle 900”) may be, without limitation, a passenger vehicle, such as a car, a track, a bus, and / or another type of vehicle that accommodates one or more passengers. In at least one embodiment, vehicle 900 may be a semi-tractor-trailer track used for hauling cargo. In at least one embodiment, vehicle 900 may be an airplane, robotic vehicle, or other kind of vehicle.

[0139] Autonomous vehicles may be described in terms of automation levels, defined by National Highway Traffic Safety Administration (“NHTSA”), a division of US Department of Transportation, and Society of Automotive Engineers (“SAE”) “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016-201806, published on June 15, 2018, Standard No. J30I6-20I609, published on September 30, 2016, and previous and future versions of this standard). In at least one embodiment, vehicle 900 may be capable of functionality’ in accordance with one or more of Level I through Level 5 of autonomous driving levels. For example, in at least one embodiment, vehicle 900 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on embodiment. [01401 In at least one embodiment, vehicle 900 may include, without limitation, components such as a chassis, a vehicle body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of a vehicle. In at least one embodiment, vehicle 900 may include, without limitation, a propulsion system 950, such as an internal combustion engine, hybrid electric power plant, an all-electric engine, and / or another propulsion system type. In at least one embodiment, propulsion system 950 may be connected to a drive train of vehicle 900, which may’ include, without limitation, a transmission, to enable propulsion of vehicle 900. In at least one embodiment, propulsion system 950 may be controlled in response to receiving signals from a tbrottle / acceierator(s) 952.

[0141] In at least one embodiment, a steering system 954, which may include, without limitation, a steering wheel, is used to steer vehicle 900 (e.g., along a desired path or route) when propulsion system 950 is operating (e.g., when vehicle 900 is in motion). In at least one embodiment, steering system 954 may’ receive signals from steering actuator(s) 956. In at least one embodiment, a steering wheel may be optional for full automation (Level 5) functionality. In at least one embodiment, a brake sensor system 946 may be used to operate vehicle brakes in response to receiving signals from brake actuator(s) 948 and / or brake sensors. [01421 In at least one embodiment, controller s) 936, which may include, without limitation, one or more system on chips (“SoCs”) (not shown in FIG. 9A) and / or graphics processing unit(s) (“GPU(s)”), provide signals (e.g., representative of commands) to one or more components and / or systems of vehicle 900. For instance, in at least one embodiment, controller(s) 936 may send signals to operate vehicle brakes via brake actuator(s) 948, to operate steering system 954 via steering actuator(s) 956, to operate propulsion system 950 via throttle / accelerator(s) 952. In at least one embodiment, controllers) 936 may include one or more onboard (e.g., integrated) computing devices that process sensor signals, and output operation commands (e.g., signals representing commands) to enable autonomous driving and / or to assist a human driver in driving vehicle 900. In at least one embodiment, controller(s) 936 may include a first controller for autonomous driving functions, a second controller for functional safety’ functions, a third controller for artificial intelligence functionality (e.g., computer vision), a fourth controller for infotainment functionality, a fifth controller for redundancy in emergency conditions, and / or other controllers. In at least one embodiment, a single controller may handle two or more of above functionalities, two or more controllers may handle a single functionality, and / or any combination thereof. [01431 In at least one embodiment, controller(s) 936 provide signals for controlling one or more components and / or sy stems of vehicle 900 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, sensor data may be received from, for example and without limitation, global navigation satellite systems (“GNSS”) sensor(s) 958 (e.g., Global Positioning System sensor(s)), RADAR sensor(s) 960, ultrasonic sensor(s) 962, LIDAR sensor(s) 964, inertial measurement unit (“TMU”) sensor(s) 966 (e.g., accelerometer(s), gyroscope(s), a magnetic compass or magnetic compasses, magnetometer(s), etc.), microphone(s) 996, stereo camera(s) 968, wide-view camera(s) 970 (e.g., fisheye cameras), infrared camera(s) 972, surround camera(s) 974 (e.g., 360 degree cameras), long-range cameras (not shown in FIG. 9A), mid-range camera(s) (not shown in FIG. 9A), speed sensor(s) 944 (e.g., for measuring speed of vehicle 900), vibration sensor(s) 942, steering sensor(s) 940, brake sensor(s) (e.g., as part of brake sensor system 946), and / or other sensor types. [01441 In at least one embodiment, one or more of controllers) 936 m ay receive inputs (e.g,, represented by input data) from an instrument cluster 932 of vehicle 900 and provide outputs (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 934, an audible annunciator, a loudspeaker, and / or via other components of vehicle 900. In at least one embodiment, outputs may include information such as vehicle velocity, speed, time, map data (e.g., a High Definition map (not shown in FIG. 9A)), location data (e.g., vehicle’s 900 location, such as on a map), direction, location of other vehicles (e.g., an occupancy grid), information about objects and status of objects as perceived by controllers) 936, etc. For example, in at least one embodiment, HMI display 934 may display information about presence of one or more objects (e.g., a street sign, caution sign, traffic light changing, etc.), and / or information about driving maneuvers vehicle has made, is making, or will make (e.g., changing lanes now, taking exit 34B in two miles, etc.).

[0145] In at least one embodiment, vehicle 900 further includes a network interface 924 which may use wireless antenna(s) 926 and / or modem(s) to communicate over one or more networks. For example, in at least one embodiment, network interface 924 may be capable of communication over Long-Tenn Evolution (“LTE”), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile communication (“GSM”), 1MT-CDMA Multi-Carrier (“CDMA2000”) networks, etc. In at least one embodiment, wireless antenna(s) 926 may also enable communication between objects in environment (e.g., vehicles, mobile devices, etc.), using local area network(s), such as Bluetooth, Bluetooth Low’ Energy (“LE”), Z-Wave, ZigBee, etc., and / or low power wide-area network(s) (“LPWANs”), such as LoRaWAN, SigFox, etc. protocols.

[0146] Logic 615 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding logic 615 are provided herein in conjunction with FIGS. 6A and / or 6B. In at least one embodiment, logic 615 may be used in vehicle 900 for inferencing or predicting operations based, at least in part, on w’eight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0147] In at least one embodiment, an embodiment consistent with said figures includes one or more processors, circuitry, or systems to cause one or more pinned shared memory buffers to be allocated to one or more neural network accelerators, wherein the one or more pinned shared memory buffers are to store a plurality of neural network training checkpoints to be used by the one or more neural network accelerators to recover from one or more errors detected during training of one or more neural networks, such as described with respect to any of FIGS. 1-5B.

[0148] FIG. 9B illustrates an example of camera locations and fields of view for autonomous vehicle 900 of FIG. 9A, according to at least one embodiment. In at least one embodiment, cameras and respective fields of view7 are one example embodiment and are not intended to be limiting. For instance, in at least one embodiment, additional and / or alternative cameras may be included and / or cameras may be located at different locations on vehicle 900.

[0149] In at least one embodiment, camera types Err cameras may include, but are not limited to, digital cameras that may be adapted for use with components and / or systems of vehicle 900. In at least one embodiment, camera(s) may operate at automotive safety integrity level (“ASIL”) B and / or at another ASIL. In at least one embodiment, camera types may be capable of any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc., depending on embodiment. In at least one embodiment, cameras may be capable of using rolling shutters, global shutters, another type of shutter, or a combination thereof. In at least one embodiment, color filter array’ may’ include a red clear clear clear (“RCCC”) color filter array, a red clear clear blue (“RCCB”) color filter array, a red blue green clear (“RBGC”) color filter array, a Foveon X3 color filter array, a Bayer sensors (“RGGB”) color filter array, a monochrome sensor color filter array, and / or another type of color filter array. In at least one embodiment, clear pixel cameras, such as cameras with an RCCC, an RCCB, and / or an RBGC color filter array, may be used in an effort to increase light sensitivity. [01501 In at least one embodiment, one or more of camera(s) may be used to perform advanced driver assistance systems (“ADAS”) functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a Multi-Function Mono Camera may be installed to provide functions including lane departure warning, traffic sign assist and intelligent headlamp control. In at least one embodiment, one or more of camera(s) (e.g., ail cameras) may record and provide image data (e.g., video) simultaneously. [01511 In at least one embodiment, one or more cameras may be mounted in a mounting assembly, such as a custom designed (three-dimensional (“3D”) printed) assembly, in order to cut out stray light and reflections from within vehicle 900 (e.g., reflections from dashboard reflected in windshield mirrors) which may interfere with camera image data capture abilities. With reference to wing-mirror mounting assemblies, in at least one embodiment, wing-mirror assemblies may be custom 3D printed so that a camera mounting plate matches a shape of a wing-m irror. In at least one embodiment, camera(s) may be integrated into wing-mirrors. In at least one embodiment, for side-view cameras, camera(s) may also be integrated wrthin four pillars at each comer of a cabin. [01521 In at least one embodiment, cameras with a field of view that include portions of an environment in front of vehicle 900 (e.g., front-facing cameras) may be used for surround view, to help identify forward facing paths and obstacles, as well as aid in, with help of one or snore of controller(s) 936 and / or control SoCs, providing information critical to generating an occupancy grid and / or determining preferred vehicle paths. In at least one embodiment, front-facing cameras may be used to perform many similar ADAS functions as LIDAR, including, without limitation, emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, front-facing cameras may also be used for ADAS functions and systems including, without limitation, Lane Departure Warnings (“LDW”), Autonomous Cruise Control (“ACC”), and / or other functions such as traffic sign recognition.

[0153] In at least one embodiment, a variety of cameras may be used in a front-facing configuration, including, for example, a monocular camera platform that includes a CMOS (“complementary metal oxide semiconductor”) color imager. In at least one embodiment, a wide-view camera 970 may be used to perceive objects coming into view from a periphery (e.g., pedestrians, crossing traffic or bicycles). Although only one wide-view camera 970 is illustrated in FIG. 9B, in other embodiments, there may be any number (including zero) wide-view' cameras on vehicle 900. In at least one embodiment, any number of long-range camera(s) 998 (e.g., a long-view stereo camera pair) may be used for depth-based object detection, especially for objects for which a neural network has not yet been trained. In at least one embodiment, long-range camera(s) 998 may also be used for object detection and classification, as well as basic object tracking. [01541 In at least one embodiment, any number of stereo camera(s) 968 may also be included in a frontfacing configuration. In at least one embodiment, one or more of stereo camera(s) 968 may include an integrated control unit comprising a scalable processing unit, which may provide a programmable logic (“FPGA”) and a multi-core micro-processor with an integrated Controller Area Network (“CAN”) or Ethernet interface on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of an environment of vehicle 900, including a distance estimate for all points in an image. In at least one embodiment, one or more of stereo camera(s) 968 may include, without limitation, compact stereo vision sensor(s) that may include, without limitation, two camera lenses (one each on left and right) and an image processing chip that may measure distance from vehicle 900 to target object and use generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo camera(s) 968 may be used in addition to, or alternatively from, those described herein.

[0155] In at least one embodiment, cameras with a field of view that include portions of environment to sides of vehicle 900 (e.g., side-view cameras) may be used for surround view, providing information used to create and update an occupancy grid, as well as to generate side impact collision warnings. For example, in at least one embodiment, surround camera(s) 974 (e.g., four surround cameras as illustrated in FIG. 9B) could be positioned on vehicle 900. In at least one embodiment, surround camera(s) 974 may include, without limitation, any number and combination of wide-view cameras, fisheye camera(s), 360 degree camera(s), and / or similar cameras. For instance, in at least one embodiment, four fisheye cameras may be positioned on a front, a rear, and sides of vehicle 900. In at least one embodiment, vehicle 900 may use three surround camera(s) 974 (e.g., left, right, and rear), and may leverage one or more other camera(s) (e.g., a forward-facing camera) as a fourth surround-view camera.

[0156] In at least one embodiment, cameras with a field of view that include portions of an environment behind vehicle 900 (e.g., rear-view cameras) may be used for parking assistance, surround view, rear collision warnings, and creating and updating an occupancy grid. In at least one embodiment, a w ide variety of cameras may be used including, but not limited to, cameras that are also suitable as a front-facing camera(s) (e.g., long-range cameras 998 and / or mid-range camera(s) 976, stereo camera(s) 968, infrared camera(s) 972, etc.,) as described herein. [01571 In at least one embodiment, an embodiment consistent with said figures includes one or more processors, circuitry, or systems to cause one or more pinned shared memory buffers to be allocated to one or more neural network accelerators, wherein the one or more pinned shared memory buffers are to store a plurality of neural network training checkpoints to be used by the one or more neural network accelerators to recover from one or more errors detected during training of one or more neural networks, such as described with respect to any of FIGS. 1-5B. [01581 FIG. 9C is a block diagram illustrating an example system architecture for autonomous vehicle 900 of FIG. 9A, according to at least one embodiment. In at least one embodiment, each of components, features, and systems of vehicle 900 in FIG. 9C is illustrated as being connected via a bus 902. In at least one embodiment, bus 902 may include, without limitation, a CAN data interface (alternatively referred to herein as a “CAN bus”). In at least one embodiment, a CAN may be a network inside vehicle 900 used to aid in control of various features and functionality of vehicle 900, such as actuation of brakes, acceleration, braking, steering, windshield wipers, etc. In at least one embodiment, bus 902 may be configured to have dozens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, bus 902 may be read to find steering wheel angle, ground speed, engine revolutions per minute (“RPMs”), button positions, and / or other vehicle status indicators. In at least one embodiment, bus 902 may be a CAN bus that is ASIL B compliant.

[0159] In at least one embodiment, in addition to, or alternatively from CAN, FlexRay and / or Ethernet protocols may be used. In at least one embodiment, there may be any number of busses forming bus 902, which may include, without limitation, zero or more CAN busses, zero or more FlexRay busses, zero or more Ethernet busses, and / or zero or more other topes of busses using different protocols. In at least one embodiment, two or more busses may be used to perform different functions, and / or may be used for redundancy. For example, a first bus may be used for collision avoidance functionality and a second bus may be used for actuation control. In at least one embodiment, each bus of bus 902. may communicate with any of components of vehicle 900, and two or more busses of bus 902 may communicate with corresponding components. In at least one embodiment, each of any number of system(s) on chip(s) (“SoC(s)”) 904 (such as SoC 904(A) and SoC 904(B)), each of controller^) 936, and / or each computer within vehicle may have access to same input data (e.g., inputs from sensors of vehicle 900), and may be connected to a common bus, such CAN bus.

[0160] In at least one embodiment, vehicle 900 may include one or more controller^) 936, such as those described herein with respect to FIG. 9A. In at least one embodiment, controller(s) 936 may be used for a variety of functions. In at least one embodiment, controller(s) 936 may be coupled to any of various other components and systems of vehicle 900, and may be used for control of vehicle 900, artificial intelligence of vehicle 900, infotainment for vehicle 900, and / or other functions.

[0161] In at least one embodiment, vehicle 900 may include any number of SoCs 904. In at least one embodiment, each of SoCs 904 may include, without limitation, central processing units (“CPU(s)”) 906, graphics processing units (“GPU(s)”) 908, processor(s) 910, cache(s) 912, accelerator(s) 914, data store(s) 916, and / or other components and features not illustrated. In at least one embodiment, SoC(s) 904 may be used to control vehicle 900 in a variety of platforms and systems. For example, in at least one embodiment, SoC(s) 904 may be combined in a system (e.g., system of vehicle 900) with a High Definition (“HD”) map 922 which may obtain map refreshes and / or updates via network interface 924 from one or more servers (not shown in FIG. 9C). [01621 In at least one embodiment, CPU(s) 906 may include a CPU cluster or CPU complex (alternatively referred to herein as a “CCPLEX”). In at least one embodiment, CPU(s) 906 may include multiple cores and / or level two (“L2”) caches. For instance, in at least one embodiment, CPU(s) 906 may include eight cores in a coherent multi-processor configuration. In at least one embodiment, CPU(s) 906 may include four dual-core clusters where each cluster has a dedicated L2 cache (e.g., a 2 megabyte (MB) L2 cache). In at least one embodiment, CPU(s) 906 (e.g., CCPLEX) may be configured to support simultaneous cluster operations enabling any combination of clusters of CPU(s) 906 to be active at any given time. [01631 In at least one embodiment, one or more of CPU(s) 906 may implement power management capabilities that include, without limitation, one or more of folio-wing features: individual hardware blocks may be clock-gated automatically when idle to save dynamic power; each core clock may be gated when such core is not actively executing instructions due to execution of Wait for Interrupt (“WFI”) / Wait for Event (“WFE”) instructions; each core may be independently power-gated; each core cluster may be independently clock-gated when all cores are clock-gated or power-gated; and / or each core cluster may be independently power-gated when all cores are power-gated. In at least one embodiment, CPU(s) 906 may-further implement an enhanced algorithm for managing power states, where allowed power states and expected wakeup times are specified, and hardware / microcode determines which best power state to enter for core, cluster, and CCPLEX. In at least one embodiment, processing cores may support simplified power state entry sequences in software wath work offloaded to microcode. [0164j In at least one embodiment, GPU(s) 908 may- include an integrated GPU (alternatively referred to herein as an “iGPU”). In at least one embodiment, GPU(s) 908 may be programmable and may be efficient for parallel workloads. In at least one embodiment, GPU(s) 908 may use an enhanced tensor instruction set. In at least one embodiment, GPU(s) 908 may include one or more streaming microprocessors, where each streaming microprocessor may include a level one (“LI”) cache (e.g., an LI cache with at least 96 KB storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with a 512 KB storage capacity). In at least one embodiment, GPU(s) 908 may include at least eight streaming microprocessors. In at least one embodiment, GPU(s) 908 may use compute application programming interface(s) (API(s)). In at least one embodiment, GPU(s) 908 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA’s CUDA model). [01651 In at least one embodiment, one or more of GPU(s) 908 may be power-optimized for best performance in automotive and embedded use cases. For example, in at least one embodiment, GPU(s) 908 could be fabricated on Fin field-effect transistor (‘"FinFET”) circuitry. In at least one embodiment, each streaming microprocessor may incorporate a number of mixed-precision processing cores partitioned into multiple blocks. For example, and without limitation, 64 PF32 cores and 32 FP64 cores could be partitioned into four processing blocks. In at least one embodiment, each processing block could be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor cores for deep learning matrix arithmetic, a level zero (“L0”) instruction cache, a scheduler (e.g., warp scheduler) or sequencer, a dispatch unit, and / or a 64 KB register file. In at least one embodiment, streaming microprocessors may include independent parallel integer and floating-point data paths to provide for efficient execution of workloads with a mix of computation and addressing calculations. In at least one embodiment, streaming microprocessors may include independent thread scheduling capability to enable finer-grain synchronization and cooperation between parallel threads. In at least one embodiment, streaming microprocessors may include a combined LI data cache and shared memory unit in order to improve performance while simplifying programming. [01661 In at least one embodiment, one or more of GPU(s) 908 may include a high bandwidth memory (“HBM”) and / or a 16 GB HBM2 memory subsystem to provide, in some examples, about 900 GB / second peak memory bandwidth. In at least one embodiment, in addition to, or alternatively from, HBM memory', a synchronous graphics random-access memory' (“SGRAM”) may be used, such as a graphics double data rate type five synchronous random-access memory (“GDDR5”). [01671 In at least one embodiment, GPU (s) 908 may include unified memory technology. In at least one embodiment, address translation services ("‘ATS”) support may be used to allow GPU(s) 908 to access CPU(s) 906 page tables directly. In at least one embodiment, embodiment, when a GPU of GPU(s) 908 memory management unit (“'MMU”) experiences a miss, an address translation request may be transmitted to CPU(s) 906. In response, 2 CPU of CPU(s) 906 may look in its page tables for a virtual-to-physical mapping for an address and transmit translation back to GPU(s) 908, in at least one embodiment. In at least one embodiment, unified memory technology may allow a single unified virtual address space for memory of both CPU(s) 906 and GPU(s) 908, thereby simplifying GPU(s) 908 programming and porting of applications to GPU(s) 908. [0168j In at least one embodiment, GPU(s) 908 may include any number of access counters that may keep track of frequency of access of GPU(s) 908 to memory of other processors. In at least one embodiment, access counter(s) may help ensure that memory' pages are moved to physical memory' of a processor that is accessing pages most frequently, thereby improving efficiency for memory ranges shared between processors. [01691 In at least one embodiment, one or more of SoC(s) 904 may include any number of cache(s) 912, including those described herein. For example, in at least one embodiment, cache(s) 912 could include a level three (“L3”) cache that is available to both CPU(s) 906 and GPU(s) 908 (e.g., that is connected to CPU(s) 906 and GPU(s) 908). In at least one embodiment, cachets) 912 may include a write-back cache that may keep track of states of lines, such as by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, a L3 cache may include 4 MB of memory or more, depending on embodiment, although smaller cache sizes may be used. [01701 In at least one embodiment, one or more of SoC(s) 904 may include one or more accelerators) 914 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, SoC(s) 904 may include a hardware acceleration cluster that may include optimized hardware accelerators and / or large on-chip memory’. In at least one embodiment, large on-chip memory (e.g., 4 MB of SRAM), may enable a hardware acceleration cluster to accelerate neural networks and other calculations. In at least one embodiment, a hardware acceleration cluster may be used to complement GPU(s) 908 and to off-load some of tasks of GPU(s) 908 (e.g., to free up more cycles of GPU(s) 908 for performing other tasks). In at least one embodiment, accelerator(s) 914 could be used for targeted workloads (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.) that are stable enough to be amenable to acceleration. In at least one embodiment, a CNN may include a regionbased or regional convolutional neural networks (“RCNNs”) and Fast RCNNs (e.g., as used for object detection) or other type of CNN. [0171 j In at least one embodiment, accelerators) 914 (e.g., hardware acceleration cluster) may include one or more deep learning accelerator (“DLA”). In at least one embodiment, DLA(s) may include, without limitation, one or more Tensor processing units (“TPUs”) that may be configured to provide an additional ten trillion operations per second for deep learning applications and inferencing. In at least one embodiment, TPUs may be accelerators configured to, and optimized for, performing image processing functions (e.g., for CNNs, RCNNs, etc.). In at least one embodiment, DLA(s) may further be optimized for a specific set of neural network types and floating point operations, as well as inferencing. In at least one embodiment, design of DLA(s) may provide more performance per millimeter than a typical general-purpose GPU, and typically vastly exceeds performance of a CPU. In at least one embodiment, TPU(s) may perform several functions, including a single-instance convolution function, supporting, for example, INT8, INTI6, and FP16 data types for both features and weights, as well as post-processor functions. In at least one embodiment, DLA(s) may quickly and efficiently execute neural networks, especially CNNs, on processed or unprocessed data for any of a variety of functions, including, for example and without limitation: a CNN for object identification and detection using data from camera sensors; a CNN for distance estimation using data from camera sensors; a CNN for emergency vehicle detection and identification and detection using data from microphones; a CNN for facial recognition and vehicle owner identification using data from camera sensors; and / or a CNN for security and / or safety related events,

[0172] In at least one embodiment, DLA(s) may perform any function of GPU(s) 908, and by using an inference accelerator, for example, a designer may target either DLA(s) or GPU(s) 908 for any function. For example, in at least one embodiment, a designer may focus processing of CNNs and floating point operations on DLA(s) and leave other functions to GPU(s) 908 and / or accelerator(s) 914,

[0173] In at least one embodiment, accelerators) 914 may include programmable vision accelerator (“PVA”), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance system (‘"ADAS”) 938, autonomous driving, augmented reality’ (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, P VA may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA may include, for example and without limitation, any number of reduced instruction set computer (“’RISC”) cores, direct memory access (“DMA”), and / or any number of vector processors. [01741 In at least one embodiment, RISC cores may interact with image sensors (e.g., image sensors of any cameras described herein), image signal processor(s), etc. In at least one embodiment, each RISC core may include any amount of memory. In at least one embodiment, RISC cores may use any of a number of protocols, depending on embodiment. In at least one embodiment, RISC cores may execute a real-time operating system (“RTOS”). In at least one embodiment, RISC cores may be implemented using one or more integrated circuit devices, application specific integrated circuits (“ASICs”), and / or memory devices. For example, in at least one embodiment, RISC cores could include an instruction cache and / or a tightly-coupled RAM. [01751 In at least one embodiment, DMA may7 enable components of PVA to access system memory independently of CPU(s) 906. In at least one embodiment, DMA may support any number of features used to provide optimization to a PVA including, but not limited to, supporting multi-dimensional addressing and / or circular addressing. In at least one embodiment, DMA may support up to six or more dimensions of addressing, which may include, without limitation, block width, block height, block depth, horizontal block stepping, vertical block stepping, and / or depth stepping. [01761 In at least one embodiment, vector processors may be programmable processors that may7 be designed to efficiently- and flexibly execute programm ing for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, a PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, a PVA core may- include a processor subsystem, DMA engme(s) (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, a vector processing subsystem may7 operate as a primary processing engine of a PVA, and may include a vector processing unit (“VPU”), an instruction cache, and / or vector memory (e.g., “VMEM”). In at least one embodiment, VPU core may include a digital signal processor such as, for example, a single instruction, multiple data (“SIMD”), very long instruction word (‘VLIW”) digital signal processor. In at least one embodiment, a combination of SIMD and VLIW may enhance throughput and speed.

[0177] In at least one embodiment, each of vector processors may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each of vector processors may be configured to execute independently of other vector processors. In at least one embodiment, vector processors that are included in a particular PVA may be configured to employ data parallelism. For instance, in at least one embodiment, plurality of vector processors included in a single PVA may execute a common computer vision algorithm, but on different regions of an image. In at least one embodiment, vector processors included in a particular PVA may simultaneously execute different computer vision algorithms, on one image, or even execute different algorithms on sequential images or portions of an image. In at least one embodiment, among other things, any number of PVAs may be included in hardware acceleration cluster and any number of vector processors may be included in each PVA. In at least one embodiment, PVA may include additional error correcting code (“ECC”) memory7, to enhance overall system safety.

[0178] In at least one embodiment, accelerator(s) 914 may include a computer vision network on-chip and static random-access memory’ (“SRAM”), for providing a high-bandwidth, low latency7 SRAM for accelerator(s) 914. In at least one embodiment, on-chip memory may include at least 4 MB SRAM, comprising, for example and without limitation, eight field-configurable memory blocks, that may be accessible by both a PVA and a DLA. In at least one embodiment, each pair of memoiy blocks may include an advanced peripheral bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, a PVA and a DLA may access memoiy via a backbone that provides a PVA and a DLA with high-speed access to memory. In at least one embodiment, a backbone may7 include a computer vision network on-chip that interconnects a PVA and a DLA to memory (e.g., using APB).

[0179] In at least one embodiment, a computer vision network on-chip may include an interface that determines, before transmission of any control signal / address / data, that both a PVA and a DLA provide ready and valid signals. In at least one embodiment, an interface may7 provide for separate phases and separate channels for transmitting control signals / addresses / data, as well as burst-type communications for continuous data transfer. In at least one embodiment, an interface may7 comply with International Organization for Standardization (“ISO”) 26262 or International Electrotechnical Commission (“IEC”) 61508 standards, although other standards and protocols may7 be used.

[0180] In at least one embodiment, one or more of SoC(s) 904 may include a real-time ray-tracing hardware accelerator. In at least one embodiment, real-time ray-tracing hardware accelerator may be used to quickly and efficiently determine positions and extents of objects (e.g., within a world model), to generate real-time visualization simulations, for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulation, for comparison to LIDAR data for purposes of localization and / or other functions, and / or for other uses.

[0181] In at least one embodiment, accelerators) 914 can have a wide array of uses for autonomous driving. In at least one embodiment, a PVA may be used for key processing stages in ADAS and autonomous vehicles. In at least one embodiment, a PVA’s capabilities are a good match for algorithmic domains needing predictable processing, at low power and low latency. In other words, a PVA performs well on semi-dense or dense regular computation, even on small data sets, which might require predictable run-times with low latency and low power. In at least one embodiment, such as in vehicle 900, P VAs might be designed to run classic computer vision algorithms, as they can be efficient at object detection and operating on integer math.

[0182] For example, according to at least one embodiment of technology, a PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, although this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation / stereo matching on-the-fly (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, a PVA may perform computer stereo vision functions on inputs from two monocular cameras. [01831 In at least one embodiment, a P VA may be used to perform dense optical flow. For example, in at least one embodiment, a PVA could process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, a PVA is used for time of flight depth processing, by processing raw time of flight data to provide processed time of flight data, for example.

[0184] In at least one embodiment, a DLA may be used to run any type of network to enhance control and driving safety, including for example and without limitation, a neural network that outputs a measure of confidence for each object detection. In at least one embodiment, confidence may be represented or interpreted as a probability, or as providing a relative ‘‘weight” of each detection compared to other detections. In at least one embodiment, a confidence measure enables a system to make further decisions regarding which detections should be considered as true positive detections rather than false positive detections. In at least one embodiment, a system may set a threshold value for confidence and consider only detections exceeding threshold value as true positive detections. In an embodiment in which an automatic emergency braking (“AEB”) system is used, false positive detections would cause vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, highly confident detections may be considered as triggers for AEB. In at least one embodiment, a DLA may run a neural network for regressing confidence value. In at least one embodiment, neural network may take as its input at least some subset of parameters, such as bounding box dimensions, ground plane estimate obtained (e.g., from another subsystem), output from IMU sensor(s) 966 that correlates with vehicle 900 orientation, distance, 3D location estimates of object obtained from neural network and / or other sensors (e.g., LIDAR sensor(s) 964 or RADAR sensor(s) 960), among others.

[0185] In at least one embodiment, one or more of SoC(s) 904 may include data store(s) 916 (e.g., memory). In at least one embodiment, data store(s) 916 may be on-chip memory of SoC(s) 904, which may store neural networks to be executed on GPU(s) 908 and / or a DLA. In at least one embodiment, data store(s) 916 may be large enough in capacity to store multiple instances of neural networks for redundancy and safety7. In at least one embodiment, data store(s) 916 may comprise L2 or L3 cache(s). [0I86] In at least one embodiment, one or more of SoC(s) 904 may include any number of processor(s) 910 (e.g., embedded processors). In at least one embodiment, processor(s) 910 may include a boot and power management processor that may be a dedicated processor and subsystem to handle boot power and management functions and related security7 enforcement. In at least one embodiment, a boot and power management processor may be a part of a boot sequence of SoC(s) 904 and may provide runtime power management services. In at least one embodiment, a boot power and management processor may provide clock and voltage programming, assistance in system low power state transitions, management of SoC(s) 904 thermals and temperature sensors, and / or management of SoC(s) 904 power states. In at least one embodiment, each temperature sensor may be implemented as a ring-oscillator whose output frequency is proportional to temperature, and SoC(s) 904 may use ring-oscillators to detect temperatures of CPLI(s) 906, GPU(s) 908, and / or accelerator(s) 914. In at least one embodiment, if temperatures are determined to exceed a threshold, then a boot and power management processor may7 enter a temperature fault routine and put SoC(s) 904 into a lower power state and / or put vehicle 900 into a chauffeur to safe stop mode (e.g., bring vehicle 900 to a safe stop).

[0187] In at least one embodiment, processors) 910 may further include a set of embedded processors that may serve as an audio processing engine which may be an audio subsystem that enables full hardware support for multi-channel audio over multiple interfaces, and a broad and flexible range of audio I / O interfaces. In at least one embodiment, an audio processing engine is a dedicated processor core with a digital signal processor with dedicated RAM. [01881 In at least one embodiment, processor(s) 910 may further include an always-on processor engine that may7 provide necessary7 hardware features to support low power sensor management and wake use cases. In at least one embodiment, an always-on processor engine may include, without limitation, a processor core, a tightly coupled RAM. supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0189] In at least one embodiment, processors) 910 may further include a safety cluster engine that includes, without limitation, a dedicated processor subsystem to handle safety management for automotive applications. In at least one embodiment, a safety' cluster engine may include, without limitation, two or more processor cores, a tightly coupled RAM, support peripherals (e.g., timers, an interrupt controller, etc.), and / or routing logic. In a safety mode, two or more cores may operate, in at least one embodiment, in a lockstep mode and function as a single core with comparison logic to detect any differences between their operations. In at least one embodiment, processor(s) 910 may further include a real-time camera engine that may include, without limitation, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, processor(s) 910 may' further include a high-dynamic range signal processor that may include, without limitation, an image signal processor that is a hardware engine that is part of a camera processing pipeline. [01901 In at least one embodiment, processor(s) 910 may include a video image compositor that may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions needed by a video playback application to produce a final image for a player window. In at least one embodiment, a video image compositor may perform lens distortion correction on wide-view camera(s) 970, surround camera(s) 974, and / or on in-cabin monitoring camera sensor(s). In at least one embodiment, in-cabin monitoring camera sensor(s) are preferably monitored by a neural network running on another instance of SoC 904, configured to identify in cabin events and respond accordingly. In at least one embodiment, an in-cabin system may perform, without limitation, lip reading to activate cellular service and place a phone call, dictate emails, change a vehicle’s destination, activate or change a vehicle’s infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain functions are available to a driver when a vehicle is operating in an autonomous mode and are disabled otherwise.

[0191] In at least one embodiment, a video image compositor may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, where motion occurs in a video, noise reduction weights spatial information appropriately, decreasing weights of information provided by adjacent frames. In at least one embodiment, where an image or portion of an image does not include motion, temporal noise reduction performed by video image compositor may use information from a previous image to reduce noise in a current image. [01921 In at least one embodiment, a video image compositor may also be configured to perform stereo rectification on input stereo lens frames. In at least one embodiment, a video image compositor may further be used for user interface composition when an operating system desktop is in use, and GPU(s) 908 are not required to continuously render new surfaces. In at least one embodiment, when GPU(s) 908 are powered on and active doing 3D rendering, a video image compositor may be used to offload GPU(s) 908 to improve performance and responsiveness. [01931 In at least one embodiment, one or more SoC of SoC(s) 904 may further include a mobile industry processor interface (“MIPI”) camera serial interface for receiving video and input from cameras, a highspeed interface, and / or a video input block that may be used for a camera and related pixel input functions. In at least one embodiment, one or more of SoC(s) 904 may further include an input / output controllers) that may be controlled by software and may be used for receiving I / O signals that are uncommitted to a specific role.

[0194] In at least one embodiment, one or more SoC of SoC(s) 904 may further include a broad range of peripheral interfaces to enable communication with peripherals, audio encoders / decoders (“codecs”), power management, and / or other devices. In at least one embodiment, SoC(s) 904 may be used to process data from cameras (e.g., connected over Gigabit Multimedia Serial Link and Ethernet channels), sensors (e.g., LIDAR sensor(s) 964, RADAR sensor(s) 960, etc. that may be connected over Ethernet channels), data from bus 902 (e.g., speed of vehicle 900, steering wheel position, etc.), data from GNSS sensor(s) 958 (e.g., connected over a Ethernet bus or a CAN bus), etc. In at least one embodiment, one or more SoC of SoC(s) 904 may further include dedicated high-performance mass storage controllers that may include their own DMA engines, and that may be used to free CPU(s) 906 from routine data management tasks. [01951 In at least one embodiment, SoC(s) 904 may be an end-to-end platform with a flexible architecture that spans automation Levels 3-5, thereby providing a comprehensive functional safety architecture that leverages and makes efficient use of computer vision and ADAS techniques for diversity and redundancy, and provides a platform for a flexible, reliable driving software stack, along with deep learning tools. In at least one embodiment, SoC(s) 904 may be faster, more reliable, and even more energyefficient and space-efficient than conventional systems. For example, in at least one embodiment, accelerator^) 914, when combined with CPU(s) 906, GPU(s) 908, and data store(s) 916, may provide for a fast, efficient platform for Level 3-5 autonomous vehicles.

[0196] In at least one embodiment, computer vision algorithms may be executed on CPUs, which may be configured using a high-level programming language, such as C, to execute a wide variety of processing algorithms across a wide variety of visual data. However, in at least one embodiment, CPUs are oftentimes unable to meet performance requirements of many computer vision applications, such as those related to execution time and power consumption, for example. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real-time, which is used in in-vehicle ADAS applications and in practical Level 3-5 autonomous vehicles. [01971 Embodiments described herein allow for multiple neural networks to be performed simultaneously and / or sequentially, and for results to be combined together to enable Level 3-5 autonomous driving functionality. For example, in at least one embodiment, a CNN executing on a DLA or a discrete GPU (e.g., GPU(s) 920) may include text and word recognition, allowing reading and understanding of traffic signs, including signs for which a neural network has not been specifically trained. In at least one embodiment, a DLA may further include a neural network that is able to identify, interpret, and provide semantic understanding of a sign, and to pass that semantic understanding to path planning modules running on a CPU Complex. [01981 In at least one embodiment, multiple neural networks may be run simultaneously, as for Level 3, 4, or 5 driving. For example, in at least one embodiment, a warning sign stating “Caution: flashing lights indicate icy conditions,” along with an electric light, may be independently or collectively interpreted by several neural networks. In at least one embodiment, such warning sign itself may be identified as a traffic sign by a first deployed neural network (e.g., a neural network that has been trained), text “flashing lights indicate icy conditions” may be interpreted by a second deployed neural network, which informs a vehicle’s path planning software (preferably executing on a CPU Complex) that when flashing lights are detected, icy conditions exist. In at least one embodiment, a flashing light may be identified by operating a third deployed neural network over multiple frames, informing a vehicle’s path-planning software of a presence (or an absence) of flashing lights. In at least one embodiment, all three neural networks may run simultaneously, such as within a DLA and / or on GPU(s) 908. [0199 j In at least one embodiment, a CNN for facial recognition and vehicle owner identification may use data from camera sensors to identify presence of an authorized driver and / or owner of vehicle 900. In at least one embodiment, an always-on sensor processing engine may be used to unlock a vehicle when an owner approaches a driver door and turns on lights, and, in a security mode, to disable such vehicle when an owner leaves such vehicle. In this way, SoC(s) 904 provide for security against theft and / or carjacking.

[0200] In at least one embodiment, a CNN for emergency vehicle detection and identification may use data from microphones 996 to detect and identify emergency vehicle sirens. In at least one embodiment, SoC(s) 904 use a CNN for classifying environmental and urban sounds, as well as classifying visual data. In at least one embodiment, a CNN running on a DLA is trained to identify a relative closing speed of an emergency vehicle (e.g., by using a Doppler effect). In at least one embodiment, a CNN may also be trained to identify emergency vehicles specific to a local area in which a vehicle is operating, as identified by GNSS sensor(s) 958. In at least one embodiment, when operating in Europe, a CNN will seek to detect European sirens, and when in North America, a CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program may be used to execute an emergency vehicle safety routine, slowing a vehicle, pulling over to a side of a road, parking a vehicle, and / or idling a vehicle, with assistance of ultrasonic sensor(s) 962, until emergency vehicles pass.

[0201] In at least one embodiment, vehicle 900 may include CPU(s) 918 (e.g., discrete CPU(s), or dCPU(s)), that may be coupled to SoC(s) 904 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, CPU(s) 918 may include anX86 processor, for example. CPU(s) 918 may be used to perform any of a variety of functions, including arbitrating potentially inconsistent results between ADAS sensors and SoC(s) 904, and / or monitoring status and health of controller(s) 936 and / or an infotainment system on a chip (“infotainment SoC”) 930, for example. In at least one embodiment, SoC(s) 904 includes one or more interconnects, and an interconnect can include a peripheral component interconnect express (PCIe).

[0202] In at least one embodiment, vehicle 900 may include GPU(s) 920 (e.g., discrete GPU(s), or dGPU(s)), that may be coupled to SoC(s) 904 via a high-speed interconnect (e.g., NVIDIA’s NVLINK channel). In at least one embodiment, GPU(s) 920 may provide additional artificial intelligence functionality, such as by executing redundant and / or different neural networks, and may be used to train and / or update neural networks based at least in part on input (e.g., sensor data) from sensors of a vehicle 900.

[0203] In at least one embodiment, vehicle 900 may further include network interface 924 which may include, without limitation, wireless antenna(s) 926 (e.g., one or more wireless antennas for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, network interface 924 may be used to enable wireless connectivity to Internet cloud services (e.g., with server? s) and / or other network devices), with other vehicles, and / or with computing devices (e.g., client devices of passengers). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 900 and another vehicle and / or an indirect link may be established (e.g., across networks and over the Internet). In at least one embodiment, direct links may be provided using a vehicle-to-vehicle communication link. In at least one embodiment, a vehicle-to-vehicle communication link may provide vehicle 900 information about vehicles in proximity’ to vehicle 900 (e.g., vehicles in front of, on a side of, and / or behind vehicle 900). In at least one embodiment, such aforementioned functionality may be part of a cooperative adaptive cruise control functionality of vehicle 900.

[0204] In at least one embodiment, network interface 924 may include an SoC that provides modulation and demodulation functionality’ and enables controller(s) 936 to communicate over wireless networks. In at least one embodiment, network interface 924 may include a radio frequency front-end for up-conversion from baseband to radio frequency, and down conversion from radio frequency to baseband. In at least one embodiment, frequency conversions may be performed in any technically feasible fashion. For example, frequency conversions could be performed through well-known processes, and / or using super-heterodyne processes. In at least one embodiment, radio frequency front end functionality’ may be provided by a separate chip. In at least one embodiment, network interfaces may include wireless functionality' for communicating over LTE, WCDMA. UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0205] In at least one embodiment, vehicle 900 may further include data store(s) 928 which may include, without limitation, off-chip (e.g., off SoC(s) 904) storage. In at least one embodiment, data store(s) 928 may include, without limitation, one or more storage elements including RAM, SRAM, dynamic random-access memory (“DRAM”), video random-access memory (“VRAM”), flash memory', hard disks, and / or other components and / or devices that may store at least one bit of data. [02061 In at least one embodiment, vehicle 900 may further include GNSS sensor(s) 958 (e.g., GPS and / or assisted GPS sensors), to assist in mapping, perception, occupancy grid generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensor(s) 958 may be used, including, for example and without limitation, a GPS using a USB connector with an Ethemet-to-Serial (e.g., RS-232) bridge. [02071 In at least one embodiment, vehicle 900 may further include RADAR sensor(s) 960. In at least one embodiment, RADAR sensor(s) 960 may be used by vehicle 900 for long-range vehicle detection, even in darkness and / or severe weather conditions. In at least one embodiment, RADAR functional safety' levels may be ASIL B. In at least one embodiment, RADAR sensor(s) 960 may use a CAN bus and / or bus 902 (e.g., to transmit data generated by RADAR sensor(s) 960) for control and to access object tracking data, with access to Ethernet channels to access raw data in some examples. In at least one embodiment, a wide variety' of RADAR sensor types may be used. For example, and without limitation, RADAR sensor(s) 960 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more sensor of RADAR sensors(s) 960 is a Pulse Doppler RADAR sensor.

[0208] In at least one embodiment, RADAR sensor(s) 960 may include different configurations, such as long-range with narrow field of view, short-range with wide field of view, short-range side coverage, etc. In at least one embodiment, long-range RADAR may be used for adaptive cruise control functionality'. In at least one embodiment, long-range RADAR systems may provide a broad field of view realized by two or more independent scans, such as within a 250 m (meter) range. In at least one embodiment, RADAR sensor(s) 960 may' help in distinguishing between static and moving objects, and may be used by ADAS system 938 for emergency' brake assist and forward collision w-aming. In at least one embodiment, sensors 960(s) included in a long-range RADAR system may include, without limitation, monostatic multimodal RADAR with multiple (e.g., six or more) fixed RADAR antennae and a high-speed CAN and FlexRay interface. In at least one embodiment, with six antennae, a central four antennae may' create a focused beam pattern, designed to record vehicle’s 900 surroundings at higher speeds with minimal interference from traffic in adjacent lanes. In at least one embodiment, another two antennae may expand field of view, making it possible to quickly detect vehicles entering or leaving a lane of vehicle 900.

[0209] In at least one embodiment, mid-range RADAR systems may include, as an example, a range of up to 160 m (front) or 80 m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, short-range RADAR systems may include, without limitation, any number of RADAR sensor(s) 960 designed to be installed at both ends of a rear bumper. When installed at both ends of a rear bumper, in at least one embodiment, a RADAR sensor system may create two beams that constantly monitor blind spots in a rear direction and next to a vehicle. In at least one embodiment, short-range RADAR systems may be used in ADAS system 93 8 for blind spot detection and / or lane change assist.

[0210] In at least one embodiment, vehicle 900 may further include ultrasonic sensor(s) 962. In at least one embodiment, ultrasonic sensor(s) 962, which may be positioned at a front, a back, and / or side location of vehicle 900, may be used for parking assist and / or to create and update an occupancy grid. In at least one embodiment, a wide variety of ultrasonic sensor(s) 962 may be used, and different ultrasonic sensor(s) 962 may be used for different ranges of detection (e.g., 2.5 m, 4 m). In at least one embodiment, ultrasonic sensor(s) 962 may operate at functional safety’ levels of ASIL B. [02111 In at least one embodiment, vehicle 900 may include LIDAR sensor(s) 964. In at least one embodiment, LIDAR sensor(s) 964 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, LIDAR sensor(s) 964 may operate at functional safety' level ASIL B. In at least one embodiment, vehicle 900 may include multiple LIDAR sensors 964 (e.g., two, four, six, etc.) that may use an Ethernet channel (e.g., to provide data to a Gigabit Ethernet switch). [02121 In at least one embodiment, LIDAR sensor(s) 964 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available LIDAR sensor(s) 964 may’ have an advertised range of approximately 100 m, with an accuracy’ of 2 cm to 3 cm, and with support for a 100 Mbps Ethernet connection, for example. In at least one embodiment, one or more non-protruding LIDAR sensors may be used. In such an embodiment, LIDAR sensor(s) 964 may include a small device that may be embedded into a front, a rear, a side, and / or a corner location of vehicle 900. In at least one embodiment, LIDAR sensor(s) 964, in such an embodiment, may provide up to a 120-degree horizontal and 35-degree vertical field-of-view, with a 200 m range even for low-reflectivity' objects. In at least one embodiment, front-mounted LIDAR sensor(s) 964 may be configured for a horizontal field of view between 45 degrees and 135 degrees. [02131 In at least one embodiment, LIDAR technologies, such as 3D flash LIDAR, may also be used. In at least one embodiment, 3D flash LIDAR uses a flash of a laser as a transmission source, to illuminate surroundings of vehicle 900 up to approximately 200 m. In at least one embodiment, a flash LIDAR unit includes, without limitation, a receptor, which records laser pulse transit time and reflected light on each pixel, which in turn corresponds to a range from vehicle 900 to objects. In at least one embodiment, flash LIDAR may allow for highly accurate and distortion-free images of surroundings to be generated with every' laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, one at each side of vehicle 900. In at least one embodiment, 3D flash LIDAR systems include, without limitation, a solid-state 3D staring array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, flash LIDAR device may use a 5 nanosecond class 1 (eye-safe) laser pulse per frame and may capture reflected laser light as a 3D range point cloud and co-registered intensity data. [02141 In at least one embodiment, vehicle 900 may further include IMU sensor(s) 966. In at least one embodiment, IMU sensor(s) 966 may be located at a center of a rear axle of vehicle 900. In at least one embodiment, IMU sensor(s) 966 may include, for example and without limitation, accelerometer(s), magnetometer(s), gyroscope(s), a magnetic compass, magnetic compasses, and / or other sensor types. In at least one embodiment, such as in six-axis applications, IMU sensor(s) 966 may include, without limitation, accelerometers and gyroscopes. In at least one embodiment, such as in nine-axis applications, IMU sensor(s) 966 may include, without limitation, accelerometers, gyroscopes, and magnetometers.

[0215] In at least one embodiment, IMU sensor(s) 966 may be implemented as a miniature, high performance GPS-Aided Inertial Navigation System (“GPS / INS”) that combines micro-electro-mechanical systems (“MEMS”) inertial sensors, a high-sensitivity GPS receiver, and advanced Kalman filtering algorithms to provide estimates of position, velocity’, and attitude. In at least one embodiment, IMU sensor(s) 966 may enable vehicle 900 to estimate its heading without requiring input from a magnetic sensor by directly observing and correlating changes in velocity from a GPS to IMU sensor(s) 966. In at least one embodiment, IMU sensor(s) 966 and GNSS sensor(s) 958 may be combined in a single integrated unit. [02161 In at least one embodiment, vehicle 900 may include microphone(s) 996 placed in and / or around vehicle 900. In at least one embodiment, microphone(s) 996 may be used for emergency vehicle detection and identification, among other things. [02171 In at least one embodiment, vehicle 900 may further include any number of camera types, including stereo camera(s) 968, wide-view camera(s) 970, infrared camera(s) 972, surround camera(s) 974, long-range camera(s) 998, mid-range camera(s) 976, and / or other camera types. In at least one embodiment, cameras may be used to capture image data around an entire periphery of vehicle 900. In at least one embodiment, which ty pes of cameras used depends on vehicle 900. In at least one embodiment, any combination of camera ty pes may be used to provide necessary’ coverage around vehicle 900. In at least one embodiment, a number of cameras deployed may differ depending on embodiment. For example, in at least one embodiment, vehicle 900 could include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. In at least one embodiment, cameras may support, as an example and without limitation, Gigabit Multimedia Serial Link (“GMSL”) and / or Gigabit Ethernet communications. In at least one embodiment, each camera might be as described with more detail previously herein with respect to FIG. 9A and FIG. 9B. [0218 j In at least one embodiment, vehicle 900 may further include vibration sensor(s) 942. In at least one embodiment, vibration sensor(s) 942 may measure vibrations of components of vehicle 900, such as axle(s). For example, in at least one embodiment, changes in vibrations may indicate a change in road surfaces. In at least one embodiment, when two or more vibration sensors 942 are used, differences between vibrations may be used to determine friction or slippage of road surface (e.g., when a difference in vibration is between a power-driven axle and a freely rotating axle). [02191 In at least one embodiment, vehicle 900 may include ADAS system 938. In at least one embodiment, ADAS system 938 may include, without limitation, an SoC, in some examples. In at least one embodiment, ADAS system 938 may include, without limitation, any number and combination of an autonomous / adaptive / automatic cruise control (“ACC”) system, a cooperative adaptive cruise control (“CACC”) system, a forward crash warning (“FCW”) system, an automatic emergency braking (“AEB”) system, a lane departure warning (“LDW”) system, a lane keep assist (“LKA”) system, a blind spot warning (“BSW”) system, a rear cross-traffic warning (“RCTW”) system, a collision warning (“CW”) system, a lane centering (“LC”) system, and / or other systems, features, and / or functionality. [02201 In at least one embodiment, ACC system may use RADAR sensor(s) 960, LIDAR sensor(s) 964, and / or any number of camera(s). In at least one embodiment, ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, a longitudinal ACC system monitors and controls distance to another vehicle immediately ahead of vehicle 900 and automatically adjusts speed of vehicle 900 to maintain a safe distance from vehicles ahead. In at least one embodiment, a lateral ACC system performs distance keeping, and advises vehicle 900 to change lanes when necessary’. In at least one embodiment, a lateral ACC is related to other ADAS applications, such as LC and CW.

[0221] In at least one embodiment, a CACC system uses information from other vehicles that may be received via network interface 924 and / or wireless antenna(s) 926 from other vehicles via a wireless link, or indirectly, over a network connection (e.g., over the Internet). In at least one embodiment, direct links may be provided by a vehicle-to-vehicle (“V2V”) communication link, while indirect links may be provided by an infrastructure-to-vehicle (“12V”) communication link. In general, V2V communication provides information about immediately preceding vehicles (e.g., vehicles immediately ahead of and in same lane as vehicle 900), while I2V communication provides information about traffic further ahead. In at least one embodiment, a CACC system may include either or both I2V and V2V information sources. In at least one embodiment, given information of vehicles ahead of vehicle 900, a CACC system may be more reliable and it has potential to improve traffic flow smoothness and reduce congestion on road.

[0222] In at least one embodiment, an FCW system is designed to alert a driver to a hazard, so that such driver may take corrective action. In at least one embodiment, an FCW system uses a front-facing camera and / or RADAR sensor(s) 960, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, that is electrically coupled to provide driver feedback, such as a display, speaker, and / or vibrating component. In at least one embodiment, an FCW system may provide a warning, such as in form of a sound, visual warning, vibration and / or a quick brake pulse. [02231 In at least one embodiment, an AEB system detects an impending forward collision with another vehicle or other object, and may automatically apply brakes if a driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, AEB system may use front-facing camera(s) and / or RADAR sensor(s) 960, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, In at least one embodiment, when an AEB system detects a hazard, it will typically first alert a driver to take corrective action to avoid collision and, if that driver does not take corrective action, that AEB system may automatically apply brakes in an effort to prevent, or at least mitigate, an impact of a predicted collision. In at least one embodiment, an AEB system may include techniques such as dynamic brake support and / or crash imminent braking.

[0224] In at least one embodiment, an LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to alert driver when vehicle 900 crosses lane markings. In at least one embodiment, an LDW system does not activate when a driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, an LDW system may use front-side facing cameras, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, that is electrically coupled to provide driver feedback, such as a display, speaker, and / or vibrating component. In at least one embodiment, an LKA system is a variation of an LDW system. In at least one embodiment, an LKA system provides steering input or braking to correct vehicle 900 if vehicle 900 starts to exit its lane.

[0225] In at least one embodiment, a BSW system detects and warns a driver of vehicles in an automobile’s blind spot. In at least one embodiment, a BSW system may provide a visual, audible, and / or tactile alert to indicate that merging or changing lanes is unsafe. In at least one embodiment, a BSW system may provide an additional warning when a driver uses a tarn signal. In at least one embodiment, a BSW system may use rear-side facing camera(s) and / or RADAR sensor(s) 960, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, that is electrically coupled to driver feedback, such as a display, speaker, and / or vibrating component.

[0226] In at least one embodiment, an R.CTW system may provide visual, audible, and / or tactile notification when an object is detected outside a rear-camera range when vehicle 900 is backing up. In at least one embodiment, an RCTW system includes an AEB system to ensure that vehicle brakes are applied to avoid a crash. In at least one embodiment, an RCTW system may use one or more rear-facing RADAR sensor(s) 960, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, that is electrically coupled to provide driver feedback, such as a display, speaker, and / or vibrating component.

[0227] In at least one embodiment, conventional ADAS systems may be prone to false positive results which may be annoying and distracting to a driver, but typically are not catastrophic, because conventional ADAS systems alert a driver and allow that driver to decide whether a safety condition truly exists and act accordingly. In at least one embodiment, vehicle 900 itself decides, in case of conflicting results, whether to heed result from a primary computer or a secondary computer (e.g., a first controller or a second controller of controllers 936). For example, in at least one embodiment, ADAS system 938 may be a backup and / or secondary’ computer for providing perception information to a backup computer rationality module. In at least one embodiment, a backup computer rationality monitor may run redundant diverse software on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, outputs from ADAS system 938 may be provided to a supervisory' MCU. In at least one embodiment, if outputs from a primary' computer and outputs from a secondary’ computer conflict, a supervisory’ MCU determines how to reconcile conflict to ensure safe operation.

[0228] In at least one embodiment, a primary computer may be configured to provide a supervisory' MCU with a confidence score, indicating that primary' computer’s confidence in a chosen result. In at least one embodiment, if that confidence score exceeds a threshold, that supervisory' MCU may follow that primary’ computer’s direction, regardless of whether that secondary computer provides a conflicting or inconsistent result. In at least one embodiment, where a confidence score does not meet a threshold, and where primary and secondary computers indicate different results (e.g., a conflict), a supervisory' MCU may arbitrate between computers to determine an appropriate outcome. [02291 In at least one embodiment, a supervisory MCU may be configured to run a neural network(s) that is trained and configured to determine, based at least in part on outputs from a primary computer and outputs from a secondary' computer, conditions under which that second ary computer provides false alarms. In at least one embodiment, neural network(s) in a supervisory MCU may' learn when a secondary computer’s output may' be trusted, and when it cannot. For example, in at least one embodiment, when that secondary computer is a RADAR-based FCW system, a neural network(s) in that supervisory MCU may learn when an FCW system is identifying metallic objects that are not, in fact, hazards, such as a drainage grate or manhole cover that triggers an alarm. In at least one embodiment, when a secondary computer is a camera-based LDW system, a neural network in a supervisory MCU may' learn to override LDW when bicyclists or pedestrians are present and a lane departure is, in fact, a safest maneuver. In at least one embodiment, a supervisory MCU may include at least one of a DLA or a GPU suitable for running neural network(s) with associated memory. In at least one embodiment, a supervisory MCU may comprise and / or be included as a component of SoC(s) 904.

[0230] In at least one embodiment, ADAS system 938 may include a secondary computer that performs ADAS functionality using traditional rules of computer vision. In at least one embodiment, that secondary' computer may use classic computer vision rales (if-then), and presence of a neural network(s) in a supervisory MCU may improve reliability', safety and performance. For example, in at least one embodiment, diverse implementation and intentional non-identity makes an overall system more fault-tolerant, especially to faults caused by software (or software-hardware interface) functionality'. For example, in at least one embodiment, if there is a software bug or error in software running on a primary' computer, and non-identical software code running on a secondary computer provides a consistent overall result, then a supervisory MCU may have greater confidence that an overall result is correct, and a bug in software or hardware on that primary computer is not causing a material error. [0231 j In at least one embodiment, an output of ADAS system 938 may be fed into a primary computer’s perception block and / or a primary computer’s dynamic driving task block. For example, in at least one embodiment, if ADAS system 938 indicates a forward crash warning due to an object immediately ahead, a perception block may use this information when identifying objects. In at least one embodiment, a secondary computer may have its own neural network that is trained and thus reduces a risk of false positives, as described herein. [02321 In at least one embodiment, vehicle 900 may further include infotainment SoC 930 (e.g., an in-vehicle infotainment system (IVT)). Although illustrated and described as an SoC, infotainment system SoC 930, in at least one embodiment, may not be an SoC, and may include, without limitation, two or more discrete components. In at least one embodiment, infotainment SoC 930 may include, without limitation, a combination of hardware and software that may be used to provide audio (e.g., music, a personal digital assistant, navigational instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g., navigation systems, rear-parking assistance, a radio data system, vehicle related information such as fuel level, total distance covered, brake fuel level, oil level, door open / close, air filter information, etc.) to vehicle 900. For example, infotainment SoC 930 could include radios, disk players, navigation systems, video players, USB and Bluetooth connectivity’, carputers, in-car entertainment, WiFi, steering wheel audio controls, bands free voice control, a heads-up display (“HUD”), HM1 display 934, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, infotainment SoC 930 may further be used to provide information (e.g., visual and / or audible) to user(s) of vehicle 900, such as information from ADAS system 938, autonomous driving information such as planned vehicle maneuvers, trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other inform ation.

[0233] In at least one embodiment, infotainment SoC 930 may include any amount and type of GPU functionality. In at least one embodiment, infotainment SoC 930 may communicate over bus 902 with other devices, systems, and / or components of vehicle 900. In at least one embodiment, infotainment SoC 930 may be coupled to a supervisory MCU such that a GPU of an infotainment system may perform some self-driving functions in event that primary control1er(s) 936 (e.g., primary and / or backup computers of vehicle 900) fail. In at least one embodiment, infotainment SoC 930 may put vehicle 900 into a chauffeur to safe stop mode, as described herein.

[0234] In at least one embodiment, vehicle 900 may further include instrument cluster 932 (e.g., a digital dash, an electronic instrument cluster, a digital instrament panel, etc.). In at least one embodiment, instrument cluster 932 may include, without limitation, a controller and / or supercomputer (e.g., a discrete controller or supercomputer). In at least one embodiment, instrument cluster 932 may include, without limitation, any number and combination of a set of instrumentation such as a speedometer, fuel level, oil pressure, tachometer, odometer, turn indicators, gearshift position indicator, seat belt warning iight(s), parking-brake warning light(s), engine-malfunction light(s), supplemental restraint system (e.g,, airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared among infotainment SoC 930 and instrument cluster 932. In at least one embodiment, instrument cluster 932 may be included as part of infotainment SoC 930, or vice versa. [02351 In at least one embodiment, an embodiment consistent with said figures includes one or more processors, circuitry, or systems to cause one or more pinned shared memory buffers to be allocated to one or more neural network accelerators, wherein the one or more pinned shared memory' buffers are to store a plurality’ of neural network training checkpoints to be used by the one or more neural network accelerators to recover from one or more errors detected during training of one or more neural networks, such as described with respect to any of FIGS. 1-5B,

[0236] FIG. 9D is a diagram of a system for communication between cloud-based server(s) and autonomous vehicle 900 of FIG. 9A, according to at least one embodiment. In at least one embodiment, system may include, without limitation, server(s) 978, network(s) 990, and any number and type of vehicles, including vehicle 900. In at least one embodiment, server(s) 978 may include, without limitation, a plurality of GPUs 984(A)-984(H) (collectively referred to herein as GPUs 984), PCIe switches 982(A)-982(D) (collectively referred to herein as PCIe switches 982), and / or CPUs 980(A)-980(B) (collectively referred to herein as CPUs 980). In at least one embodiment, GPUs 984, CPUs 980, and PCIe switches 982 may be interconnected with high-speed interconnects such as, for example and without limitation, NVLink interfaces 988 developed by NVIDIA and / or PCIe connections 986. In at least one embodiment, GPUs 984 are connected via an NVLink and / or NVSwitch SoC and GPUs 984 and PCIe switches 982 are connected via PCIe interconnects. Although eight GPUs 984, two CPUs 980, and four PCIe switches 982 are illustrated, this is not intended to be limiting. In at least one embodiment, each of server(s) 978 may include, without limitation, any number of GPUs 984, CPUs 980, and / or PCIe switches 982, in any combination. For example, in at least one embodiment, server(s) 978 could each include eight, sixteen, thirty-two, and / or more GPUs 984,

[0237] In at least one embodiment, server(s) 978 may receive, over network(s) 990 and from vehicles, image data representative of images showing unexpected or changed road conditions, such as recently commenced road-work. In at least one embodiment, server(s) 978 may transmit, over network(s) 990 and to vehicles, neural networks 992, updated or otherwise, and / or map information 994, including, without limitation, information regarding traffic and road conditions. In at least one embodiment, updates to map information 994 may include, without limitation, updates for HD map 922, such as information regarding construction sites, potholes, detours, flooding, and / or other obstructions. In at least one embodiment, neural networks 992, and / or map information 994 may have resulted from new training and / or experiences represented in data received from any number of vehicles in an environment, and / or based at least in part on training performed at a data center (e.g., using server(s) 978 and / or other servers).

[0238] In at least one embodiment, server(s) 978 may be used to train machine learning models (e.g., neural networks) based at least in part on training data. In at least one embodiment, training data may be generated by vehicles, and / or may be generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is tagged (e.g,, where associated neural network benefits from supervised learning) and / or undergoes other pre-processing. In at least one embodiment, any amount of training data is not tagged and / or pre-processed (e.g., where associated neural network does not require supervised learning). In at least one embodiment, once machine learning models are trained, machine learning models may be used by vehicles (e.g., transmitted to vehicles over network(s) 990), and / or machine learning models may be used by server(s) 978 to remotely monitor vehicles.

[0239] In at least one embodiment, server(s) 978 may receive data from vehicles and apply data to up-to-date real-time neural networks for real-time intelligent inferencing. In at least one embodiment, server(s) 978 may include deep-learning supercomputers and / or dedicated AI computers powered by GPU(s) 984, such as a DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, server(s) 978 may include deep learning infrastructure that uses CPU-powered data centers.

[0240] In at least one embodiment, deep-learning infrastructure of server(s) 978 may be capable of fast, real-time inferencing, and may use that capability to evaluate and verify health of processors, software, and / or associated hardware in vehicle 900. For example, in at least one embodiment, deep-learning infrastructure may receive periodic updates from vehicle 900, such as a sequence of images and / or objects that vehicle 900 has located in that sequence of images (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, deep-learning infrastructure may run its own neural network to identify objects and compare them with objects identified by vehicle 900 and, sf results do not match and deep-learning infrastructure concludes that AI in vehicle 900 is malfunctioning, then server(s) 978 may transmit a signal to vehicle 900 instructing a fail-safe computer of vehicle 900 to assume control, notify passengers, and complete a safe parking maneuver.

[0241] In at least one embodiment, server(s) 978 may include GPU(s) 984 and one or more programmable inference accelerators (e.g., NVIDIA’s TensorRT 3 devices). In at least one embodiment, a combination of GPU-powered servers and inference acceleration may make real-time responsiveness possible. In at least one embodiment, such as where performance is less critical, servers powered by CPUs, FPGAs, and other processors may be used for inferencing. In at least one embodiment, hardware structure(s) 615 are used to perform one or more embodiments. Details regarding hardware structure(s) 615 are provided herein in conjunction with FIGS. 6A and / or 6B. COMPUTER SYSTEMS [02421 FIG. 10 is a block diagram illustrating an exemplaiy computer system, which may be a system with interconnected devices and components, a system-on-a-chip (SOC) or some combination thereof formed with a processor that may include execution units to execute an instruction, according to at least one embodiment. In at least one embodiment, a computer system 1000 may include, without limitation, a component, such as a processor 1002 to employ execution units including logic to perform algorithms for process data, in accordance with present disclosure, such as in embodiment described herein. In at least one embodiment, computer system 1000 may include processors, such as PENTIUM® Processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including PCs having other microprocessors, engineering workstations, set-top boxes and like) may also be used. In at least one embodiment, computer system 1000 may execute a version of WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (UNIX and Linux, for example), embedded software, and / or graphical user interfaces, may also be used. [02431 Embodiments may be used in other devices such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (‘‘PDAs”), and handheld PCs. In at least one embodiment, embedded applications may include a microcontroller, a digital signal processor (“DSP”), system on a chip, network computers (“NetPCs”), set-top boxes, network hubs, -wide area network (“WAN”) switches, or any other system that may perform one or more instructions in accordance with at least one embodiment. [02441 In at least one embodiment, computer system 1000 may include, without limitation, processor 1002 that may include, without limitation, one or more execution units 1008 to perform machine learning model training and / or inferencing according to techniques described herein. In at least one embodiment, computer system 1000 is a single processor desktop or server system, but in another embodiment, computer system 1000 may be a multiprocessor system. In at least one embodiment, processor 1002 may include, without limitation, a complex instruction set computer (“CISC”) microprocessor, a reduced instruction set computing (“RISC”) microprocessor, a very long instruction word (“VLIW”) microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor, for example. In at least one embodiment, processor 1002 may be coupled to a processor bus 1010 that may transmit data signals between processor 1002 and other components in computer system 1000.

[0245] In at least one embodiment, processor 1002. may include, without limitation, a Level 1 (“LI”) internal cache memory (“cache”) 1004. In at least one embodiment, processor 1002 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory' may reside external to processor 1002. Other embodiments may also include a combination of both internal and external caches depending on particular implementation and needs. In at least one embodiment, a register file 1006 may store different types of data in various registers including, without limitation, integer registers, floating point registers, status registers, and an instruction pointer register. [02461 In at least one embodiment, execution unit 1008, including, without limitation, logic to perform integer and floating point operations, also resides in processor 1002. In at least one embodiment, processor 1002 may also include a m icrocode (“ucode”) read only memory (“ROM”) that stores microcode for certain macro instructions. In at least one embodiment, execution unit 1008 may include logic to handle a packed instruction set 1009. In at least one embodiment, by including packed instruction set 1009 in an instruction set of a general-purpose processor, along with associated circuitry to execute instructions, operations used by many multimedia applications may be performed using packed data in processor 1002. In at least one embodiment, many multimedia applications may be accelerated and executed more efficiently by using a full width of a processor’s data bus for performing operations on packed data, which may eliminate a need to transfer smaller units of data across that processor’s data bus to perform one or more operations one data element at a time.

[0247] In at least one embodiment, execution unit 1008 may also be used in m icrocontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1000 may include, without limitation, a memory’ 1020. In at least one embodiment, memory' 1020 may be a Dynamic Random Access Memory' (“DRAM”) device, a Static Random Access Memory (“SRAM”) device, a flash memory' device, or another memory’ device. In at least one embodiment, memory 1020 may store instruction(s) 1019 and / or data 1021 represented by data signals that may be executed by processor 1002.

[0248] In at least one embodiment, a system logic chip may be coupled to processor bus 1010 and memory 1020. In at least one embodiment, a system logic chip may include, without limitation, a memory-controller hub (“MCH”) 1016, and processor 1002 may communicate with MCH 1016 via processor bus 1010. In at least one embodiment, MCH 1016 may provide a high bandwidth memory7 path 1018to memory 1020 for instruction and data storage and for storage of graphics commands, data and textures. In at least one embodiment, MCH 1016 may direct data signals between processor 1002, memory 1020, and other components in computer system 1000 and to bridge data signals between processor bus 1010, memory7 1020, and a system I / O interface 1022. In at least one embodiment, a system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 1016 may7 be coupled to memory7 1020 through high bandwidth memory path 1018 and a graphics / video card 1012 may be coupled to MCH 1016 through an Accelerated Graphics Port ("‘AGP”) interconnect 1014. [02491 In at least one embodiment, computer system 1000 may use system I / O interface 1022 as a proprietary’ hub interface bus to couple MCH 1016 to an I / O controller hub (“ICH”) 1030. In at least one embodiment, ICH 1030 may provide direct connections to some I / O devices via a local I / O bus. In at least one embodiment, a local I / O bus may include, without limitation, a high-speed I / O bus for connecting peripherals to memory' 1020, a chipset, and processor 1002. Examples may include, without limitation, an audio controller 1029, a firmware hub (“flash BIOS’’) 1028, a wireless transceiver 1026, a data storage 1024, a legacy I / O controller 1023 containing user input and keyboard interfaces 1025, a serial expansion port 1027, such as a Universal Serial Bus (“USB”) port, and a network controller 1034. In at least one embodiment, data storage 1024 may7 comprise a hard disk drive, a floppy7 disk drive, a CD-ROM device, a flash memory' device, or other mass storage device. [02501 In at least one embodiment, FIG. 10 illustrates a system, -which includes interconnected hardware devices or “chips”, whereas in other embodiments, FIG. 10 may illustrate an exemplary- SoC. In at least one embodiment, devices illustrated in FIG. 10 may- be interconnected with proprietary- interconnects, standardized interconnects (e.g., PCIe) or some combination thereof. In at least one embodiment, one or more components of computer system 1000 are interconnected using compute express link (CXL) interconnects.

[0251] Logic 615 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding logic 615 are provided herein in conjunction with FIGS. 6A and / or 6B. In at least one embodiment, logic 615 may be used in computer system 1000 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein. [02521 In at least one embodiment, an embodiment consistent with said figures includes one or more processors, circuitry, or systems to cause one or more pinned shared memory buffers to be allocated to one or more neural network accelerators, wherein the one or more pinned shared memory buffers are to store a plurality of neural network training checkpoints to be used by the one or more neural network accelerators to recover from one or more errors detected during training of one or more neural networks, such as described -with respect to any of FIGS. 1-5B.

[0253] FIG. 11 is a block diagram illustrating an electronic device 1100 for utilizing a processor 1110, according to at least one embodiment. In at least one embodiment, electronic device 1100 may be, for example and w ithout limitation, a notebook, a tower server, a rack server, a blade sen'er, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device. [02541 In at least one embodiment, electronic device 1100 may include, without limitation, processor 1110 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor 1110 is coupled using a bus or interface, such as a FC bus, a System Management Bus (“SMBus”), a Low Pin Count (LPC) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, a Universal Serial Bus (“USB”) (versions 1, 2, 3, etc.), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, FIG. 11 illustrates a system, which includes interconnected hardware devices or “chips”, whereas in other embodiments, FIG. 11 may illustrate an exemplary SoC. In at least one embodiment, devices illustrated in FIG. 11 may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe) or some combination thereof. In at least one embodiment, one or more components of FIG. 11 are interconnected using compute express link (CXL) interconnects.

[0255] In at least one embodiment, FIG. 11 may include a display 1124, a touch screen 1125, a touch pad 1130, a Near Field Communications unit (“NFC”) 1145, a sensor hub 1140, a thermal sensor 1146, an Express Chipset (“EC”) 1135, a Trusted Platform Module (“TPM”) 1138, BlOS / finnware / flash memory (“BIOS, FW Flash”) 1122, a DSP 1160, a drive 1120 such as a Solid State Disk (“SSD”) or a Hard Disk Drive (“HDD”), a wireless local area network unit (“WLAN”) 1150, a Bluetooth unit 1152, a Wireless Wide Area Network unit (“WWAN”) 1156, a Global Positioning System (GPS) unit 1155, a camera (“USB 3.0 camera”) 1154 such as a USB 3.0 camera, and / or a Low Power Double Data Rate (“LPDDR”) memory unit (“LPDDR3”) 1115 implemented in, for example, an LPDDR3 standard. These components may each be implemented in any suitable manner. [02561 In at least one embodiment, other components may be communicatively coupled to processor 1110 through components described herein. In at least one embodiment, an accelerometer 1141, an ambient light sensor (“ALS”) 1142, a compass 1143, and a gyroscope 1144 may be communicatively coupled to sensor hub 1140. In at least one embodiment, a thermal sensor 1139, a fan 1137, a keyboard 1136, and touch pad 1130 may be communicatively coupled to EC 1135. In at least one embodiment, speakers 1163, headphones 1164, and a microphone (“mic”) 1165 may be communicatively coupled to an audio unit ("‘audio codec and class D amp”) 1162, which may in turn be communicatively coupled to DSP 1160. In at least one embodiment, audio unit 1162 may include, for example and without limitation, an audio coder / decoder (“codec”) and a class D amplifier. In at least one embodiment, a SIM card (“SIM”) 1157 may be communicatively coupled to WWAN unit 1156. In at least one embodiment, components such as WLAN unit 1150 and Bluetooth unit 1152, as well as MAVAN unit 1156 may be implemented in a Next Generation Form Factor (“NGFF”).

[0257] Logic 615 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding logic 615 are provided herein in conjunction with FIGS. 6A and / or 6B. In at least one embodiment, logic 615 may be used in electronic device 1100 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0258] In at least one embodiment, an embodiment consistent with said figures includes one or more processors, circuitry, or systems to cause one or more pinned shared memory buffers to be allocated to one or more neural network accelerators, wherein the one or more pinned shared memory buffers are to store a plurality of neural network training checkpoints to be used by the one or more neural network accelerators to recover from one or more errors detected during training of one or more neural networks, such as described with respect to any of FIGS. 1-5B.

[0259] FIG. 12 illustrates a computer system 1200, according to at least one embodiment. In at least one embodiment, computer system 1200 is configured to implement various processes and methods described throughout this disclosure. [02601 In at least one embodiment, computer system 1200 comprises, without limitation, at least one central processing unit (“CPU”) 1202 that is connected to a communication bus 1210 implemented using any suitable protocol, such as PCI (“Peripheral Component Interconnect”), peripheral component interconnect express (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol(s). In at least one embodiment, computer system 1200 includes, without limitation, a main memory7 1204 and control logic (e.g., implemented as hardware, software, or a combination thereof) and data are stored in main memory7 1204, which may take form of random access memory7 (“RAM”). In at least one embodiment, a network interface subsystem (“network interface”) 1222 provides an interface to other computing devices and networks for receiving data from and transmitting data to other systems with computer system 1200. [02611 In at least one embodiment, computer system 1200, in at least one embodiment, includes, without limitation, input devices 1208, a parallel processing system 1212, and display devices 1206 that can be implemented using a conventional cathode ray tube (“CRT”), a liquid crystal display (“LCD”), a light emitting diode (“LED”) display, a plasma display, or other suitable display technologies. In at least one embodiment, user input is received from input devices 1208 such as keyboard, mouse, touchpad, microphone, etc. In at least one embodiment, each module described herein can be situated on a single semiconductor platform to form a processing system.

[0262] Logic 615 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 615 are provided herein in conjunction with FIGS. 6A and / or 613. In at least one embodiment, logic 615 may be used in computer system 1200 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein. [02631 In at least one embodiment, an embodiment consistent with said figures includes one or more processors, circuitry, or systems to cause one or more pinned shared memory buffers to be allocated to one or more neural network accelerators, wherein the one or more pinned shared memory buffers are to store a plurality of neural network training checkpoints to be used by the one or more neural network accelerators to recover from one or more errors detected during training of one or more neural networks, such as described -with respect to any of FIGS. 1-5B.

[0264] FIG. 13 illustrates a computer system 1300, according to at least one embodiment. In at least one embodiment, computer system 1300 includes, without limitation, a computer 1310 and a USB stick 1320. In at least one embodiment, computer 1310 may include, without limitation, any number and type of processors) (not sho-wn) and a memory' (not shown). In at least one embodiment, computer 1310 includes, without limitation, a server, a cloud instance, a laptop, and a desktop computer. [0265 j In at least one embodiment, USB stick 1320 includes, without limitation, a processing unit 1330, a USB interface 1340, and USB interface logic 1350. In at least one embodiment, processing unit 1330 may be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, processing unit 1330 may include, without limitation, any number and type of processing cores (not shown). In at least one embodiment, processing unit 1330 composes an application specific integrated circuit (“ASIC”) that is optimized to perform any amount and type of operations associated with machine learning. For instance, in at least one embodiment, processing unit 1330 is a tensor processing unit (“TPC”) that is optimized to perform machine learning inference operations. In at least one embodiment, processing unit 1330 is a vision processing unit (“VPU”) that is optimized to perform machine vision and machine learning inference operations. [02661 In at least one embodiment, USB interface 1340 may be any type of USB connector or USB socket. For instance, in at least one embodiment, USB interface 1340 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, USB interface 1340 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1350 may include any amount and type of logic that enables processing unit 1330 to interface with devices (e.g., computer 1310) via USB connector 1340. [02671 Logic 615 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding logic 615 are provided herein in conjunction with FIGS. 6A and / or 6B. In at least one embodiment, logic 615 may be used in computer system 1300 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein. [02681 In at least one embodiment, an embodiment consistent with said figures includes one or more processors, circuitry, or systems to cause one or more pinned shared memory buffers to be allocated to one or more neural network accelerators, wherein the one or more pinned shared memory buffers are to store a plurality7 of neural network training checkpoints to be used by the one or more neural network accelerators to recover from one or more errors detected during training of one or more neural networks, such as described with respect to any of FIGS. 1-5B.

[0269] FIG. 14A illustrates an exemplary architecture in which a plurality of GPUs 1410(1)-1410(N) is communicatively coupled to a plurality of multi-core processors 1405(1 )-1405(M) over high-speed links 1440(1 )-1440(N) (e.g., buses, point-to-point interconnects, etc.). In at least one embodiment, high-speed links 1440(1 )-1440(N) support a communication throughput of 4 GB / s, 30 GB / s, 80 GB / s or higher. In at least one embodiment, various interconnect protocols may be used including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0. In various figures, “N” and “M” represent positive integers, values of which may be different from figure to figure. In at least one embodiment, one or more GPUs in a plurality of GPUs 1410(1 )-1410(N) includes one or more graphics cores (also referred to simply as “'cores”) 1700 as disclosed m Figures 17A and 17B. In at least one embodiment, one or more graphics cores 1700 may be referred to as streaming multiprocessors (“SMs”), stream processors (“SPs”), stream processing units (“SPUs”), compute units (“CUs”), execution units (“EUs”), and / or slices, where a slice in this context can refer to a portion of processing resources in a processing unit (e.g., 16 cores, a ray tracing unit, a thread director or scheduler).

[0270] In addition, and in at least one embodiment, two or more of GPUs 1410 are interconnected over high-speed links 1429(1)-1429(2), which may be implemented using similar’ or different protocols / links than those used for high-speed links 1440(1)-1440(N). Similarly, two or more of multi-core processors 1405 may be connected over a high-speed link 1428 which may be symmetric multi-processor (SMP) buses operating at 20 GB / s, 30 GB / s, 120 GB / s or higher. Alternatively, all communication between various system components shown in FIG. 14A may be accomplished using similar protocol s / lmks (e.g., over a common interconnection fabric).

[0271] In at least one embodiment, each multi-core processor 1405 is communicatively coupled to a processor memory’ 1401(l)-1401(M), via memory' interconnects 1426(1 )-1426(M), respectively, and each GPU 1410( 1 )-1410(N) is communicatively coupled to GPU memory' 1420(l)-1420(N) over GPU memory' interconnects 1450(l)-1450(N), respectively. In at least one embodiment, memory' interconnects 1426 and 1450 may utilize similar or different memory access technologies. By way of example, and not limitation, processor memories 1401(l)-1401(M) and GPU memories 1420 may be volatile memories such as dynamic random access memories (DRAMs) (including stacked DRAMs), Graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or High Bandwidth Memory' (HBM) and / or may be non-volatile memories such as 3D XPoint or Nano-Ram. In at least one embodiment, some portion of processor memories 1401 may' be volatile memory and another portion may be non-volatile memory (e.g., using a two-level memoty (2LM) hierarchy). [02721 As described herein, although various multi-core processors 1405 and GPUs 1410 may be physically coupled to a particular memory 1401, 1420, respectively, and / or a unified memory' architecture may be implemented in which a virtual system address space (also referred to as “effective address” space) is distributed among various physical memories. For example, processor memories 1401(l)-1401(M) may each comprise 64 GB of system memory' address space and GPU memories 1420(1)-1420(N) may each comprise 32 GB of system memory' address space resulting in a total of 256 GB addressable memory when M=2 and N=4. Other values for N and M are possible. [02731 FIG. 14B illustrates additional details for an interconnection between a multi-core processor 1407 and a graphics acceleration module 1446 in accordance with one exemplary embodiment. In at least one embodiment, graphics acceleration module 1446 may include one or more GPU chips integrated on a line card which is coupled to processor 1407 via high-speed link 1440 (e.g., a PCIe bus, NVLink, etc.). In at least one embodiment, graphics acceleration module 1446 may alternatively be integrated on a package or chip with processor 1407.

[0274] In at least one embodiment, processor 1407 includes a plurality of cores 1460A-1460D (which may' be referred to as “execution units”), each with a translation lookaside buffer (“TLB”) 1461A-1461D and one or more caches 1462A-1462D. In at least one embodiment, cores 1460A-1460D may' include various other components for executing instructions and processing data that are not illustrated. In at least one embodiment, caches 1462A-1462D may' comprise Level 1 (LI) and Level 2 (L2) caches. In addition, one or more shared caches 1456 may be included in caches 1462A-1462D and shared by sets of cores 1460A-1460D. For example, one embodiment of processor 1407 includes 24 cores, each with its own LI cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, one or more L2 and L3 caches are shared by two adjacent cores. In at least one embodiment, processor 1407 and graphics acceleration module 1446 connect with system memory 1414, which may include processor memories 1401(l)-1401(M) of FIG. 14A. [02751 In at least one embodiment, coherency is maintained for data and instructions stored in various caches 1462A-1462D, 1456 and system memory' 1414 via inter-core communication over a coherence bus 1464. In at least one embodiment, for example, each cache may have cache coherency logic / circuitry associated therewith to communicate to over coherence bus 1464 in response to detected reads or writes to particular cache lines. In at least one embodiment, a cache snooping protocol is implemented over coherence bus 1464 to snoop cache accesses.

[0276] In at least one embodiment, a proxy circuit 1425 communicatively couples graphics acceleration module 1446 to coherence bus 1464, allowing graphics acceleration module 1446 to participate in a cache coherence protocol as a peer of cores 1460A-1460D. In particular, in at least one embodiment, an interface 1435 provides connectivity to proxy circuit 1425 over high-speed link 1440 and an interface 1437 connects graphics acceleration module 1446 to high-speed link 1440.

[0277] In at least one embodiment, an accelerator integration circuit 1436 provides cache management, memory access, context management, and interrupt management services on behalf of a plurality of graphics processing engines 1431(1)-1431(N) of graphics acceleration module 1446. In at least one embodiment, graphics processing engines I431(I)-1431(N) may each comprise a separate graphics processing unit (GPU). In at least one embodiment, plurality of graphics processing engines 1431 (1)-1431 (N) of graphics acceleration module 1446 include one or more graphics cores 1700 as discussed in connection with Figures 17A and 17B. In at least one embodiment, graphics processing engines 1431(1)-1431(N) alternatively may comprise different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, graphics acceleration module 1446 may be a GPU with a plurality of graphics processing engines 1431 (1)-1431 (N) or graphics processing engines 1431 (1 )-1431 (N) may be individual GPUs integrated on a common package, line card, or chip.

[0278] In at least one embodiment, accelerator integration circuit 1436 includes a memory management unit (MMU) 1439 for performing various memory management functions such as virtual-to-physical memory translations (also referred to as effective-to-real memory’ translations) and memory’ access protocols for accessing system memory 1414. In at least one embodiment, MMU 1439 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective to physical / real address translations. In at least one embodiment, a cache 1438 can store commands and data for efficient access by' graphics processing engines 1431(1)-1431(N). In at least one embodiment, data stored in cache 1438 and graphics memories 1433(1)- 1433(M) is kept coherent with core caches 1462A-1462D, 1456 and system memory 1414, possibly using a fetch unit 1444. As mentioned, this may be accomplished via proxy circuit 1425 on behalf of cache 1438 and memories 1433(1 )-1433(M) (e.g., sending updates to cache 1438 related to modifications / accesses of cache lines on processor caches 1462A-1462D, 1456 and receiving updates from cache 1438). [02791 In at least one embodiment, a set of registers 1445 store context data for threads executed by graphics processing engines 1431(1)-1431(N) and a context management circuit 1448 manages thread contexts. For example, context management circuit 1448 may perform save and restore operations to save and restore contexts of various threads during contexts switches (e.g., where a first thread is saved and a second thread is stored so that a second thread can be execute by a graphics processing engine). For example, on a context switch, context management circuit 1448 may store current register values to a designated region in memory (e.g., identified by a context pointer). It may then restore register values when returning to a context. In at least one embodiment, an interrupt management circuit 1447 receives and processes interrupts received from system devices. [02801 In at least one embodiment, virtual / effective addresses from a graphics processing engine 1431 are translated to real / physical addresses in system memory 1414 by MMU 1439. In at least one embodiment, accelerator integration circuit 1436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1446 and / or other accelerator devices. In at least one embodiment, graphics accelerator module 1446 may be dedicated to a single application executed on processor 1407 or may be shared between multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented in which resources of graphics processing engines 1431(1 )-1431(N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources may be subdivided into “slices” which are allocated to different VMs and / or applications based on processing requirements and priorities associated with VMs and / or applications. [02811 In at least one embodiment, accelerator integration circuit 1436 performs as a bridge to a system for graphics acceleration module 1446 and provides address translation and system memory cache sendees. In addition, in at least one embodiment, accelerator integration circuit 1436 may provide virtualization facilities for a host processor to manage virtualization of graphics processing engines 1431(1)-1431(N), interrupts, and memory management. [02821 In at least one embodiment, because hardware resources of graphics processing engines 1431 (1)-1431 (N) are mapped explicitly to a real address space seen by host processor 1407, any host processor can address these resources directly using an effective address value. In at least one embodiment, one function of accelerator integration circuit 1436 is physical separation of graphics processing engines 1431(1)-1431(N) so that they appear to a system as independent units. [02831 In at least one embodiment, one or more graphics memories 1433(1 )-1433(M) are coupled to each of graphics processing engines 1431(1)-1431(N), respectively and N=M. In at least one embodiment, graphics memories 1433(1)-1433(M) store instructions and data being processed by each of graphics processing engines 1431 (1)-1431 (N). In at least one embodiment, graphics memories 1433(1)-1433(M) may be volatile memories such as DRAMs (including stacked DRAMs), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memories such as 3D XPoint or Nano-Ram. [0284) In at least one embodiment, to reduce data traffic over high-speed link 1440, biasing techniques can be used to ensure that data stored in graphics memories 1433(1)-1433(M) is data that will be used most frequently by graphics processing engines 1431 (1)-1431 (N) and preferably not used by cores 1460A-1460D (at least not frequently). Similarly, in at least one embodiment, a biasing mechanism attempts to keep data needed by cores (and preferably not graphics processing engines 1431(1 )-1431(N)) within caches 1462A-1462D, 1456 and system memory 1414,

[0285] FIG. 14C illustrates another exemplary embodiment in which accelerator integration circuit 1436 is integrated within processor 1407. In this embodiment, graphics processing engines 1431(1)-1431(N) communicate directly over high-speed link 1440 to accelerator integration circuit 1436 via interface 1437 and interface 1435 (which, again, may be any form of bus or interface protocol). In at least one embodiment, accelerator integration circuit 1436 may perform similar' operations as those described with respect to FIG. 14B, but potentially at a higher throughput given its close proximity to coherence bus 1464 and caches 1462A-1462D, 1456. In at least one embodiment, an accelerator integration circuit supports different programming models including a dedicated-process programming model (no graphics acceleration module virtualization) and shared programming models (with virtualization), which may include programming models which are controlled by accelerator integration circuit 1436 and programming models which are controlled by graphics acceleration module 1446. [02861 In at least one embodiment, graphics processing engines 1431(1)-1431(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to graphics processing engines 1431(1)-1431 (N), providing virtualization within a VM / partition.

[0287] In at least one embodiment, graphics processing engines 1431(1 )-1431(N), may be shared by multiple VM / appIication partitions. In at least one embodiment, shared models may use a system hypervisor to virtualize graphics processing engines 1431(1)-1431 (N) to allow access by each operating system. In at least one embodiment, for single-partition systems without a hypervisor, graphics processing engines 1431(1 )-1431(N) are owned by an operating system. In at least one embodiment, an operating system can virtualize graphics processing engines 1431(1)-1431(N) to provide access to each process or application. [02881 In at least one embodiment, graphics acceleration module 1446 or an individual graphics processing engine 1431 (1)-1431(N) selects a process element using a process handle. In at least one embodiment, process elements are stored in system memory 1414 and are addressable using an effective address to real address translation technique described herein. In at least one embodiment, a process handle may be an implementation-specific value provided to a host process when registering its context with graphics processing engine 1431 (1)-1431 (N) (that is, calling system software to add a process element to a process element linked list). In at least one embodiment, a lower 16-bits of a process handle may be an offset of a process element within a process element linked list. [02891 FIG. 14D illustrates an exemplary accelerator integration slice 1490. In at least one embodiment, a “slice” comprises a specified portion of processing resources of accelerator integration circuit 1436. In at least one embodiment, an application is effective address space 1482 within system memory 1414 stores process elements 1483. In at least one embodiment, process elements 1483 are stored in response to GPU invocations 1481 from applications 1480 executed on processor 1407. In at least one embodiment, a process element 1483 contains process state for corresponding application 1480. In at least one embodiment, a work descriptor (WD) 1484 contained in process element 1483 can be a single job requested by an application or may contain a pointer to a queue of jobs. In at least one embodiment, WD 1484 is a pointer to a job request queue in an application’s effective address space 1482.

[0290] In at least one embodiment, graphics acceleration module 1446 and / or individual graphics processing engines 1431(1 )-1431(N) can be shared by all or a subset of processes in a system. In at least one embodiment, an infrastructure for setting up process states and sending a WD 1484 to a graphics acceleration module 1446 to start a job in a virtualized environment may be included. [02911 In at least one embodiment, a dedicated-process programming model is implementation-specific. In at least one embodiment, in this model, a single process owns graphics acceleration module 1446 or an individual graphics processing engine 1431. In at least one embodiment, when graphics acceleration module 1446 is owned by a single process, a hypervisor initializes accelerator integration circuit 1436 for an owning partition and an operating system initializes accelerator integration circuit 1436 for an owning process when graphics acceleration module 1446 is assigned.

[0292] In at least one embodiment, in operation, a WD fetch unit 1491 in accelerator integration slice 1490 fetches next WD 1484, which includes an indication of work to be done by one or more graphics processing engines of graphics acceleration module 1446. In at least one embodiment, data from WD 1484 may be stored in registers 1445 and used by MMU 1439, interrupt management circuit 1447 and / or context management circuit 1448 as illustrated. For example, one embodiment of MMU 1439 includes segment / page walk circuitry for accessing segment / page tables 1486 within an OS virtual address space 1485. In at least one embodiment, interrupt management circuit 1447 may process interrupt events 1492 received from graphics acceleration module 1446. In at least one embodiment, when performing graphics operations, an effective address 1493 generated by a graphics processing engine 1431(1 )-1431(N) is translated to a real address by MMU 1439. [02931 In at least one embodiment, registers 1445 are duplicated for each graphics processing engine 1431 (1)-1431(N) and / or graphics acceleration module 1446 and may be initialized by a hypervisor or an operating system. In at least one embodiment, each of these duplicated registers may be included m an accelerator integration slice 1490. Exemplary registers that may be initialized by a hypervisor are shown in Table 1. Table 1 - Hypervisor Initialized Registers Register # Description 1 Slice Control Register 2 Real Address (RA) Scheduled Processes Area Pointer 3 Authority Mask Override Register 4 Interrupt Vector Table Entry Offset 5 Interrupt Vector Table Entry’ Limit 6 State Register 7 Logical Partition ID 8 Real address (RA) Hypervisor Accelerator Utilization Record Pointer 9 Storage Description Register 92941 Exemplary registers that may be initialized by an operating system are shown in Table 2. Table 2 -- Operating System Initialized Registers Register # Description 1 2 Process and Thread Identification Effective Address (EA) Context Save / Restore Pointer 3 Virtual Address (VA) Accelerator Utilization Record Pointer 4 Virtual Address (VA) Storage Segment Table Pointer 5 6 Authority Mask Work descriptor [02951 In at least one embodiment, each WD 1484 is specific to a particular graphics acceleration module 1446 and / or graphics processing engines 1431(1)-1431(N). In at least one embodiment, it contains all information required by a graphics processing engine 1431 (1 )-1431(N) to do work, or it can be apointer to a memory location where an application has set up a command queue of work to be completed. [02961 FIG. 14E illustrates additional details for one exemplary embodiment of a shared model. This embodiment includes a hypervisor real address space 1498 in which a process element list 1499 is stored. In at least one embodiment, hypervisor real address space 1498 is accessible via a hypervisor 1496 which virtualizes graphics acceleration module engines for operating system 1495. [02971 In at least one embodiment, shared programming models allow for all or a subset of processes from all or a subset of partitions in a system to use a graphics acceleration module 1446. In at least one embodiment, there are two programming models where graphics acceleration module 1446 is shared by multiple processes and partitions, namely time-sliced shared and graphics directed shared. [02981 In at least one embodiment, in this model, system hypervisor 1496 owns graphics acceleration module 1446 and makes its function available to all operating systems 1495. In at least one embodiment, for a graphics acceleration module 1446 to support virtualization by system hypervisor 1496, graphics acceleration module 1446 may adhere to certain requirements, such as (1) an application’s job request must be autonomous (that is, state does not need to be maintained between jobs), or graphics acceleration module 1446 must provide a context save and restore mechanism, (2) an application’s job request is guaranteed by graphics acceleration module 1446 to complete in a specified amount of time, including any translation faults, or graphics acceleration module 1446 provides an ability to preempt processing of a job, and (3) graphics acceleration module 1446 must be guaranteed fairness between processes when operating in a directed shared programming model. [02991 In at least one embodiment, application 1480 is required to make an operating system 1495 system call with a graphics acceleration module type, a work descriptor (WD), an authority’ mask register (AMR) value, and a context save / restore area pointer (CSRP). In at least one embodiment, graphics acceleration module type describes a targeted acceleration function for a system call. In at least one embodiment, graphics acceleration module type may be a system-specific value. In at least one embodiment, WD is formatted specifically’ for graphics acceleration module 1446 and can be in a form of a graphics acceleration module 1446 command, an effective address pointer to a user-defined structure, an effective address pointer to a queue of commands, or any other data structure to describe work to be done by graphics acceleration module 1446.

[0300] In at least one embodiment, an AMR value is an AMR state to use for a current process. In at least one embodiment, a value passed to an operating system is similar to an application setting an AMR. In at least one embodiment, if accelerator integration circuit 1436 (not shown) and graphics acceleration module 1446 implementations do not support a User Authority Mask Override Register (UAMOR), an operating system may apply a current UAMOR value to an AMR value before passing an AMR in a hypervisor call. In at least one embodiment, hypervisor 1496 may optionally apply a current Authority Mask Override Register (AMOR) value before placing an AMR into process element 1483. In at least one embodiment, CSRP is one of registers 1445 containing an effective address of an area in an application’s effective address space 1482 for graphics acceleration module 1446 to save and restore context state. In at least one embodiment, this pointer is optional if no state is required to be saved between jobs or when a job is preempted. In at least one embodiment, context save / restore area may be pinned system memoiy. [03011 Upon receiving a system call, operating system 1495 may verify that application 1480 has registered and been given authority7 to use graphics acceleration module 1446. In at least one embodiment, operating system 1495 then calls hypervisor 1496 with information shown in Table 3. Table 3 - OS to Hypervisor Cali Parameters Parameter # Description 1 A work descriptor (WD) 2 An Authority7 Mask Register (AMR) value (potentially masked) An effective address (EA) Context Save / Restore Area Pointer (CSRP) 4 5 A process ID (PID) and optional thread ID (TID) A virtual address (VA) accelerator utilization record pointer (AURP) 6 Virtual address of storage segment table pointer (SSTP) 7 A logical interrupt service number (LISN) [03021 In at least one embodiment, upon receiving a hypervisor call, hypervisor 1496 verifies that operating system 1495 has registered and been given authority to use graphics acceleration module 1446. In at least one embodiment, hypervisor 1496 then puts process element 1483 into a process element linked list for a corresponding graphics acceleration module 1446 type. In at least one embodiment, a process element may include information shown in Table 4. Table 4 -Process Element Information Element # Description 1 A work descriptor (WD) 2 An Authority Mask Register (AMR.) value (potentially masked). S An effective address (EA) Context Save / Restore Area Pointer (CSRP) 4 A process ID (PID) and optional thread ID (TID) 5 A virtual address (VA) accelerator utilization record pointer (AURP) 6 Virtual address of storage segment table pointer (SSTP) 7 A logical interrupt service number (LISN) 8 Interrupt vector table, derived from hypervisor call parameters 9 A state register (SR) value 10 A logical partition ID (LPID) 11 A real address (RA) hypervisor accelerator utilization record pointer 12 Storage Descriptor Register (SDR)

[0303] In at least one embodiment, hypervisor initializes a plurality of accelerator integration slice 1490 registers 1445. [03041 As illustrated in FIG. 14F, in at least one embodiment, a unified memory is used, addressable via a common virtual memory address space used to access physical processor memories 1401 (I)-1401 (N) and GPU memories 1420(l)-1420(N). In this implementation, operations executed on GPUs 1410(1)-1410(N) utilize a same virtual / effective memory address space to access processor memories 1401(l)-1401(M) and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of a virtual / effective address space is allocated to processor memory 1401(1), a second portion to second processor memory 1401(N), a third portion to GPU memory 1420(1), and so on. In at least one embodiment, an entire virtual / effective memory space (sometimes referred to as an effective address space) is thereby distributed across each of processor memories 1401 and GPU memories 1420, allowing any' processor or GPU to access any physical memory with a virtual address mapped to that memory'.

[0305] In at least one embodiment, bias / coherence management circuitry 1494A-1494E within one or more of MMUs 1439A-1439E ensures cache coherence between caches of one or more host processors (e.g., 1405) and GPUs 1410 and implements biasing techniques indicating physical memories in which certain types of data should be stored. In at least one embodiment, while multiple instances of bias / coherence management circuitry 1494A-1494E are illustrated in FIG. I4F, bias / coherence circuitry may be implemented within an MMU of one or more host processors 1405 and / or within accelerator integration circuit 1436.

[0306] One embodiment allows GPU memories 1420 to be mapped as part of system memory', and accessed using shared virtual memory (SVM) technology, but without suffering performance drawbacks associated with full system cache coherence. In at least one embodiment, an ability for GPU memories 1420 to be accessed as system memory without onerous cache coherence overhead provides a beneficial operating environment for GPU offload. In at least one embodiment, this arrangement allow's software of host processor 1405 to setup operands and access computation results, without overhead of tradition I / O DMA data copies. In at least one embodiment, such traditional copies involve driver calls, interrupts and memory mapped I / O (MM10) accesses that are all inefficient relative to simple memory accesses. In at least one embodiment, an ability to access GPU memories 1420 without cache coherence overheads can be critical to execution time of an offloaded computation. In at least one embodiment, in cases with substantial streaming write memory' traffic, for example, cache coherence overhead can significantly' reduce an effective write bandwidth seen by a GPU 1410. In at least one embodiment, efficiency' of operand setup, efficiency of results access, and efficiency of GPU computation may play a role in determining effectiveness of a GPU offload,

[0307] In at least one embodiment, selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, a bias table may be used, for example, which may be a page-granular structure (e.g., controlled at a granularity of a memory page) that includes 1 or 2 bits per GPU-attached memory page. In at least one embodiment, a bias table may be implemented in a stolen memory range of one or more GPU memories 1420, with or without a bias cache in a GPU 1410 (e.g., to cache frequently / recently used entries of a bias table). Alternatively, in at least one embodiment, an entire bias table may be maintained within a GPU.

[0308] In at least one embodiment, a bias table entry associated with each access to a GPU attached memory 1420 is accessed prior to actual access to a GPU memory, causing following operations. In at least one embodiment, local requests from a GPU 1410 that find their page in GPU bias are forwarded directly to a corresponding GPU memory 1420. In at least one embodiment, local requests from a GPU that find their page in host bias are forwarded to processor 1405 (e.g., over a high-speed link as described herein). In at least one embodiment, requests from processor 1405 that find a requested page in host processor bias complete a request like a normal memory read. Alternatively, requests directed to a GPU-biased page may be forwarded to a GPU 1410. In at least one embodiment, a GPU may then transition a page to a host processor bias if it is not currently using a page. In at least one embodiment, a bias state of a page can be changed either by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of cases, a purely hardware-based mechanism.

[0309] In at least one embodiment, one mechanism for changing bias state employs an API call (e.g., OpenCL), which, in turn, calls a GPU’s device driver which, in turn, sends a message (or enqueues a command descriptor) to a GPU directing it to change a bias state and, for some transitions, perform a cache flushing operation in a host. In at least one embodiment, a cache flushing operation is used for a transition from host processor 1405 bias to GPU bias, but is not for an opposite transition. [03101 In at least one embodiment, cache coherency is maintained by temporarily rendering GPU-biased pages uncacheable by host processor 1405. In at least one embodiment, to access these pages, processor 1405 may request access from GPU 1410, which may or may not grant access right away. In at least one embodiment, thus, to reduce communication between processor 1405 and GPU 1410 it is beneficial to ensure that GPU-biased pages are those which are required by a GPU but not host processor 1405 and vice versa. [03111 Hardware structure(s) 615 are used to perform one or more embodiments. Details regarding a hardware structure(s) 615 may be provided herein in conjunction with FIGS. 6A and / or 6B. [03121 FIG. 15 illustrates exemplaiy integrated circuits and associated graphics processors that may be fabricated using one or more IP cores, according to various embodiments described herein. In addition to what is illustrated, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores. [0313j FIG. 15 is a block diagram illustrating an exemplary system on a chip integrated circuit 1500 that may be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, integrated circuit 1500 includes one or more application processor(s) 1505 (e.g., CPUs), at least one graphics processor 1510, mid may additionally include an image processor 1515 and / or a video processor 1520, any of which may be a modular IP core. In at least one embodiment, integrated circuit 1500 includes peripheral or bus logic including a USB controller 1525, a UART controller 1530, an SPI / SDIO controller 1535, and an I22S / I22C controller 1540. In at least one embodiment, integrated circuit 1500 can include a display device 1545 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1550 and a mobile industry processor interface (MIPI) display interface 1555. In at least one embodiment, storage may be provided by a flash memory subsystem 1560 including flash memoiy and a flash memory’ controller. In at least one embodiment, a memory’ interface may be provided via a memory controller 1565 for access to SDRAM or SRAM memory’ devices. In at least one embodiment, some integrated circuits additionally include an embedded security' engine 1570. [03141 Logic 615 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding logic 615 are provided herein in conjunction with FIGS. 6A and / or 6B. In at least one embodiment, logic 615 may be used in integrated circuit 1500 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein. [0315j In at least one embodiment, an embodiment consistent with said figures includes one or more processors, circuitry’, or systems to cause one or more pinned shared memory’ buffers to be allocated to one or more neural network accelerators, wherein the one or more pinned shared memory’ buffers are to store a plurality of neural network training checkpoints to be used by the one or more neural network accelerators to recover from one or more errors detected during training of one or more neural networks, such as described with respect to any of FIGS. 1-5B. [03161 FIGS. 16A-16B illustrate exemplary’ integrated circuits and associated graphics processors that may be fabricated using one or more IP cores, according to various embodiments described herein. In addition to what is illustrated, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores. [03171 FIGS. 16A-16B are block diagrams illustrating exemplary' graphics processors for use within an SoC, according to embodiments described herein. FIG. 16A illustrates an exemplary’ graphics processor 1610 of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to at least one embodiment. FIG. 16B illustrates an additional exemplary graphics processor 1640 of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, graphics processor 1610 of FIG. 16A is a low power graphics processor core. In at least one embodiment, graphics processor 1640 of FIG. 16B is a higher performance graphics processor core. In at least one embodiment, each of graphics processors 1610,1640 can be variants of graphics processor 1510 of FIG. 15,

[0318] In at least one embodiment, graphics processor 1610 includes a vertex processor 1605 and one or more fragment processor(s) I615A-I615N (e.g., 16I5A, I615B, 1615C, 1615D, through 1615N-1, and 1615N). In at least one embodiment, graphics processor 1610 can execute different shader programs via separate logic, such that vertex processor 1605 is optimized to execute operations for vertex shader programs, while one or more fragment processors) I615A-1615N execute fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, vertex processor 1605 performs a vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, fragment processor(s) 1615A-1615N use primitive and vertex data generated by vertex processor 1605 to produce a framebuffer that is displayed on a display device. In at least one embodiment, fragment processors) 1615A-1615N are optimized to execute fragment shader programs as provided for in an OpenGL API, which may be used to perform similar operations as a pixel shader program as provided for in a Direct 3D API.

[0319] In at least one embodiment, graphics processor 1610 additionally includes one or more memory management units (MMUs) 1620A-1620B, cache(s) 1625A-1625B, and circuit mterconnect(s) 1630A-1630B. In at least one embodiment, one or more MMU(s) 1620A-1620B provide for virtual to physical address mapping for graphics processor 1610, including for vertex processor 1605 and / or fragment processor(s) 1615A-1615N, which may reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more cache(s) 1625A-1625B. In at least one embodiment, one or more MMU(s) 1620A-1620B may be synchronized with other MMUs within a system , including one or more MMUs associated with one or more application processors) 1505, image processors 1515, and / or video processors 1520 of FIG. 15, such that each processor 1505-1520 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnect(s) 1630A-1630B enable graphics processor 1610 to interface with other IP cores within SoC, either via an internal bus of SoC or via a direct connection. [03201 In at least one embodiment, graphics processor 1640 includes one or more shader core(s) 1655A-1655N (e.g., 1655A, 1655B, 1655C, 1655D, 1655E, 1655F, through 1655N-1, and 1655N) as shown in FIG. 1613, which provides for a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, inchiding shader program code to implement vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, a number of shader cores can vary. In at least one embodiment, graphics processor 1640 includes an inter-core task manager 1645, which acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1655A-1655N and a tiling unit 1658 to accelerate tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in image space, for example to exploit local spatial coherence within a scene or to optimize use of internal caches. [0321 j Logic 615 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding logic 615 are provided herein in conjunction with FIGS. 6A and / or 6B. In at least one embodiment, logic 615 may be used in graphics processor 1610 and / or 1640 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein. [03221 In at least one embodiment, an embodiment consistent with said figures includes one or more processors, circuitry, or systems to cause one or more pinned shared memory buffers to be allocated to one or more neural network accelerators, wherein the one or more pinned shared memory buffers are to store a plurality of neural network training checkpoints to be used by the one or more neural network accelerators to recover from one or more errors detected during training of one or more neural networks, such as described with respect to any of FIGS. 1-5B. [O323j FIGS. 17A-17B illustrate additional exemplary graphics processor logic according to embodiments described herein. In at least one embodiment, components illustrated in and described in connection with FIGS. 17A-17B are integrated into a single system, such as a graphics processing unit (GPU), SoC, or another type of processor. FIG. 17A illustrates a graphics core 1700 that may be included w’ithin graphics processor 1510 of FIG. 15, in at least one embodiment, and may be a unified shader core 1655A-1655N as in FIG. 16B in at least one embodiment. FIG. 17B illustrates a highly-parallel general-purpose graphics processing unit (“GPGPU’', which can also be referred to as a “graphics processing unit”) 1730 suitable for deployment on a multi-chip module in at least one embodiment. In at least one embodiment, graphics processing unit 1730 is a GPGPU that comprises a graphics processor. In at least one embodiment, integrated circuit 1500 comprises graphics core 1700, e.g., to form an integrated circuit and / or to form an SoC, where such an integrated circuit and / or such an SoC perform operations described herein. [03241 In at least one embodiment, graphics core 1700 includes a shared instruction cache 1702, a texture unit 1718, and a cache / shared memory' 1720 (e.g., including LI, L2, L3, last level cache, or other caches) that are common to execution resources within graphics core 1700. In at least one embodiment, graphics core 1700 can include multiple slices 1701A-1701N or a partition for each core, and a graphics processor can include multiple instances of graphics core 1700, In at least one embodiment, each slice 1701A-1701N refers to graphics core 1700. In at least one embodiment, slices 1701A-1701N have sub-slices, which are part of a slice 1701A-1701N. In at least one embodiment, slices I70IA-170IN are independent of other slices or dependent on other slices. In at least one embodiment, slices 1701A-1701N can include support logic including a local instruction cache I704A-I704N, a thread scheduler (sequencer) 1706A-1706N, a thread dispatcher 1708A-1708N, and a set of registers 1710A-1710N. In at least one embodiment, slices 1701A-1701N can include a set of additional function units (AFUs 1712A-1712N), floating-point units (FPUs 17I4A-17I4N), integer arithmetic logic units (ALUs 1716A-1716N), address computational units (ACUs 1713A-1713N), double-precision floating-point units (DPFPUs 1715A-1715N), and matrix processing units (MPUs 1717A-1717N). In at least one embodiment, MPUs 1717A-1717N are referred to as matrix engines,

[0325] In at least one embodiment, each slice 1701A-1701N includes one or more engines for floating point and integer vector operations and one or more engines to accelerate convolution and matrix operations in AI, machine learning, or large dataset workloads. In at least one embodiment, one or more slices 1701A-1701N include one or more vector engines to compute a vector (e.g., compute mathematical operations for vectors). In at least one embodiment, a vector engine can compute a vector operation in 16-bit floating point (also referred to as 'TP16U, 32-bit floating point (also referred to as “FP32”), or 64-bit floating point (also referred to as “FP64”). In at least one embodiment, one or more slices 1701A-1701N includes 16 vector engines that are paired with 16 matrix math units to compute matriUtensor operations, where vector engines and math units are exposed via matrix extensions. In at least one embodiment, a slice a specified portion of processing resources of a processing unit, e.g., 16 cores and a ray tracing unit or 8 cores, a thread scheduler, a thread dispatcher, and additional functional units for a processor. In at least one embodiment, graphics core 1700 includes one or more matrix engines to compute matrix operations, e.g., when computing tensor operations. [03261 In at least one embodiment, one or more slices 1701A-170IN includes one or more ray tracing units to compute ray tracing operations (e.g., 16 ray tracing units per slice slices 1701A-1701N). In at least one embodiment, a ray tracing unit computes ray traversal, triangle intersection, bounding box intersect, or other ray fracing operations. [0327 j In at least one embodiment, one or more slices 1701 A-170IN includes a media slice that encodes, decodes, and / or transcodes data; scales and / or format converts data; and / or performs video quality operations on video data. [03281 In at least one embodiment, one or more slices 1701A-1701N are linked to L2 cache and memory fabric, link connectors, high-bandwidth memory' (HBM) (e.g., HBM2e, HDM3) stacks, and amedia engine. In at least one embodiment, one or more slices 1701 A-l 701N include multiple cores (e.g., 16 cores) and multiple ray tracing units (e.g., 16) paired to each core. In at least one embodiment, one or more slices 1701A-170IN has one or more LI caches. In at least one embodiment, one or more slices 1701A-1701N include one or more vector engines; one or more instruction caches to store instructions; one or more LI caches to cache data; one or more shared local memories (SLMs) to store data, e.g., corresponding to instructions; one or more samplers to sample data; one or more raj- fracing units to perform ray fracing operations; one or more geometries to perform operations in geometry pipelines and / or apply geometric transformations to vertices or polygons; one or more rasterizers to describe an image in vector graphics format (e.g., shape) and convert it into a raster image (e.g., a series of pixels, dots, or lines, which when displayed together, create an image that is represented by shapes); one or more a Hierarchical Depth Buffer (Hiz) to buffer data; and / or one or more pixel backends. In at least one embodiment, a slice 1701 A-l 701N includes a memoiy fabric, e.g., an L2 cache.

[0329] In at least one embodiment, FPUs 1714A-1714N can perform single-precision (32-bit) and halfprecision (16-bit) floating point operations, while DPFPUs 17I5A-17I5N perform double precision (64-bit) floating point operations. In at least one embodiment, ALUs 1716A-1716N can perform variable precision integer operations at 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed precision operations. In at least one embodiment, MPUs 1717A-1717N can also be configured for mixed precision matrix operations, including half-precision floating point and 8-bit integer operations. In at least one embodiment, MPUs 1717-1717N can perform a variety of matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix to matrix multiplication (GEMM). In at least one embodiment, AFIJs 17I2A-17I2N can perform additional logic operations not supported by floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0330] Logic 615 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding logic 615 are provided herein in conjunction with FIGS. 6A and / or 6B. In at least one embodiment, logic 615 may be used in graphics core 1700 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein. [0331 j In at least one embodiment, graphics core 1700 includes an interconnect and a link fabric sublayer that is attached to a switch and a GPU-GPU bridge that enables multiple graphics processors 1700 (e.g., 8) to be interlinked without glue to each other with load / store units (LSUs), data transfer units, and sync semantics across multiple graphics processors 1700. In at least one embodiment, interconnects include standardized interconnects (e.g., PCIe) or some combination thereof.

[0332] In at least one embodiment, graphics core 1700 includes multiple tiles. In at least one embodiment, a tile is an individual die or one or more dies, where individual dies can be connected with an interconnect (e.g., embedded multi-die interconnect bridge (EMIB)). In at least one embodiment, graphics core 1700 includes a compute tile, a memory' tile (e.g., where a memoty tile can be exclusively accessed by different tiles or different chipsets such as a Rambo tile), substrate tile, a base tile, a HMB tile, a link tile, and EMIB tile, where all tiles are packaged together in graphics core 1700 as part of a GPU. In at least one embodiment, graphics core 1700 can include multiple tiles in a single package (also referred to as a “multi tile package”). In at least one embodiment, a compute tile can have 8 graphics cores 1700, an L I cache; and a base tile can have a host interface with PCIe 5.0, HBM2e, MDFI, and EMIB, a link tile with 8 links, 8 ports with an embedded switch. In at least one embodiment, tiles are connected with face-to-face (F2F) chip-on-chip bonding through fine-pitched, 36-micron, microbumps (e.g., copper pillars). In at least one embodiment, graphics core 1700 includes memory fabric, which includes memory, and is tile that is accessible by multiple tiles. In at least one embodiment, graphics core 1700 stores, accesses, or loads its own hardware contexts in memoty, where a hardware context is a set of data loaded from registers before a process resumes, and where a hardware context can indicate a state of hardware (e.g., state of a GPU). [03331 In at least one embodiment, graphics core 1700 includes serializer / deserializer (SERDES) circuitry that converts a serial data stream to a parallel data stream, or converts a parallel data stream to a serial data stream.

[0334] In at least one embodiment, graphics core 1700 includes a high speed coherent unified fabric (GPU to GPU), load / store units, bulk data transfer and sync semantics, and connected GPUs through an embedded switch, where a GPU-GPU bridge is controlled by a controller.

[0335] In at least one embodiment, graphics core 1700 performs an API, where said API abstracts hardware of graphics core 1700 and access libraries with instructions to perform math operations (e.g., math kernel library), deep neural network operations (e.g., deep neural network library), vector operations, collective communications, thread building blocks, video processing, data analytics library', and / or ray tracing operations.

[0336] In at least one embodiment, an embodiment consistent with said figures includes one or more processors, circuitry, or systems to cause one or more pinned shared memory buffers to be allocated to one or more neural network accelerators, wherein the one or more pinned shared memory buffers are to store a plurality of neural network training checkpoints to be used by the one or more neural network accelerators to recover from one or more errors detected during Raining of one or more neural networks, such as described with respect to any of FIGS. 1-5B. [03371 FIG. 17B illustrates GPGPU 1730 that can be configured to enable highly-parallel compute operations to be performed by an array of graphics processing units, in at least one embodiment. In at least one embodiment, GPGPU 1730 can be linked directly to other instances of GPGPU 1730 to create a multiGPU cluster to improve training speed for deep neural networks. In at least one embodiment, GPGPU 1730 includes a host interface 1732 to enable a connection with a host processor. In at least one embodiment, host interface 1732 is a PCI Express interface. In at least one embodiment, host interface 1732 can be a vendor-specific communications interface or communications fabric. In at least one embodiment, GPGPU 1730 receives commands from a host processor and uses a global scheduler 1734 (which may be referred to as a thread sequencer and / or asynchronous compute engine) to distribute execution threads associated with those commands to a set of compute clusters 1736A-1736H. In at least one embodiment, compute clusters 1736A-1736H share a cache memory 1738. In at least one embodiment, cache memory 1738 can serve as a higher-level cache for cache memories within compute clusters 1736A-1736H. In at least one embodiment, compute clusters 1736A-1736H comprise a slice or are referred to as “slices.” In at least one embodiment, GPGPU 1730 is part of an SoC such as part of integrated circuit 1500 (FIG. 15). [03381 In at least one embodiment, GPGPU 1730 includes memory 1744A-1744B coupled with compute clusters 1736A-1736H via a set of memory controllers 1742A-1742B (e.g., one or more controllers for HBM2e). In at least one embodiment, memory 1744A-1744B can include various types of memory devices including dynamic random access memory' (DRAM) or graphics random access memory, such as synchronous graphics random access memory' (SGRAM), including graphics double data rate (GDDR) memory.

[0339] In at least one embodiment, compute clusters 1736A-1736H each include a set of graphics cores, such as graphics core 1700 of FIG. 17A, which can include multiple types of integer and floating point logic units that can perform computational operations at a range of precisions including suited for machine learning computations. For example, in at least one embodiment, at least a subset of floating point units in each of compute clusters 1736A-1736H can be configured to perform 16-bit or 32.-bit floating point operations, while a different subset of floating point units can be configured to perform 64-bit floating point operations. [03401 In at least one embodiment, multiple instances of GPGPU 1730 can be configured to operate as a compute cluster. In at least one embodiment, communication used by compute clusters 1736A-1736H for synchronization and data exchange varies across embodiments. In at least one embodiment, multiple instances of GPGPU 1730 communicate over host interface 1732. In at least one embodiment, GPGPU 1730 includes an I / O hub 1739 that couples GPGPU 1730 with a GPU link 1740 that enables a direct connection to other instances of GPGPU 1730. In at least one embodiment, GPU link 1740 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1730. In at least one embodiment, GPU link 1740 couples with a high-speed interconnect to transmit and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1730 are located in separate data processing systems and communicate via a network device that is accessible via host interface 1732. In at least one embodiment GPU link 1740 can be configured to enable a connection to a host processor in addition to or as an alternative to host interface 1732.

[0341] In at least one embodiment, GPGPU 1730 can be configured to train neural networks. In at least one embodiment, GPGPU 1730 can be used within an inferencing platform. In at least one embodiment, in which GPGPU 1730 is used for inferencing, GPGPU 1730 may include fewer compute clusters 1736A-1736H relative to when GPGPU 1730 is used for training a neural network. In at least one embodiment, memory technology associated with memory 1744A-1744B may differ between inferencing and training configurations, with higher bandwidth memory technologies devoted to training configurations. In at least one embodiment, an inferencing configuration of GPGPU 1730 can support inferencing specific instructions. For example, in at least one embodiment, an inferencing configuration can provide support for one or more 8-bit integer dot product instructions, which may be used during inferencing operations for deployed neural networks.

[0342] Logic 615 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding logic 615 are provided herein in conjunction with FIGS. 6A and / or 6B. In at least one embodiment, logic 615 may be used in GPGPU 1730 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0343] In at least one embodiment, an embodiment consistent with said figures includes one or more processors, circuitry, or systems to cause one or more pinned shared memory' buffers to be allocated to one or more neural network accelerators, wherein the one or more pinned shared memory' buffers are to store a plurality of neural network train ing checkpoints to be used by the one or more neural network accelerators to recover from one or more errors detected during training of one or more neural networks, such as described with respect to any of FIGS. 1-5B. [03441 FIG. 18 is a block diagram illustrating a computing system 1800 according to at least one embodiment. In at least one embodiment, computing system 1800 includes a processing subsystem 1801 having one or more processor(s) 1802 and a system memory 1804 communicating via an interconnection path that may include a memory hub 1805. In at least one embodiment, memory hub 1805 may be a separate component within a chipset component or may be integrated within one or more processor(s) 1802. In at least one embodiment, memory’ hub 1805 couples with an I / O subsystem 1811 via a communication link 1806. In at least one embodiment, I / O subsystem 1811 includes an I / O hub 1807 that can enable computing system 1800 to receive input from one or more input device(s) 1808. In at least one embodiment, I / O hub 1807 can enable a display controller, which may be included in one or more processor(s) 1802, to provide outputs to one or more display device(s) 1810A. In at least one embodiment, one or more display device(s) 1810A coupled with I / O hub 1807 can include a local, internal, or embedded display device. [03451 In at least one embodiment, processing subsystem 1801 includes one or more parallel processor(s) 1812 coupled to memory hub 1805 via a bus or other communication link 1813, In at least one embodiment, communication link 1813 may use one of any number of standards based communication Imk technologies or protocols, such as, but not limited to PCI Express, or may be a vendor-specific communications interface or communications fabric. In at least one embodiment, one or more parallel processor(s) 1812 form a computationally focused parallel or vector processing system that can include a large number of processing cores and / or processing clusters, such as a many-integrated core (MIC) processor. In at least one embodiment, some or all of parallel processor(s) 1812 form a graphics processing subsystem that can output pixels to one of one or more display device(s) 1810A coupled via I / O Hub 1807. In at least one embodiment, parallel processor(s) 1812 can also include a display controller and display-interface (not shown) to enable a direct connection to one or more display device(s) 1810B. In at least one embodiment, parallel processor(s) 1812 include one or more cores, such as graphics cores 1700 discussed herein. [03461 In at least one embodiment, a system storage unit 1814 can connect to I / O hub 1807 to provide a storage mechanism for computing system 1800. In at least one embodiment, an 170 switch 1816 can be used to provide an interface mechanism to enable connections between I / O hub 1807 and other components, such as a network adapter 1818 and / or a wireless network adapter 1819 that may be integrated into platform, and various other devices that can be added via one or more add-in device(s) 1820. In at least one embodiment, network adapter 1818 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 1819 can include one or more of a Wi-Fi, Bluetooth, near field communication (NFC), or other network device that includes one or more wireless radios.

[0347] In at least one embodiment, computing system 1800 can include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, and like, may- also be connected to 170 hub 1807. In at least one embodiment, communication paths interconnecting various components in FIG. 18 may be implemented using any suitable protocols, such as PCI (Peripheral Component Interconnect) based protocols (e.g., PCI-Express), or other bus or point-to-point communication interfaces and / or protocol(s), such as NV-Link high-speed interconnect, or interconnect protocols. [03481 In at least one embodiment, parallel processor(s) 1812 incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitutes a graphics processing unit (GPU), e.g., parallel processor(s) 1812 includes graphics core 1700. In at least one embodiment, parallel processor(s) 1812 incorporate circuitry' optimized for general purpose processing. In at least embodiment, components of computing system 1800 may7 be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, parallel processor(s) 1812, memory hub 1805, processor(s) 1802, and I / O hub 1807 can be integrated into a system on chip (SoC) integrated circuit. In at least one embodiment, components of computing system 1800 can be integrated into a single package to form a system in package (SIP) configuration. In at least one embodiment, at least a portion of components of computing system 1800 can be integrated into a multichip module (MCM), which can be interconnected with other multi-chip modules into a modular computing system. [0.349] Logic 615 are used to perform referencing and / or training operations associated with one or more embodiments. Details regarding logic 615 are provided herein in conjunction with FIGS. 6A and / or 6B. In at least one embodiment, logic 615 may be used in computing system 1800 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0350] In at least one embodiment, an embodiment consistent with said figures includes one or more processors, circuitry, or systems to cause one or more pinned shared memory buffers to be allocated to one or more neural network accelerators, wherein the one or more pinned shared memory buffers are to store a plurality of neural network training checkpoints to be used by the one or more neural network accelerators to recover from one or more errors detected during training of one or more neural networks, such as described with respect to any of FIGS. 1-5B. PROCESSORS [03511 FIG. I9A illustrates a parallel processor 1900 according to at least one embodiment. In at least one embodiment, various components of parallel processor 1900 may be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits (ASICs), or field programmable gate arrays (FPGA). In at least one embodiment, illustrated parallel processor 1900 is a variant of one or more parallel processors) 1812 shown in FIG. 18 according to an exemplary embodiment. In at least one embodiment, a parallel processor 1900 includes one or more graphics cores 1700. [03521 In at least one embodiment, parallel processor 1900 includes a parallel processing unit 1902. In at least one embodiment, parallel processing unit 1902 includes an I / O unit 1904 that enables communication with other devices, including other instances of parallel processing unit 1902. In at least one embodiment, I / O unit 1904 may be directly connected to other devices. In at least one embodiment, I / O unit 1904 connects with other devices via use of a hub or switch interface, such as a memory hub 1905. In at least one embodiment, connections between memory hub 1905 and I / O unit 1904 form a communication link 1913. In at least one embodiment, I / O unit 1904 connects with a host interface 1906 and a memory crossbar 1916, where host interface 1906 receives commands directed to performing processing operations and memory crossbar 1916 receives commands directed to performing memory7 operations.

[0353] In at least one embodiment, when host interface 1906 receives a command buffer via I / O unit 1904, host interface 1906 can direct work operations to perform those commands to a front end 1908. In at least one embodiment, front end 1908 couples with a scheduler 1910 (which may be referred to as a sequencer), which is configured to distribute commands or other work items to a processing cluster array 1912. In at least one embodiment, scheduler 1910 ensures that processing cluster array 1912. is properly configured and in a valid state before tasks are distributed to a cluster of processing cluster array 1912. In at least one embodiment, scheduler 1910 is implemented via firmware logic executing on a microcontroller. In at least one embodiment, microcontroller implemented scheduler 1910 is configurable to perform complex scheduling and work distribution operations at coarse and fine granularity7, enabling rapid preemption and context switching of threads executing on processing array 1912. In at least one embodiment, host software can prove workloads for scheduling on processing cluster array 1912 via one of multiple graphics processing paths. In at least one embodiment, workloads can then be automatically7 distributed across processing array cluster 1912 by scheduler 1910 logic within a microcontroller including scheduler 1910.

[0354] In at least one embodiment, processing cluster array 1912 can include up to “N” processing clusters (e.g., cluster 1914A, cluster 1914B, through cluster 1914N), where “N” represents a positive integer (which may be a different integer “N” than used in other figures). In at least one embodiment, each cluster 1914A-1914N of processing cluster array 1912 can execute a large number of concurrent threads. In at least one embodiment, scheduler 1910 can allocate work to clusters 1914A-1914N of processing cluster array 1912 using various scheduling and / or work distribution algorithms, wdiich may vary depending on workload arising for each type of program or computation. In at least one embodiment, scheduling can be handled dynamically by scheduler 1910, or can be assisted in part by compiler logic during compilation of program logic configured for execution by processing cluster array7 1912. In at least one embodiment, different clusters 1914A-1914N of processing cluster array 1912 can be allocated for processing different types of programs or for performing different types of computations.

[0355] In at least one embodiment, processing cluster array7 1912 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array7 1912 is configured to perform general-purpose parallel compute operations. For example, in at least one embodiment, processing cluster array 1912 can include logic to execute processing tasks including filtering of video and / or audio data, performing modeling operations, including physics operations, and performing data transformations. [03561 In at least one embodiment, processing cluster array 1912 is configured to perform parallel graphics processing operations. In at least one embodiment, processing cluster array 1912 can include additional logic to support execution of such graphics processing operations, including but not limited to, texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing cluster array 1912 can be configured to execute graphics processing related shader programs such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing unit 1902 can transfer data from system memory via I / O unit 1904 for processing. In at least one embodiment, during processing, transferred data can be stored to on-chip memory' (e.g., parallel processor memory 1922) during processing, then written back to system memory. [03571 In at least one embodiment, when parallel processing unit 1902 is used to perform graphics processing, scheduler 1910 can be configured to divide a processing workload into approximately equal sized tasks, to better enable distribution of graphics processing operations to multiple clusters 1914A-1914N of processing cluster array 1912. In at least one embodiment, portions of processing cluster array 1912 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations, to produce a rendered image for display. In at least one embodiment, intermediate data produced by one or more of clusters I914A-I914N may be stored in buffers to allow intermediate data to be transmitted between clusters 1914A-1914N for further processing. [03581 In at least one embodiment, processing cluster array 1912 can receive processing tasks to be executed via scheduler 1910, which receives commands defining processing tasks from front end 1908. In at least one embodiment, processing tasks can include indices of data to be processed, e.g., surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how’ data is to be processed (e.g., what program is to be executed). In at least one embodiment, scheduler 1910 may be configured to fetch indices corresponding to tasks or may receive indices from front end 1908. In at least one embodiment, front end 1908 can be configured to ensure processing cluster array 1912 is configured to a valid state before a workload specified by incoming command buffers (e.g., batch-buffers, push buffers, etc.) is initiated.

[0359] In at least one embodiment, each of one or more instances of parallel processing unit 1902 can couple with a parallel processor memory 1922. In at least one embodiment, parallel processor memory7 1922 can be accessed via memory7 crossbar 1916, which can receive memory' requests from processing cluster array7 1912 as well as I / O unit 1904. In at least one embodiment, memory' crossbar 1916 can access parallel processor memory’ 1922 via a memory interface 1918. In at least one embodiment, memory’ interface 1918 can include multiple partition units (e.g., partition unit 1920A, partition unit 1920B, through partition unit 1920N) that can each couple to a portion (e.g,, memory unit) of parallel processor memory 1922. In at least one embodiment, a number of partition units 1920A-1920N is configured to be equal to a number of memory units, such that a first partition unit 1920A has a corresponding first memory' unit 1924A, a second partition unit 1920B has a corresponding memory' unit 1924B, and an N-th partition unit 1920N has a corresponding N-th memory unit 1924N. In at least one embodiment, a number of partition units 1920A-1920N may not be equal to a number of memory units.

[0360] In at least one embodiment, memory units 1924A-1924N can include various types of memory devices, including dynamic random access memory' (DRAM) or graphics random access memory', such as synchronous graphics random access memory' (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 1924A-1924N may also include 3D stacked memory', including but not limited to high bandwidth memoiy (HBM), HBM2e, or HDM3. In at least one embodiment, render targets, such as frame buffers or texture maps may be stored across memory units 1924A-1924N, allowing partition units 1920A-1920N to write portions of each render target in parallel to efficiently use available bandwidth of parallel processor memory' 1922. In at least one embodiment, a local instance of parallel processor memory 1922 may be excluded in favor of a unified memory design that utilizes system memory in conjunction with local cache memory. [0361j In at least one embodiment, any one of clusters 1914A-1914N of processing cluster array 1912 can process data that will be written to any of memory' units 1924A-1924N within parallel processor memory 1922. In at least one embodiment, memoiy crossbar 1916 can be configured to transfer an output of each cluster 1914A-1914N to any partition unit 1920A-192ON or to another cluster 1914A-1914N, which can perform additional processing operations on an output. In at least one embodiment, each cluster 1914A-1914N can communicate with mem ory interface 1918 through memory' crossbar 1916 to read from or write to various external memoiy' devices. In at least one embodiment, memory' crossbar 1916 has a connection to memory’ interface 1918 to communicate with I / O unit 1904, as well as a connection to a local instance of parallel processor memory 1922, enabling processing units within different processing clusters 1914A-1914N to communicate with system memory or other memoiy that is not local to parallel processing unit 1902. In at least one embodiment, memory' crossbar 1916 can use virtual channels to separate traffic streams between clusters 1914A-1914N and partition units 1920A-1920N.

[0362] In at least one embodiment, multiple instances of parallel processing unit 1902 can be provided on a single add-in card, or multiple add-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 1902 can be configured to interoperate even if different instances have different numbers of processing cores, different amounts of local parallel processor memory', and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 1902 can include higher precision floating point units relative to other instances. In at least one embodiment, systems incorporating one or more instances of parallel processing unit 1902 or parallel processor 1900 can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems. [03631 FIG. 19B is a block diagram of a partition unit 1920 according to at least one embodiment. In at least one embodiment, partition unit 1920 is an instance of one of partition units 1920A-1920N of FIG. 19A. In at least one embodiment, partition unit 1920 includes an L2 cache 1921, a frame buffer interface 1925, and a ROP 1926 (raster operations unit). In at least one embodiment, L2 cache 1921 is a read / write cache that is configured to perform load and store operations received from memory crossbar 1916 and ROP 1926. In at least one embodiment, read misses and urgent write-back requests are output by L2 cache 1921 to frame buffer interface 1925 for processing. In at least one embodiment, updates can also be sent to a frame buffer via frame buffer interface 1925 for processing. In at least one embodiment, frame buffer interface 1925 interfaces with one of memory units in parallel processor memory, such as memory’ units 1924A-1924N of FIG. 19A (e.g., within parallel processor memory 1922). [03641 In at least one embodiment, ROP 1926 is a processing unit that performs raster operations such as stencil, z test, blending, etc. In at least one embodiment, ROP 1926 then outputs processed graphics data that is stored in graphics memory'. In at least one embodiment, ROP 1926 includes compression logic to compress depth or color data that is written to memory’ and decompress depth or color data that is read from memory. In at least one embodiment, compression logic can be lossless compression logic that makes use of one or more of multiple compression algorithms. In at least one embodiment, a type of compression that is performed by ROP 1926 can vary based on statistical characteristics of data to be compressed. For example, in at least one embodiment, delta color compression is performed on depth and color data on a per-tile basis. [03651 In at least one embodiment, ROP 1926 is included within each processing cluster (e.g., cluster 1914A-1914N of FIG. 19A) instead of within partition unit 1920. In at least one embodiment, read and write requests for pixel data are transmitted over memory crossbar 1916 instead of pixel fragment data. In at least one embodiment, processed graphics data may' be displayed on a display device, such as one of one or more display device(s) 1810 of FIG. 18, routed for further processing by processor(s) 1802, or routed for further processing by' one of processing entities within parallel processor 1900 of FIG. 19 A. [03661 FIG. 19C is a block diagram of a processing cluster 1914 within a parallel processing unit according to at least one embodiment. In at least one embodiment, a processing cluster is an instance of one of processing clusters 1914A-1914N of FIG. 19A. In at least one embodiment, processing cluster 1914 can be configured to execute many threads in parallel, where “thread” refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, single-instruction, multipledata (SIMO) instruction issue techniques are used to support parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single-instruction, multiple-thread (SIMT) techniques are used to support parallel execution of a large number of generally synchronized threads, using a common instruction unit configured to issue instructions to a set of processing engines within each one of processing clusters. [0.367] In at least one embodiment, operation of processing cluster 1914 can be controlled via a pipeline manager 1932 that distributes processing tasks to SIMT parallel processors. In at least one embodiment, pipeline manager 1932 receives instructions from scheduler 1910 of FIG. 19A and manages execution of those instructions via a graphics multiprocessor 1934 and / or a texture unit 1936. In at least one embodiment, graphics multiprocessor 1934 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of differing architectures may be included within processing cluster 1914. In at least one embodiment, one or more instances of graphics multiprocessor 1934 erm be included within a processing cluster 1914. In at least one embodiment, graphics multiprocessor 1934 can process data and a data crossbar 1940 can be used to distribute processed data to one of multiple possible destinations, including other shader units. In at least one embodiment, pipeline manager 1932 can facilitate distribution of processed data by specifying destinations for processed data to be distributed via data crossbar 1940. [03681 In at least one embodiment, each graphics multiprocessor 1934 within processing cluster 1914 can include an identical set of functional execution logic (e.g., arithmetic logic units, load-store units, etc.). In at least one embodiment, functional execution logic can be configured in a pipelined manner in which new instructions can be issued before previous instructions are complete. In at least one embodiment, functional execution logic supports a variety of operations including integer and floating point arithmetic, comparison operations, Boolean operations, bit-shifting, and computation of various algebraic functions. In at least one embodiment, same functional-unit hardware can be leveraged to perform different operations and any combination of functional units may be present.

[0369] In at least one embodiment, instructions transmitted to processing cluster 1914 constitute a thread. In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a common program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within a graphics multiprocessor 1934. In at least one embodiment, a thread group may include fewer threads than a number of processing engines within graphics multiprocessor 1934. In at least one embodiment, -when a thread group includes fewer threads than a number of processing engines, one or more of processing engines may be idle during cycles in which that thread group is being processed. In at least one embodiment, a thread group may also include more threads than a number of processing engines within graphics multiprocessor 1934. In at least one embodiment, when a thread group includes more threads than number of processing engines within graphics multiprocessor 1934, processing can be performed over consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed concurrently on a graphics multiprocessor 1934. [03701 In at least one embodiment, graphics multiprocessor 1934 includes an internal cache memory to perform load and store operations. In at least one embodiment, graphics multiprocessor 1934 can forego an internal cache and use a cache memory (e.g., LI cache 1948) within processing cluster 1914. In at least one embodiment, each graphics multiprocessor 1934 also has access to L2 caches within partition units (e.g., partition units 1920A-1920N of FIG. 19A) that are shared among all processing clusters 1914 and may be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 1934 may also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 1902 may be used as global memory. In at least one embodiment, processing cluster 1914 includes multiple instances of graphics multiprocessor 1934 and can share common instructions and data, which may be stored in LI cache 1948.

[0371] In at least one embodiment, each processing cluster 1914 may include an MMU 1945 (memory management unit) that is configured to map virtual addresses into physical addresses. In at least one embodiment, one or more instances of MMLT 1945 may reside within memory interface 1918 of FIG. 19A. In at least one embodiment, MMU 1945 includes a set of page table entries (PTEs) used to map a virtual address to a physical address of a tile and optionally a cache line index. In at least one embodiment, MMU 1945 may include address translation lookaside buffers (TLB) or caches that may reside within graphics multiprocessor 1934 or LI 1948 cache or processing cluster 1914. In at least one embodiment, a physical address is processed to distribute surface data access locally to allow for efficient request interleaving among partition units. In at least one embodiment, a cache line index may be used to determine whether a request for a cache line is a hit or miss.

[0372] In at least one embodiment, a processing cluster 1914 may be configured such that each graphics multiprocessor 1934 is coupled to a texture unit 1936 for performing texture mapping operations, e.g., determining texture sample positions, reading texture data, and filtering texture data. In at least one embodiment, texture data is read from an internal texture LI cache (not shown) or from an LI cache within graphics multiprocessor 1934 and is fetched from an L2 cache, local parallel processor memory, or sy stem memory, as needed. In at least one embodiment, each graphics multiprocessor 1934 outputs processed tasks to data crossbar 1940 to provide processed task to another processing cluster 1914 for further processing or to store processed task in an L2 cache, local parallel processor memory’, or system memory’ via memoiy crossbar 1916. In at least one embodiment, a preROP 1942 (pre-raster operations unit) is configured to receive data from graphics multiprocessor 1934, and direct data to ROP units, which may be located with partition units as described herein (e.g., partition units 1920A-1920N of FIG. 19A). In at least one embodiment, preROP 1942 unit can perform optimizations for color blending, organizing pixel color data, and performing address translations. [03731 Logic 615 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding logic 615 are provided herein in conjunction with FIGS. 6A and / or 6B. In at least one embodiment, logic 615 may be used in graphics processing cluster 1914 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein. [03741 In at least one embodiment, an embodiment consistent with said figures includes one or more processors, circuitry, or systems to cause one or more pinned shared memory buffers to be allocated to one or more neural network accelerators, wherein the one or more pinned shared memory buffers are to store a plurality7 of neural network training checkpoints to be used by the one or more neural network accelerators to recover from one or more errors detected during training of one or more neural networks, such as described with respect to any of FIGS. 1-5B.

[0375] FIG. 19D shows a graphics multiprocessor 1934 according to at least one embodiment. In at least one embodiment, graphics multiprocessor 1934 couples with pipeline manager 1932 of processing cluster 1914. In at least one embodiment, graphics multiprocessor 1934 has an execution pipeline including but not limited to an instruction cache 1952, an instruction unit 1954, an address mapping unit 1956, a register file 1958, one or more general purpose graphics processing unit (GPGPU) cores 1962, and one or more load / store units 1966, where one or more load / store units 1966 can perform load / store operations to load / store instructions corresponding to performing an operation. In at least one embodiment, GPGPU cores 1962 and load / store units 1966 are coupled with cache memoiy 1972 and shared memoiy 1970 via a memory and cache interconnect 1968. In at least one embodiment, GPGPU cores 1962 are part of an SoC such as part of integrated circuit 1500 in FIG. 15.

[0376] In at least one embodiment, instruction cache 1952 receives a stream of instructions to execute from pipeline manager 1932. In at least one embodiment, instructions are cached in instruction cache 1952 and dispatched for execution by an instruction unit 1954. In at least one embodiment, instruction unit 1954 can dispatch instructions as thread groups (e.g,, warps, wavefronts, waves), with each thread of thread group assigned to a different execution unit within GPGPU cores 1962. In at least one embodiment, an instruction can access any of a local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, address mapping unit 1956 can be used to translate addresses in a unified address space into a distinct memory address that can be accessed by load / store units 1966. [03771 In at least one embodiment, register file 1958 provides a set of registers for functional units of graphics multiprocessor 1934. In at least one embodiment, register file 1958 provides temporary storage for operands connected to data paths of functional units (e.g., GPGPU cores 1962, load / store units 1966) of graphics multiprocessor 1934. In at least one embodiment, register file 1958 is divided between each of functional units such that each functional unit is allocated a dedicated portion of register file 1958. In at least one embodiment, register file 1958 is divided between different warps (which may be referred to as wavefronts and / or waves) being executed by graphics multiprocessor 1934. [03781 In at least one embodiment, GPGPU cores 1962 can each include floating point units (FPUs) and / or integer arithmetic logic units (ALUs) that are used to execute instructions of graphics multiprocessor 1934. In at least one embodiment, GPGPU cores 1962 can be similar in architecture or can differ in architecture. In at least one embodiment, a first portion of GPGPU cores 1962 include a single precision FPU and an integer ALU while a second portion of GPGPU cores include a double precision FPU. In at least one embodiment, FPUs can implement IEEE 754-2008 standard floating point arithmetic or enable variable precision floating point arithmetic. In at least one embodiment, graphics multiprocessor 1934 can additionally include one or more fixed function or special function units to perform specific functions such as copy rectangle or pixel blending operations. In at least one embodiment, one or more of GPGPU cores 1962 can also include fixed or special function logic. [03791 In at least one embodiment, GPGPU cores 1962 include SIMD logic capable of performing a single instruction on multiple sets of data. In at least one embodiment, GPGPU cores 1962 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically’ execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for GPGPU cores can be generated at compile time by a shader compiler or automatically generated when executing programs written and compiled for single program multiple data (SPMD) or SIMT architectures. In at least one embodiment, multiple threads of a program configured for an SIMT execution model can executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads that perform same or similar operations can be executed in parallel via a single SIMD8 logic unit.

[0380] In at least one embodiment, memory and cache interconnect 1968 is an interconnect network that connects each functional unit of graphics multiprocessor 1934 to register file 1958 and to shared memory 1970. In at least one embodiment, memory7 and cache interconnect 1968 is a crossbar interconnect that allows load / store unit 1966 to implement load and store operations between shared memory 1970 and register file 1958. In at least one embodiment, register file 1958 can operate at a same frequency as GPGPU cores 1962, thus data transfer between GPGPU cores 1962 and register file 195 8 can have very' low latency. In at least one embodiment, shared memory' 1970 can be used to enable communication between threads that execute on functional units -within graphics multiprocessor 1934. In at least one embodiment, cache memory 1972 can be used as a data cache for example, to cache texture data communicated between functional units and texture unit 1936. In at least one embodiment, shared memory 1970 can also be used as a program managed cache. In at least one embodiment, threads executing on GPGPU cores 1962 can programmatically store data within shared memory in addition to automatically cached data that is stored within cache memory 1972. [03811 In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to host / processor cores to accelerate graphics operations, machine-learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. In at least one embodiment, a GPU may be communicatively coupled to host processor / cores over a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, an SoC comprises a parallel processor or GPGPU as described herein, wdiere said parallel processor or said GPGPU is performed on said SoC. In at least one embodiment, a GPU may be integrated on a package or chip as cores and communicatively coupled to cores over an internal processor bus / interconnect internal to a package or chip. In at least one embodiment, regardless a manner in which a GPU is connected, processor cores may allocate work to such GPU in a form of sequences of commands / instructions contained in a work descriptor. In at least one embodiment, that GPU then uses dedicated circuitry / logic for efficiently processing these commands / instructions. [03821 Logic 615 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding logic 615 are provided herein in conjunction with FIGS. 6A and / or 6B. In at least one embodiment, logic 615 may be used in graphics multiprocessor 1934 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein. [0383 j In at least one embodiment, an embodiment consistent with said figures includes one or more processors, circuitry’, or systems to cause one or more pinned shared memory’ buffers to be allocated to one or more neural network accelerators, wherein the one or more pinned shared memory’ buffers are to store a plurality of neural network training checkpoints to be used by the one or more neural network accelerators to recover from one or more errors detected during training of one or more neural networks, such as described with respect to any of FIGS. 1-5B. [03841 FIG. 20 illustrates a muiti-GPU computing system 2000, according to at least one embodiment. In at least one embodiment, muiti-GPU computing system 2000 can include a processor 2002 coupled to multiple general purpose graphics processing units (GPGPUs) 2006A-D via a host interface switch 2004. In at least one embodiment, host interface switch 2004 is a PCI express switch device that couples processor 2002 to a PCI express bus over which processor 2002 can communicate with GPGPUs 2006A-D. In at least one embodiment, GPGPUs 2006A-D can interconnect via a set of high-speed point-to-point GPU-to- GPU links 2016, In at least one embodiment, GPU-to-GPU links 2016 connect to each of GPGPUs 2006A-D via a dedicated GPU link. In at least one embodiment, P2P GPU links 2016 enable direct communication between each of GPGPUs 2006A-D without requiring communication over host interface bus 2004 to which processor 2002 is connected. In at least one embodiment, with GPU-to-GPU traffic directed to P2P GPU links 2016, host interface bus 2004 remains available for system memory access or to communicate with other instances of multi-GPU computing system 2000, for example, via one or more network devices. While in at least one embodiment GPGPUs 2006A-D connect to processor 2002 via host interface switch 2004, in at least one embodiment processor 2002 includes direct support for P2P GPU links 2016 and can connect directly to GPGPUs 2006A-D. In at least one embodiment, GPGPUs 2006A-D is part of an SoC such as part of integrated circuit 1500 in FIG. 15, wherein GPGPUs 2006A-D performs operations described herein.

[0385] Logic 615 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding logic 615 are provided herein in conjunction with FIGS. 6A and / or 6B. In at least one embodiment, logic 615 may be used in multi-GPU computing system 2000 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein. [03861 In at least one embodiment, multi-GPU computing system 2000 includes one or more graphics cores 1700.

[0387] In at least one embodiment, an embodiment consistent with said figures includes one or more processors, circuitry, or systems to cause one or more pinned shared memory buffers to be allocated to one or more neural network accelerators, wherein the one or more pinned shared memory buffers are to store a plurality of neural network training checkpoints to be used by the one or more neural network accelerators to recover from one or more errors detected during training of one or more neural networks, such as described with respect to any of FIGS. I-5B. [03881 FIG. 21 is a block diagram of a graphics processor 2100, according to at least one embodiment. In at least one embodiment, graphics processor 2100 includes a ring interconnect 2102, a pipeline front-end 2104, a media engine 2137, and graphics cores 2180A-2180N. In at least one embodiment, ring interconnect 2102 couples graphics processor 2100 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 2100 is one of many processors integrated within a multi-core processing system. In at least one embodiment, graphics processor 2100 includes graphics core 1700.

[0389] In at least one embodiment, graphics processor 2100 receives batches of commands via ring interconnect 2102. In at least one embodiment, incoming commands are interpreted by a command streamer 2103 in pipeline front-end 2104. In at least one embodiment, graphics processor 2100 includes scalable execution logic to perform 3D geometty processing and media processing via graphics core(s) 2180A-2180N. In at least one embodiment, for 3D geometry processing commands, command streamer 2103 supplies commands to geometry pipeline 2136. In at least one embodiment, for at least some media processing commands, command streamer 2103 supplies commands to a video front end 2134, which couples with media engine 2137. In at least one embodiment, media engine 2137 includes a Video Quality Engine (VQE) 2130 for video and image post-processing and a multi-format encode / decode (MFX) 2133 engine to provide hardware-accelerated media data encoding and decoding. In at least one embodiment, geometry' pipeline 2136 and media engine 2137 each generate execution threads for thread execution resources provided by at least one graphics core 2180. [03901 In at least one embodiment, graphics processor 2100 includes scalable thread execution resources featuring graphics cores 2180A-2180N (which can be modular and are sometimes referred to as core slices), each having multiple sub-cores 2150A-2150N, 2160A-2160N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor 2100 can have any number of graphics cores 2180 A. In at least one embodiment, graphics processor 2100 includes a graphics core 2180A having at least a first subcore 2150A and a second sub-core 2160A. In at least one embodiment, graphics processor 2100 is a low power processor with a single sub-core (e.g., 2150A). In at least one embodiment, graphics processor 2100 mcludes multiple graphics cores 2180A-2180N, each including a set of first sub-cores 2150A-2150N and a set of second sub-cores 2160A-2160N. In at least one embodiment, each sub-core in first sub-cores 2150A-2150N includes at least a first set of execution units 2152A-2152N and media / texture samplers 2154A-2154N. In at least one embodiment, each sub-core in second sub-cores 2160A-2160N includes at least a second set of execution units 2162A-2162N and samplers 2164A-2164N. In at least one embodiment, each sub-core 2150A-2150N, 2160A-2160N shares a set of shared resources 2170A-2170N. In at least one embodiment, shared resources include shared cache memory’ and pixel operation logic. In at least one embodiment, graphics processor 2100 includes load / store units in pipeline front-end 2104. [03911 Logic 615 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding logic 615 are provided herein in conjunction with FIGS. 6A and / or 6B. In at least one embodiment, logic 615 may be used in graphics processor 2100 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein. [03921 In at least one embodiment, an embodiment consistent with said figures includes one or more processors, circuitry', or systems to cause one or more pinned shared memory' buffers to be allocated to one or more neural network accelerators, wherein the one or more pinned shared memory' buffers are to store a plurality’ of neural network training checkpoints to be used by the one or more neural network accelerators to recover from one or more errors detected during training of one or more neural networks, such as described with respect to any of FIGS. 1-5B.

[0393] FIG. 22 is a block diagram illustrating micro-architecture for a processor 2200 that may include logic circuits to perform instructions, according to at least one embodiment. In at least one embodiment, processor 2200 may perform instructions, including x86 instractions, ARM instructions, specialized instructions for application-specific integrated circuits (ASICs), etc. In at least one embodiment, processor 2200 may include registers to store packed data, such as 64-bit wide MMX™ registers in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, Calif. In at least one embodiment, MMX registers, available in both integer and floating point forms, may operate with packed data elements that accompany single instruction, multiple data (“SIMD”) and streaming SIMD extensions (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers relating to SSE2, SSE3, SSE4, AVX, or beyond (referred to generically as “SSEx”) technology may hold such packed data operands. In at least one embodiment, processor 2200 may perforin instructions to accelerate machine learning or deep learning algorithms, training, or inferencing. [03941 In at least one embodiment, processor 2200 includes an in-order front end (“front end”) 2201 to fetch instructions to be executed and prepare instructions to be used later in a processor pipeline. In at least one embodiment, front end 2201 may include several units. In at least one embodiment, an instruction prefetcher 2226 fetches instructions from memory and feeds instructions to an instruction decoder 2228 which in turn decodes or interprets instructions. For example, in at least one embodiment, instruction decoder 2228 decodes a received instruction into one or more operations called “micro-instructions” or “micro-operations” (also called “micro ops” or “uops” or “p-ops”) that a machine may execute. In at least one embodiment, instruction decoder 2228 parses an instruction into an opcode and corresponding data and control fields that may be used by micro-architecture to perform operations in accordance with at least one embodiment. In at least one embodiment, a trace cache 2230 may assemble decoded uops into program ordered sequences or traces in a uop queue 2234 for execution. In at least one embodiment, when trace cache 2230 encounters a complex instruction, a microcode ROM 2232 provides uops needed to complete an operation. [0395j In at least one embodiment, some instructions may be converted into a single micro-op, whereas others need several micro-ops to complete full operation. In at least one embodiment, if more than four micro-ops are needed to complete an instruction, instruction decoder 2228 may access microcode ROM 2232 to perform that instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-ops for processing at instruction decoder 2228. In at least one embodiment, an instruction may be stored within microcode ROM 2232 should a number of micro-ops be needed to accomplish such operation. In at least one embodiment, trace cache 2230 refers to an entry point programmable logic array (“PLA”) to determine a correct micro-instruction pointer for reading microcode sequences to complete one or more instructions from microcode ROM 2232 in accordance with at least one embodiment. In at least one embodiment, after microcode ROM 2232 finishes sequencing micro-ops for an instruction, front end 2201 of a machine may resume fetching micro-ops from trace cache 2230. [0396j In at least one embodiment, out-of-order execution engine (“out of order engine”) 2203 may prepare instructions for execution. In at least one embodiment, out-of-order execution logic has a number of buffers to smooth out and re-order flow of instructions to optimize performance as they go down a pipeline and get scheduled for execution. In at least one embodiment, out-of-order execution engine 2203 includes, without limitation, an allocator / register renamer 2240, a memory' nop queue 2242, an integer / fioating point uop queue 2244, a memory scheduler 2246, a fast scheduler 2202, a slow / general floating point scheduler (“slow / general FP scheduler”) 2204, and a simple floating point scheduler (“simple FP scheduler”) 2206. In at least one embodiment, fast schedule 2202, slow / general floating point scheduler 2204, and simple floating point scheduler 2206 are also collectively referred to herein as “uop schedulers 2202, 2204, 2206.” In at least one embodiment, allocator / register renamer 2240 allocates machine buffers and resources that each uop needs m order to execute. In at least one embodiment, allocator / register renamer 2240 renames logic registers onto entries in a register file. In at least one embodiment, allocator / register renamer 2240 also allocates an entry for each uop in one of two uop queues, memory uop queue 2242 for memory' operations and integer / fioating point uop queue 2244 for non-memory operations, in front of memory scheduler 2246 and uop schedulers 2202, 2204, 2206. In at least one embodiment, uop schedulers 2202, 2204, 2206, determine when a uop is ready to execute based on readiness of their dependent input register operand sources and availability of execution resources uops need to complete their operation. In at least one embodiment, fast scheduler 2202 may schedule on each half of a main clock cycle while slow / general floating point scheduler 2204 and simple floating point scheduler 2206 may schedule once per main processor clock cycle. In at least one embodiment, uop schedulers 2202, 2204, 2206 arbitrate for dispatch ports to schedule uops for execution.

[0397] In at least one embodiment, execution block 22.11 includes, without limitation, an integer register file / bypass network 2208, a floating point register file / bypass network (“FP register file / bypass network”) 2210, address generation units (“AGUs”) 2212 and 2214, fast Arithmetic Logic Units (ALUs) (“fast ALUs”) 2216 and 2218, a slow Arithmetic Logic Unit (“slow ALU”) 2220, a floating point ALU (“FP”) 2222, and a floating point move unit (“FP move”) 2224. In at least one embodiment, integer register file / bypass network 2208 and floating point register file / bypass network 2210 are also referred to herein as “register files 2208, 2210.” In at least one embodiment, AGUSs 2212 and 2214, fast ALLTs 2216 and 2218, slow' ALU 2220, floating point ALU 2222, and floating point move unit 2224 are also referred to herein as “execution units 2212, 2214, 2216, 2218, 2220, 2222, and 2224.” In at least one embodiment, execution block 2211 may include, without limitation, any number (including zero) and type of register files, bypass networks, address generation units, and execution units, in any combination.

[0398] In at least one embodiment, register networks 2208, 2210 may be arranged between nop schedulers 2202, 2204, 2206, and execution units 2212, 2214, 2216, 2218, 2220, 2222, and 2224. In at least one embodiment, integer register file,'bypass network 2208 performs integer operations. In at least one embodiment, floating point register file / bypass network 2210 performs floating point operations. In at least one embodiment, each of register networks 2208, 22.10 may include, without limitation, a bypass network that may bypass or forward just completed results that have not yet been written into a register file to new dependent uops. In at least one embodiment, register networks 2208, 2210 may communicate data with each other. In at least one embodiment, integer register file / bypass network 2208 may include, without limitation, two separate register files, one register file for a low-order thirty-two bits of data and a second register file for a high order thirty-two bits of data. In at least one embodiment, floating point register file / bypass network 2210 may include, without limitation, 128-bit wide entries because floating point instructions typically have operands from 64 to 128 bits in width. [03991 In at least one embodiment, execution units 2212, 2214, 2216, 2218, 2220, 2222, 2224 may execute instructions. In at least one embodiment, register networks 2208, 2.210 store integer and floating point data operand values that micro-instructions need to execute. In at least one embodiment, processor 2200 may include, without limitation, any number and combination of execution units 2212, 2214, 2216, 2218, 2220, 2222, 2224. In at least one embodiment, floating point ALU 2222 and floating point move unit 2224, may execute floating point, MMX, SIMD, AVX and SSE, or other operations, including specialized machine learning instructions. In at least one embodiment, floating point ALU 2222 may include, without limitation, a 64-bit by 64-bit floating point divider to execute divide, square root, and remainder micro ops. In at least one embodiment, instructions involving a floating point value may be handled with floating point hardware. In at least one embodiment, ALU operations may be passed to fast ALUs 2216, 2218. In at least one embodiment, fast ALUS 2216, 2218 may execute fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations go to slow ALU 2220 as slow ALU 2220 may include, without limitation, integer execution hardware for long-latency type of operations, such as a multiplier, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations may be executed by AGUs 2212, 2214. In at least one embodiment, fast ALU 2216, fast ALU 22.18, and slow ALU 2220 may perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2216, fast ALU 2218, and slow ALU 2220 may be implemented to support a variety' of data bit sizes including sixteen, thirty -two, 128, 256, etc. In at least one embodiment, floating point ALU 2222 and floating point move unit 2224 may be implemented to support a range of operands having bits of various widths, such as 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0400] In at least one embodiment, nop schedulers 2202, 2204, 2206 dispatch dependent operations before a parent load has finished executing. In at least one embodiment, as uops may be speculatively scheduled and executed in processor 2200, processor 2200 may also include logic to handle memory misses. In at least one embodiment, if a data load misses in a data cache, there may be dependent operations in flight in a pipeline that have left a scheduler with temporarily incorrect data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, dependent operations might need to be replayed and independent ones may be allowed to complete. In at least one embodiment, schedulers and a replay mechanism of at least one embodiment of a processor may also be designed to catch instruction sequences for text string comparison operations.

[0401] In at least one embodiment, “registers” may refer to on-board processor storage locations that may be used as part of instructions to identify operands. In at least one embodiment, registers may be those that may be usable from outside of a processor (from a programmer’s perspective). In at least one embodiment, registers might not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform functions described herein. In at least one embodiment, registers described herein may be implemented by circuitry within a processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, integer registers store 32-bit integer data. A register file of at least one embodiment also contains eight multimedia SIMD registers for packed data. [04021 In at least one embodiment, processor 2200 or each core of processor 2200 includes one or more prefetchers, one or more fetchers, one or more pre-decoders, one or more decoders to decode data (e.g., instructions), one or more instruction queues to process instructions (e.g., corresponding to operations or API calls), one or more micro-operation (pOP) cache to store pOPs, one or more micro-operation (pOP) queues, an in-order execution engine, one or more load buffers, one or more store buffers, one or more reorder buffers, one or more fill buffers, an out-of-order execution engine, one or more ports, one or more shift and / or shifter units, one or more fused multiply accumulate (FMA) units, one or more load and store units (“LSUs”) to perform load of store operations corresponding to loading / storing data (e.g., instructions) to perform an operation (e.g., perform an API, an API call), one or more matrix multiply accumulate (MMA) units, and / or one or more shuffle units to perform any function further described herein with respect to said processor 2200. In at least one embodiment processor 2200 can access, use, perform, or execute instructions corresponding to calling an API. [04031 In at least one embodiment, processor 2200 includes one or more ultra path interconnects (UPIs), e.g., that is a point-to-point processor interconnect; one or more PCIe’s; one or more accelerators to accelerate computations or operations; and / or one or more memory controllers. In at least one embodiment, processor 2200 includes a shared last level cache (LLC) that is coupled to one or more memory controllers, which can enable shared memory' access across processor cores. [04041 In at least one embodiment, processor 2200 or a core of processor 2200 has a mesh architecture where processor cores, on-chip caches, memory controllers, and I / O controllers are organized in rows and columns, with wires and switches connecting them at each intersection to allow for turns. In at least one embodiment, processor 2200 has one or more higher memory bandwidths (HMBs, e.g., HMBe) to store data or cache data, e.g., in Double Data Rate 5 Synchronous Dynamic Random-Access Memory7 (DDRS SDRAM). In at least one embodiment, one or more components of processor 2200 are interconnected using compute express link (CXL) interconnects. In at least one embodiment, a memory controller uses a "least recently used" (LRU) approach to determine what gets stored in a cache. In at least one embodiment, processor 2200 includes one or more PCIe’s (e.g., PCIe 5.0).

[0405] Logic 615 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding logic 615 are provided herein in conjunction with FIGS. 6A and / or 6B. In at least one embodiment portions or all of logic 615 may be incorporated into execution block 2211 and other memory or registers shown or not shown. For example, in at least one embodiment, training and / or inferencing techniques described herein may use one or more of ALUs illustrated in execution block 2211. Moreover, weight parameters may be stored in on-chip or off-chip memory’ and / or registers (shown or not shown) that configure ALUs of execution block 2211 to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein. [04061 In at least one embodiment, an embodiment consistent with said figures includes one or more processors, circuitry’, or systems to cause one or more piimed shared memory’ buffers to be allocated to one or more neural network accelerators, wherein the one or more pinned shared memory’ buffers are to store a plurality of neural network training checkpoints to be used by the one or more neural network accelerators to recover from one or more errors detected during training of one or more neural networks, such as described with respect to any of FIGS. 1-5B. [04071 FIG. 23 illustrates a deep learning application processor 2300, according to at least one embodiment. In at least one embodiment, deep learning application processor 2300 uses instructions that, if executed by deep learning application processor 2300, cause deep learning application processor 2300 to perform some or all of processes and techniques described throughout this disclosure. In at least one embodiment, deep learning application processor 2300 is an application-specific integrated circuit (ASIC). In at least one embodiment, application processor 2300 performs matrix multiply operations either “hard wired” into hardware as a result of performing one or more instructions or both. In at least one embodiment, deep learning application processor 2300 includes, without limitation, processing clusters 2310(1)-2310(12), Inter-Chip Links (“ICLs”) 2320(1)-2320(12), Inter-Chip Controllers (“ICCs”) 2330(1)-2330(2), high-bandwidth memory second generation (“HBM2”) 2340(1)-2340(4), memory' controllers (“Mem Ctrlrs”) 2342(1)-2342(4), high bandwidth memory physical layer (“HBM PHY”) 2344(1)-2344(4), a management-controller central processing unit (“management-controller CPU”) 2350, a Serial Peripheral Interface, Inter-Integrated Circuit, and General Purpose Input / Output block (“SP1, FC, GPIO”) 2360, a peripheral component interconnect express controller and direct memory access block (“PCle Controller and DMA”) 2370, and a sixteen-lane peripheral component interconnect express port (“PCI Express x 16”) 2380. [04081 In at least one embodiment, processing clusters 2310 may perform deep learning operations, including inference or prediction operations based on weight parameters calculated one or more training techniques, including those described herein. In at least one embodiment, each processing cluster 2310 may include, without limitation, any number and type of processors. In at least one embodiment, deep learning application processor 2300 may include any number and type of processing clusters 2300. In at least one embodiment, Inter-Chip Links 2320 are bi-directional. In at least one embodiment, Inter-Chip Links 2320 and Inter-Chip Controllers 2330 enable multiple deep learning application processors 2300 to exchange information, including activation information resulting from performing one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, deep learning application processor 2300 may include any number (including zero) and type of ICLs 2320 and ICCs 2330. [04091 In at least one embodiment, HBM2s 2340 provide a total of 32 Gigabytes (GB) of memory'. In at least one embodiment, HBM2 2340(i) is associated with both memory controller 2342(i) and HBM PHY 2344(i) where “i” is an arbitrary' integer. In at least one embodiment, any number of HBM2s 2340 may provide any type and total amount of high bandwidth memory’ and may be associated with any number (including zero) and type of memory controllers 2342 and HBM PHYs 2344. In at least one embodiment, SPI, FC, GPIO 2360, PCle Controller and DMA 2370, and / or PCle 2380 may be replaced with any number and type of blocks that enable any number and type of communication standards in any technically feasible fashion. [04101 Logic 615 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding logic 615 are provided herein in conjunction with FIGS. 6A and / or 6B. In at least one embodiment, deep learning application processor is used to train a machine learning model, such as a neural network, to predict or infer information provided to deep learning application processor 2300. In at least one embodiment, deep learning application processor 2300 is used to infer or predict information based on a trained machine learning model (e.g., neural network) that has been trained by another processor or system or by deep Seaming application processor 2300. In at least one embodiment, processor 2300 may be used to perform one or more neural network use cases described herein.

[0411] In at least one embodiment, an embodiment consistent with said figures includes one or more processors, circuitry, or systems to cause one or more pinned shared memory' buffers to be allocated to one or more neural network accelerators, wherein the one or more pinned shared memory' buffers are to store a plurality’ of neural network training checkpoints to be used by the one or more neural network accelerators to recover from one or more errors detected during training of one or more neural networks, such as described with respect to any of FIGS. 1-5B. [04121 FIG. 24 is a block diagram of a neuromorphic processor 2400, according to at least one embodiment. In at least one embodiment, neuromorphic processor 2400 may receive one or more inputs from sources external to neuromorphic processor 2400. In at least one embodiment, these inputs may be transmitted to one or more neurons 2.402 within neuromorphic processor 2400. In at least one embodiment, neurons 2402 and components thereof may be implemented using circuitry or logic, including one or more arithmetic logic units (ALUs). In at least one embodiment, neuromorphic processor 2400 may include, without limitation, thousands or millions of instances of neurons 2402, but any suitable number of neurons 2402 may be used. In at least one embodiment, each instance of neuron 2402 may include a neuron i...

Claims

1. A processor comprising: one or more circuits to cause one or more pinned shared memory buffers to be allocated to one or more neural network accelerators, wherein the one or more pinned shared memory buffers are to store a plurality of neural network training checkpoints to be used by the one or more neural network accelerators to recover from one or more errors detected during training of one or more neural networks.

2. The processor of claim 1, wherein:the neural network training checkpoints indicate training states of a neural network modified by a training process;the one or more neural network accelerators comprise at least a GPU;the one or more eircuhs are to copy a training state from a GPU memory' associated with the GPU to the pinned shared memory' buffer to create a checkpoint of the training state in the pinned shared memory buffer; andthe copy is performed using a memory-to-memory copy operation that does not create an additional copy of the training state in a process memory of the training process.

3. The processor of claim 2, wherein the pinned shared memory' buffer is:allocated separately from the training process so that the pinned shared memory' buffer is not deallocated when the training process terminates; andpinned so that pages of the pinned shared memory buffer are not swapped out to a secondary' storage.

4. The processor of claim 2 or 3, wherein:the pinned shared memory buffer is pre-allocated as a continuous memory region with capacity to store a plurality of checkpoints generated during the training; andthe continuous memory' region is pinned via a single operating system call.

5. The processor of any of claims 2 to 4, wherein the memory-to-memoty copy' operation is performed using a memory' copy' API and does not use a file access API.

6. The processor of any of claims 2 to 5, w’herein:the training process creates new checkpoints for individual training steps performed during the training; andthe training process does not pause to wait for a new' checkpoint to be created for a previous training step before proceeding with a next training step.

7. Tire processor of any of claim 2 to 6, wherein:the copy of the training state from the GPU memory to the pinned shared memory buffer is performed asynchronously from the training process; andthe training process receives an asynchronous event indicating completion of the copy.

8. Tire processor of any of claims 2 to 7, wherein one or more circuits are to:execute a supervisor process to:monitor a plurality of training processes for errors;detect that the training process has terminated or is to be terminated due to an error: andin response to tire detection, start a second training process to resume work of the trainingprocess from a last checkpoint of the training process.

9. A method, comprising: causing one or more pinned shared memory' buffers to be allocatedto one or more neural network accelerators, wherein the one or more pinned shared memory buffers are to store a plurality of neural network training checkpoints to be used by the one or more neural network accelerators to recover from one or more errors detected during training of one or more neural networks,10. The method of claim 9, further comprising:executing a training process to tram a neural network, wherein:the neural network training checkpoints indicate training states of the neural network as modified by the training process;the one or more neural network accelerators comprise at least a GPU;the method comprises copying a training state from a GPU memo", associated with the GPU to the pinned shared memory' buffer to create a checkpoint of the training state in the pinned shared memory buffer; andthe copy is performed using a memory-to-memory copy operation that does not create an additional copy of the training state in a process memory’ of the training process.

11. The method of claim 10, wherein the pinned shared storage is:allocated separately from the training process so that the pinned shared memory' buffer is not deallocated when the training process terminates; andpinned so that pages of the pinned shared memory buffer are not swapped out to a secondary' storage.

12. The method of claim 10 or 11, wherein:the pinned shared memory buffer is pre-allocated as a continuous memory' region with capacity to store a plurality of checkpoints generated during the training; andthe continuous memory' region is pinned via a single operating system call.

13. The method of any' of claims 10 to 12, wherein:the training process creates new checkpoints for individual training steps performed during the training; andthe training process does not pause to wait for a new checkpoint to be created for a previous training step before proceeding with a next training step.

14. The method of any of claims 10 to 13, further comprising:the copy of the training state from the GPU memory' to the pinned shared memory’ buffer is performed asynchronously' from the training process; andthe training process receives an asynchronous event indicating completion of the copy.

15. The method of any of claims 10 to 14, furthering comprising:executing a supervisor process, wherein the execution includes:monitoring a plurality of training processes for errors;detecting that the training process has terminated or is to be terminated due to an error; and in response to the detection, starting a second training process to resume work of the training process from a last checkpoint of the training process.

16. A system, comprising: one or more computer devices to cause one or more pinned shared memory buffers to be allocated to one or more neural network accelerators, wherein the one or more pinned shared memory' buffers are to store a plurality' of neural network training checkpoints to be used by the one or more neural network accelerators to recover from one or more errors detected during training of one or more neural networks.

17. The system of claim 16, wherein:the neural network training checkpoints indicate training states of a neural network modified by a training process;the one or more neural network accelerators comprise at least a GPU;the one or more computer devices are to copy a training state from a GPU memory associated with the GPU to the pinned shared memory,’ buffer to create a checkpoint of the training state in the pinned shared memory buffer; andthe copy is performed using a memory-to-memory copy operation that does not create an additional copy of the training state in a process memory of the training process.

18. The system of claim 17, wherein:the pinned shared memory buffer is pre-allocated as a continuous memory region with capacity to store a plurality' of checkpoints generated during the training; andthe continuous memory' region is pinned via a single operating system call.

19. The sy stem of claim 17 or 18, wherein:the training process creates new checkpoints for individual training steps performed during the training; andthe training process does not pause to wait for a new checkpoint to be created for a previous training step before proceeding with a next training step.

20. The system of any of claims 17 to 19, wherein one or more computer devices are to: determine that the training process has terminated or is to be terminated due to an error; and start a second training process to resume work of the training process from a last checkpoint of the training process.A

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