Inference model for optimizing a front-end module (FEM) in a wireless communication device

Abstract

A distributed inference model for optimizing a front end module (FEM) in a wireless communication device is disclosed. In one aspect, various tunable elements within the FEM may have optimal settings based on operating conditions. Optimal settings may be found by creating an inference model (e.g., by machine learning or deep learning artificial intelligence (AI) techniques). The inference model may then be associated with a microprocessor in a transceiver. The model uses, as input, current operating conditions based on data from a baseband processor (BBP) and the FEM and calculates appropriate settings for adjustable elements within the FEM. In addition, the inference model may be distributed across various microprocessors within the FEM or the BBP. The size of the distributed reasoning model can be determined according to the size and power of the corresponding associated microprocessor.

Description

(19) State Intellectual Property Office (12) Invention Patent Application (10) Application Publication Number (43) Application Publication Date (21) Application Number 202480050669.3 (22) Application Date 2024.06.03 (30) Priority Data 63 / 472,217 2023.06.09 US 63 / 507,351 2023.06.09 US 63 / 507,376 2023.06.09 US 63 / 507,380 2023.06.09 US 63 / 539,361 2023.09.20 US 63 / 539,367 2023.09.20 US (85) PCT International Application Entering National Phase Date 2026.02.02 (86) Application data for PCT international application PCT / US2024 / 032239 2024.06.03 (87) Publication data for PCT international application WO2024 / 253999 EN 2024.12.12 (71) Applicant QORVO, Inc., USA Address USA (72) Inventors G. Maxim Li Yuyong N. Karat C.T. Brown J. Johnson P. Brickto M. Granger-Jones C. Lovesco S. Pap B. Scott (74) Patent Agency China Council for the Promotion of International Trade Patent & Trademark Office Co., Ltd. 11038 Patent Attorney Zhang Dan (51) Int.Cl. H04B 1 / 04 (2006.01) H04B 1 / 40 (2006.01) (54) Invention title For optimizing the front-end module (FEM) in wireless communication devices Abstract of the inference model (57) discloses a distributed inference model for optimizing a front-end module (FEM) in a wireless communication device. In one aspect, various tunable elements within the FEM can have optimal settings based on operating conditions. The optimal settings can be found by creating an inference model (e.g., through machine learning or deep learning artificial intelligence (AI) techniques). The inference model can then be associated with a microprocessor in a transceiver. The model will use current operating conditions based on data from a baseband processor (BBP) and the FEM as input and calculate appropriate settings for the tunable elements within the FEM. Additionally, the inference model can be distributed across various microprocessors within the FEM or the BBP. The size of the distributed inference model can be determined based on the size and power of the corresponding associated microprocessor. Claims 7 pages Description 20 pages Drawings 41 pages CN 121620873 A 2026.03.06 CN 1 21 62 08 73 A 1. A transceiver comprising: a front-end module (FEM) comprising:A bus interface configured to couple to a communication bus for receiving inference model settings from a baseband processor (BBP) or application processor (AP); a plurality of tunable elements, each having an associated control register; a first model microprocessor including a first portion of the inference model, configured to write settings to at least one of the associated control registers based on the inference model settings from the BBP, wherein at least a second of the associated control registers is configured to be written; and a plurality of detectors configured to sense operating conditions and report measurements related to the operating conditions to the first model microprocessor. 2. The transceiver of claim 1, further comprising: the BBP, the BBP including a second model microprocessor configured to use a second portion of the inference model. 3. The transceiver of claim 2, wherein the first portion of the inference model is computationally less powerful than the second portion of the inference model. 4. The transceiver of claim 1, further comprising a power management integrated circuit (PMIC), the PMIC including: a PMIC bus interface configured to be coupled to the communication bus; and an adjustable element configured to adjust based on an output from the inference model. 5. The transceiver of claim 4, wherein the PMIC further includes a PMIC model microprocessor including a PMIC portion of the inference model, and the adjustable element is configured to adjust based on an output from the PMIC portion of the inference model. 6. The transceiver of claim 4, wherein the adjustable element is configured to adjust based on an output received from the inference model via the communication bus. 7. The transceiver of claim 2, further comprising a second FEM coupled to the communication bus. 8. The transceiver of claim 7, wherein the second FEM is configured to receive an output from a second portion of the inference model via the communication bus. 9. The transceiver of claim 7, wherein the second FEM includes a third model microprocessor and is configured to use a third portion of the inference model with the third model microprocessor. 10. The transceiver of claim 1, wherein the model microprocessor is configured to generate an interpolation setting using the first model microprocessor based on information received from the BBP. 11. The transceiver of claim 1, further comprising beamforming circuitry coupled to the communication bus. 12. The transceiver of claim 11, wherein the beamforming circuitry includes a second model microprocessor, wherein...A second model microprocessor is configured to operate together with a second portion of the inference model. 13. A wireless communication device (WCD) comprising: a communication bus; a front-end module (FEM) coupled to the communication bus, the FEM including a setting register and adjustable elements set by the setting register; a baseband processor (BBP) coupled to the communication bus; an application processor (AP) coupled to the communication bus; and an inference model distributed among at least two of the FEM, the BBP, and the AP, wherein the inference model is configured to operate on an associated model microprocessor and is configured to write settings to the setting register in the FEM. 14. The WCD of claim 13, further comprising a power management integrated circuit (PMIC), wherein the inference model is at least partially distributed to the PMIC. 15. A method for controlling an adjustable element in a front-end module (FEM), comprising: receiving first information from a first portion of an inference model via a communication bus at the FEM; generating second information using a second portion of the inference model in a model microprocessor within the FEM; writing settings into a setting register in the FEM based on the first information and the second information; and adjusting the tunable element in the FEM based on the setting register. 16. The method of claim 15, further comprising generating the first information at a baseband processor. 17. The method of claim 15, further comprising generating the first information at an application processor. 18. The method of claim 15, wherein generating additional information includes generating different information relative to the first information. 19. The method of claim 15, further comprising sending third information to a power management integrated circuit (PMIC) via the communication bus, wherein the third information is also derived from the first portion of the inference model. 20. A front-end module (FEM) comprising: a plurality of tunable elements, each tunable element having an associated control register; and a model microcontroller including an inference model, the model microcontroller being configured to write settings into each of the associated control registers based on reported operating conditions. 21. The FEM of claim 20, further comprising a plurality of detectors configured to sense operating conditions and report measurements associated with the operating conditions to the model microcontroller. 22. The FEM of claim 20, wherein the plurality of tunable elements includes bias circuitry for a power amplifier.23. The FEM of claim 20, wherein the plurality of tunable elements includes load line circuitry. 24. The FEM of claim 20, wherein the model microcontroller is further configured to receive baseband information from a baseband processor (BBP) via a communication bus. 25. The FEM of claim 24, wherein the baseband information includes at least one of modulation type, bandwidth, and power level. 26. The FEM of claim 24, wherein the baseband information includes at least one of bit error rate (BER), average power ratio (APR), and maximum power reduction (MPR). 27. The FEM of claim 21, wherein the plurality of detectors includes a temperature sensor. 28. The FEM of claim 21, wherein the plurality of detectors includes a local power supply voltage sensor. 29. The FEM of claim 20, wherein the model microcontroller is further configured to receive inference model patches from a remote server. 30. A baseband processor (BBP) comprising: a bus interface configured to be coupled to a front-end module (FEM) via a communication bus; and a model microcontroller configured to: use baseband information with an inference model to generate settings of control registers in the FEM; and transmit the settings to the FEM via the bus interface. 31. The BBP of claim 30, wherein the model microcontroller is further configured to: receive FEM information from the FEM via the bus interface; and generate the settings of the control registers in the FEM based at least in part on the FEM information. 32. The BBP of claim 30, wherein the baseband information includes at least one of modulation type, bit error rate (BER), power level, bandwidth, and frequency band. 33. The BBP of claim 31, wherein the FEM information includes at least one of temperature, local power supply voltage, detected interceptors, power level, and voltage standing wave ratio (VSWR). 34. A method for creating an inference model for use by a model microcontroller in a transceiver, the method comprising: measuring an output of the transceiver; linking the output to an input of the transceiver to assemble a training dataset; providing the training dataset to an artificial intelligence module to generate possible inference models; evaluating the possible inference models with a performance check; adjusting the training dataset if the performance check fails; and deploying the possible inference models to the transceiver if the performance check passes. 35. The method of claim 34, wherein evaluating the possible inference models includes testing performance using the input of the transceiver and adjusting tunable elements in the transceiver based on the output of the possible inference models.36. The method of claim 34, further comprising using static adjustment to control some elements in the transceiver. 37. A front-end module (FEM) comprising: a plurality of tunable elements, each tunable element having an associated control register; and a model microcontroller including and running an inference model, the model microcontroller being configured to output reported operating conditions based on the inference model and write settings to each of the associated control registers. 38. The FEM of claim 37, further comprising a plurality of detectors configured to sense operating conditions and report measurements related to the operating conditions to the model microcontroller. 39. The FEM of claim 37, wherein the plurality of tunable elements includes bias circuitry for a power amplifier. 40. The FEM of claim 37, wherein the plurality of tunable elements includes load line circuitry. 41. The FEM of claim 37, wherein the model microcontroller is further configured to receive baseband information from a baseband processor (BBP) via a communication bus. 42. The FEM of claim 41, wherein the baseband information includes at least one of modulation type, bandwidth, and power level. 43. The FEM of claim 41, wherein the baseband information includes at least one of bit error rate (BER), average power ratio (APR), and maximum power reduction (MPR). 44. The FEM of claim 38, wherein the plurality of detectors includes a temperature sensor. 45. The FEM of claim 38, wherein the plurality of detectors includes a local power supply voltage sensor. 46. The FEM of claim 37, wherein the model microcontroller is further configured to receive inference model patches from a remote server. Claims 3 / 7 Page 4 CN 121620873 A 47. A baseband processor (BBP) comprising: a bus interface configured to be coupled to a front-end module (FEM) via a communication bus; and a modem configured to: use baseband information with an inference model to generate settings of control registers in the FEM; and transmit the settings to the FEM via the bus interface. 48. The BBP of claim 47, wherein the modem is further configured to: receive FEM information from the FEM via the bus interface; and generate settings for the control registers in the FEM. 49. An application processor (AP) comprising: a bus interface configured to be coupled to a front-end module (FEM) via a communication bus; and a processor configured to: use baseband information with an inference model to generate settings for control registers in the FEM; and transmit the settings to the FEM via the bus interface.50. The AP of claim 49, wherein the processor is further configured to: receive FEM information from the FEM via the bus interface; and generate settings for the control register in the FEM. 51. The AP of claim 49, wherein the FEM information includes at least one of temperature, local power supply voltage, detected interceptors, power level, and voltage standing wave ratio (VSWR). 52. A method of creating an inference model for use by a modem, the method comprising: measuring the output of a front-end module (FEM); linking the output to an input of the modem to assemble a training dataset; providing the training dataset to an artificial intelligence module to generate a possible inference model; evaluating the possible inference model with a performance check; adjusting the training dataset when the performance check fails; and deploying the possible inference model to a baseband processor (BBP), FEM, or application processor (AP) when the performance check passes. 53. A method for creating an inference model for use in a laboratory environment without a modem, the method comprising: measuring the output of a front-end module (FEM); linking the output to inputs of laboratory equipment and a server to assemble a training dataset; feeding the training dataset to an artificial intelligence module to generate possible inference models; evaluating the possible inference models with a performance check; adjusting the training dataset when the performance check fails; and deploying the possible inference models to a baseband processor (BBP), FEM, or application processor (AP) when the performance check passes. 54. The method of claim 52 or 53, wherein evaluating the possible inference models includes testing performance using inputs to the FEM and adjusting tunable elements in the FEM based on the outputs of the possible inference models. 55. A front-end module (FEM) comprising: a plurality of tunable elements, each tunable element having an associated control register; a model microcontroller including an inference model, the model microcontroller being configured to write settings into each of the associated control registers based on reported operating conditions; and a plurality of detectors configured to sense operating conditions and report measurements related to the operating conditions to the model microcontroller; wherein the model microcontroller is further configured to collect information about the operating conditions and settings and provide the information to control circuitry for storage in memory and transmission to a remote location. 56. The FEM of claim 55, wherein the plurality of tunable elements includes bias circuitry for a power amplifier. 57. The FEM of claim 55, wherein the plurality of tunable elements includes load line circuitry.58. The FEM of claim 55, wherein the model microcontroller is further configured to receive baseband information related to operating conditions from a baseband processor (BBP) via a communication bus. 59. The FEM of claim 55, wherein the plurality of detectors includes a temperature sensor. 60. The FEM of claim 55, wherein the plurality of detectors includes a local power supply voltage sensor. 61. The FEM of claim 55, wherein the model microcontroller is further configured to receive an inference model patch from a remote server. 62. The FEM of claim 61, wherein the inference model patch is at least partially based on information collected by the model microcontroller. 63. A baseband processor (BBP) comprising: a bus interface configured to be coupled to a front-end module (FEM) via a communication bus; and a model microcontroller configured to: use baseband information with an inference model to generate settings of control registers in the FEM; and send the settings to the FEM via the bus interface; collect information about operating conditions, the settings, and outputs derived from the settings; and provide the information to control circuitry for storage in memory and transmission to a remote location. 64. The BBP of claim 63, wherein the model microcontroller is further configured to: receive FEM information from the FEM via the bus interface; and generate the settings of the control register in the FEM based at least in part on the FEM information. 65. The BBP of claim 64, wherein the information regarding the output is based at least in part on the FEM information. 66. A wireless communication device (WCD) comprising: a transceiver including: a communication bus; a front-end module (FEM) coupled to the communication bus, the FEM including: a plurality of tunable elements; and a plurality of sensors configured to provide information about operating conditions; a baseband processor (BBP) coupled to the communication bus; an application processor (AP) coupled to the BBP; and a model microcontroller located in one of the FEM, the BBP, or the AP, the model microcontroller including an inference model configured to generate settings of control registers in the FEM based on reported operating conditions; a memory; and control circuitry coupled to the memory and communicatively coupled to the inference model, the control circuitry being configured to: collect information about operating conditions and settings; store the information in the memory; and transmit the information to a remote location.67. The WCD of claim 66, wherein the control circuitry is embedded in the application processor. 68. The WCD of claim 66, wherein the control circuitry is configured to transmit information in response to an information quantity exceeding a threshold. 69. The WCD of claim 66, wherein the control circuitry is configured to transmit information in response to a polling query from the remote location. 70. A method for updating an inference model for use by a model microcontroller in a transceiver, the method comprising: creating an initial inference model using laboratory measurements of a front-end module (FEM); receiving information from a plurality of FEMs deployed in a wireless communication device (WCD); and retraining a version of the initial inference model using the information from the plurality of FEMs. 71. The method of claim 70, further comprising updating the initial inference model based on information from a combination of a baseband processor (BBP) and the FEM in a laboratory setting. 72. The method of claim 70, further comprising sending an updated version of the inference model to the deployed WCD. 73. A baseband processor (BBP) comprising: a communication bus configured to communicate with at least a front-end module (FEM) having programmable registers therein; and control circuitry coupled to the communication bus and configured to: request a write operation to the programmable registers in the FEM via an FEM software driver; receive an option palette of register bundles from the FEM software driver, wherein each of the option palettes of the register bundles is optimized for different operating conditions; and select a register bundle from the option palettes based on operating conditions known to the control circuitry. 74. The BBP of claim 73, wherein the FEM software driver includes a programming abstraction layer (PAL) configured to interface between an inference model in the FEM software driver and the control circuitry. 75. The BBP of claim 73, wherein the FEM software driver is external to the BBP. 76. The BBP of claim 74, wherein the inference model is programmed to consider multidimensional operating conditions and select register settings from a multidimensional lookup table (LUT). 77. The BBP of claim 73, wherein the FEM software driver is further configured to write to the programmable register based on the register bundle selected by the control circuitry. 78. A baseband processor (BBP) comprising: a communication bus configured to communicate with at least a front-end module (FEM) having programmable registers therein; and control circuitry coupled to the communication bus and configured to: request a write operation to the programmable register in the FEM via an FEM software driver, wherein the request for the write operation includes information about operating conditions; and a rightClaim 6 / 7, page 7, CN 121620873, A: Receives a register bundle derived from the inference model based on the information regarding operating conditions from the FEM software driver; and writes to the programmable register based on the register bundle. 79. The BBP of claim 78, further comprising a programming abstraction layer (PAL) for interfacing between the inference model and the control circuitry. 80. The BBP of claim 78, wherein the operating conditions include one or more conditions selected from the group consisting of: operating frequency band, communication generation, modulation signal type, modulation bandwidth, modulation backoff power ratio, MPR, and transmit and receive carrier aggregation configuration. Claims 7 / 7 Page 8 CN 121620873 A Inference Model for Optimizing a Front-End Module (FEM) in a Wireless Communication Device

[0001] Priority Claim

[0002] This application claims priority to U.S. Provisional Patent Application Serial No. 63 / 472,217, filed June 9, 2023, entitled “SYSTEMS AND METHODS FOR OPTIMIZING A FRONT-END MODULE (FEM) IN A WIRELESS MOBILE DEVICE”, the entire contents of which are incorporated herein by reference.

[0003] This application also claims priority to U.S. Provisional Patent Application Serial No. 63 / 507,380, filed June 9, 2023, entitled “DISTRIBUTED BIG-SMALL SYSTEM WITH MULTIPLE EDGE 1A DL / ML MODELS DRIVEN BY LOCAL FEM EVENTS TO RESPOND TO ENVIRONMENT CONDITIONS IMPACT ON FEM SETTINGS,” the entire contents of which are incorporated herein by reference.

[0004] This application also claims priority to U.S. Provisional Patent Application Serial No. 63 / 507,376, filed June 9, 2023, entitled “SEQUENTIAL MULTI-STEP MODEM 1A DL / ML MODEL TRAINING USING FEM, BASEBAND AND USER GENERATED DATASETS AND CALIBRATION DATA,” the entire contents of which are incorporated herein by reference.

[0005] This application also claims to be filed on September 20, 2023, entitled “SYSTEMS AND METHODS FOR ITERATIVELY OPTIMIZING”.

[0006] This application also claims priority to U.S. Provisional Patent Application Serial No. 63 / 539,361, entitled “A FRONT-END MODULE (FEM) IN A WIRELESS COMMUNICATION DEVICE,” the entire contents of which are incorporated herein by reference.

[0007] This application also claims priority to U.S. Provisional Patent Application Serial No. 63 / 539,367, filed September 20, 2023, entitled “DISTRIBUTED INFERENCE MODEL FOR A FRONT-END MODULE (FEM) IN A WIRELESS COMMUNICATION DEVICE,” the entire contents of which are incorporated herein by reference. Priority is claimed in U.S. Provisional Patent Application Serial No. 63 / 507,351 for “MODEL”, the entire contents of which are incorporated herein by reference. Technical Field

[0008] The present disclosure relates generally to front-end modules (FEMs) in wireless communication devices and methods for optimizing operation under different operating conditions. Background Art

[0009] Computing devices are ubiquitous in modern society, and more specifically, mobile communication devices have become increasingly common. The prevalence of these mobile communication devices is partly due to the numerous functions now available on such devices. The increased processing power in such devices means that mobile communication devices have evolved from simple communication tools into sophisticated mobile multimedia centers, thus enhancing the user experience. With the proliferation of available functions in such devices, the pressure to find ways to reduce power consumption has also increased. Wireless mobile communication devices rely on RF (radio frequency) front-end modules (FEMs) and RF transceivers to transmit and receive wireless signals that enable or facilitate the use of the functions available on such devices. RF FEMs include power amplifiers and other circuitry to regulate the signal used for transmission in one direction and to regulate the signal used for transmission in another direction. The incoming signal is processed by baseband in the direction of the signal. The efficient operation of the FEM is unidirectional, which can reduce power consumption. Therefore, there is room for innovation in optimizing the efficient operation of the FEM. Summary of the Invention

[0010] The aspects disclosed in the detailed embodiments include methods for optimizing the front-end module (FEM) in a wireless communication device.Distributed inference model. In particular, the various tunable elements within the FEM can have optimal settings based on operating conditions. Optimal settings can be found by creating an inference model (e.g., through machine learning or deep learning artificial intelligence (AI) techniques). The inference model can then be associated with a microprocessor in the transceiver. The model will use the current operating conditions based on data from the baseband processor (BBP) and the FEM as input and calculate the appropriate settings for the tunable elements within the FEM.

[0011] Additionally, the inference model can be distributed across various microprocessors within the FEM or BBP. The size of the distributed inference model can be determined based on the size and power of the corresponding associated microprocessor. In this way, no single device bears the entire burden of processing the inference model. This can result in less traffic on the communication bus and a smaller overall device size. Furthermore, such optimization in the FEM can lead to power savings and / or an improved user experience.

[0012] The aspects disclosed in the detailed embodiments also include systems and methods for iteratively optimizing the FEM in the WCD. In particular, the various tunable elements within the FEM can have optimal settings based on operating conditions. The optimal settings can be found by creating an inference model (e.g., through machine learning or deep learning AI techniques). The inference model is then associated with a microprocessor in the transceiver. The model will use current operating conditions based on data from the BBP and FEM as input and calculate the appropriate settings for adjustable elements within the FEM. Additionally, the FEM can provide measurements to a remote server, which will then be used as part of a training dataset for future learning processes and to update the inference model used in the FEM. Using such an inference model to calculate the settings of the FEM allows for extensive flexibility and opportunities for post-market optimization of the FEM. Furthermore, such optimization can lead to power savings and / or improved user experience.

[0013] In this regard, in one aspect, a transceiver is disclosed. The transceiver includes an FEM that includes a bus interface configured to be coupled to a communication bus for receiving inference model settings from a BBP or application processor (AP). The FEM also includes a plurality of tunable elements, each having an associated control register and a model microprocessor including a first portion of an inference model. Based on inference model settings from the BBP, the first model microprocessor is configured to write settings into at least one of the associated control registers, and at least a second of the associated control registers is configured to be written. The FEM also includes a plurality of detectors configured to sense operating conditions and report measurements related to the operating conditions to the model microprocessor.

[0014] In another aspect, a wireless communication device (WCD) is disclosed. The wireless communication device includes a communication bus and coupling.The FEM is connected to a communication bus, and the FEM includes a setting register and an adjustable element set by the setting register. The wireless communication device also includes a BBP coupled to the communication bus and an AP coupled to the communication bus. The wireless communication device also includes an inference model distributed among at least two of the FEM, BBP, and AP, wherein the inference model is configured to operate on an associated model microprocessor and is configured to write settings into the setting register in the FEM.

[0015] In another aspect, a method for controlling an adjustable element in an FEM is disclosed. The method includes receiving first information from a first portion of an inference model at the FEM via a communication bus, and generating second information using a second portion of the inference model in a model microprocessor in the FEM. The method also includes writing settings into the setting register in the FEM based on the first and second information, and adjusting the tunable element in the FEM based on the setting register.

[0016] In this regard, in one aspect, an FEM is disclosed. The FEM includes multiple tunable elements, each having an associated control register and a model microcontroller including an inference model. The model microcontroller is configured to write settings into each of the associated control registers based on the operating conditions reported on page 2 / 20 of the specification, 10 CN 121620873 A.

[0017] In another aspect, a BBP is disclosed. The BBP includes a bus interface configured to couple to the FEM via a communication bus and a model microcontroller. The model microcontroller is configured to use baseband information with the inference model to generate settings of the control registers in the FEM and to send the settings to the FEM via the bus interface.

[0018] In another aspect, a method for creating an inference model for use by a model microcontroller in a transceiver is disclosed. The method includes measuring the output of the transceiver, linking the output to the input of the transceiver to assemble a training dataset, and providing the training dataset to an artificial intelligence module to generate possible inference models. The method also includes evaluating the possible inference models with a performance check, adjusting the training dataset when the performance check fails, and deploying the possible inference models to the transceiver when the performance check passes.

[0019] In another aspect, an FEM is disclosed. The FEM includes a plurality of tunable elements, each tunable element having an associated control register and a model microcontroller that includes and runs an inference model. The model microcontroller is configured to output operating conditions based on the inference model and write settings into each associated control register.

[0020] In another aspect, a BBP is disclosed. The BBP includes a bus interface configured to be coupled to the FEM via a communication bus. The BBP also includes a modem configured to use baseband communication with the inference model.Information is used to generate settings for control registers in the FEM and send the settings to the FEM via a bus interface.

[0021] In another aspect, an AP is disclosed. The AP includes a bus interface configured to be coupled to the FEM via a communication bus; and a processor configured to use baseband information with an inference model to generate settings for control registers in the FEM and send the settings to the FEM via the bus interface.

[0022] In another aspect, a method for creating an inference model for use by a modem is disclosed. The method includes measuring the output of the FEM, linking the output to the input of the modem to assemble a training dataset, and providing the training dataset to an artificial intelligence module to generate possible inference models. The method also includes evaluating the possible inference models with a performance check, adjusting the training dataset when the performance check fails, and deploying the possible inference models to a BBP, FEM, or AP when the performance check passes.

[0023] In another aspect, a method for creating an inference model for use in a laboratory environment without a modem. The method includes measuring the output of the FEM, linking the output to the input of laboratory equipment and a server to assemble a training dataset, and providing the training dataset to an artificial intelligence module to generate possible inference models. The method also includes evaluating possible inference models with a performance check, adjusting the training dataset when the performance check fails, and deploying the possible inference models to a BBP, FEM, or AP when the performance check passes.

[0024] In another aspect, an FEM is disclosed. The FEM includes a plurality of tunable elements, each having an associated control register and a model microcontroller including an inference model, the model microcontroller being configured to write settings into each of the associated control registers based on reported operating conditions. The FM also includes a plurality of detectors configured to sense operating conditions and report measurements related to the operating conditions to the model microcontroller, wherein the model microcontroller is also configured to collect information about the operating conditions and settings and provide the information to control circuitry for storage in memory and transmission to a remote location.

[0025] In one aspect, a BBP is disclosed. The BBP includes a bus interface configured to be coupled to the FEM via a communication bus. The BBP also includes a model microcontroller configured to use baseband information with the inference model to generate settings for control registers in the FEM, send the settings to the FEM via a bus interface, collect information about operating conditions, settings, and outputs derived from the settings, and provide the information to control circuitry for storage in memory and transmission to a remote location. Specification 3 / 20 pages 11 CN 121620873 A

[0026] In another aspect, a WCD is disclosed. A wireless communication device includes a transceiver that includes a communication bus.The FEM is coupled to a communication bus, the FEM including multiple tunable elements and multiple sensors configured to provide information about operating conditions. The wireless communication device also includes a BBP coupled to the communication bus, an AP coupled to the BBP, and a model microcontroller located in one of the FEM, BBP, or AP, the model microcontroller including an inference model configured to generate settings of control registers in the FEM based on reported operating conditions. The wireless communication device also includes a memory and control circuitry coupled to the memory and communicatively coupled to the inference model. The control circuitry is configured to collect information about operating conditions and settings, store the information in the memory, and transmit the information to a remote location.

[0027] In another aspect, a method for updating an inference model for use by a model microcontroller in a transceiver is disclosed. The method includes creating an initial inference model using laboratory measurements of the FEM, receiving information from multiple FEMs deployed in a WCD, and retraining a version of the initial inference model using information from the multiple FEMs.

[0028] In one aspect, a BBP is disclosed. The BBP includes a communication bus configured to communicate with at least a front-end module (FEM) having programmable registers therein. The BBP also includes control circuitry coupled to the communication bus and configured to request write operations to programmable registers in the FEM via an FEM software driver, and to receive a palette of register bundles from the FEM software driver, wherein each of the palettes of register bundles is optimized for different operating conditions, and to select a register bundle from the palettes based on operating conditions known to the control circuitry.

[0029] In one aspect, a BBP is disclosed. The BBP includes a communication bus configured to communicate with at least an FEM having programmable registers therein. The BBP also includes control circuitry coupled to the communication bus and configured to request write operations to programmable registers in the FEM via an FEM software driver, wherein the request for the write operation includes information about operating conditions, and to receive a register bundle derived from an inference model based on the information about the operating conditions from the FEM software driver, and to write to the programmable registers based on the register bundles.

[0030] Another aspect of this disclosure focuses on how information is provided from the inference model so that it can be written into relevant registers to modify the behavior of tunable elements in the transport chain. More specifically, a programming abstraction layer (PAL) can exist between the inference model and the operating system in a device such as a BBP or AP. The BBP or AP sends a request for a write command to the PAL, which queries the inference model and responds with a palette of options from which the BBP or AP selects based on operating criteria. This approach is particularly useful when the query source has information related to operating conditions that the inference model may not be able to access. (See accompanying drawings)

[0031] FIG1 is a block diagram of a conventional transceiver having a front-end module (FEM) and a baseband processor (BBP) whose settings can be adjusted based on operating conditions;

[0032] FIG2A is a block diagram of a transmission chain of a transceiver from FIG1 having two adjustable items that can be adjusted based on operating conditions;

[0033] FIG2B is a lookup table (LUT) that can store the values ​​of the adjustable items of FIG2A;

[0034] FIG3 is a block diagram of a conventional transceiver having an FEM and a BBP and many items that can be adjusted based on operating conditions;

[0035] FIG4A is a block diagram of a transceiver having an inference model in a BBP according to one aspect of the present disclosure;

[0036] FIG4B is a block diagram of a transceiver having an inference model in an FEM according to one aspect of the present disclosure;

[0037] FIG5 is a flowchart showing how to create an inference model for use in a transceiver;

[0038] FIG6 is a flowchart showing how the inference model is then used in the transceiver;

[0039] Figure 7A is a block diagram of a training environment according to an exemplary aspect of this disclosure, which relies solely on information from the FEM to construct a training dataset;

[0040] Figure 7B is a block diagram of a training environment according to an exemplary aspect of this disclosure, which uses information from both the BBP and the FEM to construct a training dataset;

[0041] Figure 8A is a block diagram of a transceiver according to an exemplary aspect of this disclosure, which has a model microprocessor using an inference model placed in the BBP;

[0042] Figure 8B is a block diagram of a transceiver according to an exemplary aspect of this disclosure, which has a model microprocessor using an inference model placed in the FEM;

[0043] Figure 8C is a block diagram of a transceiver according to an exemplary aspect of this disclosure, which has a model microprocessor using an inference model placed in an external processor;

[0044] Figure 9 is a more detailed block diagram of an FEM according to an aspect of this disclosure, which has adjustable elements that can be tuned based on settings provided by the inference model;

[0045] Figure 10 is a block diagram of a wireless communication device having multiple FEM components according to an exemplary aspect of the present disclosure, all of which can be controlled using an inference model;

[0046] Figure 11 is a block diagram of a transceiver according to an exemplary aspect of the present disclosure, wherein all tunable elements are controlled by an inference model;

[0047] Figure 12 is a block diagram of a transceiver according to an exemplary aspect of the present disclosure, wherein some of the tunable elements are controlled by a static LUT, and other tunable elements are dynamically controlled by an inference model;

[0048] Figure 13 is a block diagram of a transceiver using carrier aggregation according to an exemplary aspect of the present disclosure, which creates multiple interceptors whose performance is optimized by an inference model;

[0049] Figure 14 is a block diagram of a transceiver with beam steering and a multiple-input multiple-output (MIMO) antenna array according to an exemplary aspect of the present disclosure, the performance of which is optimized by an inference model;

[0050] Figure 15 is a block diagram of a mobile terminal according to the present disclosure, which may include the inference models of Figures 4A to 14;

[0051] Figure 16 is a flowchart illustrating an iterative process for training the inference model of the present disclosure and subsequently redeploying the updated inference model to a communication device;

[0052] Figure 17A is a block diagram of a first inference model that can benefit from the iterative updates of the present disclosure, wherein the wireless communication device does not have artificial intelligence;

[0053] Figure 17B is a block diagram of a second inference model that can benefit from the iterative updates of the present disclosure implemented in software within the wireless communication device;

[0054] Figure 17C is a block diagram of a third inference model that can benefit from the iterative updates of the present disclosure implemented in hardware within the wireless communication device;

[0055] Figure 18 is a block diagram of a system that collects information from multiple deployed communication devices, retrains the inference model based on this information, and then redistributes the updated inference model to multiple communication devices as well as to the inference model provided in newly sold devices;

[0056] Figure 19 is a block diagram illustrating how the training set is pruned so that the size of the final product inference model is designed to fit smaller computing devices;

[0057] Figure 20 is a block diagram illustrating an inference model distributed across multiple chips in an FEM;

[0058] Figure 21 is a block diagram illustrating an inference model distributed across multiple chips in an FEM and in an application processor;

[0059] Figure 22 is a block diagram illustrating a transceiver with a distributed inference model, where primary processing occurs in a BBP and is differentially adjusted by the inference model in the FEM;

[0060] Figure 23 is a block diagram of a transceiver where the power management integrated circuit (PMIC) is controlled by the distributed inference model;

[0061] Figure 24 is a block diagram of a transceiver, wherein the PMIC includes a portion of the distributed inference model;

[0062] Figure 25 is a block diagram of a transceiver and an application processor (AP), wherein the inference model is distributed between the BPP and the AP, simultaneously controlling multiple FEMs;

[0063] Figure 26 is a block diagram of a transceiver and an AP, wherein the inference model is distributed between the BPP, the AP, and multiple FEMs;

[0064] Figure 27 is a block diagram of a transceiver with multiple FEMs and multiple PMICs, wherein the inference model is distributed across multiple chips in the transceiver;

[0065] Figure 28 is a block diagram of a transceiver and an AP, wherein the inference model is distributed across FEMs and the AP;

[0066] Figure 29 is a block diagram illustrating that the training set for an FEM inference model can be based on FEM measurements only;

[0067] Figure 30 is a block diagram illustrating that the training set of the inference model in the AP can be based on measurements of the BBP, AP, and / or FEM;

[0068] Figure 31 is a block diagram of a beamformer in a millimeter-wave (mmWave) FEM that can be used with the transceiver of the present disclosure, wherein the inference model is distributed in the beamformer; and

[0069] Figure 32 is a block diagram of a wireless communication device having multiple millimeter-wave FEMs and a distributed inference model;

[0070] Figure 33 is a block diagram of an FEM driver responding to a write request from the BBP according to aspects of the present disclosure, wherein the BBP provides information about operating conditions from which the FEM driver can select a beam register setting from a palette;

[0071] Figure 34 is a block diagram of an FEM driver responding to a write request from the BBP according to aspects of the present disclosure, wherein the BBP provides information about operating conditions from which the FEM driver can select a beam register setting from a multidimensional palette;

[0072] Figure 35 is a block diagram of an FEM driver responding to a write request from a BBP, wherein the BBP does not provide information about operating conditions, but the BBP can select a bundle from the provided palette based on information about the palette known to the BBP;

[0073] Figure 36 is a block diagram of an FEM driver responding to a write request from a BBP, wherein the BBP does not provide information about operating conditions, and the FEM driver provides a palette to the BBP for selection; and

[0074] Figure 37 is a block diagram illustrating a programming abstraction layer that can facilitate the interface with the inference model. Detailed Description

[0075] The embodiments set forth below represent the information necessary to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of this disclosure and will understand the application of these concepts not specifically set forth herein. It should be understood that these concepts and applications fall within the scope of this disclosure and the appended claims.

[0076] It should be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish different elements. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0077] It should be understood that when an element such as a layer, region, or substrate is referred to as "on another element" or "extending to another element," it may be directly on or directly extending to the other element, or an intermediary element may also be present. In contrast...Under these circumstances, when an element is referred to as "directly on another element" or "directly extending to another element," there is no intermediary element. (See specification 6 / 20, page 14, CN 121620873 A). Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as "above another element" or "extending above another element," it may be directly above or extending directly above another element, or an intermediary element may be present. In contrast, when an element is referred to as "directly on another element" or "extending directly above another element," there is no intermediary element. It will also be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to another element, or an intermediary element may be present. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, there is no intermediary element.

[0078] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe the relationship between one element, layer or region and another element, layer or region illustrated in the figures. It should be understood that these terms and those discussed above are intended to include different orientations of the device other than those depicted in the figures.

[0079] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” and / or “containing” as used herein specify the presence of the said feature, integral, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0080] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that, unless explicitly defined herein, the terms used herein should be interpreted as having the meaning consistent with their meaning in the context of this specification and related art, and will not be interpreted in an idealized or overly formal sense.

[0081] As a note on the initial naming, it should be understood that certain categories of linguistic purists may distinguish between a baseband processor (BBP), a transceiver (which may be an intermediate frequency processing circuit or chip), and a front-end module (FEM). However, other technical publications define a transceiver as including everything from the BBP to the antenna and including the BBP to the antenna. An FEM may be defined differently as everything between the antenna and the digital BBP; only transmit / receive switches, filters, and duplexers for band switching; or switching elements with amplifiers. In view of this different usage, this disclosure specifically defines a transceiver as a BBP, any intermediate frequency processing (IF) chip, etc.The circuitry and FEM (basically everything in the transmission direction up to the BBP of the antenna or in the reception direction after the antenna through the BBP). While this definition may offend some purists, it is provided to avoid confusion. Similarly, the FEM is defined as the power amplifiers, switching elements, and filters located between the antenna and any IF processing circuitry system. In relevant contexts, to distinguish between the use of "transceiver" to refer to the IF circuitry and the entire path up to the antenna, the terms "transceiver circuitry" and "transceiver chain" are used respectively. It should be understood that in some aspects, all components may be housed in a single board (i.e., multiple integrated circuits, surface mount elements, etc.) or on separate components.

[0082] Additionally, the extent to which the term "about" is used in the claims is defined herein as within five percent (5%).

[0083] The aspects disclosed in the detailed embodiments include a distributed inference model for optimizing the FEM in a wireless communication device. In particular, the various tunable elements within the FEM may have optimal settings based on operating conditions. The optimal settings can be found by creating an inference model (e.g., through machine learning or deep learning AI techniques). The inference model can then be associated with a microprocessor in the transceiver. This model will use current operating conditions based on data from the baseband processor (BBP) and the FEM as input and calculate appropriate settings for the tunable elements within the FEM.

[0084] Additionally, the inference model can be distributed across various microprocessors within the FEM or BBP. The size of the distributed inference model can be determined based on the size and power of the corresponding associated microprocessor. In this way, no single device bears the entire burden of processing the inference model. This can result in less traffic on the communication bus and a smaller overall device size. (Specification 7 / 20 pages 15 CN 121620873 A) Furthermore, such optimization in the FEM can lead to power savings and / or an improved user experience.

[0085] The aspects disclosed in the detailed embodiments include systems and methods for optimizing the FEM in a wireless mobile device. In particular, various tunable elements within the FEM can have optimal settings based on operating conditions. Optimal settings can be found by creating an inference model (e.g., through machine learning or deep learning AI techniques). The inference model is then associated with a microprocessor in the transceiver. The model will use current operating conditions based on data from BBP and FEM as input and calculate the appropriate settings for adjustable elements within the FEM. Additionally, the FEM can provide measurements to a remote server, which will then be used as part of a training dataset for future learning processes. Using such an inference model to calculate the FEM settings allows for extensive flexibility and opportunities for post-sales optimization of the FEM. Furthermore, such optimization can lead to power savings and / or improved user experience.

[0086] The aspects disclosed in the specific embodiments include systems and methods for iteratively optimizing the FEM in a wireless communication device. In particular, various tunable elements within the FEM can have optimal settings based on operating conditions. The optimal settings can be found by creating an inference model (e.g., through machine learning or deep learning AI techniques). The inference model is then associated with a microprocessor in the transceiver. The model will use current operating conditions based on data from the BBP and FEM as input and calculate appropriate settings for the tunable elements within the FEM. Additionally, the FEM can provide measurements to a remote server, which will then be used as part of a training dataset for future learning processes and to update the inference model used in the FEM. Using such an inference model to calculate the settings of the FEM allows for extensive flexibility and opportunities for post-market optimization of the FEM. Furthermore, such optimization can lead to power savings and / or improved user experience.

[0087] Another aspect of this disclosure focuses on how information is provided from the inference model such that it can be written into relevant registers to modify the behavior of tunable elements in the transmission chain. More specifically, a programming abstraction layer (PAL) can exist between the inference model and the operating system in the device, such as a BBP or AP. The BBP or AP sends a request for a write command to the PAL, which queries the inference model and responds with a palette of options from which the BBP or AP selects based on operational criteria. This approach is particularly useful when the query source has information related to operational conditions that may prevent the inference model from being used.

[0088] Before elaborating on exemplary aspects of this disclosure, an overview of a conventional approach for providing adjustments based on operational conditions is provided with reference to Figures 1 through 3. A broad range of aspects of a machine learning process using an resulting inference model is discussed below with reference to Figures 4 through 6, with additional details and variations explored in subsequent figures. An iterative process for improving an inference model according to various aspects of this disclosure is explored below with reference to Figure 16. A distributed inference model is discussed below with reference to Figure 20.

[0089] In this regard, Figure 1 is a block diagram of a conventional transceiver 100 with BBP 102 and FEM 104. The IF processing circuitry is omitted for clarity. Similarly, while this use of the transceiver may not be consistent with some published definitions, it is consistent with the definitions provided above. FEM 104 is coupled to antenna 106, which in some cases may be an antenna array. FEM 104 includes a transmission chain 108 and a receiver chain 110. Transmission chain 108 may include driver amplifier 112 and output amplifier 114, as well as other circuitry such as filters, switches, etc. Additional amplifier stages (not shown) may also be present. Receiver chain 110 may include multiple low-noise amplifiers 116(1)-116(M) and other circuitry (not shown).

[0090] To maintain operational efficiency, certain “tunable” components within FEM 104 can be modified based on operating conditions. For example, as better illustrated in FIG2A, power amplifier control circuitry 200 can be coupled to power amplifier circuitry 202. More specifically, controller 204 can receive signal 206 from BBP 102 (not shown in FIG2A) via digital input / output (I / O) 208. Signal 206 may include, for example, information about power level and / or operating frequency band. Based on signal 206, controller 204 can access lookup table (LUT) 210 (better illustrated in FIG2B) to determine the bias level that will result in more efficient operation when applied to amplifiers 112, 114. Specifically, controller 204 can use bias generator circuits 212A, 212B to send bias signals to bias circuits 214A, 214B respectively, to provide selected bias to amplifiers 112, 114.

[0091] In the example of FIG2B, LUT 210 can be a two-dimensional matrix that sets the operating frequency band (Y-axis 220) relative to power (X-axis 222), where the power level is roughly divided into low, mid, and high frequency bands 224A-224C. Based on signal 206, two bits (e.g., B1, B2) are found in LUT 210 and provided to bias generator circuits 212A, 212B to generate the desired bias.

[0092] In earlier generations, such a simple two-dimensional LUT 210 was sufficient. However, the continuous evolution of wireless standards, combined with the proliferation of multiple transceiver devices with multiple tunable elements (e.g., smartphones may have cellular transceivers, WIFI transceivers, Bluetooth transceivers, infrared transceivers, etc.), greatly increases the complexity of the spectrum of tunable elements, and the complexity of LUTs increases accordingly.

[0093] As an example, FIG3 illustrates a block diagram of a conventional transceiver 300 having a BBP 302 and an FEM 304 (again, the IF circuitry is omitted for clarity). The FEM 304 can send signals to and receive signals from the BBP 302, including information about the frequency band, power level, modulation scheme, etc. (e.g., BB information). In addition, information from detectors 306(1)-306(P), including local temperature, local power supply voltage, process angle, voltage level at a specific point of the FEM 304, current level at a specific point of the FEM 304, etc. (e.g., FEM information), can be collected to further define the operating conditions in the transceiver 300. This information can be used in the multidimensional LUT 308 to provide register settings for the registers used to control the tunable elements 310(1)-310(Q). The tunable elements 310(1)-310(Q) may include bias circuitry, load lines,Switches, filters, couplers, etc.

[0094] Creating entries for a LUT 308 is a huge task. Historically, a brute-force approach was used, in which a single input variable was changed by various or a range of settings while keeping other input variables constant and measuring the output. Based on these outputs, register settings could be determined and stored in the LUT 308. After sweeping through the range of settings, another input variable was adjusted, and the process was repeated until each axis of the input had been tested relative to a reasonable number of possible values ​​on each of the other axes. For each new product, and possibly for each product update, this brute-force process could be performed from scratch. An alternative is to have a coarser resolution in the LUT 308, which can lead to inefficient operation because certain combinations of operating conditions do not have optimal register settings in the LUT 308.

[0095] This disclosure describes the use of inference models developed based on machine learning or deep learning artificial intelligence techniques to assist in optimizing operations. Inference models can be generated in a laboratory setting using a basic set of inputs and then associated with a microprocessor in a BBP or FEM, as better illustrated in Figures 4A and 4B, respectively. In this regard, Figure 4A illustrates a transceiver 400 having a BBP 402 and a FEM 404 within a mobile device. Again, it should be understood that this definition of a transceiver may be too broad, but it is consistent with the explicit definition provided above. The BBP 402 may include a microprocessor 406 loaded with an inference model. The BBP 402 can use the microprocessor 406 to dynamically compute the set of “optimal” settings for all tunable elements in the FEM 404 (e.g., elements within the transmit chain 408 or receive chain 410) for a given operating condition. In contrast, Figure 4B illustrates a transceiver 420 having a BBP 422 and a FEM 424. The FEM 424 may include a microprocessor 426 loaded with an inference model. The FEM 424 can use the microprocessor 426 to dynamically compute the set of “optimal” settings for all tunable elements in the FEM 424 (e.g., elements within the transmit chain 428 or receive chain 430) for a given operating condition.

[0096] In either case, the settings are calculated dynamically. However, some settings may also be statically adjusted based on operating conditions, and this disclosure covers such a hybrid approach of providing settings for optimal operation of the FEM.

[0097] The aspects illustrated in Figures 4A and 4B envision a single inference model located in a single device or associated with a single microprocessor. However, aspects of this disclosure consider distributed inference models that may have portions of models located in different devices and / or associated with different microprocessors. These aspects are discussed below with reference to Figure 20. Specification 9 / 20 pages 17 CN 121620873 AHowever, more context is provided before elaborating on these aspects.

[0098] Figure 5 is a flowchart illustrating a general process 500 for creating an inference model for a transceiver such as transceiver 400 or 420. Process 500 begins by defining which elements will be controlled by the inference model (e.g., which elements are dynamic and which elements are statically defined) (box 502). A series of inputs are then provided to the transceiver (box 504) (and more specifically, the FEM portion of the transceiver), and outputs based on these inputs are measured (box 506). The inputs and outputs are assembled into a training dataset (box 508). This assembly may include cleaning and labeling the dataset. The AI ​​is then trained using the training dataset (box 510). While the exact parameters of the training dataset can vary, it is conceivable that the training dataset will include input data from the BBP, such as operating band, power level, bandwidth, modulation type or generation, known interceptors (self or detected), carrier aggregation mode, modulation maximum backoff power ratio (MPR), modulation peak-to-average power ratio (PAR), etc.; data from the FEM, such as local temperature, local power supply voltage, process angle, any current FEM settings, etc.; and communication link performance data, such as bit error rate (BER), signal-to-noise ratio (SNR), etc.

[0099] In the past, a large amount of data was measured during laboratory evaluation of the FEM. In most cases, extensive scanning was performed on different adjustable settings to determine the optimal settings for a given operating condition. Most of this data was discarded, and only the “optimal” settings were saved in the LUT. In contrast, this disclosure contemplates using all data measured in the laboratory during evaluation as part of the training dataset.

[0100] It should be noted that the AI ​​can be machine learning (e.g., machine learning-dependent (e.g., using non-convolutional methods)) or deep learning (e.g., using convolutional methods). The AI ​​will output an inference model, which is then enabled (box 512) and a performance check is performed (box 514). If the inference model fails the performance check at box 514, the training dataset is adjusted (box 516), and the new dataset is used to train the AI, returning to box 510 to develop a new candidate inference model. Once the performance check passes, the model is deployed to hardware (box 518) (e.g., installed with a microprocessor in an FEM, BBP, or other external processor such as an application processor (AP). In an exemplary aspect, this deployment can be software-only, hardware-only, or a hybrid approach.

[0101] Figure 6 provides a flowchart of process 600 for developing an inference model using process 500 of Figure 5. Process 600 begins after deployment, where inputs (box 602) are received at the microprocessor associated with the inference model. These inputs may come from detectors in the FEM and / or from the BBP. The microprocessor uses the inference model to dynamically compute...The tunable element of the FEM is set up (box 604). The FEM is set up and operated (box 606). Optionally, the FEM measures the output (box 608) and reports the output data to the training station (box 610). The training station can then add the data to the training dataset and update the model (box 612). The training station can then send out patches and can use the updated model to patch the model deployed in hardware (e.g., a phone) (box 614). More details about this are provided below with reference to Figure 16.

[0102] The discussion of Figures 4A through 6 provides an accurate description of the high-level aspects of this disclosure, attempting to at least touch upon possible and / or possible variations within the material. However, for completeness, Figures 7A through 14 below are presented step-by-step using a specific arrangement of the inference model. The process of iteratively improving the inference model is discussed below with reference to Figure 16. The aspects related to the distributed inference model are discussed below with reference to Figure 20. The aspects related to the nature of the interface of the inference model are discussed below with reference to Figure 33.

[0103] In this regard, FIG7A illustrates one arrangement of block 504 of FIG5, and specifically, illustrates a case where there is little or no information from the BBP. This situation may occur when the BBP provider also sells the FEM and does not cooperate with other FEM providers to help optimize the setup. Thus, FIG7A illustrates a training environment 700 in which generator 702 provides input signal 704 to FEM 706. Input signal 704 may be the signal to be transmitted, as well as any input qualifiers such as modulation type, modulation bandwidth, peak-to-average power ratio (PAR), etc. Concurrently, FEM 706 may have registers 708 filled with candidate settings by input devices (not shown) through input interface 710 (sometimes referred to as input-output (I / O) interface). FEM 706 generates output signal 712, which may include the actual transmitted / received signal as well as signals generated by any or all detectors within FEM 706. Measurement equipment 714 can measure output signal 712. Data set 716 can receive settings, input qualifiers, measurements, and output qualifiers (e.g., noise, adjacent channel leakage ratio (ACLR), signal-to-noise and distortion ratio (SNDR), etc.). Therefore, measurements from FEM 706 can be used to extract a first dataset type without interaction or knowledge of the baseband counterpart of the radio frequency (RF) signal.

[0104] Conversely, Figure 7B illustrates a training environment 740 in which BBP 742 collaborates with FEM 744 and provides additional data to dataset 746. Specifically, BBP 742 can provide input signals, output signals, input qualifiers, and output qualifiers to dataset 746. BBP 742 can also provide candidate settings to FEM.744 is used by register 748. FEM 744 or BBP 742 can provide candidate settings to dataset 746. In addition, BBP 742 can provide more robust qualifiers, including bit error rate (BER), error vector magnitude (EVM), etc.

[0105] After constructing dataset 716 or 746, a higher power computing module (such as a dedicated AI server) is used to train the inference model. As indicated in Figure 5, multiple iterations of model training can occur until the model is acceptable. Similarly, the model can be updated using the same kind of higher power computing module based on reported data from the deployed hardware. As indicated in process 500, once the model is trained, it can be deployed to a piece of hardware where it can run and generate FEM settings based on detected operating conditions. It should be noted that although cellular devices are specifically envisioned, this disclosure is not limited thereto and can be deployed in any device including wireless transceivers (or, as explained in more detail below, multiple wireless transceivers), including but not limited to base stations, mobile terminals, set-top boxes, etc.

[0106] Depending on whether the BBP is coordinated with the FEM, the model can be deployed to either the BBP or the FEM, as shown above in Figures 4A and 4B and more in detail with reference to Figures 8A and 8B. Note that, as explained further below with reference to Figure 20, the deployment can be distributed concurrently across multiple devices. In this regard, Figure 8A illustrates a wireless mobile device 800 with a BBP 802 and an FEM 804. Optionally, an intermediate RF transceiver circuit 806 may be present (note that this usage is more consistent with some alternative definitions and is therefore described as a transceiver circuit) that upconverts the signal from baseband to intermediate frequency or downconverts the RF signal to intermediate frequency, and conditions (e.g., filters, amplifies, etc.) the intermediate frequency signal before passing the conditioned signal upstream or downstream. Alternatively, the intermediate RF transceiver circuit 806 may upconvert and downconvert between the baseband frequency and the RF frequency. BBP 802 may include a first signal processor 808 (also referred to as a modem in the figure), which operates to generate signals to be transmitted or process received signals. Additionally, BBP 802 may include a model microprocessor 810, which operates in conjunction with inference model 812 to generate register settings (FEM settings) based on operating conditions. As used herein, the term "model microprocessor" is used to refer to a microprocessor configured to work with the inference model developed by process 500. That is, it remains the processing core or other hardware capable of generating models using AI. This term does not include a piece of software analoging the microprocessor. Since most of the information used by inference model 812 comes from first signal processor 808 (e.g., BB information), therefore in BBP...The presence of a model microprocessor 810 in 802 can minimize data exchange on the digital bus 814. Although the model microprocessor 810 is shown as a different element compared to the first signal processor 808, in some respects, the first signal processor 808 may include the model microprocessor 810 (not explicitly shown). In any case, BBP 802 will transmit FEM settings on the digital bus 814 via bus interface 816. The model microprocessor 810 may also receive FEM information (FEM information) from FEM 804, which is used to help generate register settings. In an exemplary aspect, the digital bus 814 may conform to the Radio Frequency Front End (RFFE) standard described by MIPI, a copy of which is available to members at www.mipi.org. While a digital bus is explicitly contemplated, the bus may be an analog bus if desired or desired.

[0107] Continuing to refer to FIG8A, FEM 804 may include a bus interface 818 configured to couple to the digital bus 814. The settings of the FEM received via digital bus 814 are stored in register 820 and used to adjust the tunable element within the FEM 804 in the receive chain 822 or the transmit chain 824 (or both). Detector 826 can be used to collect information about the conditions of the FEM 804 (e.g., temperature, supply voltage, process angle, load voltage standing wave ratio (VSWR), etc.) and is provided to BBP 802 via digital bus 814.

[0108] In contrast, FIG8B illustrates a wireless mobile device 830 having BBP 832 and FEM 834. As described above, an optional intermediate RF transceiver circuit 806 may also be present. BBP 832 transmits BB information to FEM 834 via digital bus 814. FEM 834 may include a model microprocessor 836 that operates in conjunction with an inference model 838 to generate FEM settings based on BB information and FEM information provided directly to the model microprocessor 836 by detector 826.

[0109] Various factors can contribute to the location of the model microprocessor, including how much data must be sent across digital bus 814. In many cases, BB information is limited to a few bytes. Depending on the number of detectors 826 present, FEM information may be less than, equivalent to, or greater than BB information. BBP 802 (or 832) is typically larger and has more processing power than FEM 804 (or 834). Additionally, the computing device may have multiple FEMs for different purposes (low frequency band, mid-high frequency band, ultra-high frequency band, E-UTRA New Radio Dual Connection (ENDC), diversity receiver (DRX), antenna control system (ACS), etc.) and have pushCentralized deployment of the model may have advantages. It should be understood that there may be situations where the BBP manufacturer may not want to share operations with the FEM, which may determine the location of the model microprocessor.

[0110] Another option would be to move the model processor to a third processor outside the BBP or FEM, as better illustrated in FIG8C. Specifically, FIG8C illustrates a wireless mobile device 850 having a BBP 832 and an FEM 804. An intermediate RF transceiver circuit 806 may be present. The FEM 804 provides FEM information to the BBP 832 via a digital bus 814. The BBP 832 provides BB information and FEM information to an external processor 852. The external processor 852 may be an application processor or other microcontroller. The external processor 852 may communicate with the BBP 832 via a bus 854 and receive FEM information and BB information via a bus interface 856. The external processor 852 includes a model microprocessor 858 that works with the model 860. The model microprocessor 858 uses model 860 to generate FEM settings, which are passed to FEM 804 via BBP 832 and digital bus 814.

[0111] Various factors may lead to the use of an external processor 852. Application processors are typically the largest and most powerful processors and are usually implemented in state-of-the-art semiconductor processes. Application processors can have large computing power and memory storage and offer higher power efficiency. In addition, application processors may have dedicated computing cores developed for running AI applications such as inference models. This dedicated core can accelerate the determination of optimized FEM settings. However, using an application processor can extend the communication path and require an additional bus link from BBP to external processor 852.

[0112] Regardless of location, using a model microprocessor and inference model means generating FEM settings separately for each scenario, thereby effectively eliminating the need for LUTs. However, as noted above, some settings can be statically configured, and in such cases, LUTs may still exist. The model microprocessor may be dedicated to AI applications and have a specific AI inference model deployment environment. The local placement of the model microprocessor provides shorter communication links (e.g., via digital bus 814). The shorter distance of the local model microprocessor can result in a faster overall response time. Designers can weigh these trade-offs and position the model microprocessor according to their own design criteria.

[0113] Similarly, further details regarding how to utilize various strengths at different locations via a distributed inference model are discussed below with reference to Figure 20.

[0114] The discussion of wireless mobile devices 800, 830, and 850 features a very simplified FEM. Figure 9 illustrates in more detail an FEM 900 that can be used with the inference model of this disclosure to set up various tunable elements and includes providing FEM information for the model.The detector used by the microprocessor. Initially, the model microprocessor 902 having model 904 may exist within the FEM 900. Alternatively, the model microprocessor 902 having model 904' may be external to the FEM 900 and accessed via communication bus 906, as discussed above.

[0115] Continuing to refer to FIG9, the FEM 900 may include a bus interface 908 configured to be coupled to the communication bus 906. The bus interface 908 is broadly interpreted to cover not only the links for exchanging FEM information, BB information and / or FEM settings, but also the links for transmitting signals to be transmitted, received signals and / or other control signals. The FEM 900 may include, but is not limited to, a transmission chain 910, a receiver chain 912, a load line circuit 914, a distribution switch (DSW) 916, various filters 918(1)-918(R), an antenna switch 920, couplers 922A and 922B, a receiver load circuit 924, etc. Note that multiple transmission chains and multiple receiver chains (not shown) may exist. The transmission chain 910 may include power amplifiers 926 and 928. The receiver chain 912 may include LNAs 930 and 932. As shown, many of these components may be tunable or adjustable and may have associated registers (not shown) for controlling tuning / adjustment. FEM settings from the model microprocessor 902 (or 902') can be written into these registers, thereby controlling the operation of the FEM 900. Furthermore, many of these components include detectors 934(1)-934(S) that report operating conditions (i.e., FEM information) to the model microprocessor 902 (or 902'). Other detectors (e.g., temperature, supply voltage, process angle; not shown) may also be present and provide additional FEM information to the model microprocessor 902 (or 902'). It is conceivable which components are tunable and which have many arrangements of direct detectors, and precise arrangement is not the focus of this disclosure.

[0116] Figure 10 is a block diagram of a general portable device FEM 1000 having various types of modules 1002(1)-1002(T), including a low-noise amplifier and duplexer (LPAMID) 1002(2), a power management integrated circuit (PMIC) 1002(3), an ENDC 1002(1), etc. Each module 1002(1)-1002(T) may have adjustable elements and / or detectors that report FEM information to the model microprocessor 1004 for use by the model 1006. The FEM information can reach the model microprocessor 1004 via interface 1008. Further note that, in addition to the basic cellular transceiver, many different transceivers are envisioned.Modems, such as WIFI, Bluetooth, GPS, millimeter wave (mmWave), ultra-wideband (UWB), etc.

[0117] As noted above, a model microprocessor can use a model to determine all settings of the FEM. This is illustrated in Figure 11, where the FEM 1100 includes a model microprocessor 1102 that uses a model 1104 to generate all settings of a register 1106 that controls adjustable elements 1108(1)-1108(U). This arrangement can put a lot of stress on the inference process. It should be noted that some settings may be easily determined, even from laboratory evaluation (i.e., conventional methods). Removing these simple settings from the decision-making of the inference model may result in a smaller model that can be better optimized. Additionally, a smaller model may be generated in less time relative to the overall model.

[0118] Figure 12 illustrates an alternative possibility, wherein the FEM 1200 includes a model microprocessor 1202 that uses model 1204 to generate some settings for register 1206, with other settings stored in memory LUT 1208. Register 1206 collectively controls adjustable elements 1108(1)-1108(U).

[0119] A more challenging environment that the aspects of this disclosure can still address is the presence of higher-order carrier aggregation in the presence of multiple interceptors. Figure 13 shows a transceiver 1300 capable of using the inference model 1302 associated with model microprocessor 1304. Although shown outside of FEM 1306, as explained above, the location of model microprocessor 1304 is not central to this aspect. BBP 1308 provides demodulation information, as well as known interceptors (e.g., WIFI and Bluetooth) and other BBP information to model microprocessor 1304. Similarly, FEM 1306 provides the detected interceptor information and FEM information to model microprocessor 1304. An additional FEM 1306X may exist and this additional FEM uses the same inference model 1302.

[0120] FIG14 shows a transceiver 1400 having a BBP 1402 and an FEM 1404 having multiple antennas 1406(1)-1406(V). According to various aspects of this disclosure, model microprocessor 1408 works with model 1410 to provide FEM settings for FEM 1404. In the case of uplink multiple-input multiple-output (UL-MIMO), two or more UL transmission paths 1412 use antennas 1406(1)-1406(V) with limited isolation. Each transmission path has antennas 1406(1)-1406(V) on the way to antennas 1406(1)-1406(V).(V) Previously, dedicated output couplers 1414A and 1414B were used. Coupler signals, as direct measurements of the UL-MIMO signal, can be sent to BBP 1402, where they are converted by auxiliary demodulator 1416. The quality result signal from auxiliary demodulator 1416 can be used as part of the training data for inference model 1410. The FEM setup includes elements that can individually tune the UL-MIMO paths. Each path can have individual bias, optional load line tuning, etc. Such individual setups can be used to reduce orthogonal MIMO components and associated intermodulation devices due to antenna coupling. A similar use of inference model 1410 can be applied to the receive MIMO path. While information from BBP 1402 is useful for transceiver 1400, there may be situations where such information is unavailable and can be derived from the detectors in FEM 1404.

[0121] Referring to FIG. 15, the concepts described above can be implemented in various types of user elements 1500, such as mobile terminals, smartwatches, tablets, computers, navigation devices, access points, and similar wireless communication devices that support wireless communication (such as cellular, wireless local area network (WLAN), Bluetooth, and near field communication). User element 1500 will typically include a control system 1502, a baseband processor 1504, a transmission circuit system 1506, a receiving circuit system 1508, an antenna switching circuit system 1510, multiple antennas 1512, and a user interface circuit system 1514, which form part of a transceiver. In a non-limiting example, as an example, the control system 1502 may be a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). In this regard, the control system 1502 may at least include a microprocessor, embedded memory circuitry, and a communication bus interface. The receiving circuit system 1508 receives radio frequency signals from one or more base stations via antenna 1512 and through antenna switching circuit system 1510. The low-noise amplifier and filter of the receiving circuit system 1508 cooperate to amplify and eliminate broadband interference from the received signal for processing. Then, a down-conversion and digitization circuit system (not shown) down-converts the filtered received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter (ADC).

[0122] The baseband processor 1504 processes the digitized received signal to extract the information or data bits transmitted in the received signal. This processing typically includes demodulation, decoding, and error correction operations. The baseband processor 1504 is typically implemented in one or more digital signal processors (DSPs) and ASICs.

[0123] For transmission, the baseband processor 1504 receives from the control system 1502 information that may represent voice, data, or control information.Digital data is encoded for transmission. The encoded data is output to transmission circuitry 1506, where a digital-to-analog converter (DAC) converts the digitally encoded data into an analog signal, and a modulator modulates the analog signal onto a carrier signal at one or more desired transmission frequencies. A power amplifier amplifies the modulated carrier signal to a level suitable for transmission, and the modulated carrier signal is delivered to antenna 1512 via antenna switching circuitry 1510. Multiple antennas 1512 and replicated transmission circuitry 1506 and receiving circuitry 1508 can provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0124] Additionally, user element 1500 may include control circuitry 1550 and associated memory 1552. Aspects of this disclosure may be initiated by control circuitry 1550 and data stored in memory 1552, as better explained below.

[0125] The above discussion presents the context and possible scope of possible uses of the inference model in a wireless communication device. As noted, while the focus may be on mobile terminals such as cellular or smartphones, this disclosure is not limited to this and can be used in other wireless devices such as base stations. One of the additional advantages of the inference model is that as additional data is used to train the inference model, increasingly complex (and hopefully more accurate) models can evolve. Therefore, training the AI ​​can receive data from deployed wireless communication devices at the training site, where the data relates to operating conditions, inputs and outputs, and settings of tunable elements within the wireless communication devices. It should be noted that the more wireless communication devices contributing data, the better, as this data can be added to the dataset used to train the AI, and process 500 can iterate using a new dataset with significantly more data than the original laboratory data described on pages 14 / 20 of CN 121620873 A. Once the model passes a performance check, it can be provided back to existing deployed wireless communication devices, such as via over-the-air updates, or, in the case of base stations, by any means of providing a software patch. Furthermore, this updated model can be sent to device manufacturers so that devices subsequently sold can be sold with the updated version (rather than the original version). This process is illustrated in more detail in Figure 16.

[0126] In this regard, FIG16 illustrates process 1600, beginning with process 500 (block 1602). A wireless communication device (WCD) enters service and collects data during normal operation (block 1604) (essentially blocks 602, 604, 606, 608 of process 600). When periodically polled, or when a threshold amount of collected data is reached, the WCD transmits the data to the training facility (block 1606). More specifically, control circuitry 1550 enables the data to be collected and stored in memory 1552 during normal operation.In the middle. Control circuit 1550 may have software configured to make the WCD respond to polling from the training facility or automatically initiate data transfer (e.g., similar to automatic software updates). If needed or desired, the user may be prompted to share information. As noted above, this data collection occurs across multiple deployed WCDs. The training dataset is updated using data collected from one or more deployed WCDs (box 1608). The inference model is retrained (box 1610) and its performance is checked (box 1612). If the performance check fails, the model is retrained again at box 1610 until the performance check passes. The new model is sent to the manufacturer along with the FEM and / or BBP (box 1614). Subsequently manufactured WCDs include the updated or latest model (box 1616). Patches are provided concurrently or subsequently (or even before box 1614) to the already deployed WCDs (box 1618), and this process is repeated.

[0127] It should be noted that intermediate training steps not illustrated in Figures 15 or 16 may also exist. Specifically, the FEM can be tested independently, and the initial FEM-only dataset is used to train the model. After the FEM has been integrated into the device and the completed components have been lab-tested, the prototype model can be updated. The new dataset can then be used to retrain the model. Preliminary full-device testing can then be performed, and the new data can be used to retrain the model, all prior to device deployment.

[0128] It should be noted that the model can also be deployed in multiple ways. In the first exemplary aspect, the model is not actually deployed. Instead, the model is used to create a static LUT 1702, which is then deployed with the WCD 1700, as better illustrated in Figure 17A. The settings in the LUT 1702 are used to control the tunable elements in the BBP 1704 and FEM 1706. As previously stated, the inference model 1708 is still created in the training environment 1710 using the dataset and lab testing, as well as subsequent updates from the deployed WCD. This arrangement imposes minimal processing penalties on WCD 1700, but offers minimal flexibility in adapting to unexpected changes in the settings within LUT 1702.

[0129] Alternatively, as shown in WCD 1720 of FIG17B, WCD 1720 may include LUT 1722 in BBP 1724 (or FEM 1726), which uses a software or firmware implementation of an inference model that generates FEM settings for each operational scenario. Similarly, training environment 1710 remains as described above.

[0130] Furthermore, as shown in WCD 1740 of FIG17C, another alternative may include a hardware implementation of an inference model that generates FEM settings for FEM 1744 and / or BBP 1746 from LUT 1742.

[0131] As a further illustration of multiple training levels and multiple information sources for the dataset, Figure 18 illustrates the first training 1800 on only the Component Lab dataset (e.g., FEM only), which can be done by the component vendor (e.g., the FEM vendor). The dataset is expanded, and the 1802 model is retrained using the Telephone OEM dataset, which can be done by the Telephone OEM and / or BBP vendor. The model created at 1802 is the model originally deployed in the first generation WCD. Data is then collected from multiple WCDs 1804(1)-1804(B) and sent back to the training facility to generate iteratively optimized model 1806. These new models are then sent back to WCDs 1804(1)-1804(B) as well as any newly manufactured WCDs.

[0132] It should be noted that training with all possible inputs and outputs may make the model too cumbersome for commercially available and current processor cores used in WCDs. Therefore, weakly correlated conditions can be identified such that they can be ignored without impairing performance. Figure 19 shows an example of a correlation matrix that can be eliminated due to weak or nonexistent correlation. It should be noted that these are only examples, and in reality, they may be more closely correlated than suggested in Figure 1900. Such pruning can be performed if a performance check fails, or as part of a conditioning dataset. Further simplification can be accomplished using quantization. This process relates to the number of bits used to describe different frequencies. If the correlation is nonlinear and highly sensitive, a larger number of bits can be used to increase the resolution of the model. For less nonlinear or less sensitive correlations, a smaller number of bits can be used.

[0133] The above discussion focuses on the existence of inference models and techniques for iteratively improving inference models. However, deploying inference models to wireless communication devices can have additional opportunities for optimized operation. Specifically, different chips within a transceiver or wireless communication device can have different processing capabilities and are therefore able to handle larger or smaller inference models. Additionally, placing the inference model at a specific location within the chipset can impose communication delays when signals are routed to the inference model and output is generated. Therefore, exemplary aspects of this disclosure envision distributing the inference model across multiple parts of a wireless communication device. Distributing the inference model in this way can reduce the load on the communication bus, reduce latency, and utilize the existing computing power of the differential elements in the wireless communication device.

[0134] In this regard, FIG20 illustrates a transceiver 2000 having a BBP 2002, an FEM 2004, and an intermediate transceiver circuit 2006. The BBP 2002 may include a modem 2008, a model microprocessor 2010, and a bus interface 2012 (also referred to in the figures).(For digital I / O; these terms may be considered synonymous), which is configured to be coupled to the communication bus 2014. The model microprocessor 2010 is generally relatively robust, especially compared to the model microprocessor 2016 in the FEM 2004 or the model microprocessor 2018 in the intermediate transceiver circuit 2006. The inference model can be distributed across the model microprocessors 2010, 2016, and 2018.

[0135] Continuing to refer to FIG20, as will be well understood, the signals to be transmitted (input signals) and received signals (output signals) can be passed between the BBP 2002, the intermediate transceiver circuit 2006, and the FEM 2004 via separate buses 2020A and 2020B. The intermediate transceiver circuit 2006 may include a bus interface 2022 configured to be coupled to the communication bus 2014.

[0136] Continuing to refer to FIG. 20, FEM 2004 may include a bus interface 2024 configured to couple to communication bus 2014. FEM 2004 may also include multiple registers 2026 and multiple detectors 2028. The multiple detectors 2028 may measure temperature, voltage, process angle, bias (BI), VSWR, etc. In addition, FEM 2004 may include multiple adjustable elements 2030, such as power amplifiers or LNAs.

[0137] As described above, the adjustable elements 2030 are changed by settings in register 2026. Register 2026 may be filled by model microprocessor 2016, model microprocessor 2010, or some combination of both. Similarly, the settings of the adjustable elements in intermediate transceiver circuit 2006 may be set by model microprocessor 2018, model microprocessor 2010, or some combination of both. Detector 2028 can provide information to model microprocessor 2016, and / or aggregated events from detector 2028 can be sent to model microprocessor 2010. Because BBP 2002 has more inherent processing power, it may be suitable for model microprocessor 2010 to perform most of the heavy computation using the inference model and send FEM settings to register 2026 in FEM 2004 via communication bus 2014. Additionally, some BBP information can be sent via communication bus 2014. In some respects, BBP information can be used by the inference model in model microprocessor 2016.

[0138] While transceiver 2000 is one possibility, transceiver 2000 can be combined with application processor (AP) 2100 in which model microprocessor 2102 is located, as shown in FIG21. Inference models can be distributed across various model microprocessors 2102, 2010, 2018, and 2016. AP 2100 has much greater computing power, and therefore, model microprocessor 2102 canIt is the largest of the four. Therefore, the most computationally intensive calculations can be performed in the model microprocessor 2102. This approach places a greater burden on the communication bus 2014 and can increase latency, but the model microprocessor 2102 may also have the ability to adapt the inference model in near real-time, rather than requiring such adaptation to occur at the training facility. Specification 16 / 20 pages 24 CN 121620873 A

[0139] Instead of having a full inference model at the FEM, an interpolation inference model can be used, as shown in transceiver 2200 of FIG22. Specifically, BBP 2002 still sends the nominal FEM settings from model microprocessor 2010, but model microprocessor 2202 uses information from detector 2028 to calculate the interpolation adjustment, which is combined in combiner 2204 before being written to register 2026.

[0140] It should be understood that the use of inference models is not limited to FEMs, but can also be applied to the setup of power management integrated circuits (PMICs) such as PMIC 2300 in FIG. 23. While transceiver 2200 (or 2000) can be used, model microprocessor 2010 can provide PMIC settings via communication bus 2014. PMIC 2300 may include bus interface 2302 configured to be coupled to communication bus 2014 and use the information provided therethrough to adjust average power tracking (APT) or envelope tracking (ET) activity in PMIC 2300 in order to set Vcc tracking voltage 2304 for power amplifiers in FEM 2004.

[0141] Alternatively, in the spirit of distributed inference models, PMICs may include model microprocessors and use inference models to locally generate settings, as better seen in FIG. 24, where PMIC 2400 may include model microprocessor 2402 capable of receiving information from local detector 2404. Combining the information received from the communication bus 2014, settings can be generated for the Vcc tracker 2406.

[0142] While the above discussion envisions the inference model being distributed across several locations, it should be understood that there may be situations where it makes more sense to merge the inference model into one or two large model microprocessors. For example, such an arrangement may be appropriate when multiple FEMs are present, and the merging approach helps to reduce the likelihood of interference. Figure 25 illustrates a transceiver 2500 having multiple FEMs 2502(1)–2502(4), which may be, for example, low frequency band, mid-high frequency band (MHB), ultra-high frequency band (UHB), and ENDC. In this respect, the inference model may be merged into BBP 2504 (i.e., model 2504A), AP 2506 (i.e., model 2506A), or distributed across both. The communication bus 2508 can carry settings to FEMs 2502(1)–2502(4).

[0143] In contrast, the inference model can be distributed across multiple FEMs, as shown in FIG26. Specifically, transceiver 2600 may include FEMs 2602(1)-2602(4) having corresponding model microprocessors 2604(1)-2604(4). As in the previous aspect, detectors 2606(1)-2606(4) may provide information to the corresponding model microprocessors 2604(1)-2604(4) for determining register settings.

[0144] Furthermore, the inference model can be distributed across multiple PMICs associated with multiple FEMs, as better illustrated in FIG27. Specifically, PMICs 2700(1)-2700(2) may also include model microprocessors 2702(1)-2702(2) working with FEMs 2602(1)-2602(2) in transceiver 2600. In this aspect, there is no model microprocessor in the AP. This keeps the communication on the communication bus 2508 relatively short and may not introduce excessive latency.

[0145] However, this approach is not necessary in all cases, and as shown in FIG28, the inference model can be distributed across the AP and FEM. Specifically, in the transceiver 2800 with the associated AP 2802, the AP has a model microprocessor 2804 that works with a portion of the inference model. In this respect, the BBP 2806 does not include a model microprocessor and does not work with the inference model. FEMs 2602(1)–2602(4) will receive FEM settings from the communication bus 2508 as previously described.

[0146] It should be understood that training can be modified to accommodate the distributed inference model. Similarly, updates through the iterative process described above can be modified to accommodate the distributed inference model. In this regard, FIG29 illustrates a training environment 2900 that uses a generator 2904 and a measurement device 2906 to collect information only from the FEM 2902. Therefore, dataset 2908 only has information about FEM 2902.

[0147] In contrast, the training environment 3000 illustrated in FIG30 can be a more holistic training environment that utilizes AP 3002 to generate inputs and measures outputs from BBP 3004 and FEM 3006 to form dataset 3008 for training AI.

[0148] It should be noted that this disclosure can also be extended to beamformers, such as those that can be used with millimeter-wave (mmWave) FEMs. Similarly, the inference model can be distributed. For example, as shown in FIG31, millimeter-wave FEM 3100 can have a local model microprocessor 3102 that receives information from detector 3104 and from the model via communication bus 3108.Microprocessor 3106 receives further setup information. Model microprocessor 3106 may receive information from (or be embedded in, not shown) beamformer circuit 3110. Beamformer circuit 3110 may receive information from BBP 3112, and although not shown, BBP 3112 may also have a model microprocessor supporting a portion of the distributed inference model.

[0149] This method works even when multiple beamformers are present, as shown in FIG32. Here, a centralized model microprocessor 3200 may be present, which works with the inference model and performs most of the computation. However, each of FEMs 3100(1)-3100(3) has its own corresponding model microprocessor 3102(1)-3102(3).

[0150] The above discussion has provided a great deal of detail about how to use the inference model within various hardware configurations, but little guidance has been provided on how the inference model can actually work. The discussion in Figures 33 through 36 provides at least several possible options for how the inference model can push settings to the hardware for writing to registers. Specifically, a Programming Abstraction Layer (PAL) can be used to provide an interface from the query source to the inference model. As discussed above, the inference model can be associated with a microprocessor in the BBP, and when the BBP determines that the operation of the FEM (or other components) needs to be adjusted (i.e., the BBP will make the registers have new information written to them), the software in the BBP can send a request for register settings (e.g., as a write request) to the software driver. The PAL conceptually sits in front of the software driver and translates the request into a query to the inference model. In response to the query, the inference model returns a palette of possible register settings categorized by additional criteria (e.g., linearity, efficiency, low-power operation, etc.). The software receiving this palette from the software driver selects a bundle of register settings from the palette and provides instructions to components in the transmission chain (e.g., transceiver circuitry, PMIC, and / or FEM). These instructions can be write commands to registers of tunable components and / or instructions to other parts of the distributed inference model.

[0151] This approach also contrasts with the conventional pull model, in which the BBP passes some parameters to the FEM software driver to obtain a limited FEM RFFE setup in the form of register addresses and register data, constructs a script, and submits the script to Layer 1 for execution via the RFFE bus to program the RF FEM. As discussed above, the conventional approach is limited by the granularity of the FEM software driver's setup library and the bandwidth of the RFFE bus. Modern FEMs may require specific setups for many different communication scenarios. This need results in large multidimensional LUTs for FEM setup. Such large multidimensional LUTs are suboptimal.

[0152] For the purposes of this discussion, it is initially assumed that only inference models are used to tune the elements of the FEM. Therefore, as explained above, the FEM may have multiple registers that need to be written before processing and transmitting signals. Each operating scenario is characterized by multiple specific conditions, such as operating frequency band, modulation signal type, modulation bandwidth, etc., as explained above. As a further assumption, not every BBP manufacturer configures the BBP to share this information with the FEM. However, as noted above, if this information is used to select register settings, better FEM settings can be selected.

[0153] In this regard, FIG33 illustrates a first exemplary aspect of how inference models can be used to provide appropriate settings when the BBP shares information. More specifically, transceiver chain 3300 may include an FEM 3302 having various tunable elements as described above. The FEM 3302 may communicate with the BBP 3304 via, for example, the RFFE bus 3306 (e.g., via bus interfaces 3306A, 3306B). BBP 3304 may include control circuitry 3308, which is aware of the operating conditions described above. Control circuitry 3308 may send a write request to FEM software driver 3310, which may be associated with inference model 3312. In an exemplary aspect, inference model 3312 is external to BBP 3304 and may include a microprocessor (not shown), as previously described. In an alternative aspect, inference model 3312 and FEM software driver 3310 are loaded into the memory of BBP 3304.

[0154] FEM software driver 3310 receives the request and acts as an intermediary for the inference model. In an exemplary aspect, and as explained in more detail on pages 18 / 20 of the specification 26 CN 121620873 A below, a PAL may exist to act as an interface to BBP 3304, such that all lower-level operations are transparent to BBP 3304. In response to the request, FEM software driver 3310 queries BBP 3304 for the operating conditions of a given communication scenario. BBP 3304 provides such information in response to a driver inquiry or as part of an initial request.

[0155] FEM software driver 3310 may have a set of criteria 3314 for analyzing operating conditions and selecting a set or bundle 3316(x) from a palette 3318 of possible FEM bundles 3316(1)-3316(N). FEM bundles 3316(1)-3316(N) are assembled by inference model 3312 such that there is a bundle for each possible communication scenario. While the selection of a bundle may be based on operating conditions controlled by the modem, other operating condition criteria may also be used (e.g., low power, low battery, maximum efficiency, maximum linearity, temperature, etc.). BBP 3304 then causes the selected bundle 3316(x) to be written into the FEM.Registers in 3302.

[0156] In an exemplary aspect, information may be arranged in a multidimensional manner (e.g., a matrix with two or more dimensions), as better seen in the transport chain 3400 in FIG. 34. Paged memory for bundles 3402(1)-3402(P), etc., may be used to store such a multidimensional palette 3404. One option is to index the palette 3404 based on given operating conditions. Another option is that some criteria will be used to analyze the operating conditions and select bundles 3402(1)-3402(P) from the palette 3404.

[0157] In other cases, the BBP may not provide the operating conditions to the FEM driver software. In such cases, the FEM driver software may provide the entire palette to the BBP, and the BBP may select the appropriate bundle based on the BBP’s knowledge of the operating conditions. That is, the FEM driver software may provide a palette index along with some indication of which bundles are suitable for which operating conditions.

[0158] In this regard, FIG35 illustrates a transport chain 3500, which is similar to those transport chains previously described in that it has an FEM 3502 and a BBP 3504 communicatively coupled via a bus 3506. However, the software or control circuitry 3508 of the BBP 3504 does not provide operating conditions to the FEM driver software 3510. However, the FEM driver software 3510 may have generated multiple bundles 3516(1)-3516(N) into a palette 3518 using an inference model 3512, and may provide an index 3520 of the palette 3518 to the control circuitry 3508. The index 3520 may include some information about the palette 3518, indicating which bundles are suitable for which operating conditions. The control circuitry 3508 then uses its knowledge of the operating conditions and its knowledge of what selection criteria 3514 to use to issue a write request with a pointer 3522 regarding which bundle 3516(x) to use. Then, the FEM driver software 3510 writes these values ​​into a register in the FEM 3502. It should be noted that this method can also work when the BBP 3504 provides limited information for optimizing the desired FEM settings (e.g., optimal linearity, optimal efficiency, balance between linearity and efficiency, etc.).

[0159] Alternatively, as shown in the transport chain 3600 in FIG36, this transport chain causes a request to be sent from the control circuitry 3608 of the BBP 3604 to the FEM driver software 3610. The FEM driver software 3610 responds by providing a palette 3618 (based on inference model 3612) with multiple bundles 3616(1)–3616(N) to the control circuitry 3608 (shown as palette 3618'). A selection is made based on known operating conditions and the criteria used for selection, and the FEM driver software 3610 is instructed to write the bundle into a register in the FEM 3602.

[0160] Figure 37 provides a block diagram of the transmission chain 3700, illustrating how the PAL and the discussion in Figures 33 to 36 are not limited to the FEM setup. Specifically, the inference model can provide a palette 3702 (which may be a multidimensional LUT) with bundles as described above, wherein, for example, there may be reconfigured registers 3702R (R1-Rn), non-bias registers 3702T (T1-Tn), and bias registers 3702B (B1-Bn) optimized based on multiple dimensions 3702D, such as band modulation, MPR, bandwidth, power, etc. Furthermore, system information 3702S may be included, such as supply voltage (Vcc), any digital predistortion (DPD) coefficients, etc.

[0161] As illustrated, the modem software 3704 (i.e., the control circuitry of the BBP) can issue a write request 3706 with or without information to the FEM driver software specification page 19 / 20, 27 CN 121620873 A 3708. The PAL 3710 translates the write request into an appropriate query to interact with the inference model 3712 and any RF driver core 3714, such that the BBP or modem has no knowledge of how the inference model 3712 is constructed. Similarly, the PAL 3710 can translate information from the inference model 3712 into a format more easily processed by the modem software 3704. The modem software 3704 can then make any selections from the palette provided by the FEM driver software 3708, perform any system adjustments (e.g., DPD correction, etc.), and perform writes to elements of the transmission chain (such as transceiver circuitry 3718, FEM 3720, PMIC 3722, etc.).

[0162] It should also be noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The described operations may be performed in several different orders other than the order shown. Furthermore, the operations described in a single operational step may actually be performed in several different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It should be understood that those skilled in the art will readily appreciate that the operational steps shown in the flowcharts may undergo numerous different modifications. Those skilled in the art will also understand that information and signals can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips referenced in the detailed embodiments above may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0163] The prior description of this disclosure is provided so that any person skilled in the art can make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein are consistent with those of the art.Other variations can be applied. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but should be given the broadest scope consistent with the principles and novel features disclosed herein. Specification 20 / 20 Page 28 CN 121620873 A Figure 1 (Related Technology) Figure 2A (Related Technology) Specification Drawings 1 / 41 Page 29 CN 121620873 A Figure 2B (Related Technology) Specification Drawings 2 / 41 Page 30 CN 121620873 A Figure 3 (Related Technology) Specification Drawings 3 / 41 Page 31 CN 121620873 A Figure 4A Figure 4B Specification Drawings 4 / 41 Page 32 CN 121620873 A Figure 5 Specification Drawings 5 / 41 Page 33 CN 121620873 A Figure 6 Specification Drawings 6 / 41 Page 34 CN 121620873 A Figure 7A Specification Drawings 7 / 41 Page 35 CN 121620873 A Figure 7B Specification Drawings 8 / 41 Page 36 CN 121620873 A Figure 8A Instruction manual Figure 9 / 41, page 37, CN 121620873 A, Figure 8B; Instruction manual Figure 10 / 41, page 38, CN 121620873 A, Figure 8C; Instruction manual Figure 11 / 41, page 39, CN 121620873 A, Figure 9; Instruction manual Figure 12 / 41, page 40, CN 121620873 A, Figure 10; Instruction manual Figure 13 / 41, page 41, CN 121620873 A, Figure 11; Instruction manual Figure 14 / 41, page 42, CN 121620873 A, Figure 12; Instruction manual Figure 15 / 41, page 43, CN 121620873 A, Figure 13; Instruction manual Figure 16 / 41, page 44, CN 121620873 A, Figure 14; Instruction manual Figure 17 / 41, page 45, CN 121620873 A, Figure 15; Instruction manual Figure 18 / 41, page 46, CN 121620873 A Figure 16 Instruction Manual Drawing, Page 47 (19 / 41) CN 121620873 A Figure 17A Instruction Manual Drawing, Page 48 (20 / 41) CN 121620873 A Figure 17B Figure 17C Instruction Manual Drawing, Page 49 (21 / 41) CN 121620873 A Figure 18 Instruction Manual Drawing, Page 50 (22 / 41) CN 121620873 AFigure 19 Appendix to the Instruction Manual, Page 23 / 41, 51 CN 121620873 A Figure 20 Appendix to the Instruction Manual, Page 24 / 41, 52 CN 121620873 A Figure 21 Appendix to the Instruction Manual, Page 25 / 41, 53 CN 121620873 A Figure 22 Appendix to the Instruction Manual, Page 26 / 41, 54 CN 121620873 A Figure 23 Appendix to the Instruction Manual, Page 27 / 41, 55 CN 121620873 A Figure 24 Appendix to the Instruction Manual, Page 28 / 41, 56 CN 121620873 A Figure 25 Appendix to the Instruction Manual, Page 29 / 41, 57 CN 121620873 A Figure 26 Appendix to the Instruction Manual, Page 30 / 41, 58 CN 121620873 A Figure 27 Appendix to the Instruction Manual, Page 31 / 41, 59 CN 121620873 A Figure 28 Appendix to the Instruction Manual, Page 32 / 41 Page 60 CN 121620873 A Figure 29 Description drawing 33 / 41 Page 61 CN 121620873 A Figure 30 Description drawing 34 / 41 Page 62 CN 121620873 A Figure 31 Description drawing 35 / 41 Page 63 CN 121620873 A Figure 32 Description drawing 36 / 41 Page 64 CN 121620873 A Figure 33 Description drawing 37 / 41 Page 65 CN 121620873 A Figure 34 Description drawing 38 / 41 Page 66 CN 121620873 A Figure 35 Description drawing 39 / 41 Page 67 CN 121620873 A Figure 36 Description drawing 40 / 41 Page 68 CN 121620873 A Figure 37 Description drawing 41 / 41 Page 69 CN 121620873 A

Claims

1. A transceiver, comprising: a front-end module (FEM) comprising: a bus interface configured to be coupled to a communication bus for receiving inference model settings from a baseband processor (BBP) or an application processor (AP); a plurality of tunable elements, each tunable element having an associated control register; a first model microprocessor comprising a first portion of an inference model, based on the inference model settings from the BBP, the first model microprocessor configured to write settings to at least one of the associated control registers while at least a second one of the associated control registers is configured to be written to; and a plurality of detectors configured to sense operating conditions and report measurements related to the operating conditions to the first model microprocessor.

2. The transceiver of claim 1, further comprising: the BBP comprising a second model microprocessor configured to use a second portion of the inference model.

3. The transceiver of claim 2, wherein the first portion of the inference model is less computationally powerful than the second portion of the inference model.

4. The transceiver of claim 1, further comprising a power management integrated circuit (PMIC) comprising: a PMIC bus interface configured to be coupled to the communication bus; and an adjustable element configured to adjust based on output from the inference model.

5. The transceiver of claim 4, wherein the PMIC further comprises a PMIC model microprocessor comprising a PMIC portion of the inference model, and the adjustable element is configured to adjust based on output from the PMIC portion of the inference model.

6. The transceiver of claim 4, wherein the adjustable element is configured to adjust based on output from the inference model received over the communication bus.

7. The transceiver of claim 2, further comprising a second FEM coupled to the communication bus.

8. The transceiver of claim 7, wherein the second FEM is configured to receive output from the second portion of the inference model over the communication bus.

9. The transceiver of claim 7, wherein the second FEM comprises a third model microprocessor and is configured to use a third portion of the inference model with the third model microprocessor.

10. The transceiver of claim 1, wherein the model microprocessor is configured to generate difference settings using the first model microprocessor based on information received from the BBP.

11. The transceiver of claim 1, comprising beamforming circuitry coupled to the communication bus.

12. The transceiver of claim 11, wherein the beamforming circuitry comprises a second model microprocessor configured to operate with a second portion of the inference model.

13. A wireless communication device (WCD), comprising: a communication bus; a front-end module (FEM) coupled to the communication bus, the FEM comprising a settings register and adjustable elements set by the settings register; a baseband processor (BBP) coupled to the communication bus; an application processor (AP) coupled to the communication bus; and an inference model distributed among at least two of the FEM, the BBP, and the AP, wherein the inference model is configured to operate on an associated model microprocessor and is configured to write settings to the settings register in the FEM.

14. The WCD of claim 13, further comprising a power management integrated circuit (PMIC), and wherein the inference model is distributed at least partially to the PMIC.

15. A method of controlling adjustable elements in a front-end module (FEM), comprising: receiving, at the FEM, first information from a first portion of an inference model over a communication bus; generating, in a model microprocessor in the FEM, second information using a second portion of the inference model; writing settings into a settings register in the FEM based on the first information and the second information; and adjusting tunable elements in the FEM based on the settings register.

16. The method of claim 15, further comprising generating the first information at a baseband processor.

17. The method of claim 15, further comprising generating the first information at an application processor.

18. The method of claim 15, wherein generating additional information comprises generating different information relative to the first information.

19. The method of claim 15, further comprising sending third information to a power management integrated circuit (PMIC) over the communication bus, wherein the third information is also derived from the first portion of the inference model.

20. A front-end module (FEM), comprising: a plurality of tunable elements, each tunable element having an associated control register; and a model microcontroller comprising an inference model, the model microcontroller configured to write settings into each of the associated control registers based on reported operating conditions.

21. The FEM of claim 20, further comprising a plurality of detectors configured to sense operating conditions and report measurements related to the operating conditions to the model microcontroller.

22. The FEM of claim 20, wherein the plurality of tunable elements comprises bias circuitry for a power amplifier.

23. The FEM of claim 20, wherein the plurality of tunable elements comprises a load line circuit. ​ ​ ​ 24. The FEM of claim 20, wherein the model microcontroller is further configured to receive baseband information from a baseband processor (BBP) over a communication bus.

25. The FEM of claim 24, wherein the baseband information includes at least one of a modulation type, a bandwidth, and a power level.

26. The FEM of claim 24, wherein the baseband information includes at least one of a bit error rate (BER), an average power ratio (APR), and a maximum power reduction (MPR).

27. The FEM of claim 21, wherein the plurality of detectors includes a temperature sensor.

28. The FEM of claim 21, wherein the plurality of detectors includes a local power supply voltage sensor.

29. The FEM of claim 20, wherein the model microcontroller is further configured to receive an inference model patch from a remote server.

30. A baseband processor (BBP), comprising: a bus interface configured to couple to a front-end module (FEM) over a communication bus; and a model microcontroller configured to: generate settings for control registers in the FEM using baseband information with an inference model; and send the settings to the FEM over the bus interface.

31. The BBP of claim 30, wherein the model microcontroller is further configured to: receive FEM information from the FEM over the bus interface; and generate settings for the control registers in the FEM based at least in part on the FEM information.

32. The BBP of claim 30, wherein the baseband information includes at least one of a modulation type, a bit error rate (BER), a power level, a bandwidth, and a frequency band.

33. The BBP of claim 31, wherein the FEM information includes at least one of a temperature, a local power supply voltage, a detected interceptor, a power level, and a voltage standing wave ratio (VSWR).

34. A method of creating an inference model for use by a model microcontroller in a transceiver, the method comprising: measuring an output of a transceiver; linking the output to an input of the transceiver to assemble a training data set; providing the training data set to an artificial intelligence module to generate a possible inference model; evaluating the possible inference model with a performance check; adjusting the training data set when the performance check fails; and deploying the possible inference model to a transceiver when the performance check passes.

35. The method of claim 34, wherein evaluating the possible inference model includes testing performance using an input of a transceiver and adjusting a tunable element in the transceiver based on an output of the possible inference model.

36. The method of claim 34, further comprising controlling some elements in the transceiver with static adjustments.

37. A front-end module (FEM), comprising: a plurality of tunable elements, each tunable element having an associated control register; and a model microcontroller configured to: generate settings for the control registers using baseband information with an inference model; and send the settings to the FEM. a model microcontroller comprising and running an inference model, the model microprocessor configured to write settings to each of the associated control registers based on a reported operating condition based on inference model output.

38. The FEM of claim 37, further comprising a plurality of detectors configured to sense operating conditions and report measurements related to the operating conditions to the model microprocessor.

39. The FEM of claim 37, wherein the plurality of tunable elements comprise bias circuitry for a power amplifier.

40. The FEM of claim 37, wherein the plurality of tunable elements comprise a load line circuit.

41. The FEM of claim 37, wherein the model microcontroller is further configured to receive baseband information from a baseband processor (BBP) over a communication bus.

42. The FEM of claim 41, wherein the baseband information comprises at least one of modulation type, bandwidth, and power level.

43. The FEM of claim 41, wherein the baseband information comprises at least one of bit error rate (BER), average power ratio (APR), and maximum power reduction (MPR).

44. The FEM of claim 38, wherein the plurality of detectors comprise a temperature sensor.

45. The FEM of claim 38, wherein the plurality of detectors comprise a local power supply voltage sensor.

46. The FEM of claim 37, wherein the model microcontroller is further configured to receive an inference model patch from a remote server.

47. A baseband processor (BBP), comprising: a bus interface configured to couple to a front-end module (FEM) over a communication bus; a modem configured to: generate settings for control registers in the FEM using baseband information with an inference model; and send the settings to the FEM over the bus interface.

48. The BBP of claim 47, wherein the modem is further configured to: receive FEM information from the FEM over the bus interface; and generate settings for the control registers in the FEM.

49. An application processor (AP), comprising: a bus interface configured to couple to a front-end module (FEM) over a communication bus; and a processor configured to: generate settings for control registers in the FEM using baseband information with an inference model; and send the settings to the FEM over the bus interface.

50. The AP of claim 49, wherein the processor is further configured to: receive FEM information from the FEM over the bus interface; and generate settings for the control registers in the FEM.

51. The AP of claim 49, wherein the FEM information comprises at least one of temperature, local power supply voltage, detected intercepts, power level, and voltage standing wave ratio (VSWR).

52. A method of creating an inference model for use by a modem, the method comprising: measuring an output of a front end module (FEM); linking the output to an input of the modem to assemble a training data set; providing the training data set to an artificial intelligence module to generate a possible inference model; evaluating the possible inference model with a performance check; when the performance check fails, adjusting the training data set; and when the performance check passes, deploying the possible inference model to a baseband processor (BBP), FEM, or application processor (AP).

53. A method of creating an inference model for use in a laboratory environment without a modem, the method comprising: measuring an output of a front end module (FEM); linking the output to an input of laboratory equipment and a server to assemble a training data set; providing the training data set to an artificial intelligence module to generate a possible inference model; evaluating the possible inference model with a performance check; when the performance check fails, adjusting the training data set; and when the performance check passes, deploying the possible inference model to a baseband processor (BBP), FEM, or application processor (AP).

54. The method of claim 52 or 53, wherein evaluating the possible inference model includes testing performance using an input of a FEM and adjusting a tunable element in the FEM based on an output of the possible inference model.

55. A front end module (FEM) comprising: a plurality of tunable elements, each tunable element having an associated control register; a model microcontroller, the model microcontroller including an inference model, the model microcontroller configured to write settings to each of the associated control registers based on reported operating conditions; and a plurality of detectors configured to sense operating conditions and report measurements related to the operating conditions to the model microcontroller; wherein the model microcontroller is further configured to collect information about operating conditions and settings and provide the information to a control circuit for storage in a memory and transmission to a remote location.

56. The FEM of claim 55, wherein the plurality of tunable elements includes bias circuitry for a power amplifier.

57. The FEM of claim 55, wherein the plurality of tunable elements includes a load line circuit.

58. The FEM of claim 55, wherein the model microcontroller is further configured to receive baseband information related to operating conditions from a baseband processor (BBP) over a communication bus.

59. The FEM of claim 55, wherein the plurality of detectors includes a temperature sensor.

60. The FEM of claim 55, wherein the plurality of detectors includes a local power supply voltage sensor.

61. The FEM of claim 55, wherein the model microcontroller is further configured to receive an inference model patch from a remote server.

62. The FEM of claim 61, wherein the inference model patch is based at least in part on information collected by the model microcontroller.

63. A baseband processor (BBP), comprising: a bus interface configured to couple to a front-end module (FEM) over a communication bus; and a model microcontroller configured to: generate settings for control registers in the FEM using baseband information with an inference model; and send the settings to the FEM over the bus interface; collect information about operating conditions, the settings, and outputs derived from the settings; and provide the information to control circuitry for storage in memory and transmission to a remote location.

64. The BBP of claim 63, wherein the model microcontroller is further configured to: receive FEM information from the FEM over the bus interface; and generate the settings for the control registers in the FEM based at least in part on the FEM information.

65. The BBP of claim 64, wherein the information about outputs is based at least in part on the FEM information.

66. A wireless communication device (WCD), comprising: a transceiver, the transceiver comprising: a communication bus; a front-end module (FEM) coupled to the communication bus, the FEM comprising: a plurality of tunable elements; and a plurality of sensors configured to provide information about operating conditions; a baseband processor (BBP) coupled to the communication bus; an application processor (AP) coupled to the BBP; and a model microcontroller in one of the FEM, the BBP, or the AP, the model microcontroller comprising an inference model configured to generate settings for control registers in the FEM based on reported operating conditions; memory; and control circuitry coupled to the memory and communicatively coupled to the inference model, the control circuitry configured to: collect information about operating conditions and settings; store the information in the memory; and cause the information to be transmitted to a remote location.

67. The WCD of claim 66, wherein the control circuitry is embedded in the application processor.

68. The WCD of claim 66, wherein the control circuitry is configured to cause the information to be transmitted in response to an amount of information exceeding a threshold.

69. The WCD of claim 66, wherein the control circuitry is configured to cause the information to be transmitted in response to a polling query from the remote location.

70. A method of updating an inference model for use by a model microcontroller in a transceiver, the method comprising: creating an initial inference model using laboratory measurements of a front-end module (FEM); receiving information from a plurality of FEMs deployed in wireless communication devices (WCDs); and updating the inference model based on the received information. retrain a version of the initial inference model using the information from the plurality of FEMs.

71. The method of claim 70, further comprising updating the initial inference model based on information from a combination of a baseband processor (BBP) and FEMs in a lab.

72. The method of claim 70, further comprising sending an updated version of the inference model to a deployed WCD.

73. A baseband processor (BBP), comprising: a communication bus configured to communicate with at least a front-end module (FEM) having programmable registers therein; and a control circuit coupled to the communication bus and configured to: request, by a FEM software driver, a write operation to the programmable registers in the FEM; and receive, from the FEM software driver, a palette of register bundles, wherein each of the palette of register bundles is optimized for a different operating condition; and select a register bundle from the palette based on an operating condition known to the control circuit.

74. The BBP of claim 73, wherein the FEM software driver comprises a programming abstraction layer (PAL) configured to interface between an inference model in the FEM software driver and the control circuit.

75. The BBP of claim 73, wherein the FEM software driver is external to the BBP.

76. The BBP of claim 74, wherein the inference model is programmed to consider multi-dimensional operating conditions and select register settings from a multi-dimensional lookup table (LUT).

77. The BBP of claim 73, wherein the FEM software driver is further configured to write to the programmable registers based on the register bundle selected by the control circuit.

78. A baseband processor (BBP), comprising: a communication bus configured to communicate with at least a front-end module (FEM) having programmable registers therein; and a control circuit coupled to the communication bus and configured to: request, by a FEM software driver, a write operation to the programmable registers in the FEM, wherein the request for a write operation includes information about an operating condition; and receive, from the FEM software driver, a register bundle derived from an inference model based on the information about an operating condition; and write to the programmable registers based on the register bundle.

79. The BBP of claim 78, further comprising a programming abstraction layer (PAL) to interface between the inference model and the control circuit.

80. The BBP of claim 78, wherein the operating condition comprises one or more conditions selected from the group consisting of: an operating frequency band, a generation of a communication, a type of modulated signal, a modulation bandwidth, a modulation power ratio, MPR, a transmission and reception carrier aggregation configuration.

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