Configurable write command delay in nonvolatile memory

Abstract

To provide a memory system that includes a nonvolatile (NV) memory device with asymmetry between intrinsic read operation delay and intrinsic write operation delay, where the unmatched delays can create unusable gaps on a command bus or DQ bus, or on both the command and DQ buses, so that, in workloads that have a mix of read and write commands, such gaps impact the maximum achievable bandwidth.SOLUTION: A system 100 can select to perform memory access operations with an NV memory device with the asymmetry included in an array 140. In this case, write operations have a lower delay than read operations. The system can select to perform memory access operations with the NV memory device, where a write operation delay that matches the read operation delay.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The description relates generally to memory devices, and more specifically to configurable write command delay in memories having different write and read command delays. [Background technology]

[0002] Conventional memory devices, such as dynamic random access memory (DRAM), have matching latencies between read and write operations, allowing the controller to schedule commands in any order with a fixed latency between sending a command on the command bus and using the data bus.

[0003] Emerging three-dimensional (3D) cross-point (3DXP) media has many limitations, including non-uniform read and write latencies. Ko Commands and Data Matched Therefore, read and write commands take the same number of clock cycles (tCK) to send on the command bus, and data takes the same number of clock cycles for read and write commands. However, the delay between a write command and the data on the data (DQ) bus is significantly shorter than the delay between a read command and the data on the DQ bus.

[0004] The delay between the write command and the data on the DQ bus is the time it takes for the controller to DQ On the bus in Driven by Data Wait to wait Write commands are executed as background asynchronous processes. Yo This is because the controller Simply send the command and Immediately after the command is sent D Data sending can then be used to perform other tasks. FreedThe delay between the read command and the data on the DQ bus means that the memory device can access the data from the storage medium and send it to DQ The mismatched delays refer to the time it takes to drive onto the command bus or the DQ bus, or the command bus This can result in unusable gaps on both the DQ and DQ buses. In a workload that has a mix of read and write commands, such gaps impact the maximum achievable bandwidth.

[0005] One conventional approach to address the bandwidth inefficiencies resulting from latency mismatch is to modify the command interface to have twice the bandwidth of the data interface. However, due to higher bit rates or an increased number of command signal lines on the command bus, such an approach requires increased controller and media power. [Brief description of the drawings]

[0006] The following description includes a discussion of figures in which illustrations are given as examples of implementations. The figures should be understood as examples and not as limitations. As used herein, reference to one or more examples should be understood as describing specific features, structures, or characteristics included in at least one implementation of the invention. Phrases such as "in one example" or "in an alternative example" appearing herein provide examples of implementations of the invention and do not necessarily all refer to the same implementation. However, they are not necessarily mutually exclusive.

[0007] [Figure 1] FIG. 1 is a block diagram of a system that has an inherent difference between read and write delays and can select a mismatched write delay mode or a matched write delay mode.

[0008] [Figure 2A]FIG. 1 is a block diagram of a single rank memory system capable of selecting mismatched or matched write delay modes.

[0009] [Figure 2B] FIG. 1 is a block diagram of a two-rank memory system capable of selecting mismatched or matched write delay modes.

[0010] [Diagram 3] 1 is a timing diagram of an example system having an inherent read and write delay mismatch with a selectable write delay;

[0011] [Figure 4] 1 is an example table of bus utilization data illustrating improved utilization of a system having an inherent read and write latency mismatch that implements selectable write latency;

[0012] [Diagram 5] FIG. 1 is a flow diagram of an example of a process for selectable write latency in a system having an inherent read latency and write latency mismatch.

[0013] [Figure 6] FIG. 1 is a block diagram of an example of a memory subsystem in which selectable write delay can be implemented.

[0014] [Figure 7] FIG. 1 is a block diagram of an example of a computing system in which selectable write delay may be implemented.

[0015] [Figure 8] FIG. 1 is a block diagram of an example of a mobile device in which selectable write delay may be implemented.

[0016] A description of specific details and implementations follows, including a non-limiting description of figures that may show some or all examples, as well as other possible implementations. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] As described herein, a memory system includes a non-volatile (NV) memory device having an asymmetry between an intrinsic read operation delay and an intrinsic write operation delay. The system includes a NV memory device having an asymmetry. With Alternatively, the system may select to perform a memory access operation in which a write operation has a lower latency between a command and use of the data bus than a read operation, although a write operation may have a longer latency to completion than a read operation. Alternatively, the system may select to perform a memory access operation in which a write operation has a lower latency between a command and use of the data bus than a read operation, although a write operation may have a longer latency to completion than a read operation. Alternatively, the system may select to perform a memory access operation in which a write operation has a lower latency between a command and use of the data bus than a read operation. With A memory access operation can be selected to be performed.

[0018] In one example, the memory device comprises: Storage media To program the write latency either to the component minimum or to match the read latency, Setting When write latency is at a component minimum, the write latency is based on the architecture of the storage medium itself and may vary depending on the component The minimum is the time between the command and receipt of the write data. memoryDefines the minimum delay required by the medium. The value to match the read latency causes the memory device to add a delay to match the write latency to the read latency. In one example, the memory device matches the write latency to the read latency by having the internal storage controller add a delay internally to the write command to match the data bus usage of the write command to the inherent latency of the read command. Such an approach may allow the memory device to treat the write command the same in terms of access to the medium and data bus, only delayed due to processing the command after the delay.

[0019] By programming or setting the write latency to match the read latency, The host controller Based on command bus availability calligraphy It may be possible to issue a write or read command. 、 This is the DQ for both commands. availability Therefore, by selectively matching the write and read latencies for a particular workload, DQ bus utilization can be increased, thereby improving the bandwidth of the NV memory device. In one example, the NV memory device is a non-volatile storage device having a three-dimensional cross-point (3DXP) memory array. As one specific example, the NV memory device can be an OPTANE product available from Intel Corporation. Selectively matching the write and read latencies for a particular workload can increase DQ bus utilization, thereby improving the bandwidth of the NV memory device. In one example, the NV memory device can be a non-volatile storage device having a three-dimensional cross-point (3DXP) memory array. As one specific example, the NV memory device can be an OPTANE product available from Intel Corporation. calligraphy Read and write latency To match The application of has been observed to improve data bus utilization and increase the overall bandwidth of 3DXP devices by approximately 10%.

[0020] A host controller or system controller manages access to the memory device by allowing the host controller to selectively apply matching write and read latencies. MTrack when to issue a read or write command to a memory device Simplify the controller scheduler design for The write / read latency match is customer Achievable for use by customers Bandwidth or This may increase performance. The host controller has read and write latencies Based on inherent latency tree , not a mismatch 、 Knowing that they are the same allows the host controller to issue any command at any time.

[0021] Some memory technologies, such as DRAM (Dynamic Random Access Memory), have symmetrical latencies between reads and writes. Such symmetrical memory technologies do not have the inefficiencies of latency mismatch. Programmable write delays allow for the elimination of asymmetrical memory technologies. Use , can be implemented as a symmetric memory technology. Programmability allows the system to select mismatched or matched latency depending on the workload. In one example, if the workload has a high percentage of writes, the system can select a mismatched mode to allow the memory device to use the minimum latency. In one example, if the workload has a mix of reads and writes, the system can select a matched latency mode to make the read and write latencies symmetric.

[0022] 1 is a block diagram of a system that has an inherent difference between read and write delays and can select a mismatched or a matched write delay mode. The system 100 includes a host 110 having a memory controller 120 coupled to a memory device 130.

[0023] Memory Device 1 31 includes a memory array 140, which represents an array of memory cells or storage cells. A memory cell stores a bit of data, or multiple bits of a multilevel cell. In one example, the array 140 is partitioned as a bank of memory or other subset of memory. In one example, the memory device 130 is part of a group of memory devices, where one or more memory devices are organized as a rank of memory. A rank of memory is a group of memory resources that share chip select or enable signals and are therefore accessed in parallel.

[0024] In one example, array 140 includes non-volatile memory cells. A non-volatile (NV) memory or NV memory device maintains its state even when power to the memory is removed. A volatile memory has an indeterminate state when power to the memory is removed. In one example, the NV media of array 140 is a 3DXP media. Array 140 is Read command to DQ bus delay and Write command to DQ bus delay and but In one example, the array 140 has non-uniform read / write latencies. Including, With matching command and data utilization, read and write commands take the same number of tCKs or clock cycles, and data takes the same number of tCKs whether it is sent from memory device 130 in response to a read or sent to memory device 130 in connection with a write.

[0025] In one example, the array 140 receives the DQ bus utilization from the command. to Write (WR) delay of 142 is significantly shorter than the read (RD) delay of 144 With NV media, WR delay 142 and RD delay 144 represent intrinsic minima. TheThe minimum value is the value that must be followed to ensure proper operation of the device. A delay may be considered an intrinsic delay when it is a delay related to the physical and operational characteristics of the medium itself. The difference between the WR delay 142 and the RD delay 144 results in unusable gaps on the command bus or the DQ bus, or on both the command bus and the DQ bus. In a workload with a mix of read and write commands, these gaps affect the maximum achievable bandwidth between the memory device 130 and the host 110 or memory controller 120.

[0026] The host 110 represents a computing platform to which the memory device 130 is coupled. For example, the host 110 may be or include a computer or other computing device. The memory controller 120 represents a controller for managing access to the memory device 130. In one example, the memory controller 120 is part of a host processor (not specifically shown) of the host 110. Alternatively, depending on the connection of the memory device 130, the memory controller 120 may be considered a storage controller. In one example, the non-volatile memory of the memory device 130 may be coupled to a storage bus, such as a Peripheral Component Interconnect Express (PCIe) bus. In one example, the non-volatile memory of the memory device 130 is non-volatile, but is also byte-addressable and randomly accessible, and may be coupled to a system memory bus, such as a double data rate (DDR) memory bus.

[0027] The memory controller 120 includes: To the memory device 130 Scheduling a series of commands and sendingThe memory controller 120 includes a scheduler 122 that manages the transmission of commands to the memory device 130. The scheduler 122 includes logic for determining the order of commands and the timing requirements of the commands. The memory controller 120 makes the decision as to which commands to send and in which order. The scheduler 122 determines the order of commands to ensure compliance with timing requirements. In one example, the scheduler 122 determines in which order to schedule commands to the memory device 130 based on whether the memory device 130 is configured such that the WR delay 142 matches the RD delay 144 or whether the WR delay 142 is mismatched relative to the RD delay 144.

[0028] Memory controller 120 includes command logic 124 that generates commands for sending to memory device 130. The commands may include write commands and read commands. Memory controller 120 sends a read command on a command bus (not specifically shown), which may also be referred to as a command and address bus, and after a delay period, memory device 130 will drive the data on a data bus (not specifically shown). Memory controller 120 sends a write command on the command bus, and then sends the data on the data bus to the memory device.

[0029] In one example, memory controller 120 includes WR delay mode 126 that indicates the delay mode of memory device 130. While memory controller 120 can set the delay mode for memory device 130, memory controller 120 can also track which delay mode is being applied by memory device 130. Memory controller 120 needs to know which delay mode is being applied in order to know how to schedule commands in scheduler 122 and also to know when the data bus is being utilized.

[0030] Memory device 130 includes a controller 132 that represents logic in the memory device for receiving and decoding commands from memory controller 132. Controller 132 represents control logic within memory device 130 and is separate from memory controller 120 of host 110. Controller 132 can trigger operations within memory device 130 to execute commands sent by memory controller 120.

[0031] Memory device 130 includes registers 134 that represent one or more registers or storage locations for storing configuration information or values ​​related to the operation of memory device 130. In one example, registers 134 include one or more mode registers. In one example, registers 134 include configuration information for controlling a write delay mode of memory device 130. WR delay mode 136 represents a write delay mode in memory device 130.

[0032] In one example, the WR delay mode 136 includes two modes: a non-matching mode, which may be referred to as a first mode, and a matching mode, which may be referred to as a second mode. The labels of the first and second modes may be swapped in different implementations. The non-matching mode refers to a WR delay mode 136 in which the WR delay is different from the RD delay. The matching mode refers to a WR delay mode 136 with an additional delay such that the WR delay is matched to the RD delay. In one example, the WR delay mode includes a non-matching mode in which the WR delay of the memory device 130 is matched to the RD delay. Run Rhyme For example, the write mode may be dynamically set or configured by setting register 134 during operation of the memory.

[0033] In one example, WR DELAY MODE 136 indicates the matching mode. death , and the controller 132 receives a write command. case, the controller 132 delays processing of the write command by or approximately the difference between the intrinsic RD delay 144 and the intrinsic WR delay 142. By delaying by the difference between the two delays, the applied WR delay is extended to match the RD delay. Thus, the WR delay mode 136 can selectively vary the asymmetry between the WR delay 142 and the RD delay 144 in a matched mode and maintain the mismatched delays in a mismatched mode. In one example, the WR delay mode 136 defaults to the mismatched mode. In one example, the WR delay mode 136 defaults to the matched mode.

[0034] In one example, the memory controller 120 is configured to receive a request to be scheduled by the scheduler 122. Read Write and read commands Mixture of In one example, if the scheduler has most or mainly write operations to send to the memory device 130, the memory controller 120 sends a command to set the register 134 to select the non-matching mode. availability Coincident mode allows the scheduler to schedule commands closer together because the delay between the read and write commands is shorter. In one example, when the scheduler has a mix of read and write commands to send to memory device 130, memory controller 120 sends a command to set register 134 to select coincident mode. Coincident mode allows the scheduler to send read and write commands in any order, which may result in improved DQ bus utilization. In either case, the commands being scheduled Should It will be appreciated that if the write delay mode is already set to a mode that is optimal for the workload, the memory controller does not need to send a command to change the WR delay mode.

[0035] FIG. 2A is a block diagram of a single-rank memory system that can select between a non-matching write delay mode and a matching write delay mode. The system 202 is a Multiple The system 202 may be considered to have a memory subsystem including a memory controller 220 and a memory 230. The host 210 represents a hardware platform that controls the memory subsystem. The host 210 includes one or more processors (e.g., a central processing unit (CPU) or a graphics processing unit (GPU)) that generate requests for data stored in the memory 230.

[0036] The host 210 includes a memory controller 220, which may be integrated into a processor device. The memory controller 220 includes an I / O (input / output) 212 for connecting to a memory 230. The I / O includes connectors, signal lines, drivers, and other hardware for interconnecting a memory device to the host 410. The I / O 212 may include command I / O represented by a command (CMD) bus 242 and data I / O represented by a DQ (data) bus 244. The CMD bus 242 includes command signal lines that allow the memory controller 220 to send commands to the memory 230. The DQ bus 244 includes multiple data signal lines. For an N-bit interface, the DQ bus 244 would include DQ[0:N-1].

[0037] The memory controller 220 includes a command (CMD) logic 224 for generating commands for the memory 230. The commands can be commands for data access (e.g., read and write) or commands for configuration (e.g., mode register commands). The memory controller 220 includes a scheduler 222 for scheduling when to send the commands in a sequence of operations. The scheduler 222 can control the timing of the I / O according to known timing to improve the likelihood that the I / O is error-free. The timing is set through training. The timing can be adjusted depending on the write delay mode of the memory 230.

[0038] The memory 230 may include individual memory devices or may represent a memory module. The system 202 may store data in the memory 230. Multiple Illustrates a single rank of memory devices. A rank is a selection La Share your inn Multiple Refers to a collection or group of memory devices within a rank. Multiple The memory devices will perform operations in parallel. Rank[0] is illustrated as including N memory dies (Dies[(N-1):0]). For one or more memory dies, N may be any integer equal to or greater than 0.

[0039] Single Rank So , the system 202 cannot interleave accesses between ranks. Ability to Interleave Accesses but Even without this, the system 202 can benefit from the ability to select between consistent and inconsistent write delays. The system 202 can implement the write delay selection according to an example of the system 100.

[0040] 2B is a block diagram of a two-rank memory system capable of selecting a non-matching write delay mode or a matching write delay mode. System 204 represents an example of system 202. Host 210, memory controller 220, scheduler 222, command logic 224, I / O 212, CMD bus 242, and DQ bus 244 may be described similarly as described above with respect to system 202.

[0041] The memory 230 may include individual memory devices or may represent a memory module. The system 204 may store data in the memory 230. Multiple Illustrated are two ranks of memory devices. Rank[0] is illustrated as including N memory dies (Dies[(N-1):0]). For one or more memory dies, N may be any integer equal to or greater than 0. Rank[1] is also illustrated as including N memory dies (Dies[(N-1):0]).

[0042] Two ranks So The system 204 can interleave accesses between the ranks. Although a two-rank system is illustrated as an example, systems with more than two ranks can also benefit from interleaving and have similar advantages from the matched write delay mode. ExpectationsIt will be understood that interleaving accesses between ranks refers to switching accesses from one rank to another. Thus, the memory controller 220 can switch sending commands between ranks during write operation delays and read operation delays. If the memory system has at least two devices per channel, the memory controller 220 can write to one of the ranks and read from the other. A one-rank system has a single device or a single die or a single group of devices per channel. The ability to interleave accesses between different ranks allows the system 204 to benefit from the ability to select between matched and mismatched write delays, and also improves bandwidth utilization. The system 204 can implement the selection of the write delay according to an example of the system 100.

[0043] 3 is a timing diagram of an example of a system with an inherent read delay and write delay mismatch with selectable write delay. Diagram 310 illustrates a timing diagram of a scenario where there is a latency mismatch between WR and RD delays. Diagram 310 may illustrate a mismatched WR latency mode selection according to an example of system 100. Diagram 320 illustrates a timing diagram of a scenario where the latency is matched between WR and RD delays. Diagram 320 may illustrate a matched WR latency mode selection according to an example of system 100.

[0044] Diagrams 310 and 320 illustrate specific examples of system configurations. It will be understood that different timings may be used for different system configurations. In addition, different devices may have different characteristics, which will result in different system operations.

[0045] In diagrams 310 and 320, each segment of the timing diagram represents a clock cycle. In the illustrated example, a read or write command takes eight clock cycles to issue (8tCK). In addition, the duration of a write or read command is 100 ms. For data of About Cycle too It takes 8 clock cycles. Data of It will be understood that the cycles may differ from 8tCK, but diagrams 310 and 320 provide 8 clock cycles as an example.

[0046] To identify the timing flow of commands to data associated with a particular command on the DQ bus, reads and writes are labeled consecutively. In diagram 310, R0 indicates rank[0] and R1 indicates rank[1]. Thus, it will be understood that diagram 310 represents a two-rank system and the commands on the command bus indicate switching between the two ranks. Additionally, there is DQ[R0] representing the data bus of rank[0] and DQ[R1] representing the data bus of rank[1].

[0047] Starting from the left of the diagram, the first command is a write for rank[0] (command WR0), followed by WR1 for rank[1], WR2 for rank[0], and WR3 for rank[1]. The "L" before WR2 indicates that a WR Between to WR Delay of The The delays may vary for different systems and are illustrated as examples only.

[0048] In diagram 310, D0, which corresponds to WR0, appears on DQ[R0] after approximately 19 tCK, which represents the minimum WR delay of the media. D1 on DQ[R1] is followed by D2 on DQ[R0], and D3 on DQ[R1]. D1, D2, and D3 follow similar delays for their write commands.

[0049] Diagram 310 also illustrates RD4 of rank[0], RD5 of rank[1], RD6 of rank[0], RD7 of rank[1], RD8 of rank[0], and R9 of rank[1]. In one example, the access may include an identification signal or other such signal preceding the read command as a transition from write to read. Such signaling is not included in this diagram because it is not necessary in all implementations. The white block across the DQ bus is labeled WR-RD latency difference and indicates a long delay between the read command and the read data on the DQ bus. This delay will be observed to be much longer than the minimum delay for the write data. In one example tested, The The latency difference was 73tCK at 2400MT / s, 97tCK at 3200MT / s, and 126tCK at 4000MT / s.

[0050] After the difference in read and write latency blocks, there is a block labeled "L" on the data bus that represents the inherent latency in the system when switching between writing and reading. This delay may be different in different systems. The purpose of illustrating the delays in diagram 310 is to show that there may be an inherent system delay that is present even when the WR delay matches the RD delay. Not all delays or signaling are illustrated in diagram 310.

[0051] After a delay, RD D4, corresponding to 4, appears on DQ[R0], followed by D5 on DQ[R1], followed by D6 on DQ[R0], followed by D7 on DQ[R1]. D5, D6, and D7 follow similar delays relative to their read commands. Data D8 and D9 are not shown in diagram 310, but follow similarly.

[0052] Diagram 310 illustrates an example of a 3DXP memory in which the delay between the write command and the write data delay is significantly shorter than the delay of the read command and read data on the DQ bus. The delay asymmetry or mismatch occurs when data from a previous read command is not available for a write command even though the DQ bus or CA bus is available for the command to be issued. For This can result in a scenario where the memory controller must ensure that the data does not conflict with the time it is needed. To avoid this conflict, memory controllers traditionally insert idle states. The box showing the latency difference is an example of a DQ idle state.

[0053] In diagram 320, the sequence of write and read commands is the same as illustrated in diagram 310. Starting from the left of the diagram, the first command is a write for rank[0] (command WR0), followed by WR1 for rank[1], WR2 for rank[0], and WR3 for rank[1]. In diagram 320, D0, which corresponds to WR0, appears on DQ[R0] after a time consistent with the read delay. The delay is shown in the example diagram 320 to be in the range of 100 tCK, although this diagram may not be entirely accurate due to additional signaling and delays that may be added. In addition to signaling that may not be shown, the delay may vary due to transfer rate or other factors. Regardless of the exact number of cycles, diagram 320 illustrates the delay from the WR command to the WR data. to The delay is from the RD command to the RD data. to 10 illustrates a delay matching the write command D1 on DQ[R1], followed by D2 on DQ[R0], and D3 on DQ[R1]. D1, D2, and D3 follow similar delays for their write commands.

[0054] Diagram 320 also illustrates RD4 of rank[0], RD5 of rank[1], RD6 of rank[0], RD7 of rank[1], RD8 of rank[0], and R9 of rank[1]. In one example, a media controller (not shown) adds delay to eliminate the WR-RD latency difference illustrated in diagram 310. Thus, the read and write delays are the same in diagram 320. In one example, the memory controller may configure the memory devices in mismatched modes. To Selectively Place In this case, the read and write timing may be similar to that shown in diagram 310. The memory controller may then place the memory device in a corresponding mode. To Selectively Place it , in this case the read and write timing may be similar to that shown in diagram 320.

[0055] In diagram 320, the write command is followed by the write data. Up to The same delay is applied after the read command. of Read data is On the DQ bus Appears. Therefore, RD D4, corresponding to 4, appears on DQ[R0], followed by D5 on DQ[R1], followed by D6 on DQ[R0], followed by D7 on DQ[R1]. D4, D5, D6, and D7 follow similar delays as their read commands D0, D1, D2, and D3 follow for their respective write commands. Data D8 and D9 are not shown in diagram 320, but follow similarly.

[0056] It will be appreciated that the completion of a write operation (receiving and executing a write command) takes longer in the example of diagram 320 than in the example of diagram 310. Despite the longer write completion time, there is a mix of writes and reads. In case, Due to the latency match, the bus utilization of the system will increase. In one example, the system is scheduled ShouldBased on the type of operation, one can switch between non-matching and matching delay modes. Minimal write latency can be an advantage when the majority of operations involve write commands.

[0057] 4 is an example table of bus utilization data illustrating improved utilization of a system having an inherent read and write delay mismatch that implements selectable write delay. Table 400 illustrates an example of system test results according to system 100 including an NV memory device.

[0058] Transfer rate in Megatransfers per second (MT / s), raw bandwidth (BW) in Gigabytes per second (GB / s), 2:1 efficiency of 2 reads for every 1 write, and effective bandwidth in GB / s (Effective) We evaluated four metrics of BW. The first two columns of the results show the Read Output vs. Write 2:1 workload 4 illustrates results for a one-rank (1R) system with 100 MHz WR latency, 100 MHz RD ...

[0059] For a one-rank system running at 2400MT / s, the raw BW was 19.2GB / s for both the unmatched and matched cases. The 2:1 efficiency for unmatched latency was 57%, while the 2:1 efficiency for matched latency was 68%. By switching to matched latency, the effective bandwidth improved from 10.9GB / s in unmatched mode to 13.1GB / s in matched mode.

[0060] For a two-rank system running at 2400MT / s, the raw BW was 19.2GB / s for both the mismatched and matched cases. The 2:1 efficiency for mismatched latency was 77%, while the 2:1 efficiency for matched latency was 87%. The ability to switch between ranks improved bandwidth utilization over a single-rank system. For the two-rank system, going to matched latency improved the effective bandwidth from 14.7GB / s in mismatched mode to 16.6GB / s in matched mode.

[0061] For a one-rank system running at 2800MT / s, the raw BW was 22.4GB / s for both the unmatched and matched cases. The 2:1 efficiency for unmatched latency was 52%, while the 2:1 efficiency for matched latency was 64%. By switching to matched latency, the effective bandwidth improved from 11.8GB / s in unmatched mode to 14.4GB / s in matched mode.

[0062] For a two-rank system running at 2800MT / s, the raw BW was 22.4GB / s for both the unmatched and matched cases. The 2:1 efficiency for unmatched latency was 73%, while the 2:1 efficiency for matched latency was 83%. For the two-rank system, going to matched latency improved the effective bandwidth from 16.3GB / s in the unmatched mode to 18.6GB / s in the matched mode. Hence, the higher raw bandwidth for both the one-rank and two-rank systems. So 2:1 efficiency reduction death However, the effective bandwidth teeth Improved.

[0063] For a one-rank system running at 3200MT / s, the raw BW was 25.6GB / s for both the unmatched and matched cases. The 2:1 efficiency for unmatched latency was 50%, while the 2:1 efficiency for matched latency was 62%. By switching to matched latency, the effective bandwidth improved from 12.7GB / s in unmatched mode to 15.8GB / s in matched mode.

[0064] For a two-rank system running at 3200MT / s, the raw BW was 25.6GB / s for both the unmatched and matched cases. The 2:1 efficiency for unmatched latency was 70%, while the 2:1 efficiency for matched latency was 81%. For the two-rank system, going to matched latency improved the effective bandwidth from 17.9GB / s in the unmatched mode to 20.8GB / s in the matched mode.

[0065] For a one-rank system running at 4000MT / s, the raw BW was 32.0GB / s for both the unmatched and matched cases. The 2:1 efficiency for unmatched latency was 43%, while the 2:1 efficiency for matched latency was 55%. By switching to matched latency, the effective bandwidth improved from 13.8GB / s in the unmatched mode to 17.7GB / s in the matched mode.

[0066] For a two-rank system running at 4000MT / s, the raw BW was 32.0GB / s for both the unmatched and matched cases. The 2:1 efficiency for unmatched latency was 63%, while the 2:1 efficiency for matched latency was 75%. For the two-rank system, going to matched latency improved the effective bandwidth from 20.3GB / s in unmatched mode to 24.1GB / s in matched mode.

[0067] In each test situation, the two-rank system represents an improvement over an equivalent one-rank system. BringAdditionally, the ability to select the WR delay to match the RD delay also significantly improved system performance over comparable systems that had mismatched WR / RD latencies, in both one-rank and two-rank systems.

[0068] 5 is a flow diagram of an example of a process for selectable write delay in a system having an inherent read delay and write delay mismatch. Process 500 represents a process that may be applied in a memory system according to any example herein. As a specific example, process 500 for dynamically selecting a write delay may be applied by system 100 of FIG. 1, system 202 of FIG. 2A, or system 204 of FIG. 2B.

[0069] Operations represented to the left of the dashed line may be performed by a host, such as a host controller or a memory controller. Operations represented to the right of the dashed line may be performed by the memory device itself.

[0070] In one example, the host is Coming A traffic pattern of memory accesses is identified (block 502). Should A write delay condition for the memory may be identified (block 504). Coming If the write delay for the memory access is not as desired, the system can decide to change the write delay mode of the memory device. In one example, the host can determine which write delay mode the memory device is currently applying and which write delay mode is being applied. Coming The decision is made based on what would be favorable for the traffic patterns.

[0071] If the host is changing the write (WR) delay mode (block 506: “YES” branch), in one example, the host uses 、 or have the memory set to write delay mode Send a command to(Block 508). In one example, the host sends a mode register write command or other command to change the configuration settings of the memory device.

[0072] The memory receives and processes the command (block 510). Depending on the selected mode, the memory device may decide to set the write delay mode to a non-matching delay mode or a matching delay mode (block 512). Non-matching delay mode refers to a mode in which the write delay and read delay remain at their asymmetric values. Matching delay mode refers to a mode in which the write delay and read delay are set equal. R Refers to the mode.

[0073] If the selected mode is a non-matching mode, in one example, the memory can set a configuration register to set the write delay to the minimum delay of the storage medium to be non-matching to the read delay (block 514).If the selected mode is a matching mode, in one example, the memory can set a configuration register to set the write delay to be matched to the read delay (block 516).

[0074] The host may send a write command (block 518). In response to the write command, the memory may receive and process the write command (block 520). After sending the write command (block 518), if the selected mode is a mismatch mode (block 522: "mismatch" branch), in one example, the host sends the write data after a media minimum delay (block 524). The minimum delay may refer to the inherent delay inherent in the storage medium. On the data bus For writing of Instead of waiting to place the data, the host can send the data as soon as the minimum timing is met. The memory receives and decodes the command and places the data on the DQ bus. About Wait for the minimum WR delay (block 526). The host: Other write commands Delay between command and data With less528, which is the data bus for the data command. availability This can result in additional scheduling complexity due to the discrepancy in read and write requests. Such complexity can limit the scheduler's read and write scheduling.

[0075] If the selected mode is a matching mode (block 522: "matching" branch), in one example, the host sends the write data after a read delay (block 530). The read delay is longer than the inherent delay inherent in the storage medium for writing. Instead of sending the data as soon as the minimum timing is met, the host delays sending the data such that the data bus utilization has the same delay between the read and write commands. twist The memory receives and decodes the command and waits for a delay to read the data on the DQ bus (block 532).

[0076] Thus, in one example, The host To receive data in response to a read D The data bus is being accessed, or The host Whether the host is accessing the bus after a write command to send data to memory, After the command Data bus usage is the same one The host will ensure that the delay is others The access command With reduced complexity The commands may be sent, allowing the scheduler to schedule the commands in any order (block 534).

[0077] 6 is a block diagram of an example of a memory subsystem in which selectable write delay may be implemented. System 600 includes elements of a processor and a memory subsystem in a computing device. System 600 provides an example of a system according to system 100 of FIG. 1, system 202 of FIG. 2A, or system 204 of FIG. 2B.

[0078] In one example, the memory array 660 includes: Read Output command From data bus use Delay (Read (RD) Delay 664) and calligraphy Included Commands From data bus use In one example, the write latency 662 is greater than the read latency 664. versus or read delay 664 versus The selection and application of the write delay 662 may be according to any of the examples herein. In one example, the scheduler 626 of the memory controller 620 includes a delay timer 628 for applying timing delays to the scheduling of commands and data based on the write delay mode selected for the memory device 640. The delay logic 654 may represent logic within the memory device 640 for applying a write delay mode to add a delay to the write command to comply with the selected mode.

[0079] Processor 610 represents a processing unit of a computing platform that may run an operating system (OS) and applications, which may collectively be referred to as a host or user of memory. The OS and applications perform operations that result in memory access. Processor 610 may include one or more separate processors. Each of the separate processors may include a single processing unit, a multi-core processing unit, or a combination thereof. The processing units may be a primary processor, such as a CPU (Central Processing Unit), a peripheral processor, such as a GPU (Graphics Processing Unit), or a combination thereof. Memory access may also be initiated by devices such as a network controller or a hard disk controller. Such devices may be integrated with or attached to the processor in some systems, via a bus (e.g., PCI Express), or a combination thereof. System 600 may be implemented as a SOC (System on a Chip) or with standalone components.

[0080] In one example, reference to a memory device may refer to a non-volatile memory device whose state is deterministic even when power is removed from the device. In one example, the non-volatile memory device is a block addressable memory device, such as NAND or NOR technology. Thus, the memory device may also include future generations of non-volatile devices, such as three-dimensional cross-point memory devices, other byte-addressable non-volatile memory devices. The memory device may include a non-volatile byte-addressable medium that stores data based on the resistance state of a memory cell or the phase of a memory cell. In one example, the memory device may use a chalcogenide phase change material (e.g., chalcogenide glass). In one example, the memory device may be or include multi-threshold level NAND flash memory, NOR flash memory, single or multi-level phase change memory (PCM) or switched phase change memory (PCM), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM) incorporating memristor technology, or rotational transfer torque (STT) MRAM, or any combination of the above, or other memory.

[0081] The memory controller 620 represents one or more memory controller circuits or devices for the system 600. The memory controller 620 represents control logic that generates memory access commands in response to execution of operations by the processor 610. The memory controller 620 accesses one or more memory devices 640. The memory devices 640 can be DRAM devices according to any of those mentioned above. In one example, the memory devices 640 are organized and managed as different channels. Each channel couples to buses and signal lines that couple multiple memory devices in parallel. Each channel is independently operable. Thus, each channel is independently accessed and controlled, and timing, data transfer, command and address exchange, and other operations are separate for each channel. Coupling may refer to electrical coupling, communicative coupling, physical coupling, or combinations thereof. Physical coupling may include direct contact. Electrical coupling includes interfaces or interconnects that allow electricity to flow between components or allow signaling between components, or both. A communicative coupling includes any connection, including wired or wireless, that allows the components to exchange data.

[0082] In one example, the settings for each channel are controlled by a separate mode register or other register settings. In one example, each memory controller 620 manages a separate memory channel, although system 600 can be configured to have multiple channels managed by a single controller or multiple controllers on a single channel. In one example, memory controller 620 is part of a host processor or host processor device 610, such as logic implemented on the same die or in the same package space as the processor.

[0083] The memory controller 620 includes I / O interface logic 622 that couples to a memory bus, such as the memory channel mentioned above. The I / O interface logic 622 (and the I / O interface logic 642 of the memory device 640) may include pins, pads, connectors, signal lines, traces or wires, or other hardware that connects to the device, or a combination thereof. The I / O interface logic 622 may include a hardware interface. As illustrated, the I / O interface logic 622 includes at least a driver / transceiver for the signal lines. Generally, wires in an integrated circuit interface couple with pads, pins or connectors to interface with signal lines or traces or other wires between devices. The I / O interface logic 622 may include drivers, receivers, transceivers or terminations or other circuits or combinations of circuits for exchanging signals on the signal lines between the devices. The exchange of signals includes at least one of transmission or reception. Although I / O 622 is shown coupled from memory controller 620 to I / O 642 of memory device 640, it will be understood that in implementations of system 600 where groups of memory devices 640 are accessed in parallel, multiple memory devices may include I / O interfaces to the same interface of memory controller 620. An implementation of system 600 includes one or more memory modules 670. I / O 642 may include interface hardware of the memory modules in addition to interface hardware on the memory devices themselves. Other memory controllers 620 include separate interfaces to other memory devices 640.

[0084] The bus between the memory controller 620 and the memory devices 640 may be implemented as multiple signal lines coupling the memory controller 620 to the memory devices 640. The bus may typically include at least a clock (CLK) 632, a command / address (CMD) 634, and write data (DQ) and read data (DQ) 636, as well as zero or more other signal lines 638. In one example, the bus or connection between the memory controller 620 and the memory may be referred to as a memory bus. In one example, the memory bus is a multi-drop bus. The signal line for CMD may be referred to as a "C / A bus" (or ADD / CMD bus, or some other designation indicating transfer of command (C or CMD) and address (A or ADD) information), and the signal lines for write and read DQ may be referred to as a "data bus." In one example, the independent channels have different clock signals, C / A bus, data bus, and other signal lines. Thus, the system 600 may be considered to have multiple "buses" in the sense that independent interface paths may be considered separate buses. In addition to the lines explicitly shown, it will be understood that the buses may include at least one of strobe signaling lines, alert lines, auxiliary lines, or other signal lines, or combinations thereof. It will also be understood that serial bus technology may be used for the connection between the memory controller 620 and the memory devices 640. An example of a serial bus technology is the transmission of high speed data with 8B10B encoding and an embedded clock over a single differential pair of signals in each direction. In one example, CMD 634 represents a signal line shared with multiple memory devices in parallel. In one example, multiple memory devices share the encoded command signal line of CMD 634, each with a separate chip select (CS_n) signal line for selecting an individual memory device.

[0085] It will be appreciated that in the example of the system 600, the bus between the memory controller 620 and the memory devices 640 includes an auxiliary command bus CMD 634 and an auxiliary bus DQ 636 for carrying write data and read data. In one example, the data bus may include bidirectional lines for read data and write / command data. In another example, the auxiliary bus DQ 636 may include a unidirectional write signal line for writes and data from the host to the memory, and a unidirectional line for read data from the memory to the host. Depending on the memory technology and system design chosen, other signals 638 may accompany the bus or sub-buses, such as strobe lines DQ. Based on the design of the system 600, or implementation if a design supports multiple implementations, the data bus may have more or less bandwidth per memory device 640. For example, the data bus may support memory devices having either a x4 interface, a x8 interface, a x16 interface, or other interfaces. The W in the definition "xW" is an integer that refers to the interface size or interface width of the memory device 640, representing the number of signal lines for exchanging data with the memory controller 620. The interface size of a memory device is the controlling factor as to how many memory devices can be used simultaneously per channel in the system 600 or coupled in parallel to the same signal lines. In one example, high bandwidth memory devices, wide interface devices or stacked memory configurations or combinations thereof can enable a wider interface, such as a x128 interface, a x256 interface, a x512 interface, a x1024 interface or other data bus interface width.

[0086] In one example, the memory device 640 and the memory controller 620 exchange data over the data bus in bursts or a series of consecutive data transfers. A burst corresponds to a number of transfer cycles related to the bus frequency. In one example, a transfer cycle can be a full clock cycle of transfers occurring on the same clock or strobe signal edge (e.g., rising edge). In one example, a full clock cycle, referring to a cycle of the system clock, is divided into a number of unit intervals (UIs). Each UI is a transfer cycle. For example, a double data rate transfer triggers on both edges (e.g., rising and falling) of the clock signal. A burst can last for a configured number of UIs. This can be a configuration stored in a register or triggered on the fly. For example, a series of eight consecutive transfer periods can be considered a burst length of 8 (BL8), and each memory device 640 can transfer data in each UI. Thus, a x8 memory device operating at BL8 can transfer 64 bits of data (8 data signal lines x 8 data bits transferred per line via the burst). It will be understood that this simple example is illustrative only and is not limiting.

[0087] Memory devices 640 represent memory resources for system 600. In one example, each memory device 640 is a separate memory die. In one example, each memory device 640 can be an interface with multiple (e.g., two) channels per device or die. Each memory device 640 includes I / O interface logic 642 with a bandwidth (e.g., x16 or x8 or some other interface bandwidth) determined by the implementation of the device. The I / O interface logic 642 allows the memory device to interface with memory controller 620. The I / O interface logic 642 can include a hardware interface and may follow the I / O 622 of the memory controller, but at the memory device end. In one example, multiple memory devices 640 are connected in parallel to the same command and data bus. In another example, multiple memory devices 640 are connected in parallel to the same command bus and connected to different data buses. For example, system 600 can be configured with multiple memory devices 640 coupled in parallel. Each memory device responds to commands and accesses its internal memory resources 660. For a write operation, each memory device 640 can write a portion of the entire data word, and for a read operation, each memory device 640 can fetch a portion of the entire data word, with the remaining bits of the word being provided or received in parallel by the other memory devices.

[0088] In one example, the memory device 640 is disposed directly on a motherboard of a computing device or a host system platform (e.g., a PCB (printed circuit board) on which the processor 610 is disposed). In one example, the memory device 640 may be organized into a memory module 670. In one example, the memory module 670 represents a dual in-line memory module (DIMM). In one example, the memory module 670 represents another organization of multiple memory devices for sharing at least a portion of the access or control circuitry. The circuitry may be a separate circuit, separate device, or separate board from the host system platform. The memory module 670 may include multiple memory devices 640 and may include support for multiple separate channels to the included memory devices disposed therein. In another example, the memory device 640 may be incorporated into the same package as the memory controller 620, for example, by a technology such as a multi-chip module (MCM), package-on-package, through silicon via (TSV) or other technology or combination thereof. Similarly, in one example, multiple memory devices 640 may be incorporated into the memory module 670. They may themselves be incorporated into the same package as the memory controller 620. It will be appreciated that in these and other implementations, the memory controller 620 may be part of the host processor 610.

[0089] Memory devices 640 each include one or more memory arrays 660. Memory arrays 660 represent addressable memory locations or storage locations of data. Typically, memory arrays 660 are managed as rows of data and accessed via control of wordlines (rows) and bitlines (individual bits within a row). Memory arrays 660 may be organized as separate channels, ranks, banks, and partitions of memory. A channel may refer to an independent control path to storage locations in memory device 640. A rank may refer to a common location across multiple memory devices in parallel (e.g., the same row address in different devices). A bank may refer to a sub-array of memory locations in memory device 640. In one example, a bank of memory is divided into sub-banks with at least a portion of the shared circuitry (e.g., drivers, signal lines, control logic) for the sub-banks. This allows for separate addressing and access. It will be understood that channels, ranks, banks, sub-banks, bank groups, or other organization of memory locations, and combinations of such organization may overlap in their application to physical resources. For example, the same physical memory location may be accessed through a particular channel as a particular bank that may also belong to a rank. Thus, the organization of memory resources may be understood inclusively, not exclusively.

[0090] In one example, the memory device 640 includes one or more registers 644. The registers 644 represent one or more storage devices or storage locations that provide configuration or settings for operation of the memory device. In one example, the registers 644 can provide storage locations in the memory device 640 for storing data accessed by the memory controller 620 as part of control or management operations. In one example, the registers 644 include one or more mode registers. In one example, the registers 644 include one or more general-purpose registers. Configurations of locations in the registers 644 can configure the memory device 640 to operate in different "modes." Command information can trigger different operations in the memory device 640 based on the mode. Additionally or alternatively, different modes can also trigger different operations from address information or other signal lines depending on the mode. Settings in the registers 644 can indicate configurations of I / O settings (e.g., timing, termination or ODT (on-die termination) 646, driver configurations or other I / O settings).

[0091] In one example, the memory device 640 includes an ODT 646 as part of the interface hardware associated with the I / O 642. The ODT 646 may be configured as described above and may provide an impedance setting that is applied to the interface to designated signal lines. In one example, the ODT 646 is applied to the DQ signal lines. In one example, the ODT 646 is applied to the command signal lines. In one example, the ODT 646 is applied to the address signal lines. In one example, the ODT 646 may be applied to any combination of the foregoing. The ODT setting may be changed based on whether the memory device is a selected target or non-target device of an access operation. The ODT 646 setting may affect the timing and reflection of the signaling on the termination lines. Careful control over the ODT 646 may enable faster operation with improved matching of the applied impedance and load. The ODT 646 may be applied to certain signal lines of the I / O interface 642, 622 (e.g., ODT for the DQ lines or ODT for the CA lines), but not necessarily to all signal lines.

[0092] The memory device 640 includes a controller 650 that represents control logic within the memory device for controlling internal operations within the memory device. For example, the controller 650 decodes commands sent by the memory controller 620 and generates internal operations to execute or satisfy the commands. The controller 650 may be referred to as an internal controller and is separate from the host's memory controller 620. The controller 650 may determine which mode is selected based on the register 644 and may configure operations for accessing the memory resources 660 or other operations internally based on the selected mode. The controller 650 generates control signals to control the routing of bits within the memory device 640 to provide an appropriate interface for the selected mode and send the command to the appropriate memory location or address. The controller 650 includes a command logic 652 that may decode command encodings received on the command and address signal lines. Thus, the command logic 652 may be or may include a command decoder. Using the command logic 652, the memory device may identify the command and generate internal operations to execute the requested command.

[0093] Referring back to the memory controller 620, the memory controller 620 includes command (CMD) logic 624, which represents logic or circuitry for generating commands to be sent to the memory device 640. Generating a command may refer to preparing a pre-scheduled command or a queued command for transmission. Generally, signaling within the memory subsystem includes address information within or accompanying the command to indicate or select one or more memory locations where the memory device should execute the command. In response to scheduling a transaction for the memory device 640, the memory controller 620 can issue a command via the I / O 622 to cause the memory device 640 to execute the command. In one example, the controller 650 of the memory device 640 receives and decodes the command and address information received from the memory controller 620 via the I / O 642. Based on the received command and address information, the controller 650 can execute the command by controlling the timing of operations of logic and circuits within the memory device 640. The controller 650 is responsible for compliance with standards or specifications, such as timing and signaling requirements, within the memory device 640. The memory controller 620 can implement compliance with standards or specifications through scheduling and control of accesses.

[0094] The memory controller 620 includes a scheduler 626, which represents logic or circuitry for generating and ordering transactions to be sent to the memory device 640. From one perspective, the main function of the memory controller 620 can be said to be scheduling memory accesses and other transactions to the memory device 640. Such scheduling may include generating the transactions themselves to implement requests for data by the processor 610 and to maintain data integrity (e.g., using refresh-related commands). A transaction may include one or more commands, and thus may result in the transfer of commands or data or both in one or more timing cycles, such as a clock cycle or unit interval. A transaction may be for an access, such as a read or write or related command, or a combination thereof. Other transactions may include memory management commands for configuration, settings, data integrity, or other commands or a combination thereof.

[0095] The memory controller 620 typically includes logic, such as a scheduler 626, to enable selection and ordering of transactions to improve performance of the system 600. Thus, the memory controller 620 can select which of the outstanding transactions should be sent to the memory device 640 and in what order. This is typically accomplished using logic that is much more complex than a simple first-in, first-out algorithm. The memory controller 620 manages the transmission of transactions to the memory device 640 and manages the timing associated with the transactions. In one example, transactions have deterministic timing. The timing can be managed by the memory controller 620 and used in determining how to schedule transactions with the scheduler 626.

[0096] 7 is a block diagram of an example of a computing system in which selectable write delay may be implemented. System 700 represents a computing device according to any of the examples herein and may be a laptop computer, a desktop computer, a tablet computer, a server, a gaming or entertainment control system, an embedded computing device or other electronic device. System 700 provides an example of a system according to system 100 of FIG. 1, system 202 of FIG. 2A, or system 204 of FIG. 2B.

[0097] In one example, the memory 730 includes: Read Output command From data bus use Delay (read delay) and calligraphy Included Commands From data bus use 7 represents a memory having an asymmetry between the delay (write delay) of the read command and that of the read command. RD-DLY represents the read delay and WR-DLY represents the write delay. RD-DLY / WR-DLY 792 represents the delay applied for writes to memory 730. In one example, the write delay is selectable to either not match the read delay or match the read delay. The selection and application of the write delay may be according to any of the examples herein. Delay logic 790 represents logic in memory subsystem 720 for selecting a write delay mode and applying the selected write delay to the memory access transaction. Delay logic 790 may represent logic in memory controller 722 for applying the write delay and determining how to schedule commands and when to send the write data on the data bus. Delay logic 790 may represent logic in memory 730 for applying a write delay mode and adding a delay to the write command to comply with the selected mode.

[0098] System 700 includes a processor 710. Processor 710 may include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), processing core or other processing hardware, or combination thereof, to provide processing or execution of instructions for system 700. Processor 710 controls the overall operation of system 700 and may be or include one or more programmable general-purpose or application-specific microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or combinations of such devices.

[0099] In one example, the system 700 includes an interface 712 coupled to the processor 710. The interface 712 may represent a higher speed or high throughput interface for a system component that requires a higher bandwidth connection, such as the memory subsystem 720 or the graphics interface component 740. The interface 712 represents an interface circuit that may be a standalone component or may be integrated into a processor die. The interface 712 may be integrated on the processor die as a circuit or integrated into a system on chip as a component. If present, the graphics interface 740 interfaces to a graphics component for providing a visual display to a user of the system 700. The graphics interface 740 may be a standalone component or may be integrated into the processor die or system on chip. In one example, the graphics interface 740 can drive a high definition (HD) or ultra high definition (UHD) display that provides output to a user. In one example, the display may include a touch screen display. In one example, graphics interface 740 generates displays based on data stored in memory 730, or based on operations performed by processor 710, or both.

[0100] Memory subsystem 720 represents the main memory of system 700 and provides storage for data values ​​used in the execution of codes or routines executed by processor 710. Memory subsystem 720 may include one or more memory devices 730, such as one or more types of random access memory (RAM), such as read-only memory (ROM), flash memory, DRAM, 3DXP (three-dimensional crosspoint) or other memory devices or combinations of such devices. Memory 730 stores and hosts, among other things, an operating system (OS) 732 for providing a software platform for the execution of instructions within system 700. Additionally, applications 734 may be executed on the software platform of OS 732 from memory 730. Applications 734 represent programs. The programs have their own operating logic for the execution of one or more functions. Processes 736 represent agents or routines that provide auxiliary functions to OS 732 or one or more applications 734 or a combination thereof. OS 732, applications 734 and processes 736 provide the software logic for providing the functionality for system 700. In one example, memory subsystem 720 includes memory controller 722, which is a memory controller that generates and issues commands to memory 730. It will be appreciated that memory controller 722 may be a physical part of processor 710 or a physical part of interface 712. For example, memory controller 722 may be an integrated memory controller that is integrated into a circuit with processor 710, such as integrated into a processor die or a system on a chip.

[0101] Although not specifically illustrated, it will be understood that system 700 may include one or more buses or bus systems between devices, such as a memory bus, a graphics bus, an interface bus, or others. A bus or other signal lines may communicatively or electrically couple components to each other, or may communicatively and electrically couple components. A bus may include physical communication lines, point-to-point connections, bridges, adapters, controllers, or other circuits, or combinations thereof. A bus may include, for example, one or more of a system bus, a Peripheral Component Interconnect (PCI) bus, a HyperTransport Architecture bus or an Industry Standard Architecture (ISA) bus, a Small Computer System Interface (SCSI) bus, a Universal Serial Bus (USB), or other buses, or combinations thereof.

[0102] In one example, the system 700 includes an interface 714 that may be coupled to the interface 712. The interface 714 may be a slower interface than the interface 712. In one example, the interface 714 represents an interface circuit that may include standalone components and integrated circuits. In one example, multiple user interface and / or peripheral components are coupled to the interface 714. The network interface 750 provides the system 700 with the ability to communicate with remote devices (e.g., servers or other computing devices) over one or more networks. The network interface 750 may include an Ethernet adapter, a wireless interconnection component, a cellular network interconnection component, a Universal Serial Bus (USB) or other wired or wireless standards-based or proprietary interface. The network interface 750 may exchange data with remote devices. Such exchange may include transmitting data stored in memory or receiving data stored in memory.

[0103] In one example, system 700 includes one or more input / output (I / O) interfaces 760. I / O interface 760 may include one or more interface components through which a user interacts with system 700 (e.g., voice, alphanumeric, haptic / touch, or other interface modalities). Peripheral interface 770 may include any hardware interface not specifically mentioned above. Peripheral generally refers to devices that connect dependently to system 700. A dependent connection is one in which system 700 provides a software or hardware platform or where operations are executed on and a user interacts with the platform.

[0104] In one example, the system 700 includes a storage subsystem 780 for storing data in a non-volatile manner. In one example, in certain system implementations, at least certain components of the storage 780 may overlap with components of the memory subsystem 720. The storage subsystem 780 includes a storage device 784. The storage device 784 may be or include any conventional medium for storing large amounts of data in a non-volatile manner, such as one or more magnetic disks, solid state disks, 3DXP disks, or optical-based disks, or combinations thereof. The storage 784 holds code or instructions and data 786 in a persistent state (i.e., the value is retained even if power to the system 700 is interrupted). While the storage 784 may be generally considered to be a "memory," the memory 730 is typically an execution or operating memory for providing instructions to the processor 710. While the storage 784 is non-volatile, the memory 730 may include a volatile memory (i.e., the value or state of the data is indeterminate if power to the system 700 is interrupted). In one example, the storage subsystem 780 includes a controller 782 for interfacing with storage 784. In one example, the controller 782 may be a physical part of the interface 714 or the processor 710, or may include circuitry or logic in both the processor 710 and the interface 714.

[0105] The power source 702 provides power to the components of the system 700. More specifically, the power source 702 typically interfaces with one or more power sources 704 in the system 700 to provide power to the components of the system 700. In one example, the power source 704 includes an AC-DC (alternating current-direct current) adapter for plugging into a wall outlet. Such an AC power source can be a renewable energy (e.g., solar power) power source 702. In one example, the power source 702 includes a DC power source, such as an external AC-DC converter. In one example, the power source 702 or the power source 704 includes wireless charging hardware for charging via proximity to a charging magnetic field. In one example, the power source 702 can include an internal battery or fuel cell power source.

[0106] 8 is a block diagram of an example of a mobile device in which selectable write delay may be implemented. System 800 represents a mobile computing device, such as a computing tablet, a mobile phone or smartphone, a wearable computing device, or other mobile device, or an embedded computing device. It will be understood that not all components of such a device are shown in system 800, although certain of these components are generally shown. System 800 provides an example of a system according to system 100 of FIG. 1, system 202 of FIG. 2A, or system 204 of FIG. 2B.

[0107] In one example, memory 862 represents a memory having an asymmetry between the delay of a read command to data bus utilization (read delay) and the delay of a write command to data bus utilization (write delay). RD-DLY represents read delay and WR-DLY represents write delay. RD-DLY / WR-DLY 892 represents a delay applied for writing to memory 862. In one example, the write delay is selectable to either not match the read delay or match the read delay. The selection and application of the write delay may be according to any example herein. Delay logic 890 represents logic within memory subsystem 860 for selecting a write delay mode and applying the selected write delay to memory access transactions. Delay logic 890 may represent logic within memory controller 864 for applying the write delay and determining how to schedule commands and when to send write data on the data bus. Delay logic 890 may represent logic within memory 862 for applying a write delay mode to add a delay to a write command to comply with a selected mode.

[0108] The system 800 includes a processor 810 that performs the main processing operations of the system 800. The processor 810 may include one or more physical devices such as a microprocessor, an application processor, a microcontroller, a programmable logic device, or other processing means. The processing operations performed by the processor 810 include the execution of an operating platform or operating system on which applications and device functions are executed. The processing operations include operations related to I / O (input / output) with a human user or other devices, operations related to power management, operations related to connecting the system 800 to another device, or combinations thereof. The processing operations may also include operations related to audio I / O, display I / O, or other interfaces, or combinations thereof. The processor 810 can execute data stored in memory. The processor 810 can write or edit data stored in memory.

[0109] In one example, the system 800 includes one or more sensors 812. The sensors 812 represent embedded sensors or interfaces to external sensors, or a combination thereof. The sensors 812 enable the system 800 to monitor or detect one or more conditions of the environment or device in which the system 800 is implemented. The sensors 812 may include environmental sensors (such as temperature sensors, motion detectors, light detectors, cameras, chemical sensors (e.g., carbon monoxide sensors, carbon dioxide sensors, or other chemical sensors), pressure sensors, accelerometers, gyroscopes, medical or physiological sensors (e.g., biosensors, heart rate monitors, or other sensors for detecting physiological attributes), or other sensors, or combinations thereof. The sensors 812 may also include sensors for biometric systems, such as fingerprint recognition systems, face detection or recognition systems, or other systems that detect or recognize features of a user. The sensors 812 should be understood broadly and not as a limitation on the many different types of sensors that may be implemented with the system 800. In one example, the one or more sensors 812 couple to the processor 810 via a front-end circuit integrated into the processor 810. In one example, the one or more sensors 812 couple to the processor 810 via another component of the system 800.

[0110] In one example, system 800 includes an audio subsystem 820 that represents hardware (e.g., audio hardware and audio circuitry) and software (e.g., drivers, codecs) components associated with providing audio functionality to a computing device. The audio functionality may include a speaker or headphone output and a microphone input. Devices for such functionality may be integrated into or connected to system 800. In one example, a user interacts with system 800 by providing voice commands that are received and processed by processor 810.

[0111] Display subsystem 830 represents hardware (e.g., display devices) and software components (e.g., drivers) that provide visual displays for display to a user. In one example, the display includes a haptic component or touch screen element for a user to interact with the computing device. Display subsystem 830 includes a display interface 832 that includes a particular screen or hardware device used to provide a display to a user. In one example, display interface 832 includes logic separate from processor 810 (such as a graphics processor) for performing at least some processing related to the display. In one example, display subsystem 830 includes a touch screen device that provides both output and input to a user. In one example, display subsystem 830 includes a high definition (HD) display or an ultra high definition (UHD) display that provides output to a user. In one example, the display subsystem includes or drives a touch screen display. In one example, display subsystem 830 generates display information based on data stored in memory, or based on operations performed by processor 810, or both.

[0112] The I / O controller 840 represents hardware devices and software components related to interaction with a user. The I / O controller 840 may operate to manage hardware that is part of the audio subsystem 820 or the display subsystem 830 or both. In addition, the I / O controller 840 illustrates connection points for additional devices to connect to the system 800 through which a user may interact with the system. For example, devices that may be attached to the system 800 may include a microphone device, a speaker or stereo system, a video system or other display device, a keyboard or keypad device, buttons / switches, or other I / O devices for use with a particular application, such as a card reader, or other devices.

[0113] As mentioned above, I / O controller 840 can interact with audio subsystem 820 or display subsystem 830, or both. For example, input through a microphone or other audio device may provide input or commands for one or more applications or functions of system 800. Additionally, audio output may be provided instead of or in addition to display output. In another example, if the display subsystem includes a touch screen, the display device also functions as an input device that may be managed, at least in part, by I / O controller 840. Additional buttons or switches may also be present on system 800 to provide I / O functions managed by I / O controller 840.

[0114] In one example, I / O controller 840 manages devices such as accelerometers, cameras, light or other environmental sensors, gyroscopes, global positioning systems (GPS) or other hardware or sensors 812 that may be included in system 800. Inputs may be part of direct user interaction as well as providing environmental input to the system that affects its operation (such as filtering noise, adjusting the display for brightness detection, applying a flash for a camera or other features).

[0115] In one example, the system 800 includes a power management 850 that manages battery power usage and functions related to battery charging and power saving operation. The power management 850 manages power from a power source 852 that provides power to the components of the system 800. In one example, the power source 852 includes an AC-DC (alternating current-direct current) adapter for plugging into a wall outlet. Such an AC source can be a renewable energy source (e.g., solar power, motion-based power). In one example, the power source 852 includes only DC power, which can be provided by a DC source such as an external AC-DC converter. In one example, the power source 852 includes wireless charging hardware for charging via proximity to a charging magnetic field. In one example, the power source 852 can include an internal battery or a fuel cell power source.

[0116] The memory subsystem 860 includes a memory device 862 for storing information in the system 800. The memory subsystem 860 may include non-volatile (state does not change when power to the memory device is interrupted) or volatile (state is indeterminate when power to the memory device is interrupted) memory devices or a combination thereof. The memory 860 may store application data, user data, music, photos, documents or other data, as well as system data (whether long-term or temporary) related to the execution of applications and functions of the system 800. In one example, the memory subsystem 860 includes a memory controller 864 (which may also be considered part of the control of the system 800 and potentially part of the processor 810). The memory controller 864 includes a scheduler that generates and issues commands to control access to the memory device 862.

[0117] The connections 870 include hardware devices (e.g., wireless or wired connectors and communication hardware or a combination of wired and wireless hardware) and software components (e.g., drivers, protocol stacks) to enable the system 800 to communicate with external devices. The external devices can be other computing devices, separate devices such as wireless access points or base stations, and peripherals such as headsets, printers or other devices. In one example, the system 800 exchanges data with the external devices for storage in memory or for display on a display device. The exchanged data can include data to be stored in memory or data already stored in memory for reading, writing or editing the data.

[0118] The connection 870 may include multiple different types of connections. For generalization, the system 800 is illustrated with a cellular connection 872 and a wireless connection 874. The cellular connection 872 generally refers to a cellular network connection provided by a wireless carrier, such as provided via GSM (Global System for Mobile Communications) or a variant or derivative thereof, or CDMA (Code Division Multiple Access) or a variant or derivative thereof, TDM (Time Division Multiplexing) or a variant or derivative thereof, LTE (Long Term Evolution, also referred to as "4G", "5G"), or other cellular service standards. The wireless connection 874 refers to a wireless connection that is not cellular and may include a personal area network (such as Bluetooth), a local area network (such as WiFi), or a wide area network (such as WiMAX), or other wireless communication, or a combination thereof. Wireless communication refers to the transfer of data through the use of modulated electromagnetic radiation through a non-solid medium. Wired communication occurs by a solid communication medium.

[0119] Peripheral connections 880 include hardware interfaces and connectors as well as software components (e.g., drivers, protocol stacks) for making peripheral connections. It will be appreciated that system 800 can be both a peripheral device connected to other computing devices ("out" 882) and to system 800 ("from" 884). System 800 will typically have a "docking" connector for connecting to other computing devices for purposes such as managing (e.g., downloading, uploading, modifying, synchronizing) content on system 800. In addition, docking connectors may enable system 800 to connect to certain peripherals that allow system 800 to control content output to, for example, an audiovisual system or other system.

[0120] In addition to proprietary docking connectors or other proprietary connection hardware, system 800 may make peripheral connections 880 through common or standards-based connectors. Common types may include Universal Serial Bus (USB) connectors (which may include any of a number of different hardware interfaces), MiniDisplayPort (MDP), DisplayPort including High-Definition Multimedia Interface (HDMI®), or other types.

[0121] Generally with respect to the description herein, in one example, a non-volatile (NV) memory device includes an array of memory cells having an asymmetry between an intrinsic read operation delay and an intrinsic write operation delay, and a register for storing a value for selecting between two modes of write operation delay, the first mode having a first write operation delay that does not match the read operation delay, and the second mode having a second write operation delay that matches the read operation delay.

[0122] In one example, the NV memory device defaults to a first mode. In one example, the NV memory device defaults to a second mode. In one example, the registers runtime In one example, the array of memory cells includes an array of three-dimensional cross-point (3DXP) memory cells.

[0123] Generally with respect to the description herein, in one example, a controller includes a hardware interface for coupling to a plurality of non-volatile (NV) memory devices having an asymmetry between intrinsic read operation delay and intrinsic write operation delay, and a scheduler for scheduling commands to write values ​​of registers of the NV memory devices, the values ​​being for selecting between two modes of write operation delay, the first mode having a first write operation delay that does not match the read operation delay, and the second mode having a second write operation delay that matches the read operation delay.

[0124] In one example, the NV memory device defaults to a first mode. In one example, the NV memory device defaults to a second mode. In one example, the scheduler N V Write operations to send to the memory device Many Have case To ,The scheduler checks whether the register Select the first mode The command to write to the register is In one example, the scheduler schedules commands that have a mix of write and read operations to send to the NV memory device. case To ,The scheduler checks whether the register Selecting the second mode like Register To In one example, when the second mode is selected, the scheduler schedules commands for write operations and commands for read operations in any order. In one example, the scheduler schedules commands for the NV memory device. runtime In one example, the NV memory device is organized as a plurality of ranks of memory devices and the scheduler schedules commands to select a write operation delay for each rank. In one example, the scheduler switches sending commands between different ranks during the write operation delay and the read operation delay. In one example, the NV memory device includes a three-dimensional cross point (3DXP) memory device.

[0125] Generally with respect to the description herein, in one example, a method includes receiving a first command to set a value of a register to select between two modes of write operation delay for a non-volatile (NV) memory device, the first mode having a first write operation delay that does not match the read operation delay and the second mode having a second write operation delay that matches the read operation delay, the NV memory device having an asymmetry between the intrinsic read operation delay and the intrinsic write operation delay, and receiving a second command to trigger a write operation, the write operation being performed with the write operation delay of the selected first mode or the second mode.

[0126] In one example, the method further includes defaulting to the first mode. In one example, the method further includes defaulting to the second mode. In one example, receiving the first command includes: runtime To dynamically configure registers during runtime In one example, the NV memory device includes a three-dimensional cross-point (3DXP) memory device.

[0127] The illustrated flow diagrams herein provide examples of a sequence of various processing operations. The flow diagrams may depict physical operations as well as operations performed by software or firmware routines. The flow diagrams may illustrate an example of an implementation of states of a finite state machine (FSM) that may be implemented in hardware and / or software. The order of operations, although shown in a particular sequence or order, may be modified unless otherwise specified. Thus, the illustrated diagrams should be understood as examples only, and the processes may be performed in different orders and some operations may be performed in parallel. Additionally, one or more operations may be omitted. Thus, not all implementations perform all operations.

[0128] To the extent that various operations or functions are described herein, they may be described or defined as software code, instructions, configurations and / or data. The content may be directly executable ("object" or "executable"), source code or difference code ("delta" or "patch" code). The software content of what is described herein may be provided via an article of manufacture in which the content is stored, or via a method of operating a communications interface to transmit data through the communications interface. A machine-readable storage medium may cause a machine to perform the described functions or operations and includes any mechanism for storing information in a form accessible by a machine (e.g., computing device, electronic system, etc.), such as recordable / non-recordable media (e.g., read-only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.). A communications interface includes any mechanism for interfacing to either a hardwired, wireless, optical, etc. medium for communicating with another device, such as a memory bus interface, a processor bus interface, an Internet connection, a disk controller, etc. The communications interface may be configured by providing configuration parameters and / or sending signals to prepare the communications interface to provide data signals describing the software content. The communications interface may be accessed via one or more commands or signals sent to the communications interface.

[0129] Various components described herein may be means for performing the described operations or functions. Each component described herein includes software, hardware, or a combination thereof. A component may be implemented as a software module, a hardware module, special-purpose hardware (e.g., special-purpose hardware, application-specific integrated circuits (ASICs), digital signal processors (DSPs), etc.), an embedded controller, a hardwired circuit, etc.

[0130] In addition to what is described herein, various modifications may be made to the disclosed and implementations of the invention without departing from the scope thereof. Thus, the illustrations and examples herein should be construed in an illustrative and not a limiting sense. The scope of the invention should be evaluated solely by reference to the claims that follow. [Other possible items] [Item 1] an array of memory cells having an asymmetry between an intrinsic read operation delay and an intrinsic write operation delay; a register for storing a value for selecting between two modes of write operation delay, the first mode having a first write operation delay that does not match the read operation delay, and the second mode having a second write operation delay that matches the read operation delay; A non-volatile (NV) memory device comprising: [Item 2] 2. The NV memory device of claim 1, wherein the NV memory device is set to the first mode by default. [Item 3] Item 2. The NV memory device of item 1, wherein the NV memory device is set to the second mode by default. [Item 4] 2. The NV memory device of claim 1, wherein the register is dynamically configurable during run-time of the NV memory device. [Item 5] Item 2. The NV memory device of item 1, wherein the array of memory cells includes an array of three-dimensional cross-point (3DXP) memory cells. [Item 6] a hardware interface for coupling to a plurality of non-volatile (NV) memory devices having an asymmetry between an intrinsic read operation delay and an intrinsic write operation delay; a scheduler for scheduling commands to write a value of a register of the NV memory device, the value being for selecting between two modes of write operation delay, the first mode having a first write operation delay that does not match the read operation delay, and the second mode having a second write operation delay that matches the read operation delay; and Including, the controller. [Item 7] 7. The controller of claim 6, wherein the NV memory device is defaulted to the first mode. [Item 8] 7. The controller of claim 6, wherein the NV memory device is defaulted to the second mode. [Item 9] The controller of item 6, wherein the scheduler schedules the command to write the value of the register to select the first mode when the scheduler has mostly write operations to send to the NV memory device. [Item 10] The controller of item 6, wherein the scheduler schedules the command to write the register to select the second mode when the scheduler has a mix of write and read operations to send to the NV memory device. [Item 11] Item 11. The controller of item 10, wherein when the second mode is selected, the scheduler schedules commands for write operations and commands for read operations in any order. [Item 12] 7. The controller of claim 6, wherein the scheduler schedules the command to dynamically write the value of the register during execution time of the NV memory device. [Item 13] 7. The controller of claim 6, wherein the NV memory devices are organized as a plurality of ranks of memory devices, and the scheduler schedules the command to select the write operation delay for each rank. [Item 14] Item 14. The controller of item 13, wherein the scheduler alternates sending commands between different ranks during the write operation delay and the read operation delay. [Item 15] 7. The controller of claim 6, wherein the NV memory device comprises a three-dimensional cross-point (3DXP) memory device. [Item 16] receiving a first command to set a value of a register to select between two modes of write operation delay for a non-volatile (NV) memory device, the first mode having a first write operation delay that does not match a read operation delay and the second mode having a second write operation delay that matches the read operation delay, the NV memory device having an asymmetry between an intrinsic read operation delay and an intrinsic write operation delay; receiving a second command to trigger a write operation, the write operation being performed with the write operation delay of the selected first mode or second mode; A method comprising: [Item 17] Item 17. The method of item 16, further comprising a step of defaulting to the first mode. [Item 18] Item 17. The method of item 16, further comprising a step of defaulting to the second mode. [Item 19] Item 17. The method of item 16, wherein receiving the first command includes receiving the first command during run-time of the NV memory device to dynamically configure the register during run-time. [Item 20] Item 17. The method of item 16, wherein the NV memory device comprises a three-dimensional cross-point (3DXP) memory device.

Claims

1. an array of memory cells having an asymmetry between an intrinsic read operation delay and an intrinsic write operation delay; a register for storing a value for selecting between two write operation delay modes, the first write delay mode having a first write operation delay that does not match the read operation delay, and the second write delay mode having a second write operation delay that matches the read operation delay; A non-volatile (NV) memory device comprising:

2. The NV memory device of claim 1, wherein the value specifies the first write delay mode or the second write delay mode based on a mix ratio of commands for scheduled read operations and commands for scheduled write operations. when a value of a ratio of commands for the read operation to commands for the write operation is greater than or equal to a predetermined threshold, the value specifies the second write delay mode; The NV memory device of claim 2 , wherein if the value of the ratio of commands for the read operation to commands for the write operation is less than the predetermined threshold, the value specifies the first write delay mode.

4. An NV memory device as described in any one of claims 1 to 3, wherein the intrinsic read operation delay defines a minimum delay for accessing the array for a read operation, and the intrinsic write operation delay defines a minimum delay for accessing the array for a write operation.

5. An NV memory device as described in any one of claims 1 to 4, wherein the second write operation delay is the intrinsic write operation delay plus the difference between the intrinsic read operation delay and the intrinsic write operation delay.

6. The NV memory device of claim 1 , wherein the NV memory device defaults to the first write delay mode.

7. The NV memory device of claim 1 , wherein the NV memory device defaults to the second write delay mode.

8. The NV memory device of claim 1 , wherein the registers are dynamically configurable during run-time of the NV memory device.

9. The NV memory device of claim 1 , wherein the array of memory cells comprises an array of three-dimensional cross-point (3DXP) memory cells.

10. a hardware interface for coupling to a plurality of non-volatile (NV) memory devices having an asymmetry between an intrinsic read operation delay and an intrinsic write operation delay; a scheduler for scheduling commands to write a value of a register of the NV memory device, the value being for selecting between two modes of write operation delay, a first write delay mode having a first write operation delay that does not match a read operation delay, and a second write delay mode having a second write operation delay that matches the read operation delay; and A controller comprising:

11. The controller of claim 10, wherein the intrinsic read operation delay defines a minimum delay for accessing an array of memory cells of the NV memory device for a read operation, and the intrinsic write operation delay defines a minimum delay for accessing the array for a write operation.

12. The controller of claim 10 or 11, wherein the NV memory device defaults to the first write delay mode.

13. The controller of claim 10 or 11, wherein the NV memory device defaults to the second write delay mode.

14. 14. The controller of claim 10, wherein when the scheduler has relatively more commands for write operations to send to the NV memory device than commands for read operations, the scheduler schedules the command to write the value of the register to select the first write delay mode.

15. The controller of claim 14, wherein when the first write delay mode is selected, the scheduler schedules commands with a shorter delay than the second write delay mode.

16. 14. The controller of claim 10, wherein when the scheduler has relatively more commands for read operations to send to the NV memory device than commands for write operations, the scheduler schedules the command to write the value of the register to select the second write delay mode.

17. 17. The controller of claim 16, wherein when the second write delay mode is selected, the scheduler schedules commands for write operations and commands for read operations in any order.

18. The controller of claim 10 , wherein the scheduler schedules the commands to dynamically write the values ​​of the registers during runtime of the NV memory device.

19. 19. The controller of claim 10, wherein the NV memory devices are organized into a plurality of ranks of memory devices, and the scheduler schedules the commands to select the write operation delay for each rank.

20. 20. The controller of claim 19, wherein the scheduler alternates sending commands between ranks during the write operation delay and the read operation delay.

21. The controller of claim 10 , wherein the NV memory device comprises a three-dimensional cross-point (3DXP) memory device.

22. 1. A method for configuring a write operation delay, comprising: receiving a first command to set a value of a register to select between two write operation delay modes of a non-volatile (NV) memory device, the first write delay mode having a first write operation delay that does not match a read operation delay and the second write delay mode having a second write operation delay that matches the read operation delay, the NV memory device having an asymmetry between an intrinsic read operation delay and an intrinsic write operation delay; receiving a second command to trigger a write operation, the write operation being performed with the write operation delay of the selected first write delay mode or the second write delay mode; A method comprising:

23. The method of claim 22, wherein the intrinsic read operation delay defines a minimum delay for accessing an array of memory cells of the NV memory device for a read operation, and the intrinsic write operation delay defines a minimum delay for accessing the array for a write operation.

24. 23. The method of claim 22, further comprising defaulting to the first write delay mode.

25. 23. The method of claim 22, further comprising defaulting to the second write delay mode.

26. 26. The method of claim 22, wherein receiving the first command comprises receiving the first command during runtime to dynamically configure the register during runtime of the NV memory device.

27. 27. The method of any one of claims 22 to 26, wherein the NV memory device comprises a three-dimensional cross-point (3DXP) memory device.

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